From 4824de3bbf903219f8b23d67ee65b850631a8490 Mon Sep 17 00:00:00 2001 From: Florian Boor Date: Mon, 30 Aug 2010 00:31:48 +0200 Subject: linux: 2.6.28 patch and workarounds for smartqv7. --- recipes/linux/linux-2.6.28/smartqv7/defconfig | 1515 + .../linux/linux-2.6.28/smartqv7/smartqv7-git.patch | 220559 ++++++++++++++++++ recipes/linux/linux_2.6.28.bb | 17 +- 3 files changed, 222090 insertions(+), 1 deletion(-) create mode 100644 recipes/linux/linux-2.6.28/smartqv7/defconfig create mode 100644 recipes/linux/linux-2.6.28/smartqv7/smartqv7-git.patch diff --git a/recipes/linux/linux-2.6.28/smartqv7/defconfig b/recipes/linux/linux-2.6.28/smartqv7/defconfig new file mode 100644 index 0000000000..c9ba2f0323 --- /dev/null +++ b/recipes/linux/linux-2.6.28/smartqv7/defconfig @@ -0,0 +1,1515 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28 +# Tue Nov 10 14:34:35 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_SHMEM is not set +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_TCC=y + +# +# Boot options +# + +# +# Power management +# + +# +# TCC Core Type +# +CONFIG_ARCH_TCC8900=y +CONFIG_TCC_R_AX=y +# CONFIG_TCC_R_XX is not set + +# +# TCC Board Type +# +CONFIG_MACH_TCC8900=y +CONFIG_DRAM_DDR2=y +# CONFIG_DRAM_MDDR is not set +# CONFIG_RAM_128MB is not set +CONFIG_RAM_256MB=y +# CONFIG_HD720p_LEVEL41 is not set +# CONFIG_HD720p_LEVEL51 is not set +# CONFIG_HD1080p_LEVEL41 is not set +CONFIG_HD1080p_LEVEL51=y +CONFIG_TCC_STRING="tcc8900" + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=200 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_UNEVICTABLE_LRU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/ndda1 rw rootwait splash quiet" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set + +# +# Dynamic Power Management +# +CONFIG_DPM=y +CONFIG_DPM_PROCFS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_ADVANCED is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +CONFIG_NL80211=y +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_WIRELESS_EXT_SYSFS is not set +CONFIG_MAC80211=m + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +# CONFIG_IEEE80211_CRYPT_CCMP is not set +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=2 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_TCC_NAND_V6 is not set +CONFIG_TCC_NAND_V7=y +CONFIG_MISC_DEVICES=y +CONFIG_SMARTQV_ENCRYPT=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +CONFIG_MARVELL_8686_SDIO=m +CONFIG_MARVELL_8686_PROC_FS=y +CONFIG_MARVELL_8686_DEBUG=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +CONFIG_TOUCHSCREEN_TCCTS=y +# CONFIG_LCD01 is not set +# CONFIG_LCD11 is not set +CONFIG_LCD10=y +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_TCC=y +CONFIG_SERIAL_TCC_CONSOLE=y +# CONFIG_SERIAL_TCC_DMA is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_TCC_CKC_IOCTL=y +CONFIG_TCC_USER_INTR=y +CONFIG_TCC_BL=y +CONFIG_TCC_POWER_CTL=y +# CONFIG_LCD_4 is not set +CONFIG_LCD_7=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_TCC=y + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_TCC_I2C_WM8731 is not set +CONFIG_TCC_I2C_WM8987=y +CONFIG_TCC_I2C_PCA953X=y +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_TCC8900=y +CONFIG_FB_TCC_A070VW04=y +# CONFIG_FB_TCC_TD043MTEX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_LOGO=y +CONFIG_LOGO_CENTER=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_TCC_SOC=y +CONFIG_SND_TCC_SOC_I2S=y +# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set +# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set +CONFIG_SND_TCC_SOC_BOARD_WM8987=y +CONFIG_AUDIO_CODEC_PROCFS=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM8987=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m + +# +# Special HID drivers +# +# CONFIG_HID_COMPAT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BRIGHT is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DELL is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# Telechips DWC OTG Controller Drivers +# +CONFIG_TCC_DWC_OTG=m +CONFIG_TCC_DWC_OTG_DUAL_ROLE=y +# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set +# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set +# CONFIG_TCC_DWC_OTG_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_DPCM=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_OPTION=m +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +CONFIG_USB_GADGET_TCC_OTG=y +CONFIG_USB_TCC_OTG=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_TCC_SDHC=y +CONFIG_MMC_TCC_SDHC_CORE0=y +CONFIG_MMC_TCC_SDHC_CORE1=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_NEW_LEDS=y +# CONFIG_LEDS_CLASS is not set + +# +# LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_TCC=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="cp437" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_AUFS_FS=m +CONFIG_AUFS_BRANCH_MAX_127=y +# CONFIG_AUFS_BRANCH_MAX_511 is not set +# CONFIG_AUFS_BRANCH_MAX_1023 is not set +# CONFIG_AUFS_BRANCH_MAX_32767 is not set +CONFIG_AUFS_HINOTIFY=y +# CONFIG_AUFS_RDU is not set +# CONFIG_AUFS_SHWH is not set +# CONFIG_AUFS_BR_RAMFS is not set +# CONFIG_AUFS_DEBUG is not set +CONFIG_AUFS_BDEV_LOOP=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=m +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=m +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/recipes/linux/linux-2.6.28/smartqv7/smartqv7-git.patch b/recipes/linux/linux-2.6.28/smartqv7/smartqv7-git.patch new file mode 100644 index 0000000000..d077008ba0 --- /dev/null +++ b/recipes/linux/linux-2.6.28/smartqv7/smartqv7-git.patch @@ -0,0 +1,220559 @@ +diff --git a/Documentation/ABI/testing/debugfs-aufs b/Documentation/ABI/testing/debugfs-aufs +new file mode 100644 +index 0000000..4110b94 +--- /dev/null ++++ b/Documentation/ABI/testing/debugfs-aufs +@@ -0,0 +1,40 @@ ++What: /debug/aufs/si_/ ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ Under /debug/aufs, a directory named si_ is created ++ per aufs mount, where is a unique id generated ++ internally. ++ ++What: /debug/aufs/si_/xib ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ It shows the consumed blocks by xib (External Inode Number ++ Bitmap), its block size and file size. ++ When the aufs mount option 'noxino' is specified, it ++ will be empty. About XINO files, see ++ Documentation/filesystems/aufs/aufs.5 in detail. ++ ++What: /debug/aufs/si_/xino0, xino1 ... xinoN ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ It shows the consumed blocks by xino (External Inode Number ++ Translation Table), its link count, block size and file ++ size. ++ When the aufs mount option 'noxino' is specified, it ++ will be empty. About XINO files, see ++ Documentation/filesystems/aufs/aufs.5 in detail. ++ ++What: /debug/aufs/si_/xigen ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ It shows the consumed blocks by xigen (External Inode ++ Generation Table), its block size and file size. ++ If CONFIG_AUFS_EXPORT is disabled, this entry will not ++ be created. ++ When the aufs mount option 'noxino' is specified, it ++ will be empty. About XINO files, see ++ Documentation/filesystems/aufs/aufs.5 in detail. +diff --git a/Documentation/ABI/testing/sysfs-aufs b/Documentation/ABI/testing/sysfs-aufs +new file mode 100644 +index 0000000..ca49330 +--- /dev/null ++++ b/Documentation/ABI/testing/sysfs-aufs +@@ -0,0 +1,25 @@ ++What: /sys/fs/aufs/si_/ ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ Under /sys/fs/aufs, a directory named si_ is created ++ per aufs mount, where is a unique id generated ++ internally. ++ ++What: /sys/fs/aufs/si_/br0, br1 ... brN ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ It shows the abolute path of a member directory (which ++ is called branch) in aufs, and its permission. ++ ++What: /sys/fs/aufs/si_/xi_path ++Date: March 2009 ++Contact: J. R. Okajima ++Description: ++ It shows the abolute path of XINO (External Inode Number ++ Bitmap, Translation Table and Generation Table) file ++ even if it is the default path. ++ When the aufs mount option 'noxino' is specified, it ++ will be empty. About XINO files, see ++ Documentation/filesystems/aufs/aufs.5 in detail. +diff --git a/Makefile b/Makefile +index 71e98e9..1f805ad 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,7 +1,7 @@ + VERSION = 2 + PATCHLEVEL = 6 + SUBLEVEL = 28 +-EXTRAVERSION = ++#EXTRAVERSION = .10 + NAME = Erotic Pickled Herring + + # *DOCUMENTATION* +@@ -190,8 +190,10 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ + # Default value for CROSS_COMPILE is not to prefix executables + # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile + export KBUILD_BUILDHOST := $(SUBARCH) +-ARCH ?= $(SUBARCH) +-CROSS_COMPILE ?= ++ARCH ?= arm ++#CROSS_COMPILE ?= /opt/arm-2009q1/bin/arm-none-linux-gnueabi- ++CROSS_COMPILE ?= /opt/armv6/codesourcery/bin/arm-none-linux-gnueabi- ++#CROSS_COMPILE ?= /opt/codesourcery/bin/arm-none-linux-gnueabi- + + # Architecture as present in compile.h + UTS_MACHINE := $(ARCH) +@@ -338,9 +340,9 @@ LINUXINCLUDE := -Iinclude \ + + KBUILD_CPPFLAGS := -D__KERNEL__ $(LINUXINCLUDE) + ++#Debug KERNEL + KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ +- -fno-strict-aliasing -fno-common \ +- -Werror-implicit-function-declaration ++ -fno-strict-aliasing -fno-common + KBUILD_AFLAGS := -D__ASSEMBLY__ + + # Read KERNELRELEASE from include/config/kernel.release (if it exists) +@@ -521,6 +523,21 @@ ifneq (CONFIG_FRAME_WARN,0) + KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN}) + endif + ++ifeq ($(CONFIG_ARCH_TCC), y) ++# KBUILD_CFLAGS += -D_TCC_ -D_LINUX_ ++ KBUILD_CPPFLAGS += -D_TCC_ -D_LINUX_ ++ ARCH_DIR := $(TCC_STRING) ++endif ++ ++ifeq ($(CONFIG_TCC_R_AX), y) ++ KBUILD_CFLAGS += -DTCC_R_AX ++ KBUILD_CPPFLAGS += -DTCC_R_AX ++endif ++ifeq ($(CONFIG_TCC_R_XX), y) ++ KBUILD_CFLAGS += -DTCC_R_XX ++ KBUILD_CPPFLAGS += -DTCC_R_XX ++endif ++ + # Force gcc to behave correct even for buggy distributions + # Arch Makefiles may override this setting + KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector) +@@ -682,6 +699,7 @@ quiet_cmd_vmlinux__ ?= LD $@ + # Generate new vmlinux version + quiet_cmd_vmlinux_version = GEN .version + cmd_vmlinux_version = set -e; \ ++ if [ ! -d .svn ]; then\ + if [ ! -r .version ]; then \ + rm -f .version; \ + echo 1 >.version; \ +@@ -689,6 +707,9 @@ quiet_cmd_vmlinux_version = GEN .version + mv .version .old_version; \ + expr 0$$(cat .old_version) + 1 >.version; \ + fi; \ ++ else\ ++ echo $(shell svnversion -n .) >.version;\ ++ fi;\ + $(MAKE) $(build)=init + + # Generate System.map +@@ -1181,6 +1202,7 @@ $(clean-dirs): + $(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@) + + clean: archclean $(clean-dirs) ++ @rm -f linux.rom + $(call cmd,rmdirs) + $(call cmd,rmfiles) + @find . $(RCS_FIND_IGNORE) \ +@@ -1215,6 +1237,9 @@ distclean: mrproper + -o -name '.*.rej' -o -size 0 \ + -o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \ + -type f -print | xargs rm -f ++ @find $(srctree) $(RCS_FIND_IGNORE) \ ++ \( -name 'tcc' \) \ ++ -type l -print | xargs rm -f + + + # Packaging of the kernel to various formats +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 9722f8b..1ab1281 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -34,7 +34,7 @@ config SYS_SUPPORTS_APM_EMULATION + + config GENERIC_GPIO + bool +- default n ++ default y + + config GENERIC_TIME + bool +@@ -549,6 +549,12 @@ config ARCH_MSM + interface to the ARM9 modem processor which runs the baseband stack + and controls some vital subsystems (clock and power control, etc). + ++config ARCH_TCC ++ bool "Telechips TCC8900" ++ help ++ Support for the following Telechips TCC series SoCs: ++ TCC8900. ++ + endchoice + + source "arch/arm/mach-clps711x/Kconfig" +@@ -627,6 +633,10 @@ source "arch/arm/mach-ks8695/Kconfig" + + source "arch/arm/mach-msm/Kconfig" + ++if ARCH_TCC ++source "arch/arm/mach-tcc8900/Kconfig" ++endif ++ + # Definitions to make life easier + config ARCH_ACORN + bool +@@ -808,7 +818,7 @@ config HZ + default 200 if ARCH_EBSA110 || ARCH_S3C2410 + default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER + default AT91_TIMER_HZ if ARCH_AT91 +- default 100 ++ default 200 + + config AEABI + bool "Use the ARM EABI to compile the kernel" +@@ -1037,7 +1047,7 @@ endmenu + + menu "CPU Power Management" + +-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) ++if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || ARCH_TCC) + + source "drivers/cpufreq/Kconfig" + +@@ -1171,6 +1181,8 @@ menu "Power management options" + + source "kernel/power/Kconfig" + ++source "drivers/dpm/Kconfig" ++ + config ARCH_SUSPEND_POSSIBLE + def_bool y + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index bd6e281..79ec63c 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -94,6 +94,9 @@ CHECKFLAGS += -D__arm__ + head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o + textofs-y := 0x00008000 + ++ machine-$(CONFIG_ARCH_TCC) := tcc8900 ++ plat-$(CONFIG_ARCH_TCC) := tcc ++ textofs-$(CONFIG_ARCH_TCC) := 0x00100000 + machine-$(CONFIG_ARCH_RPC) := rpc + machine-$(CONFIG_ARCH_EBSA110) := ebsa110 + machine-$(CONFIG_ARCH_CLPS7500) := clps7500 +diff --git a/arch/arm/configs/SmartV5_defconfig b/arch/arm/configs/SmartV5_defconfig +new file mode 100644 +index 0000000..3968036 +--- /dev/null ++++ b/arch/arm/configs/SmartV5_defconfig +@@ -0,0 +1,1515 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Tue Nov 10 14:36:48 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_LOCK_KERNEL=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_SYSFS_DEPRECATED_V2 is not set ++CONFIG_RELAY=y ++# CONFIG_NAMESPACES is not set ++# CONFIG_BLK_DEV_INITRD is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_EMBEDDED=y ++# CONFIG_UID16 is not set ++CONFIG_SYSCTL_SYSCALL=y ++# CONFIG_KALLSYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++# CONFIG_BUG is not set ++# CONFIG_ELF_CORE is not set ++# CONFIG_COMPAT_BRK is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_SHMEM is not set ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_SLUB_DEBUG is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_TINY_SHMEM=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++CONFIG_DRAM_DDR2=y ++# CONFIG_DRAM_MDDR is not set ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++CONFIG_HD1080p_LEVEL51=y ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_PREEMPT=y ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/ndda1 rw rootwait splash quiet" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_TABLE=y ++# CONFIG_CPU_FREQ_DEBUG is not set ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_STAT_DETAILS is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_GOV_USERSPACE=m ++CONFIG_CPU_FREQ_GOV_ONDEMAND=m ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++CONFIG_BINFMT_MISC=m ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=m ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++# CONFIG_NETFILTER_ADVANCED is not set ++ ++# ++# Core Netfilter Configuration ++# ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NF_CONNTRACK is not set ++CONFIG_NETFILTER_XTABLES=m ++# CONFIG_NETFILTER_XT_TARGET_MARK is not set ++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++# CONFIG_NETFILTER_XT_MATCH_MARK is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++CONFIG_BT=m ++CONFIG_BT_L2CAP=m ++CONFIG_BT_SCO=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++ ++# ++# Bluetooth device drivers ++# ++CONFIG_BT_HCIBTUSB=m ++# CONFIG_BT_HCIBTSDIO is not set ++# CONFIG_BT_HCIUART is not set ++# CONFIG_BT_HCIBCM203X is not set ++# CONFIG_BT_HCIBPA10X is not set ++# CONFIG_BT_HCIBFUSB is not set ++# CONFIG_BT_HCIVHCI is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++# CONFIG_WIRELESS_OLD_REGULATORY is not set ++CONFIG_WIRELESS_EXT=y ++# CONFIG_WIRELESS_EXT_SYSFS is not set ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++# CONFIG_MAC80211_LEDS is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=m ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=y ++CONFIG_MISC_DEVICES=y ++CONFIG_SMARTQV_ENCRYPT=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=m ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=m ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++CONFIG_MARVELL_8686_PROC_FS=y ++CONFIG_MARVELL_8686_DEBUG=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC95XX=m ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_RNDIS_HOST=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++# CONFIG_WAN is not set ++CONFIG_PPP=m ++# CONFIG_PPP_MULTILINK is not set ++# CONFIG_PPP_FILTER is not set ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++# CONFIG_SLIP is not set ++CONFIG_SLHC=m ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++CONFIG_INPUT_MOUSE=y ++# CONFIG_MOUSE_PS2 is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_UINPUT=m ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++# CONFIG_SERIAL_TCC_DMA is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_TCC_POWER_CTL=y ++CONFIG_LCD_4=y ++# CONFIG_LCD_7 is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++# CONFIG_FB_TCC_A070VW04 is not set ++CONFIG_FB_TCC_TD043MTEX=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++CONFIG_LOGO_CENTER=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_DRIVERS is not set ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=m ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++CONFIG_USB_KBD=m ++CONFIG_USB_MOUSE=m ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BRIGHT is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DELL is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=m ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=m ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++CONFIG_USB_STORAGE_DATAFAB=y ++CONFIG_USB_STORAGE_FREECOM=y ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_DPCM=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++CONFIG_USB_STORAGE_ONETOUCH=y ++CONFIG_USB_STORAGE_KARMA=y ++CONFIG_USB_STORAGE_CYPRESS_ATACB=y ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_OPTION=m ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++CONFIG_MMC_TCC_SDHC_CORE1=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++CONFIG_FUSE_FS=m ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="cp437" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=m ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_AUFS_FS=m ++CONFIG_AUFS_BRANCH_MAX_127=y ++# CONFIG_AUFS_BRANCH_MAX_511 is not set ++# CONFIG_AUFS_BRANCH_MAX_1023 is not set ++# CONFIG_AUFS_BRANCH_MAX_32767 is not set ++CONFIG_AUFS_HINOTIFY=y ++# CONFIG_AUFS_RDU is not set ++# CONFIG_AUFS_SHWH is not set ++# CONFIG_AUFS_BR_RAMFS is not set ++# CONFIG_AUFS_DEBUG is not set ++CONFIG_AUFS_BDEV_LOOP=y ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++# CONFIG_NLS_ISO8859_1 is not set ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_DEBUG_USER is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=m ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=m ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=m ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=m ++CONFIG_CRC_CCITT=m ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=m ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=m ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/SmartV5_initramfs_defconfig b/arch/arm/configs/SmartV5_initramfs_defconfig +new file mode 100644 +index 0000000..5a44041 +--- /dev/null ++++ b/arch/arm/configs/SmartV5_initramfs_defconfig +@@ -0,0 +1,1471 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Mon Aug 17 16:10:25 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="../rootfs" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++CONFIG_HD1080p_LEVEL41=y ++# CONFIG_HD1080p_LEVEL51 is not set ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttySAC0,115200n8 rdinit=/sbin/init" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++CONFIG_MAC80211_LEDS=y ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=y ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++# CONFIG_MARVELL_8686_PROC_FS is not set ++# CONFIG_MARVELL_8686_DEBUG is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_LCD_4=y ++# CONFIG_LCD_7 is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++# CONFIG_FB_TCC_A070VW04 is not set ++CONFIG_FB_TCC_TD043MTEX=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/SmartV5_ramdisk_defconfig b/arch/arm/configs/SmartV5_ramdisk_defconfig +new file mode 100644 +index 0000000..3b3e147 +--- /dev/null ++++ b/arch/arm/configs/SmartV5_ramdisk_defconfig +@@ -0,0 +1,1469 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Thu Sep 17 18:45:58 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++CONFIG_HD1080p_LEVEL51=y ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="root=/dev/ram rw initrd=0x40700000,0x1000000 init=/linuxrc console=ttySAC0" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++CONFIG_MAC80211_LEDS=y ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=m ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++# CONFIG_MARVELL_8686_PROC_FS is not set ++# CONFIG_MARVELL_8686_DEBUG is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_LCD_4=y ++# CONFIG_LCD_7 is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++# CONFIG_FB_TCC_A070VW04 is not set ++CONFIG_FB_TCC_TD043MTEX=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_AUFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/SmartV7_defconfig b/arch/arm/configs/SmartV7_defconfig +new file mode 100644 +index 0000000..c9ba2f0 +--- /dev/null ++++ b/arch/arm/configs/SmartV7_defconfig +@@ -0,0 +1,1515 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Tue Nov 10 14:34:35 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_LOCK_KERNEL=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_SYSFS_DEPRECATED_V2 is not set ++CONFIG_RELAY=y ++# CONFIG_NAMESPACES is not set ++# CONFIG_BLK_DEV_INITRD is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_EMBEDDED=y ++# CONFIG_UID16 is not set ++CONFIG_SYSCTL_SYSCALL=y ++# CONFIG_KALLSYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++# CONFIG_BUG is not set ++# CONFIG_ELF_CORE is not set ++# CONFIG_COMPAT_BRK is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_SHMEM is not set ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_SLUB_DEBUG is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_TINY_SHMEM=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++CONFIG_DRAM_DDR2=y ++# CONFIG_DRAM_MDDR is not set ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++CONFIG_HD1080p_LEVEL51=y ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_PREEMPT=y ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttySAC0,115200n8 root=/dev/ndda1 rw rootwait splash quiet" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_TABLE=y ++# CONFIG_CPU_FREQ_DEBUG is not set ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_STAT_DETAILS is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_GOV_USERSPACE=m ++CONFIG_CPU_FREQ_GOV_ONDEMAND=m ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++CONFIG_BINFMT_MISC=m ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=m ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++# CONFIG_NETFILTER_ADVANCED is not set ++ ++# ++# Core Netfilter Configuration ++# ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NF_CONNTRACK is not set ++CONFIG_NETFILTER_XTABLES=m ++# CONFIG_NETFILTER_XT_TARGET_MARK is not set ++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++# CONFIG_NETFILTER_XT_MATCH_MARK is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++CONFIG_BT=m ++CONFIG_BT_L2CAP=m ++CONFIG_BT_SCO=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++ ++# ++# Bluetooth device drivers ++# ++CONFIG_BT_HCIBTUSB=m ++# CONFIG_BT_HCIBTSDIO is not set ++# CONFIG_BT_HCIUART is not set ++# CONFIG_BT_HCIBCM203X is not set ++# CONFIG_BT_HCIBPA10X is not set ++# CONFIG_BT_HCIBFUSB is not set ++# CONFIG_BT_HCIVHCI is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++# CONFIG_WIRELESS_OLD_REGULATORY is not set ++CONFIG_WIRELESS_EXT=y ++# CONFIG_WIRELESS_EXT_SYSFS is not set ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++# CONFIG_MAC80211_LEDS is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=m ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=y ++CONFIG_MISC_DEVICES=y ++CONFIG_SMARTQV_ENCRYPT=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=m ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=m ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++CONFIG_MARVELL_8686_PROC_FS=y ++CONFIG_MARVELL_8686_DEBUG=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC95XX=m ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_RNDIS_HOST=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++# CONFIG_WAN is not set ++CONFIG_PPP=m ++# CONFIG_PPP_MULTILINK is not set ++# CONFIG_PPP_FILTER is not set ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++# CONFIG_SLIP is not set ++CONFIG_SLHC=m ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ATKBD is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++CONFIG_INPUT_MOUSE=y ++# CONFIG_MOUSE_PS2 is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_UINPUT=m ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++# CONFIG_SERIAL_TCC_DMA is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_TCC_POWER_CTL=y ++# CONFIG_LCD_4 is not set ++CONFIG_LCD_7=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++CONFIG_FB_TCC_A070VW04=y ++# CONFIG_FB_TCC_TD043MTEX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++CONFIG_LOGO_CENTER=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_DRIVERS is not set ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=m ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++CONFIG_USB_KBD=m ++CONFIG_USB_MOUSE=m ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_BRIGHT is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DELL is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=m ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=m ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++CONFIG_USB_STORAGE_DATAFAB=y ++CONFIG_USB_STORAGE_FREECOM=y ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_DPCM=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++CONFIG_USB_STORAGE_ONETOUCH=y ++CONFIG_USB_STORAGE_KARMA=y ++CONFIG_USB_STORAGE_CYPRESS_ATACB=y ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_OPTION=m ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++CONFIG_MMC_TCC_SDHC_CORE1=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++CONFIG_FUSE_FS=m ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="cp437" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=m ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_AUFS_FS=m ++CONFIG_AUFS_BRANCH_MAX_127=y ++# CONFIG_AUFS_BRANCH_MAX_511 is not set ++# CONFIG_AUFS_BRANCH_MAX_1023 is not set ++# CONFIG_AUFS_BRANCH_MAX_32767 is not set ++CONFIG_AUFS_HINOTIFY=y ++# CONFIG_AUFS_RDU is not set ++# CONFIG_AUFS_SHWH is not set ++# CONFIG_AUFS_BR_RAMFS is not set ++# CONFIG_AUFS_DEBUG is not set ++CONFIG_AUFS_BDEV_LOOP=y ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++# CONFIG_NLS_ISO8859_1 is not set ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_DEBUG_USER is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=m ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=m ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=m ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=m ++CONFIG_CRC_CCITT=m ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=m ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=m ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/SmartV7_initramfs_defconfig b/arch/arm/configs/SmartV7_initramfs_defconfig +new file mode 100644 +index 0000000..500da3d +--- /dev/null ++++ b/arch/arm/configs/SmartV7_initramfs_defconfig +@@ -0,0 +1,1472 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Thu Aug 27 19:32:38 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="../rootfs" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++CONFIG_HD1080p_LEVEL41=y ++# CONFIG_HD1080p_LEVEL51 is not set ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttySAC0,115200n8 rdinit=/sbin/init" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++CONFIG_MAC80211_LEDS=y ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=y ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++# CONFIG_MARVELL_8686_PROC_FS is not set ++# CONFIG_MARVELL_8686_DEBUG is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++# CONFIG_LCD_4 is not set ++CONFIG_LCD_7=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++CONFIG_FB_TCC_A070VW04=y ++# CONFIG_FB_TCC_TD043MTEX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++CONFIG_HIDRAW=y ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++CONFIG_USB_HIDDEV=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_OPTION=m ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/SmartV7_ramdisk_defconfig b/arch/arm/configs/SmartV7_ramdisk_defconfig +new file mode 100644 +index 0000000..8956b6b +--- /dev/null ++++ b/arch/arm/configs/SmartV7_ramdisk_defconfig +@@ -0,0 +1,1469 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Thu Sep 17 18:15:58 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++CONFIG_HD1080p_LEVEL51=y ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="root=/dev/ram rw initrd=0x40700000,0x1000000 init=/linuxrc console=ttySAC0" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=m ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_MAC80211=m ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++CONFIG_MAC80211_LEDS=y ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++# CONFIG_IEEE80211_CRYPT_CCMP is not set ++# CONFIG_IEEE80211_CRYPT_TKIP is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_TCC_NAND_V6 is not set ++CONFIG_TCC_NAND_V7=m ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++CONFIG_MARVELL_8686_SDIO=m ++# CONFIG_MARVELL_8686_PROC_FS is not set ++# CONFIG_MARVELL_8686_DEBUG is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_KEYBOARD_GPIO=y ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++# CONFIG_LCD_4 is not set ++CONFIG_LCD_7=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=y ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_GPIO=y ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_TCC_I2C_WM8731 is not set ++CONFIG_TCC_I2C_WM8987=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++CONFIG_FB_TCC_A070VW04=y ++# CONFIG_FB_TCC_TD043MTEX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8731 is not set ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++CONFIG_SND_TCC_SOC_BOARD_WM8987=y ++CONFIG_AUDIO_CODEC_PROCFS=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8987=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_NEW_LEDS=y ++# CONFIG_LEDS_CLASS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++# CONFIG_LEDS_TRIGGER_TIMER is not set ++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_AUFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/tcc8900_defconfig b/arch/arm/configs/tcc8900_defconfig +new file mode 100644 +index 0000000..62b225b +--- /dev/null ++++ b/arch/arm/configs/tcc8900_defconfig +@@ -0,0 +1,1422 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Fri Sep 4 12:18:28 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++# CONFIG_GENERIC_GPIO is not set ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++CONFIG_DRAM_DDR2=y ++# CONFIG_DRAM_MDDR is not set ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++# CONFIG_HD720p_LEVEL41 is not set ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++CONFIG_HD1080p_LEVEL51=y ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="root=/dev/ram rw initrd=0x40700000,0x1000000 init=/linuxrc console=ttySAC0" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++CONFIG_BLK_DEV_IDECD=y ++CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y ++# CONFIG_BLK_DEV_IDETAPE is not set ++# CONFIG_BLK_DEV_IDESCSI is not set ++CONFIG_IDE_TASK_IOCTL=y ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++CONFIG_BLK_DEV_PLATFORM=y ++# CONFIG_BLK_DEV_PATA_TCC89X is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++CONFIG_ATA=y ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_SATA_PMP=y ++CONFIG_ATA_SFF=y ++# CONFIG_SATA_MV is not set ++CONFIG_SATA_TCC=y ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++CONFIG_LCD11=y ++# CONFIG_LCD10 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_TCC_POWER_CTL=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++CONFIG_TCC_I2C_WM8731=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++ ++# ++# Telechips GPSB (General Purpose Serial Bus) Controller Drivers ++# ++# CONFIG_SPI_TCC_MASTER is not set ++CONFIG_TSIF_TCC_SLAVE=y ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_TCC_SOC=y ++CONFIG_SND_TCC_SOC_I2S=y ++CONFIG_SND_TCC_SOC_BOARD_WM8731=y ++# CONFIG_SND_TCC_SOC_BOARD_WM8581 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8731=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/configs/tcc8900_wifi_defconfig b/arch/arm/configs/tcc8900_wifi_defconfig +new file mode 100644 +index 0000000..e2f4046 +--- /dev/null ++++ b/arch/arm/configs/tcc8900_wifi_defconfig +@@ -0,0 +1,1453 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28 ++# Wed Aug 5 16:39:32 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++# CONFIG_GENERIC_GPIO is not set ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++CONFIG_RELAY=y ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_KALLSYMS_EXTRA_PASS=y ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_ARCH_TCC=y ++ ++# ++# Boot options ++# ++ ++# ++# Power management ++# ++ ++# ++# TCC Core Type ++# ++CONFIG_ARCH_TCC8900=y ++CONFIG_TCC_R_AX=y ++# CONFIG_TCC_R_XX is not set ++ ++# ++# TCC Board Type ++# ++CONFIG_MACH_TCC8900=y ++# CONFIG_RAM_128MB is not set ++CONFIG_RAM_256MB=y ++CONFIG_DRAM_DDR2=y ++# CONFIG_DRAM_MDDR is not set ++CONFIG_HD720p_LEVEL41=y ++# CONFIG_HD720p_LEVEL51 is not set ++# CONFIG_HD1080p_LEVEL41 is not set ++# CONFIG_HD1080p_LEVEL51 is not set ++CONFIG_TCC_STRING="tcc8900" ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="root=/dev/ram rw initrd=0x40700000,0x1000000 init=/linuxrc console=ttySAC0" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++CONFIG_BINFMT_AOUT=y ++CONFIG_BINFMT_MISC=y ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_APM_EMULATION is not set ++ ++# ++# Dynamic Power Management ++# ++CONFIG_DPM=y ++CONFIG_DPM_PROCFS=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=y ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++CONFIG_TCP_MD5SIG=y ++# CONFIG_IPV6 is not set ++CONFIG_NETWORK_SECMARK=y ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++CONFIG_NETFILTER_ADVANCED=y ++ ++# ++# Core Netfilter Configuration ++# ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_XTABLES is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++# CONFIG_IP_NF_QUEUE is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++CONFIG_NET_SCHED=y ++ ++# ++# Queueing/Scheduling ++# ++# CONFIG_NET_SCH_CBQ is not set ++# CONFIG_NET_SCH_HTB is not set ++# CONFIG_NET_SCH_HFSC is not set ++# CONFIG_NET_SCH_PRIO is not set ++# CONFIG_NET_SCH_MULTIQ is not set ++# CONFIG_NET_SCH_RED is not set ++# CONFIG_NET_SCH_SFQ is not set ++# CONFIG_NET_SCH_TEQL is not set ++# CONFIG_NET_SCH_TBF is not set ++# CONFIG_NET_SCH_GRED is not set ++# CONFIG_NET_SCH_DSMARK is not set ++# CONFIG_NET_SCH_NETEM is not set ++ ++# ++# Classification ++# ++# CONFIG_NET_CLS_BASIC is not set ++# CONFIG_NET_CLS_TCINDEX is not set ++# CONFIG_NET_CLS_ROUTE4 is not set ++# CONFIG_NET_CLS_FW is not set ++# CONFIG_NET_CLS_U32 is not set ++# CONFIG_NET_CLS_RSVP is not set ++# CONFIG_NET_CLS_RSVP6 is not set ++# CONFIG_NET_CLS_FLOW is not set ++# CONFIG_NET_EMATCH is not set ++# CONFIG_NET_CLS_ACT is not set ++CONFIG_NET_SCH_FIFO=y ++ ++# ++# Network testing ++# ++CONFIG_NET_PKTGEN=y ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=y ++CONFIG_NL80211=y ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++CONFIG_MAC80211=y ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++# CONFIG_MAC80211_RC_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT_PID=y ++# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set ++CONFIG_MAC80211_RC_DEFAULT="pid" ++# CONFIG_MAC80211_MESH is not set ++# CONFIG_MAC80211_LEDS is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_IEEE80211=y ++CONFIG_IEEE80211_DEBUG=y ++CONFIG_IEEE80211_CRYPT_WEP=y ++CONFIG_IEEE80211_CRYPT_CCMP=y ++CONFIG_IEEE80211_CRYPT_TKIP=y ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++CONFIG_DEBUG_DEVRES=y ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=16384 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=y ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8187 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++CONFIG_TOUCHSCREEN_TCCTS=y ++# CONFIG_LCD01 is not set ++# CONFIG_LCD11 is not set ++CONFIG_LCD10=y ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_TCC=y ++CONFIG_SERIAL_TCC_CONSOLE=y ++CONFIG_SERIAL_TCC_DMA=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_TCC_CKC_IOCTL=y ++CONFIG_TCC_USER_INTR=y ++CONFIG_TCC_BL=y ++CONFIG_TCC_POWER_CTL=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++CONFIG_I2C_TCC=y ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++CONFIG_TCC_I2C_WM8731=y ++CONFIG_TCC_I2C_PCA953X=y ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_TCC_MASTER is not set ++CONFIG_TSIF_TCC_SLAVE=y ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_FB_TCC8900=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_COMPAT=y ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_SUSPEND=y ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# Telechips DWC OTG Controller Drivers ++# ++CONFIG_TCC_DWC_OTG=y ++CONFIG_TCC_DWC_OTG_DUAL_ROLE=y ++# CONFIG_TCC_DWC_OTG_DEVICE_ONLY is not set ++# CONFIG_TCC_DWC_OTG_HOST_ONLY is not set ++# CONFIG_TCC_DWC_OTG_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++CONFIG_USB_GADGET_TCC_OTG=y ++CONFIG_USB_TCC_OTG=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++CONFIG_MMC_DEBUG=y ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++CONFIG_MMC_TCC_SDHC=y ++CONFIG_MMC_TCC_SDHC_CORE0=y ++# CONFIG_MMC_TCC_SDHC_CORE1 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++CONFIG_RTC_INTF_DEV_UIE_EMUL=y ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_TCC=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++# CONFIG_EXT2_FS_POSIX_ACL is not set ++# CONFIG_EXT2_FS_SECURITY is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_DNOTIFY is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++CONFIG_JOLIET=y ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_ERRORS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_MICHAEL_MIC=y ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y +diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h +index 39d949b..ecab89b 100644 +--- a/arch/arm/include/asm/mach/map.h ++++ b/arch/arm/include/asm/mach/map.h +@@ -26,6 +26,7 @@ struct map_desc { + #define MT_HIGH_VECTORS 8 + #define MT_MEMORY 9 + #define MT_ROM 10 ++#define MT_MEMORY_TCC 11 + + #ifdef CONFIG_MMU + extern void iotable_init(struct map_desc *, int); +diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h +index b2cc1fc..880b390 100644 +--- a/arch/arm/include/asm/mach/time.h ++++ b/arch/arm/include/asm/mach/time.h +@@ -41,8 +41,31 @@ struct sys_timer { + #ifndef CONFIG_GENERIC_TIME + unsigned long (*offset)(void); + #endif ++#ifdef CONFIG_NO_IDLE_HZ ++ struct dyn_tick_timer *dyn_tick; ++#endif ++}; ++ ++#ifdef CONFIG_NO_IDLE_HZ ++ ++#define DYN_TICK_ENABLED (1 << 1) ++ ++struct dyn_tick_timer { ++ spinlock_t lock; ++ unsigned int state; /* Current state */ ++ int (*enable)(void); /* Enables dynamic tick */ ++ int (*disable)(void); /* Disables dynamic tick */ ++ void (*reprogram)(unsigned long); /* Reprograms the timer */ ++ int (*handler)(int, void *); + }; + ++void timer_dyn_reprogram(void); ++#else ++#define timer_dyn_reprogram() do { } while (0) ++#endif ++ ++ ++ + extern struct sys_timer *system_timer; + extern void timer_tick(void); + +diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S +index 21e17dc..6e493dc 100644 +--- a/arch/arm/kernel/head.S ++++ b/arch/arm/kernel/head.S +@@ -1,9 +1,13 @@ + /* + * linux/arch/arm/kernel/head.S + * +- * Copyright (C) 1994-2002 Russell King +- * Copyright (c) 2003 ARM Limited +- * All Rights Reserved ++ * Author: ++ * Modified: 10th Jun, 2009 ++ * ++ * Copyright (C) 1994-2002 Russell King ++ * Copyright (c) 2003 ARM Limited ++ * Copyright (C) 2008-2009 Telechips ++ * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -38,7 +42,7 @@ + * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. + */ + #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 +-#error KERNEL_RAM_VADDR must start at 0xXXXX8000 ++@#error KERNEL_RAM_VADDR must start at 0xXXXX8000 + #endif + + .globl swapper_pg_dir +@@ -76,15 +80,71 @@ + */ + .section ".text.head", "ax" + ENTRY(stext) ++ b __startup__ ++ ++ /* ++ ************************************************************************* ++ * Telechips data ++ ************************************************************************* ++ */ ++ .word 0xffff0106 /* HardwareID */ ++ FirmwareVersion: ++ .word 0x3A726556 /* Ver: */ ++ .word 0x34333231 /* 1234 */ ++ FirmwareCheckSum: ++ .word 0x00000000 /* Firmware CRC32 Value Until 128Kbyte */ ++ DACVersion: ++ .word 0x00000000 /* Not Used Area - Reserved */ ++ FirmwareCheckSumEnd: ++ .word 0x00000000 /* Firmware CRC32 Value From 128Kbye to End */ ++ FirmwareSize: ++ .word 0x00000000 /* Firmware Total Size */ ++ SerialNumber: ++ .word 0x00000000 /* SN[3:0] */ ++ .word 0x00000000 /* SN[7:4] */ ++ .word 0x00000000 /* SN[11:8] */ ++ .word 0x00000000 /* SN[15:12] */ ++ .word 0x00000000 /* SN[19:16] */ ++ .word 0x00000000 /* SN[23:20] */ ++ .word 0x00000000 /* SN[27:24] */ ++ .word 0x00000000 /* SN[31:28] */ ++ .word 0x00000000 /* SN[35:32] */ ++ .word 0x00000000 /* SN[39:36] */ ++ .word 0x00000000 /* SN[43:40] */ ++ .word 0x00000000 /* SN[47:44] */ ++ .word 0x00000000 /* SN[51:48] */ ++ .word 0x00000000 /* SN[55:52] */ ++ .word 0x00000000 /* SN[59:56] */ ++ .word 0x00000000 /* SN[63:60] */ ++ ++__startup__: + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode + @ and irqs disabled + mrc p15, 0, r9, c0, c0 @ get processor id + bl __lookup_processor_type @ r5=procinfo r9=cpuid + movs r10, r5 @ invalid processor (r5=0)? + beq __error_p @ yes, error 'p' ++ ++ mov r0, r9 @ print CPU_TYPE ++@ bl printhex8 ++ mov r0, #',' ++@ bl printch ++ ++#if defined(CONFIG_MACH_TCC8900) ++ ldr r1, =0xfa0 @ Machine type = TCC8900 , actually this value should comes from bootloader ++#elif defined(CONFIG_MACH_TCC9100) ++ ldr r1, =0xfa1 @ Machine type = TCC9100 ++#elif defined(CONFIG_MACH_TCC9200) ++ ldr r1, =0xfa2 @ Machine type = TCC9200 ++#endif ++ + bl __lookup_machine_type @ r5=machinfo + movs r8, r5 @ invalid machine (r5=0)? + beq __error_a @ yes, error 'a' ++ ++ movs r0, r5 @ print MACH_TYPE ++@ bl printhex8 ++ + bl __vet_atags + bl __create_page_tables + +diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c +index 2f3eb79..4e566e4 100644 +--- a/arch/arm/kernel/irq.c ++++ b/arch/arm/kernel/irq.c +@@ -109,10 +109,13 @@ static struct irq_desc bad_irq_desc = { + * come via this function. Instead, they should provide their + * own 'handler' + */ ++extern inline void arch_idle_off(void); + asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) + { + struct pt_regs *old_regs = set_irq_regs(regs); + ++ arch_idle_off(); ++ + irq_enter(); + + /* +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +index 1f1eecc..949813a 100644 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -673,11 +673,44 @@ static int __init customize_machine(void) + } + arch_initcall(customize_machine); + ++unsigned int TCC_VPU_SIZE; ++EXPORT_SYMBOL(TCC_VPU_SIZE); ++ + void __init setup_arch(char **cmdline_p) + { + struct tag *tags = (struct tag *)&init_tags; + struct machine_desc *mdesc; + char *from = default_command_line; ++ ++ /* ++ * Telechips Board Memory Setting ++ * - refer to arch/arm/mach-tcc8900/include/mach/memory.h ++ */ ++ unsigned long mem_flag = *(volatile unsigned long *)(phys_to_virt(0x40200000)); ++ printk(KERN_ERR "mem_flag = %d\n", mem_flag); ++ switch(mem_flag) { ++ case 0: ++ strcat(default_command_line, " mem=214M"); ++ TCC_VPU_SIZE = 24; ++ break; ++ case 1: ++ strcat(default_command_line, " mem=188M"); ++ TCC_VPU_SIZE = 50; ++ break; ++ case 2: ++ strcat(default_command_line, " mem=138M"); ++ TCC_VPU_SIZE = 100; ++ break; ++ case 3: ++ strcat(default_command_line, " mem=194M"); ++ TCC_VPU_SIZE = 44; ++ break; ++ default: ++ printk(KERN_NOTICE "mem_flag was setted wrong\n"); ++ strcat(default_command_line, " mem=214M"); ++ TCC_VPU_SIZE = 24; ++ break; ++ } + + setup_processor(); + mdesc = setup_machine(machine_arch_type); +@@ -831,7 +864,13 @@ static int c_show(struct seq_file *m, void *v) + seq_puts(m, "\n"); + + seq_printf(m, "Hardware\t: %s\n", machine_name); ++#if defined(CONFIG_TCC_R_AX) ++ seq_printf(m, "Revision\t: %s\n", "AX"); ++#elif defined(CONFIG_TCC_R_XX) ++ seq_printf(m, "Revision\t: %s\n", "XX"); ++#else + seq_printf(m, "Revision\t: %04x\n", system_rev); ++#endif + seq_printf(m, "Serial\t\t: %08x%08x\n", + system_serial_high, system_serial_low); + +diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c +index c68b44a..126e645 100644 +--- a/arch/arm/kernel/time.c ++++ b/arch/arm/kernel/time.c +@@ -367,6 +367,108 @@ static struct sysdev_class timer_sysclass = { + .resume = timer_resume, + }; + ++#ifdef CONFIG_NO_IDLE_HZ ++static int timer_dyn_tick_enable(void) ++{ ++ struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; ++ unsigned long flags; ++ int ret = -ENODEV; ++ ++ if (dyn_tick) { ++ spin_lock_irqsave(&dyn_tick->lock, flags); ++ ret = 0; ++ if (!(dyn_tick->state & DYN_TICK_ENABLED)) { ++ ret = dyn_tick->enable(); ++ ++ if (ret == 0) ++ dyn_tick->state |= DYN_TICK_ENABLED; ++ } ++ spin_unlock_irqrestore(&dyn_tick->lock, flags); ++ } ++ ++ return ret; ++} ++ ++static int timer_dyn_tick_disable(void) ++{ ++ struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; ++ unsigned long flags; ++ int ret = -ENODEV; ++ ++ if (dyn_tick) { ++ spin_lock_irqsave(&dyn_tick->lock, flags); ++ ret = 0; ++ if (dyn_tick->state & DYN_TICK_ENABLED) { ++ ret = dyn_tick->disable(); ++ ++ if (ret == 0) ++ dyn_tick->state &= ~DYN_TICK_ENABLED; ++ } ++ spin_unlock_irqrestore(&dyn_tick->lock, flags); ++ } ++ ++ return ret; ++} ++ ++/* ++ * Reprogram the system timer for at least the calculated time interval. ++ * This function should be called from the idle thread with IRQs disabled, ++ * immediately before sleeping. ++ */ ++void timer_dyn_reprogram(void) ++{ ++ struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; ++ unsigned long next, seq, flags; ++ ++ if (!dyn_tick) ++ return; ++ ++ spin_lock_irqsave(&dyn_tick->lock, flags); ++ if (dyn_tick->state & DYN_TICK_ENABLED) { ++ next = next_timer_interrupt(); ++ do { ++ seq = read_seqbegin(&xtime_lock); ++ dyn_tick->reprogram(next - jiffies); ++ } while (read_seqretry(&xtime_lock, seq)); ++ } ++ spin_unlock_irqrestore(&dyn_tick->lock, flags); ++} ++ ++static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf) ++{ ++ return sprintf(buf, "%i\n", ++ (system_timer->dyn_tick->state & DYN_TICK_ENABLED) >> 1); ++} ++ ++static ssize_t timer_set_dyn_tick(struct sys_device *dev, const char *buf, ++ size_t count) ++{ ++ unsigned int enable = simple_strtoul(buf, NULL, 2); ++ ++ if (enable) ++ timer_dyn_tick_enable(); ++ else ++ timer_dyn_tick_disable(); ++ ++ return count; ++} ++static SYSDEV_ATTR(dyn_tick, 0644, timer_show_dyn_tick, timer_set_dyn_tick); ++ ++/* ++ * dyntick=enable|disable ++ */ ++static char dyntick_str[4] __initdata = ""; ++ ++static int __init dyntick_setup(char *str) ++{ ++ if (str) ++ strlcpy(dyntick_str, str, sizeof(dyntick_str)); ++ return 1; ++} ++ ++__setup("dyntick=", dyntick_setup); ++#endif ++ + static int __init timer_init_sysfs(void) + { + int ret = sysdev_class_register(&timer_sysclass); +@@ -374,6 +476,18 @@ static int __init timer_init_sysfs(void) + system_timer->dev.cls = &timer_sysclass; + ret = sysdev_register(&system_timer->dev); + } ++#ifdef CONFIG_NO_IDLE_HZ ++ if (ret == 0 && system_timer->dyn_tick) { ++ ret = sysdev_create_file(&system_timer->dev, &attr_dyn_tick); ++ ++ /* ++ * Turn on dynamic tick after calibrate delay ++ * for correct bogomips ++ */ ++ if (ret == 0 && dyntick_str[0] == 'e') ++ ret = timer_dyn_tick_enable(); ++ } ++#endif + + return ret; + } +diff --git a/arch/arm/mach-tcc8900/Kconfig b/arch/arm/mach-tcc8900/Kconfig +new file mode 100644 +index 0000000..5649917 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/Kconfig +@@ -0,0 +1,107 @@ ++# arch/arm/mach-tcc8900/Kconfig ++# Copyright 2009 Telechips ++# License under GPLv2 ++ ++comment "TCC Core Type" ++ depends on ARCH_TCC ++ ++config ARCH_TCC8900 ++ bool "TCC Based System" ++ depends on ARCH_TCC ++ ++choice ++ prompt "TCC Revision type" ++ depends on ARCH_TCC8900 ++ default TCC_R_AX ++ help ++ Select Revision type ++config TCC_R_AX ++ bool "Revision AX" ++ depends on ARCH_TCC && ARCH_TCC8900 ++config TCC_R_XX ++ bool "Revision XX" ++ depends on ARCH_TCC && ARCH_TCC8900 ++endchoice ++ ++ ++comment "TCC Board Type" ++ depends on ARCH_TCC && ARCH_TCC8900 ++ ++config MACH_TCC8900 ++ bool "TCC8900" ++ depends on ARCH_TCC && ARCH_TCC8900 ++ default y ++ help ++ Support for the TCC8900 demo board, Say Y here if you ++ have such a device. ++ ++choice ++ prompt "DRAM Type" ++ depends on ARCH_TCC8900 ++ default DRAM_DDR2 ++ help ++ Select DRAM Type ++config DRAM_DDR2 ++ bool "DRAM_DDR2" ++ help ++ Select DRAM DDR2 ++config DRAM_MDDR ++ bool "DRAM_MDDR" ++ help ++ Select DRAM MDDR ++endchoice ++ ++ ++choice ++ prompt "RAM Size" ++ depends on ARCH_TCC8900 ++ default RAM_256MB ++ help ++ Select DRAM Spec ++config RAM_128MB ++ bool "128MB" ++ help ++ Select DRAM size 128MB ++config RAM_256MB ++ bool "256MB" ++ depends on DRAM_DDR2 ++ help ++ Select DRAM size 256MB ++endchoice ++ ++ ++choice ++ prompt "HD Spec" ++ depends on ARCH_TCC8900 ++ default HD1080p_LEVEL51 ++ help ++ Select HD and LEVEL spec ++config HD720p_LEVEL41 ++ bool "HD720p_LEVEL41" ++ help ++ Select HD720p and LEVEL 4.1 ++config HD720p_LEVEL51 ++ bool "HD720p_LEVEL51" ++ help ++ Select HD720p and LEVEL 5.1 ++config HD1080p_LEVEL41 ++ bool "HD1080p_LEVEL41" ++ help ++ Select HD1080p and LEVEL 4.1 ++config HD1080p_LEVEL51 ++ bool "HD1080p_LEVEL51" ++ depends on RAM_256MB ++ help ++ Select HD1080p and LEVEL 5.1 ++endchoice ++ ++ ++config TCC_STRING ++ string "Default dir name" ++ depends on ARCH_TCC8900 ++ default "tcc8900" ++ help ++ "tcc8900" ++ Default dir name for MACH_TCC8900 ++ Don't edit!!! ++ +diff --git a/arch/arm/mach-tcc8900/Makefile b/arch/arm/mach-tcc8900/Makefile +new file mode 100644 +index 0000000..97c5099 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/Makefile +@@ -0,0 +1,53 @@ ++# ++# Makefile for the linux kernel. ++# ++# Common support ++obj-$(CONFIG_ARCH_TCC) += io.o irq.o devices.o time.o tca_ckc.o idle.o gpio.o ++ ++# Specific board support ++obj-$(CONFIG_MACH_TCC8900) += board-tcc8900.o ++ ++ ++ifeq ($(CONFIG_ARCH_TCC),y) ++$(shell ln -fsn $(CONFIG_TCC_STRING) $(srctree)/arch/arm/mach-tcc8900/tcc) ++endif ++ ++ifeq ($(CONFIG_DRAM_DDR2), y) ++file_1 = tcc_ckcddr2_141to190.c ++file_2 = tcc_ckcddr2_200to290.c ++file_3 = tcc_ckcddr2_300to330.c ++tmp_file = tcc_ckcddr2.newfile ++endif ++ifeq ($(CONFIG_DRAM_MDDR), y) ++file_1 = tcc_ckcmddr_100to160.c ++file_2 = tcc_ckcmddr_20to90.c ++tmp_file = tcc_ckcmddr.newfile ++endif ++ ++from_str ='0xB' ++to_str ='0xF' ++ ++ifeq ($(CONFIG_DRAM_DDR2), y) ++$(shell sed 's/${from_str}/${to_str}/g' $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_1) > $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file}) ++$(shell mv -f $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file} $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_1)) ++$(shell sed 's/${from_str}/${to_str}/g' $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_2) > $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file}) ++$(shell mv -f $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file} $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_2)) ++$(shell sed 's/${from_str}/${to_str}/g' $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_3) > $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file}) ++$(shell mv -f $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file} $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_3)) ++endif ++ifeq ($(CONFIG_DRAM_MDDR), y) ++$(shell sed 's/${from_str}/${to_str}/g' $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_1) > $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file}) ++$(shell mv -f $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file} $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_1)) ++$(shell sed 's/${from_str}/${to_str}/g' $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_2) > $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file}) ++$(shell mv -f $(srctree)/arch/arm/mach-tcc8900/tcc/${tmp_file} $(srctree)/arch/arm/mach-tcc8900/tcc/$(file_2)) ++endif ++ ++ifeq ($(CONFIG_DRAM_DDR2), y) ++obj-$(CONFIG_ARCH_TCC) += tcc_ckc_ctrl.o tcc/arm_ioctlutil.o tcc/tcc_ckcddr2_141to190.o tcc/tcc_ckcddr2_200to290.o tcc/tcc_ckcddr2_300to330.o ++endif ++ifeq ($(CONFIG_DRAM_MDDR), y) ++obj-$(CONFIG_ARCH_TCC) += tcc_ckc_ctrl.o tcc/arm_ioctlutil.o tcc/tcc_ckcmddr_100to160.o tcc/tcc_ckcmddr_20to90.o ++endif ++ ++obj-$(CONFIG_PM) += pm.o pm_asm.o ++ +diff --git a/arch/arm/mach-tcc8900/Makefile.boot b/arch/arm/mach-tcc8900/Makefile.boot +new file mode 100644 +index 0000000..dd6c7a8 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/Makefile.boot +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x10008000 ++params_phys-y := 0x10000100 ++initrd_phys-y := 0x10800000 +diff --git a/arch/arm/mach-tcc8900/board-tcc8900.c b/arch/arm/mach-tcc8900/board-tcc8900.c +new file mode 100644 +index 0000000..638d63d +--- /dev/null ++++ b/arch/arm/mach-tcc8900/board-tcc8900.c +@@ -0,0 +1,98 @@ ++/* lnux/arch/arm/mach-tcc8900/board-tcc8900.c ++ * ++ * Author: ++ * Created: 10th Feb, 2009 ++ * Description: ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++extern void __init tcc8900_irq_init(void); ++extern void __init tcc8900_map_common_io(void); ++ ++ ++static struct spi_board_info tcc8900_spi0_board_info[] = { ++ { ++ .modalias = "spidev", ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 40 * 1000 * 1000, ++ }, ++}; ++ ++static struct spi_board_info tcc8900_spi1_board_info[] = { ++ { ++ .modalias = "spidev", ++ .bus_num = 1, ++ .chip_select = 0, ++ .max_speed_hz = 40 * 1000 * 1000, ++ }, ++}; ++ ++static struct i2c_board_info __initdata tcc8900_i2c_board_info[] = { ++ { ++// I2C_BOARD_INFO("tps65011", 0x48), ++// .type = "", ++// .addr = 0xff, ++// .irq = IRQ_EINT20, ++ } ++}; ++ ++static void tcc8900_power_off(void) ++{ ++ gpio_direction_output(GPIO_SPEAKER_EN, 0); ++ gpio_direction_output(GPIO_PWR_EN, 0); ++} ++ ++static void __init tcc8900_map_io(void) ++{ ++ pm_power_off = tcc8900_power_off; ++ tcc8900_map_common_io(); ++ tcc8902_pm_init(); ++} ++ ++static void __init tcc8900_init_irq(void) ++{ ++ tcc8900_irq_init(); ++// tcc8900_gpio_init(); ++} ++ ++static void __init tcc8900_init_machine(void) ++{ ++ spi_register_board_info(tcc8900_spi0_board_info, ARRAY_SIZE(tcc8900_spi0_board_info)); ++ spi_register_board_info(tcc8900_spi1_board_info, ARRAY_SIZE(tcc8900_spi1_board_info)); ++ i2c_register_board_info(-1, tcc8900_i2c_board_info, ARRAY_SIZE(tcc8900_i2c_board_info)); ++} ++ ++MACHINE_START(TCC8900, "Telechips TCC8900 Demo Board") ++ /* Maintainer: Telechips Linux BSP Team */ ++ .phys_io = 0xf0000000, ++ .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, ++ .boot_params = PHYS_OFFSET + 0x00000100, ++ .map_io = tcc8900_map_io, ++ .init_irq = tcc8900_init_irq, ++ .init_machine = tcc8900_init_machine, ++ .timer = &tcc8900_timer, ++MACHINE_END +diff --git a/arch/arm/mach-tcc8900/devices.c b/arch/arm/mach-tcc8900/devices.c +new file mode 100644 +index 0000000..51068f0 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/devices.c +@@ -0,0 +1,861 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/devices.c ++ * ++ * Author: ++ * Created: 10th Feb, 2009 ++ * Description: ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/*---------------------------------------------------------------------- ++ * Device : Touch Driver resource ++ * Description: tcc8900_touch_resources ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_TOUCHSCREEN_TCCTS) || defined(CONFIG_TOUCHSCREEN_TCCTS_MODULE) ++static struct resource tcc8900_touch_resources[] = { ++ [0] = { ++ .start = 0xF05F4000, ++ .end = 0xF05F4000 + 0x20, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_TSADC, ++ .end = INT_TSADC, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = INT_EI2, ++ .end = INT_EI2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_touchscreen_device = { ++ .name = "tcc-ts", ++ .id = -1, ++ .resource = tcc8900_touch_resources, ++ .num_resources = ARRAY_SIZE(tcc8900_touch_resources), ++}; ++ ++static inline void tcc8900_init_touch_ts(void) ++{ ++ platform_device_register(&tcc8900_touchscreen_device); ++} ++#endif /* CONFIG_TOUCHSCREEN_TCCTS */ ++ ++static struct platform_device hhtech_gpio_device = { ++ .name = "hhtech_gpio", ++ .id = -1, ++ .resource = NULL, ++ .num_resources = 0, ++}; ++ ++static inline void tcc8900_init_hhtech_gpio(void) ++{ ++ platform_device_register(&hhtech_gpio_device); ++} ++ ++/*---------------------------------------------------------------------- ++ * Device : DM9000 resource ++ * Description: tcc8900_dm9000_resources ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_TCC_DM9000) || defined(CONFIG_TCC_DM9000_MODULE) ++static struct resource tcc8900_dm9000_resource[] = { ++ [0] = { ++ .start = (0xF05C0000), ++ .end = (0xF05C0000)+ 0x3, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = (0xF05C0000)+ 0x4, ++ .end = (0xF05C0000)+ 0x4 + 0x3f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = INT_EI4, ++ .end = INT_EI4, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, ++ } ++ ++}; ++ ++/* for the moment we limit ourselves to 16bit IO until some ++ * better IO routines can be written and tested ++*/ ++static struct dm9000_plat_data bast_dm9000_platdata = { ++ .flags = DM9000_PLATF_8BITONLY, ++}; ++ ++static struct platform_device tcc8900_dm9000_device = { ++ .name = "dm9000", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(tcc8900_dm9000_resource), ++ .resource = tcc8900_dm9000_resource, ++ .dev = { ++ .platform_data = &bast_dm9000_platdata, ++ } ++}; ++ ++static inline void tcc8900_init_dm9000(void) ++{ ++ platform_device_register(&tcc8900_dm9000_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : DM9000 resource ++ * Description: tcc8900_dm9ks_resources ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_DM9KS) || defined(CONFIG_DM9KS_MODULE) ++static struct platform_device tcc8900_dm9ks_device = { ++ .name = "dm9ks", ++ .id = -1, ++}; ++ ++static inline void tcc8900_init_dm9ks(void) ++{ ++ platform_device_register(&tcc8900_dm9ks_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : RTC resource ++ * Description: tcc8900_rtc_resources ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_RTC_DRV_TCC) || defined(CONFIG_RTC_DRV_TCC_MODULE) ++static struct resource tcc8900_rtc_resource[] = { ++ [0] = { ++ .start = 0xF05F2000, ++ .end = 0xF05F20FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_RTC, ++ .end = INT_RTC, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device tcc8900_rtc_device = { ++ .name = "tcc-rtc", ++ .id = -1, ++ .resource = tcc8900_rtc_resource, ++ .num_resources = ARRAY_SIZE(tcc8900_rtc_resource), ++ .dev = { ++ .platform_data = NULL, ++ } ++}; ++ ++static inline void tcc8900_init_rtc(void) ++{ ++ platform_device_register(&tcc8900_rtc_device); ++} ++#endif /* CONFIG_RTC_DRV_TCC */ ++ ++ ++#if defined(CONFIG_I2C_TCC) || defined(CONFIG_I2C_TCC_MODULE) ++/*---------------------------------------------------------------------- ++ * Device : I2C resource ++ * Description: tcc8900_i2c_resources has master0 and master1 ++ *----------------------------------------------------------------------*/ ++static struct resource tcc8900_i2c_resources[] = { ++ [0] = { ++ .start = 0xF0530000, /* I2C master ch0 base address */ ++ .end = 0xF0530040, /* I2C master ch1 base address */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = 50, /* I2C ch0 50Kbps */ ++ .end = 50, /* I2C ch1 50Kbps */ ++ .flags = IORESOURCE_MEM, ++ }, ++// [1] = { ++// .start = INT_I2C, /* I2C master ch[0,1] irq number */ ++// .end = INT_I2C, /* I2C ch1 irq number */ ++// .flags = IORESOURCE_IRQ, ++// }, ++ ++ /* SMU_I2C */ ++ [2] = { ++ .start = 0xF0405000, /* SMU_I2C master ch0 SATA-PHY base address */ ++ .end = 0xF0405040, /* SMU_I2C master ch1 HDMI-PHY base address */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [3] = { ++ .start = 100, /* SMU_I2C ch0 100Kbps */ ++ .end = 100, /* SMU_I2C ch1 100Kbps */ ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device tcc8900_i2c_device = { ++ .name = "tcc-i2c", ++ .id = -1, ++ .resource = tcc8900_i2c_resources, ++ .num_resources = ARRAY_SIZE(tcc8900_i2c_resources), ++}; ++ ++static inline void tcc8900_init_i2c(void) ++{ ++ platform_device_register(&tcc8900_i2c_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : I2C GPIO resource ++ * Description: ++ *----------------------------------------------------------------------*/ ++ ++#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) ++static struct i2c_gpio_platform_data pdata = { ++ .sda_pin = TCC_GPD6, ++ .sda_is_open_drain = 0, ++ .scl_pin = TCC_GPD5, ++ .scl_is_open_drain = 0, ++ .udelay = 50, /* ~100 kHz */ ++}; ++ ++static struct platform_device tcc8900_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 4, ++ .dev.platform_data = &pdata, ++}; ++ ++static void tcc8900_init_i2c_gpio() ++{ ++ platform_device_register(&tcc8900_i2c_gpio_device); ++} ++#endif ++ ++/*---------------------------------------------------------------------- ++ * Device : LCD Frame Buffer resource ++ * Description: ++ *----------------------------------------------------------------------*/ ++static u64 tcc8900_device_lcd_dmamask = 0xffffffffUL; ++struct platform_device tcc8900_lcd_device = { ++ .name = "tccxxx-lcd", ++ .id = -1, ++ .dev = { ++ .dma_mask = &tcc8900_device_lcd_dmamask, ++// .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++static inline void tcc8900_init_lcd(void) ++{ ++ platform_device_register(&tcc8900_lcd_device); ++} ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : Serial-ATA resource ++ * Description: ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_SATA_TCC) || defined(CONFIG_SATA_TCC_MODULE) ++static struct resource sata_resources[] = { ++ [0] = { ++ .start = 0xF0560000, ++ .end = 0xF0560800, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_SATA, ++ .end = INT_SATA, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_sata_device = { ++ .name = "tcc-sata", ++ .id = 0, ++ .resource = sata_resources, ++ .num_resources = ARRAY_SIZE(sata_resources), ++}; ++ ++static inline void tcc8900_init_sata(void) ++{ ++ platform_device_register(&tcc8900_sata_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : SPI(GPSB) Master resource ++ * Description: ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_SPI_TCC_MASTER) || defined(CONFIG_SPI_TCC_MASTER_MODULE) ++static struct resource spi0_resources[] = { ++ [0] = { ++ .start = 0xF0536000, ++ .end = 0xF0536038, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_GPSB0_DMA, ++ .end = INT_GPSB0_DMA, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_spi0_device = { ++ .name = "tcc-spi", ++ .id = 0, ++ .resource = spi0_resources, ++ .num_resources = ARRAY_SIZE(spi0_resources), ++}; ++ ++static struct resource spi1_resources[] = { ++ [0] = { ++ .start = 0xF0536100, ++ .end = 0xF0536138, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_GPSB1_DMA, ++ .end = INT_GPSB1_DMA, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_spi1_device = { ++ .name = "tcc-spi", ++ .id = 1, ++ .resource = spi1_resources, ++ .num_resources = ARRAY_SIZE(spi1_resources), ++}; ++ ++static inline void tcc8900_init_spi(void) ++{ ++ platform_device_register(&tcc8900_spi0_device); ++ platform_device_register(&tcc8900_spi1_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : SPI(TSIF) Slave resource ++ * Description: ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_TSIF_TCC_SLAVE) || defined(CONFIG_TSIF_TCC_SLAVE_MODULE) ++static struct platform_device tcc_tsif_device = { ++ .name = "tcc-tsif", ++ .id = -1, ++}; ++ ++static inline void tcc8900_init_tsif(void) ++{ ++ platform_device_register(&tcc_tsif_device); ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : SD/MMC resource ++ * Description: tcc8900_mmc_core0_resource ++ * tcc8900_mmc_core1_resource ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_MMC_TCC_SDHC_CORE0) || defined(CONFIG_MMC_TCC_SDHC_CORE0_MODULE) ++static u64 tcc8900_device_mmc0_dmamask = 0xffffffffUL; ++static struct resource tcc8900_mmc_core0_resource[] = { ++ [0] = { ++ .start = 0xF05A0000, ++ .end = 0xF05A00FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_SD0, ++ .end = INT_SD0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++struct platform_device tcc8900_mmc0_device = { ++ .name = "tcc-sdhc0", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(tcc8900_mmc_core0_resource), ++ .resource = tcc8900_mmc_core0_resource, ++ .dev = { ++ .dma_mask = &tcc8900_device_mmc0_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++ ++#if defined(CONFIG_MMC_TCC_SDHC_CORE1) || defined(CONFIG_MMC_TCC_SDHC_CORE1_MODULE) ++static u64 tcc8900_device_mmc1_dmamask = 0xffffffffUL; ++static struct resource tcc8900_mmc_core1_resource[] = { ++ [0] = { ++ .start = 0xF05A0200, ++ .end = 0xF05A02FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_SD1, ++ .end = INT_SD1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++struct platform_device tcc8900_mmc1_device = { ++ .name = "tcc-sdhc1", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(tcc8900_mmc_core1_resource), ++ .resource = tcc8900_mmc_core1_resource, ++ .dev = { ++ .dma_mask = &tcc8900_device_mmc1_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++ ++#if defined(CONFIG_MMC_TCC_SDHC) || defined(CONFIG_MMC_TCC_SDHC_MODULE) ++static inline void tcc8900_init_mmc(void) ++{ ++#if defined(CONFIG_MMC_TCC_SDHC_CORE0) ++ platform_device_register(&tcc8900_mmc0_device); ++#endif ++#if defined(CONFIG_MMC_TCC_SDHC_CORE1) ++ platform_device_register(&tcc8900_mmc1_device); ++#endif ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : UART resource ++ * Description: uart0_resources ++ * uart1_resources ++ * uart2_resources (not used) ++ * uart3_resources (not used) ++ * uart4_resources (not used) ++ * uart5_resources (not used) ++ *----------------------------------------------------------------------*/ ++static struct resource uart0_resources[] = { ++ /* PA -> VA */ ++ [0] = { ++ .start = 0xF0532000, ++ .end = 0xF05320FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART0, ++ .end = INT_UART0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart0_device = { ++ .name = "tcc8900-uart", ++ .id = 0, ++ .resource = uart0_resources, ++ .num_resources = ARRAY_SIZE(uart0_resources), ++}; ++ ++static struct resource uart1_resources[] = { ++ [0] = { ++ .start = 0xF0532100, ++ .end = 0xF05321FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART1, ++ .end = INT_UART1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart1_device = { ++ .name = "tcc8900-uart", ++ .id = 1, ++ .resource = uart1_resources, ++ .num_resources = ARRAY_SIZE(uart1_resources), ++}; ++ ++#if 0 ++static struct resource uart2_resources[] = { ++ [0] = { ++ .start = 0xF0532200, ++ .end = 0xF05322FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART2, ++ .end = INT_UART2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart2_device = { ++ .name = "tcc8900-uart", ++ .id = 2, ++ .resource = uart2_resources, ++ .num_resources = ARRAY_SIZE(uart2_resources), ++}; ++ ++static struct resource uart3_resources[] = { ++ [0] = { ++ .start = 0xF0532300, ++ .end = 0xF05323FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART3, ++ .end = INT_UART3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart3_device = { ++ .name = "tcc8900-uart", ++ .id = 3, ++ .resource = uart3_resources, ++ .num_resources = ARRAY_SIZE(uart3_resources), ++}; ++ ++static struct resource uart4_resources[] = { ++ [0] = { ++ .start = 0xF0532400, ++ .end = 0xF05324FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART4, ++ .end = INT_UART4, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart4_device = { ++ .name = "tcc8900-uart", ++ .id = 4, ++ .resource = uart4_resources, ++ .num_resources = ARRAY_SIZE(uart4_resources), ++}; ++ ++static struct resource uart5_resources[] = { ++ [0] = { ++ .start = 0xF0532500, ++ .end = 0xF05325FF, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UART5, ++ .end = INT_UART5, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_uart5_device = { ++ .name = "tcc8900-uart", ++ .id = 5, ++ .resource = uart5_resources, ++ .num_resources = ARRAY_SIZE(uart5_resources), ++}; ++#endif ++ ++static inline void tcc8900_init_uart(void) ++{ ++ platform_device_register(&tcc8900_uart0_device); ++#if 0 ++ platform_device_register(&tcc8900_uart1_device); ++ platform_device_register(&tcc8900_uart2_device); ++ platform_device_register(&tcc8900_uart3_device); ++ platform_device_register(&tcc8900_uart4_device); ++ platform_device_register(&tcc8900_uart5_device); ++#endif ++} ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : USB HOST1.1 OHCI resource ++ * Description: tcc8900_ohci_resources ++ *----------------------------------------------------------------------*/ ++ #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) ++ static u64 tcc8900_device_ohci_dmamask = 0xffffffffUL; ++ ++ static struct resource tcc8900_ohci_resources[] = { ++ [0] = { ++ .start = 0xF0500000, ++ .end = 0xF050005C, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_U11H, ++ .end = INT_U11H, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ohci_device = { ++ .name = "tcc-ohci", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(tcc8900_ohci_resources), ++ .resource = tcc8900_ohci_resources, ++ .dev = { ++ .dma_mask = &tcc8900_device_ohci_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++}; ++ ++static int tcc8900_ohci_init(struct device *dev) ++{ ++ return 0; ++} ++ ++static struct tccohci_platform_data tcc8900_ohci_platform_data = { ++ .port_mode = USBOHCI_PPM_PERPORT, ++ .init = tcc8900_ohci_init, ++}; ++ ++void __init tcc_set_ohci_info(struct tccohci_platform_data *info) ++{ ++ ohci_device.dev.platform_data = info; ++} ++ ++static inline void tcc8900_init_usbhost(void) ++{ ++ platform_device_register(&ohci_device); ++ tcc_set_ohci_info(&tcc8900_ohci_platform_data); ++} ++#endif /*CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE*/ ++ ++ ++/*---------------------------------------------------------------------- ++ * Device : USB DWC OTG resource ++ * Description: dwc_otg_resources ++ *----------------------------------------------------------------------*/ ++#if defined(CONFIG_TCC_DWC_OTG) || defined(CONFIG_TCC_DWC_OTG_MODULE) ++static u64 tcc8900_dwc_otg_dmamask = 0xffffffffUL; ++static struct resource dwc_otg_resources[] = { ++ [0] = { ++ .start = 0xF0550000, ++ .end = 0xF0550100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = INT_UOTG, ++ .end = INT_UOTG, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device tcc8900_dwc_otg_device = { ++ .name = "dwc_otg", ++ .id = 0, ++ .resource = dwc_otg_resources, ++ .num_resources = ARRAY_SIZE(dwc_otg_resources), ++ .dev = { ++ .dma_mask = &tcc8900_dwc_otg_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++}; ++ ++static inline void tcc8900_init_dwc_otg(void) ++{ ++ int ret; ++ ret = platform_device_register(&tcc8900_dwc_otg_device); ++} ++#endif ++ ++static struct gpio_keys_button hhmid_buttons[] = { ++#if defined (CONFIG_LCD_4) ++ { ++ .gpio = TCC_GPD19, ++ .code = KEY_PAGEUP, ++ .desc = "Button 3", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPD18, ++ .code = KEY_LEFTALT, ++ .desc = "Button 1", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPD17, ++ .code = KEY_PAGEDOWN, ++ .desc = "Button 2", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPF10, ++ .code = KEY_POWER, ++ .desc = "Button 0", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++#else ++ ++ { ++ .gpio = TCC_GPD17, ++ .code = KEY_PAGEUP, ++ .desc = "Button 5", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ ++ { ++ .gpio = TCC_GPD16, ++ .code = KEY_PAGEDOWN, ++ .desc = "Button 4", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ ++ { ++ .gpio = TCC_GPD15, ++ .code = KEY_LEFTALT, ++ .desc = "Button 3", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPD18, ++ .code = KEY_ENTER, ++ .desc = "Button 1", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPD19, ++ .code = KEY_ESC, ++ .desc = "Button 2", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++ { ++ .gpio = TCC_GPF10, ++ .code = KEY_POWER, ++ .desc = "Button 0", ++ .active_low = 1, ++ .debounce_interval = 5, ++ }, ++#endif ++}; ++ ++//static struct gpio_keys_platform_data hhmid_button_data __initdata = { ++static struct gpio_keys_platform_data hhmid_button_data = { ++ .buttons = hhmid_buttons, ++ .nbuttons = ARRAY_SIZE(hhmid_buttons), ++}; ++ ++static struct platform_device hhmid_button_device = { ++ .name = "gpio-keys", ++ .id = 0, ++ .num_resources = 0, ++ .dev = { ++ .platform_data = &hhmid_button_data, ++ } ++}; ++ ++static inline void tcc8900_init_hhmid_button(void) ++{ ++ int ret; ++ ret = platform_device_register(&hhmid_button_device); ++} ++/* ++ * This gets called after board-specific INIT_MACHINE, and initializes most ++ * on-chip peripherals accessible on this board (except for few like USB): ++ * ++ * (a) Does any "standard config" pin muxing needed. Board-specific ++ * code will have muxed GPIO pins and done "nonstandard" setup; ++ * that code could live in the boot loader. ++ * (b) Populating board-specific platform_data with the data drivers ++ * rely on to handle wiring variations. ++ * (c) Creating platform devices as meaningful on this board and ++ * with this kernel configuration. ++ * ++ * Claiming GPIOs, and setting their direction and initial values, is the ++ * responsibility of the device drivers. So is responding to probe(). ++ * ++ * Board-specific knowlege like creating devices or pin setup is to be ++ * kept out of drivers as much as possible. In particular, pin setup ++ * may be handled by the boot loader, and drivers should expect it will ++ * normally have been done by the time they're probed. ++ */ ++static int __init tcc8900_init_devices(void) ++{ ++ tcc8900_init_hhtech_gpio(); ++ ++#if defined(CONFIG_I2C_TCC) || defined(CONFIG_I2C_TCC_MODULE) ++ tcc8900_init_i2c(); ++#endif ++ ++#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) ++ tcc8900_init_i2c_gpio(); ++#endif ++ ++#if defined(CONFIG_TCC_DM9000) || defined(CONFIG_TCC_DM9000_MODULE) ++ tcc8900_init_dm9000(); ++#endif ++#if defined(CONFIG_DM9KS) || defined(CONFIG_DM9KS_MODULE) ++ tcc8900_init_dm9ks(); ++#endif ++ ++#if defined(CONFIG_RTC_DRV_TCC) || defined(CONFIG_RTC_DRV_TCC_MODULE) ++ tcc8900_init_rtc(); ++#endif ++ ++ tcc8900_init_uart(); ++ tcc8900_init_lcd(); ++ ++#if defined(CONFIG_SPI_TCC_MASTER) || defined(CONFIG_SPI_TCC_MASTER_MODULE) ++ tcc8900_init_spi(); ++#endif ++#if defined(CONFIG_TSIF_TCC_SLAVE) || defined(CONFIG_TSIF_TCC_SLAVE_MODULE) ++ tcc8900_init_tsif(); ++#endif ++ ++#if defined(CONFIG_TOUCHSCREEN_TCCTS) || defined(CONFIG_TOUCHSCREEN_TCCTS_MODULE) ++ tcc8900_init_touch_ts(); ++#endif ++ ++#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) ++ tcc8900_init_usbhost(); ++#endif ++#if defined(CONFIG_TCC_DWC_OTG) || defined(CONFIG_TCC_DWC_OTG_MODULE) ++ tcc8900_init_dwc_otg(); ++#endif ++ ++#if defined(CONFIG_MMC_TCC_SDHC) || defined(CONFIG_MMC_TCC_SDHC_MODULE) ++ tcc8900_init_mmc(); ++#endif ++ ++#if defined(CONFIG_SATA_TCC) || defined(CONFIG_SATA_TCC_MODULE) ++ tcc8900_init_sata(); ++#endif ++ ++ tcc8900_init_hhmid_button(); ++ ++ return 0; ++} ++ ++arch_initcall(tcc8900_init_devices); +diff --git a/arch/arm/mach-tcc8900/gpio.c b/arch/arm/mach-tcc8900/gpio.c +new file mode 100644 +index 0000000..a4c80d5 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/gpio.c +@@ -0,0 +1,192 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/gpio.c ++ * ++ * Support functions for TCC8900 GPIO ++ * ++ * Copyright (C) 2009 Telechips ++ * Written by linux ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include /* cansleep wrappers */ ++ ++void tcc_gpio_cfgpin(unsigned int pin, unsigned int function, unsigned int out) ++{ ++ unsigned long mask, fn_val, flags, offs, fn_offs, fn_num, en_val; ++ void __iomem *base, *en_addr, *fn_addr; ++ ++ base = (void __iomem *)tcc_p2v(HwGPIO_BASE); ++ base += TCC_GPIO_BASE(pin) * 0x40; ++ offs = TCC_GPIO_OFFSET(pin); ++ fn_num = offs / 8; // Get port configuration register number ++ en_addr = base + 0x4; // Get output enable register address ++ fn_addr = base + 0x24 + fn_num * 4; // Get port configuration register adrress ++ fn_offs = (offs % 8) * 4; // Get offset in port configuration register ++ mask = 0xF << fn_offs; ++ ++ local_irq_save(flags); ++ local_irq_disable(); ++ fn_val = __raw_readl(fn_addr); ++ fn_val &= ~mask; ++ fn_val |= (function << fn_offs); ++ __raw_writel(fn_val, fn_addr); ++ // When configured into gpio function ++ if(function == 0) { ++ en_val = __raw_readl(en_addr); ++ if(out) // output ++ en_val |= (1 << offs); ++ else ++ en_val &= ~(1 << offs); ++ __raw_writel(en_val, en_addr); ++ } ++ ++ local_irq_restore(flags); ++} ++ ++EXPORT_SYMBOL(tcc_gpio_cfgpin); ++ ++unsigned int tcc_gpio_getcfg(unsigned int pin) ++{ ++ void __iomem *base, *fn_addr; ++ unsigned long mask, offs, fn_offs, fn_num; ++ ++ base = (void __iomem *)tcc_p2v(HwGPIO_BASE); ++ base += TCC_GPIO_BASE(pin) * 0x40; ++ offs = TCC_GPIO_OFFSET(pin); ++ fn_num = offs / 8; // Get port configuration register number ++ fn_addr = base + 0x24 + fn_num * 4; // Get port configuration register adrress ++ fn_offs = (offs % 8) * 4; // Get offset in port configuration register ++ mask = 0xF << fn_offs; ++ ++ return ((__raw_readl(fn_addr) & mask) >> fn_offs); ++} ++ ++EXPORT_SYMBOL(tcc_gpio_getcfg); ++ ++/* 0: pull-up/down disabled, 1: pull-up enabled, 2: pull-down enabled */ ++void tcc_gpio_pullup(unsigned int pin, unsigned int to) ++{ ++ unsigned long offs = TCC_GPIO_OFFSET(pin); ++ unsigned long flags, up, mask, pd_num, pd_offs; ++ void __iomem *base, *pd_addr; ++ ++ base = (void __iomem *)tcc_p2v(HwGPIO_BASE); ++ base += TCC_GPIO_BASE(pin) * 0x40; ++ pd_num = offs / 16; // Get pull-up/down function register number ++ pd_addr = base + 0x1C + pd_num * 4; // Get pull-up/down function register adrress ++ pd_offs = (offs % 16) * 2; // Get offset in pull-up/down function register ++ ++ mask = 0x3 << pd_offs; ++ ++ local_irq_save(flags); ++ local_irq_disable(); ++ ++ up = __raw_readl(pd_addr); ++ up &= ~mask; ++ up |= to << pd_offs; ++ __raw_writel(up, pd_addr); ++ ++ local_irq_restore(flags); ++} ++ ++EXPORT_SYMBOL(tcc_gpio_pullup); ++ ++void tcc_gpio_setpin(unsigned int pin, unsigned int to) ++{ ++ void __iomem *base; ++ unsigned long offs = TCC_GPIO_OFFSET(pin); ++ unsigned long flags; ++ unsigned long dat; ++ ++ base = (void __iomem *)tcc_p2v(HwGPIO_BASE); ++ base += TCC_GPIO_BASE(pin) * 0x40; ++ local_irq_save(flags); ++ local_irq_disable(); ++ ++ dat = __raw_readl(base); ++ dat &= ~(1 << offs); ++ dat |= to << offs; ++ __raw_writel(dat, base); ++ ++ local_irq_restore(flags); ++} ++ ++EXPORT_SYMBOL(tcc_gpio_setpin); ++ ++unsigned int tcc_gpio_getpin(unsigned int pin) ++{ ++ void __iomem *base; ++ unsigned long offs = TCC_GPIO_OFFSET(pin); ++ unsigned long dat; ++ ++ base = (void __iomem *)tcc_p2v(HwGPIO_BASE); ++ base += TCC_GPIO_BASE(pin) * 0x40; ++ dat = __raw_readl(base); ++ dat &= (1 << offs); ++ return (dat >> offs); ++} ++ ++EXPORT_SYMBOL(tcc_gpio_getpin); ++ ++int tcc_gpio_direction_input(unsigned int gpio) ++{ ++ tcc_gpio_cfgpin(gpio, 0, TCC_GPIO_INPUT); ++ tcc_gpio_pullup(gpio, 0); // pull-up/down disable ++ ++ return 0; ++} ++EXPORT_SYMBOL(tcc_gpio_direction_input); ++ ++int tcc_gpio_direction_output(unsigned int gpio, int value) ++{ ++ tcc_gpio_cfgpin(gpio, 0, TCC_GPIO_OUTPUT); ++ ++ /* REVISIT can we write the value first, to avoid glitching? */ ++ tcc_gpio_setpin(gpio, value); ++ ++ return 0; ++} ++EXPORT_SYMBOL(tcc_gpio_direction_output); ++ ++int gpio_to_irq(unsigned int pin) ++{ ++ switch(pin) ++ { ++ case TCC_GPD15: ++ return 8; ++ case TCC_GPD16: ++ return 9; ++ case TCC_GPD17: ++ return 11; ++ case TCC_GPD18: ++ return 12; ++ case TCC_GPD19: ++ return 13; ++ case TCC_GPF10: ++ return 14; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(gpio_to_irq); ++ ++int __init tcc8900_gpio_init(void) ++{ ++ return 0; ++} +diff --git a/arch/arm/mach-tcc8900/idle.c b/arch/arm/mach-tcc8900/idle.c +new file mode 100644 +index 0000000..d77265d +--- /dev/null ++++ b/arch/arm/mach-tcc8900/idle.c +@@ -0,0 +1,49 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/idle.c ++ * ++ * Author: ++ * Created: June 10, 2008 ++ * Description: TCC89/91/92 idle function ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see the file COPYING, or write ++ * to the Free Software Foundation, Inc., ++ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++#include ++#include ++#include ++#include ++ ++volatile static PCKC pCKC = (volatile PCKC)tcc_p2v(HwCLK_BASE); ++volatile static unsigned int bCLK0CTRL; ++volatile unsigned int idle_expired; ++ ++inline void tcc_idle(void) ++{ ++ idle_expired = 1; ++ local_irq_enable(); ++ bCLK0CTRL = pCKC->CLK0CTRL; ++ pCKC->CLK0CTRL |= (Hw20|0xFF00); ++ while (idle_expired); ++ pCKC->CLK0CTRL = bCLK0CTRL; ++ local_irq_disable(); ++} ++ ++inline void arch_idle_off(void) ++{ ++ idle_expired = 0; ++} ++ ++/* end of file */ +diff --git a/arch/arm/mach-tcc8900/include/bsp.h b/arch/arm/mach-tcc8900/include/bsp.h +new file mode 100644 +index 0000000..7b3fe3b +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/bsp.h +@@ -0,0 +1,62 @@ ++/**************************************************************************** ++* FileName : bsp.h ++* Description : ++**************************************************************************** ++* ++* TCC Version : 1.0 ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************/ ++ ++#ifndef __BSP_H__ ++#define __BSP_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#if defined(_LINUX_) ++#ifndef VOLATILE ++#define VOLATILE ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#else ++ ++#ifndef VOLATILE ++#define VOLATILE volatile ++#endif ++ ++//system os header file ++#include ++ ++//argument structur and define file ++#include ++ ++//globals macro, defines file ++#include ++ ++//bsp option config file ++#include ++ ++//Physical Base address file ++#include ++ ++//Kernel Ioctl ++#include ++#include ++#include ++#include ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // __BSP_H__ +diff --git a/arch/arm/mach-tcc8900/include/hhtech_gpio.h b/arch/arm/mach-tcc8900/include/hhtech_gpio.h +new file mode 100644 +index 0000000..c14cf19 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/hhtech_gpio.h +@@ -0,0 +1,77 @@ ++/**************************************************************** ++ * $ID: hhtech_gpio.h 三, 18 2月 2009 10:16:56 +0800 wk $ * ++ * * ++ * Description: * ++ * * ++ * Maintainer: wk@hhcn.com * ++ * * ++ * CopyRight (c) 2009 HHTech * ++ * www.hhcn.com, www.hhcn.org * ++ * All rights reserved. * ++ * * ++ * This file is free software; * ++ * you are free to modify and/or redistribute it * ++ * under the terms of the GNU General Public Licence (GPL). * ++ * * ++ * Last modified: 二, 08 12月 2009 19:02:55 +0800 by duanius # ++ ****************************************************************/ ++ ++#ifndef __HHTECH_GPIO_H ++#define __HHTECH_GPIO_H ++ ++/*====================================================================== ++ * GPIO ++ */ ++ ++//SD ++#define GPIO_SD_WP TCC_GPF12 /* SD write protect detect, 1:protected */ ++#define GPIO_SD_DETE TCC_GPF13 /* SD insert detect, 0:inserted */ ++ ++//USB ++#if defined(CONFIG_LCD_4) ++#define GPIO_USB_HOSTPWR_EN TCC_GPF25 /* USB Host drv Enable 1:open 0:off */ ++#else ++#define GPIO_USB_HOSTPWR_EN TCC_GPA2 /* USB Host drv Enable 1:open 0:off */ ++#endif ++#define GPIO_USB_EN TCC_GPA15 /* USB Improving voltage Enable, 1:open 0:off */ ++#define GPIO_USB_OTGDRV_EN TCC_GPA12 /* USB otg drv Enable, 1:open 0:off */ ++ ++//Headphone and Speaker ++#define GPIO_HEADPHONE_S TCC_GPD7 /* Headphone insert detect, 0:inserted */ ++#define GPIO_SPEAKER_EN TCC_GPD8 /* Speaker Enable 0:off 1:open */ ++ ++//Charging ++#define GPIO_DC_DETE TCC_GPF8 /* DC insert Detect, 0:inserted */ ++#define GPIO_CHARG_S1 TCC_GPF1 /* Charging status 1,*/ ++#define GPIO_CHARG_S2 TCC_GPF2 /* Charging status 2,*/ ++#define GPIO_CHARGER_EN TCC_GPF0 /* Quick charging mode enable, 1:open */ ++ ++//System Power ++#define GPIO_PWR_EN TCC_GPF6 /* System power control, 0:off 1:open */ ++#define GPIO_PWR_HOLD TCC_GPF10 /* System power detect, 0:detected */ ++ ++//TVOUT ++#define GPIO_TVOUT_EN TCC_GPD9 /* Video TVOUT control, 1:open */ ++ ++//Wifi ++#define GPIO_WIFI_EN TCC_GPB15 /* Wifi power control, 1:on */ ++ ++//HDMI ++#define GPIO_HDMI_EN TCC_GPF25 /* HDMI power control, 1:on */ ++#define GPIO_HDMIPWR_EN TCC_GPF4 ++#define GPIO_HDMI_HPD TCC_GPA14 /* HDMI line insert Detect, 1:inserted */ ++ ++//LED ++#if defined(CONFIG_LCD_4) ++#define GPIO_LED1_EN TCC_GPE6 /* Green LED, 0:on */ ++#define GPIO_LED2_EN TCC_GPE7 /* Red LED, 0:on */ ++#else ++#define GPIO_LED1_EN TCC_GPE7 /* Green LED, 0:on */ ++#define GPIO_LED2_EN TCC_GPE6 /* Red LED, 0:on */ ++#endif ++ ++//LCD ++#define GPIO_LCD_BACKLIGHT_EN TCC_GPA5 /* LCD backlight control, 1:on */ ++#define GPIO_LCD_PWR_EN TCC_GPA4 /* LCD power control, 1:on */ ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/TCC89x_Physical.h b/arch/arm/mach-tcc8900/include/mach/TCC89x_Physical.h +new file mode 100644 +index 0000000..496a801 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/TCC89x_Physical.h +@@ -0,0 +1,1164 @@ ++/**************************************************************************** ++ * FileName : TCC89x_Physical.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++/**************************************************************************** ++ ++ Revision History ++ ++ **************************************************************************** ++ ++ ****************************************************************************/ ++ ++/************************************************************************ ++* TCC89x Internal Register Definition File ++************************************************************************/ ++#ifndef __TCC89x_H__ ++#define __TCC89x_H__ ++ ++ ++/************************************************************************ ++* Bit Field Definition ++************************************************************************/ ++#define Hw37 (1LL << 37) ++#define Hw36 (1LL << 36) ++#define Hw35 (1LL << 35) ++#define Hw34 (1LL << 34) ++#define Hw33 (1LL << 33) ++#define Hw32 (1LL << 32) ++#define Hw31 0x80000000 ++#define Hw30 0x40000000 ++#define Hw29 0x20000000 ++#define Hw28 0x10000000 ++#define Hw27 0x08000000 ++#define Hw26 0x04000000 ++#define Hw25 0x02000000 ++#define Hw24 0x01000000 ++#define Hw23 0x00800000 ++#define Hw22 0x00400000 ++#define Hw21 0x00200000 ++#define Hw20 0x00100000 ++#define Hw19 0x00080000 ++#define Hw18 0x00040000 ++#define Hw17 0x00020000 ++#define Hw16 0x00010000 ++#define Hw15 0x00008000 ++#define Hw14 0x00004000 ++#define Hw13 0x00002000 ++#define Hw12 0x00001000 ++#define Hw11 0x00000800 ++#define Hw10 0x00000400 ++#define Hw9 0x00000200 ++#define Hw8 0x00000100 ++#define Hw7 0x00000080 ++#define Hw6 0x00000040 ++#define Hw5 0x00000020 ++#define Hw4 0x00000010 ++#define Hw3 0x00000008 ++#define Hw2 0x00000004 ++#define Hw1 0x00000002 ++#define Hw0 0x00000001 ++#define HwZERO 0x00000000 ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 2 SMU & PMU_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 1. Clock Controller Register Define (Base Addr = 0xF0400000) // R/W ++************************************************************************/ ++//--------------------------------------------------------------------------------------------- ++//31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ++// |CFGEN|MODE | NCKOE/DPRD | ++//15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ++// NCKOE/DMIN | NCKOE/DMAX | NCKOE/DCDIV | | CKSEL | ++//---------------------------------------------------------------------------------------------- ++#define HwCLK_BASE *(volatile unsigned long *)0xF0400000 ++#define HwCKC ((PCKC)&HwCLK_BASE) ++ ++/************************************************************************ ++* 2. Vectored Priority Interrupt Controller Register Map(Base Addr = 0xF0401000) ++************************************************************************/ ++#define HwPIC_BASE *(volatile unsigned long *)0xF0401000 ++#define HwVIC_BASE *(volatile unsigned long *)0xF0401200 ++#define HwPIC ((PPIC)&HwPIC_BASE) ++#define HwVIC ((PVIC)&HwVIC_BASE) ++ ++ ++// Interrupt Enable 0 ++#define HwINT0_EHI0 Hw31 // R/W, External Host Interface0 Interrupt Enable ++#define HwINT0_ECC Hw30 // R/W, ECC Interrupt Enable ++#define HwINT0_DMA Hw29 // R/W, DMA Controller Interrupt Enable ++#define HwINT0_TSADC Hw28 // R/W, TSADC Interrupt Enable ++#define HwINT0_G2D Hw27 // R/W, Graphic Engine 2D Hardware Interrupt Enable ++#define HwINT0_3DMMU Hw26 // R/W, 3D MMU Interrupt Enable ++#define HwINT0_3DGP Hw25 // R/W, 3D Geometary Interrupt Enable ++#define HwINT0_3DPP Hw24 // R/W, 3D Pixel Processor Interrupt Enable ++#define HwINT0_VCDC Hw23 // R/W, Video CODEC Interrupt Enable ++#define HwINT0_JPGD Hw22 // R/W, JPEG Decoder Interrupt Enable ++#define HwINT0_JPGE Hw21 // R/W, JPEG Encoder Interrupt Enable ++#define HwINT0_VIPET Hw20 // R/W, VIPET Controller Interrupt Enable ++#define HwINT0_LCD1 Hw19 // R/W, LCD Controller1 Interrupt Enable ++#define HwINT0_LCD0 Hw18 // R/W, LCD Controller0 Interrupt Enable ++#define HwINT0_CAM Hw17 // R/W, Camera Interrupt Enable ++#define HwINT0_SC1 Hw16 // R/W, Mem-to-Mem Scaler1 Interrupt Enable ++#define HwINT0_SC0 Hw15 // R/W, Mem-to-Mem Scaler0 Interrupt Enable ++#define HwINT0_EI11 Hw14 // R/W, External Interrupt11 Enable ++#define HwINT0_EI10 Hw13 // R/W, External Interrupt10 Enable ++#define HwINT0_EI9 Hw12 // R/W, External Interrupt9 Enable ++#define HwINT0_EI8 Hw11 // R/W, External Interrupt8 Enable ++#define HwINT0_EI7 Hw10 // R/W, External Interrupt7 Enable ++#define HwINT0_EI6 Hw9 // R/W, External Interrupt6 Enable ++#define HwINT0_EI5 Hw8 // R/W, External Interrupt5 Enable ++#define HwINT0_EI4 Hw7 // R/W, External Interrupt4 Enable ++#define HwINT0_EI3 Hw6 // R/W, External Interrupt3 Enable ++#define HwINT0_EI2 Hw5 // R/W, External Interrupt2 Enable ++#define HwINT0_EI1 Hw4 // R/W, External Interrupt1 Enable ++#define HwINT0_EI0 Hw3 // R/W, External Interrupt0 Enable ++#define HwINT0_SMUI2C Hw2 // R/W, SMU_I2C Interrupt Enable ++#define HwINT0_TC1 Hw1 // R/W, Timer1 Interrupt Enable ++#define HwINT0_TC0 Hw0 // R/W, Timer0 Interrupt Enable ++ ++// Interrupt Enable 1 ++#define HwINT1_AEIRQ Hw31 // R/W, Not maskable error ARM DMA interrupt enable ++#define HwINT1_ASIRQ Hw30 // R/W, Secure ARM DMA select interrupt enable ++#define HwINT1_AIRQ Hw29 // R/W, Non secure ARM DMA interrupt enable ++#define HwINT1_APMU Hw28 // R/W, ARM System Metrics interrupt enable ++#define HwINT1_AUDIO Hw27 // R/W, AUDIO interrupt enable ++#define HwINT1_ADMA Hw26 // R/W, AUDIO DMA interrupt enable ++#define HwINT1_DAITX Hw25 // R/W, DAI transmit interrupt enable ++#define HwINT1_DAIRX Hw24 // R/W, DAI receive interrupt enable ++#define HwINT1_CDRX Hw23 // R/W, CDIF receive interrupt enable ++#define HwINT1_TSIF1 Hw22 // R/W, TS interface 1 interrupt enable ++#define HwINT1_TSIF0 Hw21 // R/W, TS interface 0 interrupt enable ++#define HwINT1_GPS2 Hw20 // R/W, GPS AGPS interrupt enable ++#define HwINT1_GPS1 Hw19 // R/W, GPS TCXO expired interrupt enable ++#define HwINT1_GPS0 Hw18 // R/W, GPS RTC expired interrupt enable ++#define HwINT1_NotUsed Hw17 // R/W, Reserved ++#define HwINT1_UOTG Hw16 // R/W, USB 2.0 OTG interrupt enable ++#define HwINT1_UART Hw15 // R/W, UART interrupt enable ++#define HwINT1_SPDTX Hw14 // R/W, SPDIF transmitter interrupt enable ++#define HwINT1_SD1 Hw13 // R/W, SD/MMC 1 interrupt enable ++#define HwINT1_SD0 Hw12 // R/W, SD/MMC 0 interrupt enable ++#define HwINT1_RTC Hw11 // R/W, RTC interrupt enable ++#define HwINT1_RMT Hw10 // R/W, Remote Control interrupt enable ++#define HwINT1_NFC Hw9 // R/W, Nand flash controller interrupt enable ++#define HwINT1_MS Hw8 // R/W, Memory Stick interrupt enable ++#define HwINT1_MPEFEC Hw7 // R/W, MPEFEC interrupt enable ++#define HwINT1_I2C Hw6 // R/W, I2C interrupt enable ++#define HwINT1_HDD Hw5 // R/W, HDD controller interrupt enable ++#define HwINT1_GPSB Hw4 // R/W, GPSB Interrupt Enable ++#define HwINT1_NotUsed1 Hw3 // R/W, Reserved ++#define HwINT1_HDMI Hw2 // R/W, HDMI interrupt enable ++#define HwINT1_NotUsed2 Hw1 // R/W, Reserved ++#define HwINT1_EHI1 Hw0 // R/W, External Host Interface1 Interrupt Enable ++ ++#define HwALLMSK_FIQ Hw1 // FIQ mask register ++#define HwALLMSK_IRQ Hw0 // IRQ mask register ++ ++/*********************************************************************** ++* 3. Timer/Counter Register Map (Base Address = 0xF0403000) ++************************************************************************/ ++#define HwTMR_BASE *(volatile unsigned long *)0xF0403000 // Timer/Counter Base Register ++ ++/*********************************************************************** ++* 4. PMU(POWER MANAGEMENT UNIT) Register Map (Base Address = 0xF0404000) ++************************************************************************/ ++#define HwPMU_BASE *(volatile unsigned long *)0xF0404000 //R/W PMU Control Register ++ ++/******************************************************************************* ++* 5. SMUI2C Controller Register Define (Base Addr = 0xF0405000) ++********************************************************************************/ ++#define HwSMU_I2CMASTER0_BASE *(volatile unsigned long *)0xF0405000 ++#define HwSMU_I2CMASTER1_BASE *(volatile unsigned long *)0xF0405040 ++#define HwSMU_I2CICLK_BASE *(volatile unsigned long *)0xF0405080 //I2C_SCL divider Regist ++#define HwI2CSTATUS_BASE *(volatile unsigned long *)0xF05300C0 ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 3 GPIO_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 1. GPIO Register Map (Base Address = 0xF0102000) ++************************************************************************/ ++#define HwGPIO_BASE *(volatile unsigned long *)0xF0102000 // ++#define HwGPIOA_BASE *(volatile unsigned long *)0xF0102000 // ++#define HwGPIOB_BASE *(volatile unsigned long *)0xF0102040 // ++#define HwGPIOC_BASE *(volatile unsigned long *)0xF0102080 // ++#define HwGPIOD_BASE *(volatile unsigned long *)0xF01020C0 // ++#define HwGPIOE_BASE *(volatile unsigned long *)0xF0102100 // ++#define HwGPIOF_BASE *(volatile unsigned long *)0xF0102140 // ++#define HwEINTSEL_BASE *(volatile unsigned long *)0xF0102180 // ++#define HwGPIO ((PGPIO)&HwGPIO_BASE) ++#define HwGPIOA ((PGPION)&HwGPIOA_BASE) ++#define HwGPIOB ((PGPION)&HwGPIOB_BASE) ++#define HwGPIOC ((PGPION)&HwGPIOC_BASE) ++#define HwGPIOD ((PGPION)&HwGPIOD_BASE) ++#define HwGPIOE ((PGPION)&HwGPIOE_BASE) ++#define HwGPIOF ((PGPION)&HwGPIOF_BASE) ++#define HwEINTSEL ((PGPIOINT)&HwEINTSEL_BASE) ++ ++#define HwPORTCFG_GPFN0(X) ((X)<<0) // 0~3 ++#define HwPORTCFG_GPFN0_MASK (0xF) // HwPORTCFG_GPFN0(15) ++#define HwPORTCFG_GPFN1(X) ((X)<<4) // 4~7 ++#define HwPORTCFG_GPFN1_MASK (0xF<<4) // HwPORTCFG_GPFN1(15) ++#define HwPORTCFG_GPFN2(X) ((X)<<8) // 8~11 ++#define HwPORTCFG_GPFN2_MASK (0xF<<8) // HwPORTCFG_GPFN2(15) ++#define HwPORTCFG_GPFN3(X) ((X)<<12) // 12~15 ++#define HwPORTCFG_GPFN3_MASK (0xF<<12) // HwPORTCFG_GPFN3(15) ++#define HwPORTCFG_GPFN4(X) ((X)<<16) // 16~19 ++#define HwPORTCFG_GPFN4_MASK (0xF<<16) // HwPORTCFG_GPFN4(15) ++#define HwPORTCFG_GPFN5(X) ((X)<<20) // 20~23 ++#define HwPORTCFG_GPFN5_MASK (0xF<<20) // HwPORTCFG_GPFN5(15) ++#define HwPORTCFG_GPFN6(X) ((X)<<24) // 24~27 ++#define HwPORTCFG_GPFN6_MASK (0xF<<24) // HwPORTCFG_GPFN6(15) ++#define HwPORTCFG_GPFN7(X) ((X)<<28) // 28~31 ++#define HwPORTCFG_GPFN7_MASK (0xF<<28) // HwPORTCFG_GPFN7(15) ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 4 CORE & MEMORY BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 3. DRAM CONTROLLER Register Map (Base Address = 0xF0301000) ++************************************************************************/ ++#define HwDRAM_BASE *(volatile unsigned long *)0xF0301000 // ++#define HwDRAMM0_BASE *(volatile unsigned long *)0xF0301000 // ++#define HwDRAMM1_BASE *(volatile unsigned long *)0xF0302000 // ++#define HwDRAMMISC_BASE *(volatile unsigned long *)0xF0303000 // ++#define HwDRAMPHY_BASE *(volatile unsigned long *)0xF0304400 // ++#define HwDRAMMEMBUS_BASE *(volatile unsigned long *)0xF0305004 // ++ ++/************************************************************************ ++* 4-1. MISC CORE BUS CONFIGURATION REGISTERS (Base Addr = 0xF0101000) ++************************************************************************/ ++#define HwCORECFG_BASE *(volatile unsigned long *)0xF0101000 ++ ++/************************************************************************ ++* 4-2. Virtual MMU Table Register Define (Base Addr = 0xF7000000) ++************************************************************************/ ++#define HwVMT_BASE *(volatile unsigned long *)0x20000000 // VMT Base Regiseter ++#define HwREGION_BASE *(volatile unsigned long *)0xF0600000 // R/W, Configuration Register for Region 0 ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 5 IO BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/******************************************************************************* ++* 4. Memory Stick Host Controller Register Define (Base Addr = 0xF0590000) ++********************************************************************************/ ++#define HwSMSHC_BASE *(volatile unsigned long *)0xF0590000 ++#define HwPORTCFG_BASE *(volatile unsigned long *)0xF05F1000 ++ ++/******************************************************************************** ++* 5. SD/SDIO/MMC/CE-ATA Host Controller Register Define (Base Addr = 0xF05A0000) ++********************************************************************************/ ++#define HwSDCORE0SLOT0_BASE *(volatile unsigned long *)0xF05A0000 // Core 0 Slot 0 ++#define HwSDCORE0SLOT1_BASE *(volatile unsigned long *)0xF05A0100 // Core 0 Slot 1 ++#define HwSDCORE1SLOT2_BASE *(volatile unsigned long *)0xF05A0200 // Core 1 Slot 2 ++#define HwSDCORE1SLOT3_BASE *(volatile unsigned long *)0xF05A0300 // Core 1 Slot 3 ++ ++// Channel Control Register ++#define HwSDCHCTRL_BASE *(volatile unsigned long *)0xF05A0800 // R/W 0x0000 SD/MMC port control register ++ ++/******************************************************************************* ++* 6. NAND Flash Controller(NFC) Register Define (Base Addr = 0xF05B0000) ++********************************************************************************/ ++#define HwNFC_BASE *(volatile unsigned long *)0xF05B0000 ++#define HwNFC ((PNFC)&HwNFC_BASE) ++ ++// NFC Control Register ++#define HwNFC_CTRL_RDYIEN_EN Hw31 // Nand Flash Ready Interrupt Enable ++#define HwNFC_CTRL_RDYIEN_DIS ~Hw31 // Nand Flash Ready Interrupt Disable ++#define HwNFC_CTRL_PROGIEN_EN Hw30 // Nand Flash Program Interrupt Enable ++#define HwNFC_CTRL_PROGIEN_DIS ~Hw30 // Nand Flash Program Interrupt Disable ++#define HwNFC_CTRL_READIEN_EN Hw29 // Nand Flash Read Interrupt Enable ++#define HwNFC_CTRL_READIEN_DIS ~Hw29 // Nand Flash Read Interrupt Disable ++#define HwNFC_CTRL_DEN_EN Hw28 // Nand Flash DMA Request Enable ++#define HwNFC_CTRL_DEN_DIS ~Hw28 // Nand Flash DMA Request Disable ++#define HwNFC_CTRL_FS_RDY Hw27 // FIFO status is Ready to write and read in FIFO ++#define HwNFC_CTRL_FS_BUSY ~Hw27 // FIFO status is Busy to write and read in FIFO ++#define HwNFC_CTRL_BW_16 Hw26 // Bus width = 8bit ++#define HwNFC_CTRL_BW_8 HwZERO // Bus width = 16bit ++#define HwNFC_CTRL_CS3SEL_1 Hw25 // Nand Flash nCS3 is High (Disabled) ++#define HwNFC_CTRL_CS3SEL_0 HwZERO // Nand Flash nCS3 is Low (Enabled) ++#define HwNFC_CTRL_CS2SEL_1 Hw24 // Nand Flash nCS2 is High (Disabled) ++#define HwNFC_CTRL_CS2SEL_0 HwZERO // Nand Flash nCS2 is Low (Enabled) ++#define HwNFC_CTRL_CS1SEL_1 Hw23 // Nand Flash nCS1 is High (Disabled) ++#define HwNFC_CTRL_CS1SEL_0 HwZERO // Nand Flash nCS1 is Low (Enabled) ++#define HwNFC_CTRL_CS0SEL_1 Hw22 // Nand Flash nCS0 is High (Disabled) ++#define HwNFC_CTRL_CS0SEL_0 HwZERO // Nand Flash nCS0 is Low (Enabled) ++#define HwNFC_CTRL_CFG_nCS3 HwNFC_CTRL_CS3SEL_1 ++#define HwNFC_CTRL_CFG_nCS2 HwNFC_CTRL_CS2SEL_1 ++#define HwNFC_CTRL_CFG_nCS1 HwNFC_CTRL_CS1SEL_1 ++#define HwNFC_CTRL_CFG_nCS0 HwNFC_CTRL_CS0SEL_1 ++#define HwNFC_CTRL_CSnSEL(X) ((X)*Hw22) // Nand Flash nCS[3:0] Set ++#define HwNFC_CTRL_CFG_NOACT HwNFC_CTRL_CSnSEL(15) ++#define HwNFC_CTRL_RDY_RDY Hw21 // External Nand Flash Controller is Ready ++#define HwNFC_CTRL_RDY_BUSY ~Hw21 // External Nand Flash Controller is Busy ++#define HwNFC_CTRL_BSIZE(X) ((X)*Hw19) ++#define HwNFC_CTRL_BSIZE_1 HwNFC_CTRL_BSIZE(0) // 1Read/Write ++#define HwNFC_CTRL_BSIZE_2 HwNFC_CTRL_BSIZE(1) // 2Read/Write ++#define HwNFC_CTRL_BSIZE_4 HwNFC_CTRL_BSIZE(2) // 4Read/Write ++#define HwNFC_CTRL_BSIZE_8 HwNFC_CTRL_BSIZE(3) // 8Read/Write ++#define HwNFC_CTRL_BSIZE_MASK HwNFC_CTRL_BSIZE(3) ++#define HwNFC_CTRL_PSIZE(X) ((X)*Hw16) ++#define HwNFC_CTRL_PSIZE_256 HwNFC_CTRL_PSIZE(0) // 1 Page = 256 Half-Word ++#define HwNFC_CTRL_PSIZE_512 HwNFC_CTRL_PSIZE(1) // 1 Page = 512 Byte ++#define HwNFC_CTRL_PSIZE_1024 HwNFC_CTRL_PSIZE(2) // 1 Page = 1024 Half-Word ++#define HwNFC_CTRL_PSIZE_2048 HwNFC_CTRL_PSIZE(3) // 1 Page = 2048 Byte ++#define HwNFC_CTRL_PSIZE_4096 HwNFC_CTRL_PSIZE(4) // 1 Page = 4096 Byte ++#define HwNFC_CTRL_PSIZE_MASK HwNFC_CTRL_PSIZE(7) ++#define HwNFC_CTRL_MASK_EN Hw15 // Address/Command Mask Enable ++#define HwNFC_CTRL_CADDR Hw12 // Number of Address Cycle ++#define HwNFC_CTRL_bSTP(X) ((X)*Hw8) // Number of Base cycle for Setup Time ++#define HwNFC_CTRL_bSTP_MASK HwNFC_CTRL_bSTP(15) ++#define HwNFC_CTRL_bPW(X) ((X)*Hw4) // Number of Base cycle for Pulse Width ++#define HwNFC_CTRL_bPW_MASK HwNFC_CTRL_bPW(15) ++#define HwNFC_CTRL_bHLD(X) ((X)*Hw0) // Number of Base cycle for Hold Time ++#define HwNFC_CTRL_bHLD_MASK HwNFC_CTRL_bHLD(15) ++ ++#define HwNFC_IREQ_FLAG2 Hw6 // ++#define HwNFC_IREQ_FLAG1 Hw5 // ++#define HwNFC_IREQ_FLAG0 Hw4 // ++#define HwNFC_IREQ_IRQ2 Hw2 // Ready Interrupt ++#define HwNFC_IREQ_IRQ1 Hw1 // Program Interrupt ++#define HwNFC_IREQ_IRQ0 Hw0 // Reading Interrupt ++ ++/******************************************************************************* ++* 7. Static Memory Controller(SMC) Register Define (Base Addr = 0xF05F0000) ++********************************************************************************/ ++#define HwSMC_BASE *(volatile unsigned long *)0xF05F0000 ++#define HwSMC_STATUS *(volatile unsigned long *)0xF05F0000 // R/W Unknown Status Register ++#define HwSMC_CSNCFG0 *(volatile unsigned long *)0xF05F0020 // R 0x4b40_3183 External Chip Select0 Config Register ++#define HwSMC_CSNCFG1 *(volatile unsigned long *)0xF05F0024 // R/W 0x4b40_1104 External Chip Select1 Config Register ++#define HwSMC_CSNCFG2 *(volatile unsigned long *)0xF05F0028 // W 0x4b40_4082 External Chip Select2 Config Register ++#define HwSMC_CSNCFG3 *(volatile unsigned long *)0xF05F002C // R/W 0x4b40_20C5 External Chip Select3 Config. Register ++#define HwSMC_CSNOFFSET *(volatile unsigned long *)0xF05F0030 // R/W 0x0 Wapping Address Mode OFFSET Register ++#define HwSMC_INDIRADDR *(volatile unsigned long *)0xF05F0034 // R/W 0x0 Indirect Address ++ ++/******************************************************************************* ++* 8. External Device Interface (EDI) Register Define (Base Addr = 0xF05F6000) ++********************************************************************************/ ++#define HwEDI_BASE *(volatile unsigned long *)0xF05F6000 ++#define HwEDI ((PEDI)&HwEDI_BASE) ++ ++/******************************************************************************* ++* 9. IDE Controller Register Define (Base Addr = 0xF0520000) ++********************************************************************************/ ++#define HwIDE_BASE *(volatile unsigned long *)0xF0520000 ++ ++/******************************************************************************* ++* 10. SATA Interface Register Define (Base Addr = 0xF0560000) ++********************************************************************************/ ++#define HwSATA_BASE *(volatile unsigned long *)0xF0560000 ++//SCR5-SCR15 0x38-0x60 32 See description 0x0 Reserved for SATA Dependencies: Reads to these locations return zeros; writes have no effect ++ ++/******************************************************************************* ++* 11-1. Audio DMA Controller Register Define (Base Addr = 0xF0533000) ++********************************************************************************/ ++#define HwADMA_BASE *(volatile unsigned long *)0xF0533000 ++ ++/******************************************************************************* ++* 11-2. DAI Register Define (Base Addr = 0xF0534000) ++********************************************************************************/ ++#define HwADMA_DAIBASE *(volatile unsigned long *)0xF0534000 ++ ++/******************************************************************************* ++* 11-3. CDIF Register Define (Base Addr = 0xF0534000) ++********************************************************************************/ ++#define HwADMA_CDIFBASE *(volatile unsigned long *)0xF0534080 ++ ++/******************************************************************************* ++* 11-4. SPDIF Register Define (Base Addr = 0xF0535000/0xF0535800) ++********************************************************************************/ ++#define HwADMA_SPDIFTXBASE *(volatile unsigned long *)0xF0535000 ++ ++/******************************************************************************* ++* 12-1. DAI Register Define (Base Addr = 0xF0537000 ++********************************************************************************/ ++#define HwDAI_BASE *(volatile unsigned long *)0xF0537000 ++ ++/******************************************************************************* ++* 12-2. CDIF Register Define (Base Addr = 0xF0537000 ++********************************************************************************/ ++#define HwCDIF_BASE *(volatile unsigned long *)0xF0537080 ++ ++/******************************************************************************* ++* 13. SPDIF Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++#define HwSPDIF_BASE *(volatile unsigned long *)0xF0538000 ++ ++/******************************************************************************* ++* 14-1. USB1.1 HOST Controller & Transceiver (Base Addr = 0xF0500000) ++********************************************************************************/ ++#define HwUSBHOST_BASE *(volatile unsigned long *)0xF0500000 ++ ++/******************************************************************************* ++* 14-2 USB1.1 HOST Configuration Register (Base Addr = 0xF05F5000) ++********************************************************************************/ ++#define HwUSBHOSTCFG_BASE *(volatile unsigned long *)0xF05F5000 ++ ++/******************************************************************************* ++* 15-1. USB2.0 OTG Controller Define (Base Addr = 0xF0550000) ++********************************************************************************/ ++#define HwUSB20OTG_BASE *(volatile unsigned long *)0xF0550000 ++ ++/******************************************************************************* ++* 15-2. USB OTG Configuration Register Define (Base Addr = 0xF05F5000) ++********************************************************************************/ ++#define HwUSBOTGCFG_BASE *(volatile unsigned long *)0xF05F5000 ++ ++/******************************************************************************* ++* 15-3. USB PHY Configuration Register Define (Base Addr = 0xF05F5028) ++********************************************************************************/ ++#define HwUSBPHYCFG_BASE *(volatile unsigned long *)0xF05F5028 ++ ++/******************************************************************************* ++* 16. External Host Interface Register Define (Base Addr = 0xF0570000/0xF0580000) ++********************************************************************************/ ++#define HwEHICS0_BASE *(volatile unsigned long *)0xF0570000 ++#define HwEHICS1_BASE *(volatile unsigned long *)0xF0580000 ++ ++/******************************************************************************* ++* 17. General Purpose Serial Bus (GPSB) Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++#if 0 ++#define HwGPSBCH0_BASE *(volatile unsigned long *)0xF0057000 ++#define HwGPSBCH1_BASE *(volatile unsigned long *)0xF0057100 ++#define HwGPSBCH2_BASE *(volatile unsigned long *)0xF0057200 ++#define HwGPSBCH3_BASE *(volatile unsigned long *)0xF0057300 ++#define HwGPSBCH4_BASE *(volatile unsigned long *)0xF0057400 ++#define HwGPSBCH5_BASE *(volatile unsigned long *)0xF0057500 ++#define HwGPSBPORTCFG_BASE *(volatile unsigned long *)0xF0057800 ++#define HwGPSBPIDTABLE_BASE *(volatile unsigned long *)0xF0057F00 ++ ++#define HwGPSB_PIDT(X) *(volatile unsigned long *)(0xF0057F00+(X)*4) // R/W, PID Table Register ++#define HwGPSB_PIDT_CH2 Hw31 // Channel 2 enable ++#define HwGPSB_PIDT_CH1 Hw30 // Channel 1 enable ++#define HwGPSB_PIDT_CH0 Hw29 // Channel 0 enable ++#else ++#define HwGPSBCH0_BASE *(volatile unsigned long *)0xF0536000 ++#define HwGPSBCH1_BASE *(volatile unsigned long *)0xF0536100 ++#define HwGPSBCH2_BASE *(volatile unsigned long *)0xF0536200 ++#define HwGPSBCH3_BASE *(volatile unsigned long *)0xF0536300 ++#define HwGPSBCH4_BASE *(volatile unsigned long *)0xF0536400 ++#define HwGPSBCH5_BASE *(volatile unsigned long *)0xF0536500 ++#define HwGPSBPORTCFG_BASE *(volatile unsigned long *)0xF0536800 ++#define HwGPSBPIDTABLE_BASE *(volatile unsigned long *)0xF0536F00 ++ ++#define HwGPSB_PIDT(X) *(volatile unsigned long *)(0xF0536F00+(X)*4) // R/W, PID Table Register ++#define HwGPSB_PIDT_CH2 Hw31 // Channel 2 enable ++#define HwGPSB_PIDT_CH1 Hw30 // Channel 1 enable ++#define HwGPSB_PIDT_CH0 Hw29 // Channel 0 enable ++#endif ++ ++/******************************************************************************* ++* 18. The Transport Stream Interface (TSIF) Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++#define HwTSIF_BASE *(volatile unsigned long *)0xF053B000 ++#define HwTSIFPORTSEL_BASE *(volatile unsigned long *)0xF053B800 ++ ++/******************************************************************************* ++* 19. GPS Interface Register Define (Base Addr = ) ++********************************************************************************/ ++ ++ ++/******************************************************************************* ++* 20. Remote Control Interface Register Define (Base Addr = 0xF05F3000) ++********************************************************************************/ ++#define HwREMOCON_BASE *(volatile unsigned long *)0xF05F3000 ++ ++ ++/******************************************************************************* ++* 21. I2C Controller Register Define (Base Addr = 0xF0530000) ++********************************************************************************/ ++#define HwI2CMASTER0_BASE *(volatile unsigned long *)0xF0530000 ++#define HwI2CMASTER1_BASE *(volatile unsigned long *)0xF0530040 ++#define HwI2CSLAVE_BASE *(volatile unsigned long *)0xF0530080 ++#define HwI2CSTATUS_BASE *(volatile unsigned long *)0xF05300C0 ++ ++#define HwI2CMASTER0 ((PSMUI2CMASTER)&HwI2CMASTER0_BASE) ++#define HwI2CMASTER1 ((PSMUI2CMASTER)&HwI2CMASTER1_BASE) ++ ++/******************************************************************************* ++* 22. UART Controller Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++#define HwUARTCH0_BASE *(volatile unsigned long *)0xF0532000 ++#define HwUARTCH1_BASE *(volatile unsigned long *)0xF0532100 ++#define HwUARTCH2_BASE *(volatile unsigned long *)0xF0532200 ++#define HwUARTCH3_BASE *(volatile unsigned long *)0xF0532300 ++#define HwUARTCH4_BASE *(volatile unsigned long *)0xF0532400 ++#define HwUARTCH5_BASE *(volatile unsigned long *)0xF0532500 ++#define HwUARTPORTMUX_BASE *(volatile unsigned long *)0xF0532600 ++ ++/******************************************************************************* ++* 23. CAN Controller Register Define (Base Addr = 0xF0531000) ++********************************************************************************/ ++#define HwCAN_BASE *(volatile unsigned long *)0xF0531000 ++ ++/******************************************************************************* ++* 24. DMA Controller Register Define (Base Addr = 0xF0540000) ++********************************************************************************/ ++#define HwGDMA0_BASE *(volatile unsigned long *)0xF0540000 ++#define HwGDMA1_BASE *(volatile unsigned long *)0xF0540100 ++#define HwGDMA2_BASE *(volatile unsigned long *)0xF0540200 ++#define HwGDMA3_BASE *(volatile unsigned long *)0xF0540300 ++ ++/******************************************************************************* ++* 25. Real Time Clock(RTC) Register Define (Base Addr = 0xF05F2000) ++********************************************************************************/ ++#define HwRTC_BASE *(volatile unsigned long *)0xF05F2000 ++ ++/******************************************************************************* ++* 26. TouchScreen ADC (TSADC) Register Define (Base Addr = 0xF05F4000) ++********************************************************************************/ ++#define HwTSADC_BASE *(volatile unsigned long *)0xF05F4000 ++ ++/******************************************************************************* ++* 27. Error Correction Code Register Define (Base Addr = 0xF0539000) ++********************************************************************************/ ++#define HwECC_BASE *(volatile unsigned long *)0xF0539000 ++ ++// ECC Control ++#define HwECC_CTRL_IEN_MECC16_EN Hw20 // MLC ECC16 Decoding Interrupt Enable ++#define HwECC_CTRL_IEN_MECC16_DIS ~Hw20 // MLC ECC16 Decoding Interrupt Disable ++#define HwECC_CTRL_IEN_MECC14_EN Hw19 // MLC ECC14 Decoding Interrupt Enable ++#define HwECC_CTRL_IEN_MECC14_DIS ~Hw19 // MLC ECC14 Decoding Interrupt Disable ++#define HwECC_CTRL_IEN_MECC12_EN Hw18 // MLC ECC12 Decoding Interrupt Enable ++#define HwECC_CTRL_IEN_MECC12_DIS ~Hw18 // MLC ECC12 Decoding Interrupt Disable ++#define HwECC_CTRL_IEN_MECC8_EN Hw17 // MLC ECC8 Decoding Interrupt Enable ++#define HwECC_CTRL_IEN_MECC8_DIS ~Hw17 // MLC ECC8 Decoding Interrupt Disable ++#define HwECC_CTRL_IEN_MECC4_EN Hw16 // MLC ECC4 Decoding Interrupt Enable ++#define HwECC_CTRL_IEN_MECC4_DIS ~Hw16 // MLC ECC4 Decoding Interrupt Disable ++ ++// ECC Disable ++#define HwECC_CTRL_EN_SLCEN Hw2 // SLC ECC Encoding Enable ++#define HwECC_CTRL_EN_SLCDE (Hw2|Hw0) // SLC ECC Decoding Enable ++#define HwECC_CTRL_EN_MCL4EN (Hw2|Hw1) // MLC ECC4 Encoding Enable ++#define HwECC_CTRL_EN_MCL4DE (Hw2|Hw1|Hw0) // MLC ECC4 Decoding Enable ++#define HwECC_CTRL_EN_MCL8EN (Hw3) // MLC ECC8 Encoding Enable ++#define HwECC_CTRL_EN_MCL8DE (Hw3|Hw0) // MLC ECC8 Decoding Enable ++#define HwECC_CTRL_EN_MCL12EN (Hw3|Hw1) // MLC ECC12 Encoding Enable ++#define HwECC_CTRL_EN_MCL12DE (Hw3|Hw1|Hw0) // MLC ECC12 Decoding Enable ++#define HwECC_CTRL_EN_MCL14EN (Hw3|Hw2) // MLC ECC14 Encoding Enable ++#define HwECC_CTRL_EN_MCL14DE (Hw3|Hw2|Hw0) // MLC ECC14 Decoding Enable ++#define HwECC_CTRL_EN_MCL16EN (Hw3|Hw2|Hw1) // MLC ECC16 Encoding Enable ++#define HwECC_CTRL_EN_MCL16DE (Hw3|Hw2|Hw1|Hw0) // MLC ECC16 Decoding Enable ++#define HwECC_CTRL_EN_DIS ~(Hw3|Hw2|Hw1|Hw0) // ECC Disable ++ ++// ECC Error Number ++#define HwERR_NUM_ERR1 Hw0 // Correctable Error(SLC), Error Occurred(MLC3), 1 Error Occurred(MLC4) ++#define HwERR_NUM_ERR2 Hw1 // 2 Error Occurred(MLC4) ++#define HwERR_NUM_ERR3 (Hw1|Hw0) // 3 Error Occurred(MLC4) ++#define HwERR_NUM_ERR4 Hw2 // 4 Error Occurred(MLC4) ++#define HwERR_NUM_ERR5 (Hw2|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR6 (Hw2|Hw1) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR7 (Hw2|Hw1|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR8 Hw3 // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR9 (Hw3|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR10 (Hw3|Hw1) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR11 (Hw3|Hw1|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR12 (Hw3|Hw2) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR13 (Hw3|Hw2|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR14 (Hw3|Hw2|Hw1) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR15 (Hw3|Hw2|Hw1|Hw0) // 5 Error Occurred(MLC4) ++#define HwERR_NUM_ERR16 Hw4 // 5 Error Occurred(MLC4) ++#define HwERR_NUM_NOERR HwZERO // No Error ++#define HwERR_NUM_CORIMP (Hw1|Hw0) // Correction Impossible(SLC, MLC4) ++ ++// ECC Interrupt Control ++#define HwECC_IREQ_SEF Hw17 // SLC ECC Encoding Flag Register ++#define HwECC_IREQ_SDF Hw16 // SLC ECC Decoding Flag Register ++#define HwECC_IREQ_M4EF Hw19 // MLC ECC4 Encoding Flag Register ++#define HwECC_IREQ_M4DF Hw18 // MLC ECC4 Decoding Flag Register ++#define HwECC_IREQ_M8EF Hw21 // MLC ECC8 Encoding Flag Register ++#define HwECC_IREQ_M8DF Hw20 // MLC ECC8 Decoding Flag Register ++#define HwECC_IREQ_M12EF Hw23 // MLC ECC12 Encoding Flag Register ++#define HwECC_IREQ_M12DF Hw22 // MLC ECC12 Decoding Flag Register ++#define HwECC_IREQ_M14EF Hw25 // MLC ECC14 Encoding Flag Register ++#define HwECC_IREQ_M14DF Hw24 // MLC ECC14 Decoding Flag Register ++#define HwECC_IREQ_M16EF Hw27 // MLC ECC16 Encoding Flag Register ++#define HwECC_IREQ_M16DF Hw26 // MLC ECC16 Decoding Flag Register ++#define HwECC_IREQ_M4DI Hw2 // MLC ECC4 Decoding Interrupt Request Register ++#define HwECC_IREQ_M8DI Hw4 // MLC ECC8 Decoding Interrupt Request Register ++#define HwECC_IREQ_M12DI Hw6 // MLC ECC12 Decoding Interrupt Request Register ++#define HwECC_IREQ_M14DI Hw8 // MLC ECC14 Decoding Interrupt Request Register ++#define HwECC_IREQ_M16DI Hw10 // MLC ECC16 Decoding Interrupt Request Register ++#define HwECC_IREQ_CLR (Hw27|Hw26|Hw25|Hw24|Hw23|Hw22|Hw21|Hw20|Hw19|Hw18|Hw17|Hw16|Hw10|Hw8|Hw6|Hw4|Hw2) ++ ++/******************************************************************************* ++* 28. Multi-Protocol Encapsulation Forward Error Correction (MPEFEC) ++* Register Define (Base Addr = 0xF0510000) ++********************************************************************************/ ++#define HwMPEFEC_BASE *(volatile unsigned long *)0xF0510000 ++ ++/******************************************************************************* ++* 29. IOBUS Configuration Register Define (Base Addr = 0xF05F5000) ++********************************************************************************/ ++#define HwIOBUSCFG_BASE *(volatile unsigned long *)0xF05F5000 ++#define HwIOBUSCFG ((PIOBUSCFG)&HwIOBUSCFG_BASE) ++ ++// IOBUS AHB 0 ++#define HwIOBUSCFG_USB Hw1 // USB2.0 OTG ++#define HwIOBUSCFG_IDE Hw2 // IDE Controller ++#define HwIOBUSCFG_DMA Hw3 // DMA Controller ++#define HwIOBUSCFG_SD Hw4 // SD/MMC Controller ++#define HwIOBUSCFG_MS Hw6 // Memory Stick Controller ++#define HwIOBUSCFG_I2C Hw7 // I2C Controller ++#define HwIOBUSCFG_NFC Hw8 // NFC Controller ++#define HwIOBUSCFG_EHI0 Hw9 // External Host Interface 0 ++#define HwIOBUSCFG_EHI1 Hw10 // External Host Interface 1 ++#define HwIOBUSCFG_UART0 Hw11 // UART Controller 0 ++#define HwIOBUSCFG_UART1 Hw12 // UART Controller 1 ++#define HwIOBUSCFG_UART2 Hw13 // UART Controller 2 ++#define HwIOBUSCFG_UART3 Hw14 // UART Controller 3 ++#define HwIOBUSCFG_UART4 Hw15 // UART Controller 4 ++#define HwIOBUSCFG_UART5 Hw16 // UART Controller 5 ++#define HwIOBUSCFG_GPSB0 Hw17 // GPSB Controller 0 ++#define HwIOBUSCFG_GPSB1 Hw18 // GPSB Controller 1 ++#define HwIOBUSCFG_GPSB2 Hw19 // GPSB Controller 2 ++#define HwIOBUSCFG_GPSB3 Hw20 // GPSB Controller 3 ++#define HwIOBUSCFG_GPSB4 Hw21 // GPSB Controller 4 ++#define HwIOBUSCFG_GPSB5 Hw22 // GPSB Controller 5 ++#define HwIOBUSCFG_DAI Hw23 // DAI/CDIF Interface ++#define HwIOBUSCFG_ECC Hw24 // ECC Calculator ++#define HwIOBUSCFG_SPDIF Hw25 // SPDIF Tx Controller ++#define HwIOBUSCFG_RTC Hw26 // RTC ++#define HwIOBUSCFG_TSADC Hw27 // TSADC Controller ++#define HwIOBUSCFG_GPS Hw28 // GPS Interface ++#define HwIOBUSCFG_ADMA Hw31 // Audio DMA Controller ++ ++// IOBUS AHB 1 ++#define HwIOBUSCFG_MPE Hw0 // MPE_FEC ++#define HwIOBUSCFG_TSIF Hw1 // TSIF ++#define HwIOBUSCFG_SRAM Hw2 // SRAM Controller ++ ++#define HwIOBUSCFG_STORAGE_ECC ~(Hw17|Hw16) // Storage Bus ++#define HwIOBUSCFG_STORAGE_AHB_BUS1 Hw16 // I/O bus ++#define HwIOBUSCFG_STORAGE_AHB_BUS2 Hw17 // General purpose SRAM or DTCM ++#define HwIOBUSCFG_STORAGE_NFC (Hw17|Hw16) // Main processor data bus ++ ++/************************************************************************ ++* Channel 0 Memory Controller Register Define (Base Addr = 0xF1000000) ++************************************************************************/ ++#define HwEMC_BASE *(volatile unsigned long *)0xF1000000 // External Memory Controller Base Register ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 6 DDI_BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 4. LCD INTERFACE Register Define (Base Addr = 0xF0200000) ++************************************************************************/ ++#define HwLCDC0_BASE *(volatile unsigned long *)0xF0200000 // LCDC0 Control Base Register ++#define HwLCDLUT0_BASE *(volatile unsigned long *)0xF0200400 // LCD LUT 0 Base Register ++#define HwLCDC1_BASE *(volatile unsigned long *)0xF0204000 // LCDC1 Control Base Register ++#define HwLCDLUT1_BASE *(volatile unsigned long *)0xF0204400 // LCD LUT 1 Base Register ++ ++/************************************************************************ ++* 5. LCD System Interface Register Define (Base Addr = 0xF0200400) ++************************************************************************/ ++#define HwLCDSI_BASE *(volatile unsigned long *)0xF020C400 // LCDSI Base Register ++ ++/*********************************************************************** ++* 6. Memory to Memory Scaler Register Define (Base Addr = 0xF0210000/0xF0220000) ++************************************************************************/ ++#define HwM2MSCALER0_BASE *(volatile unsigned long *)0xF0210000 ++#define HwM2MSCALER1_BASE *(volatile unsigned long *)0xF0220000 ++ ++/************************************************************************ ++* 7. NTSC/PAL ENCODER Composite Output Register Define (Base Addr = 0xF0240000) ++************************************************************************/ ++#define HwTVE_BASE *(volatile unsigned long *)0xF0240000 // TV Encoder Base Register ++ ++/************************************************************************ ++* 8. HDMI Register Define (Base Addr = 0xF0254000) ++************************************************************************/ ++//Controller register base address ++#define HwHDMICTRL_BASE *(volatile unsigned long *)0xF0254000 //Controller register base address ++ ++//HDMI register base address ++#define HwHDMICORE_BASE *(volatile unsigned long *)0xF0255000 ++ ++//AES register base address ++#define HwHDMIAES_BASE *(volatile unsigned long *)0xF0256000 //AES register base address ++ ++//SPDIF Receiver register base address ++#define HwHDMISPDIF_BASE *(volatile unsigned long *)0xF0257000 ++ ++//I2S Receiver register base address ++#define HwHDMII2S_BASE *(volatile unsigned long *)0xF0258000 ++ ++ //CEC register base address ++#define HwHDMICEC_BASE *(volatile unsigned long *)0xF0259000 ++ ++/*********************************************************************** ++* 9-1. Camera Interface Register Define (Base Addr = 0xF0230000) ++************************************************************************/ ++#define HwCIF_BASE *(volatile unsigned long *)0xF0230000 // CIF Base Register ++#define HwCIF ((PCIF)&HwCIF_BASE) ++ ++// Input Image Color/Pattern Configuration 1 ++#define HwICPCR1_ON Hw31 // On/Off on CIF >> 0:Can't operate CIF , 1:Operating CIF ++#define HwICPCR1_PWD Hw30 // Power down mode in camera >> 0:Disable, 1:Power down mode , This power down mode is connected the PWDN of camera sensor ++#define HwICPCR1_BPS Hw23 // Bypass Scaler >> 0:Non, 1:Bypass ++#define HwICPCR1_POL Hw21 // PXCLK Polarity >> 0:Positive edge, 1:Negative edge ++#define HwICPCR1_SKPF (Hw20|Hw19|Hw18) // Skip Frame >> 0~7 #Frames skips [20:18] ++#define HwICPCR1_M420_ZERO HwZERO // Format Convert (YUV422->YUV420) , Not-Convert ++#define HwICPCR1_M420_ODD Hw17 // converted in odd line skip ++#define HwICPCR1_M420_EVEN (Hw17|Hw16) // converted in even line skip ++#define HwICPCR1_BP Hw15 // Bypass ++#define HwICPCR1_BBS_LSB8 Hw14 // When bypass 16bits mode, LSB 8bits are stored in first ++#define HwICPCR1_C656 Hw13 // Convert 656 format 0:Disable, 1:Enable ++#define HwICPCR1_CP_RGB Hw12 // RGB(555,565,bayer) color pattern ++#define HwICPCR1_PF_444 HwZERO // 4:4:4 format ++#define HwICPCR1_PF_422 Hw10 // 4:2:2 format ++#define HwICPCR1_PF_420 Hw11 // 4:2:0 format or RGB(555,565,bayer) mode ++#define HwICPCR1_RGBM_BAYER HwZERO // Bayer RGB Mode ++#define HwICPCR1_RGBM_RGB555 Hw8 // RGB555 Mode ++#define HwICPCR1_RGBM_RGB565 Hw9 // RGB565 Mode ++#define HwICPCR1_RGBBM_16 HwZERO // 16bit mode ++#define HwICPCR1_RGBBM_8DISYNC Hw6 // 8bit disable sync ++#define HwICPCR1_RGBBM_8 Hw7 // 8bit mode ++#define HwICPCR1_CS_RGBMG HwZERO // 555RGB:RGB(MG), 565RGB:RGB, 444/422/420:R/Cb/U first, Bayer RGB:BG->GR, CCIR656:YCbYCr ++#define HwICPCR1_CS_RGBLG Hw4 // 555RGB:RGB(LG), 565RGB:RGB, 444/422/420:R/Cb/U first, Bayer RGB:GR->BG, CCIR656:YCrYCb ++#define HwICPCR1_CS_BGRMG Hw5 // 555RGB:BGR(MG), 565RGB:BGR, 444/422/420:B/Cr/V first, Bayer RGB:RG->GB, CCIR656:CbYCrY ++#define HwICPCR1_CS_BGRLG (Hw5|Hw4) // 555RGB:BGR(LG), 565RGB:BGR, 444/422/420:B/Cr/V first, Bayer RGB:GB->RG, CCIR656:CrYCbY ++#define HwICPCR1_BO_SW Hw2 // Switch the MSB/LSB 8bit Bus ++#define HwICPCR1_HSP_HIGH Hw1 // Active high ++#define HwICPCR1_VSP_HIGH Hw0 // Active high ++ ++// CCIR656 Format Configuration 1 ++#define Hw656FCR1_PSL_1ST HwZERO // The status word is located the first byte of EAV & SAV ++#define Hw656FCR1_PSL_2ND Hw25 // The status word is located the second byte of EAV & SAV ++#define Hw656FCR1_PSL_3RD Hw26 // The status word is located the third byte of EAV & SAV ++#define Hw656FCR1_PSL_4TH (Hw26|Hw25) // The status word is located the forth byte of EAV & SAV ++ //FPV [23:16] 0x00FF0000, SPV [15:8] 0x0000FF00, TPV [7:0] 0x000000FF ++// CMOSIF DMA Configuratin 1 ++#define HwCDCR1_TM_INC Hw3 // INC Transfer ++#define HwCDCR1_LOCK_ON Hw2 // Lock Transfer ++#define HwCDCR1_BS_1 HwZERO // The DMA transfers the image data as 1 word to memory ++#define HwCDCR1_BS_2 Hw0 // The DMA transfers the image data as 2 word to memory ++#define HwCDCR1_BS_4 Hw1 // The DMA transfers the image data as 4 word to memory ++#define HwCDCR1_BS_8 (Hw1|Hw0) // The DMA transfers the image data as 8 word to memory (default) ++ ++// FIFO Status ++#define HwFIFOSTATE_CLR Hw21 // Clear FIFO states, 1:Clear, 0:Not Clear ++#define HwFIFOSTATE_REO Hw19 // Overlay FIFO Read ERROR, 1:The empty signal of input overlay FIFO and read enable signal are High, 0:The empty signal of overlay FIFO is low, or empty is High and read enable signal is Low. ++#define HwFIFOSTATE_REV Hw18 // V(B) Channel FiFO Read ERROR, 1:The empty signal of input V(B) channel FIFO and read enable signal are High, 0:The empty signal of V(B) channel FIFO is Low, or empty is High and read enable signal is Low. ++#define HwFIFOSTATE_REU Hw17 // U(R) Channel FiFO Read ERROR, 1:The empty signal of input U(R) channel FIFO and read enable signal are High, 0:The empty signal of U(R) channel FIFO is Low, or empty is High and read enable signal is Low. ++#define HwFIFOSTATE_REY Hw16 // Y(G) Channel FiFO Read ERROR, 1:The empty signal of input Y(G) channel FIFO and read enable signal are High, 0:The empty signal of Y(G) channel FIFO is Low, or empty is High and read enable signal is Low. ++#define HwFIFOSTATE_WEO Hw13 // Overlay FIFO Write ERROR, 1:The full signal of overlay FIFO and write enable signal are High, 0:The full signal of overlay FIFO is Low, or full is High and write enable signal is Low. ++#define HwFIFOSTATE_WEV Hw12 // V(B) Channel FiFO Write ERROR, 1:The full signal of V(B) channel FIFO and write enable signal are High, 0:The full signal of V(B) channel FIFO is Low, or full is High and write enable signal is Low. ++#define HwFIFOSTATE_WEU Hw11 // U(R) Channel FiFO Write ERROR, 1:The full signal of U(R) channel FIFO and write enable signal are High, 0:The full signal of U(R) channel FIFO is Low, or full is High and write enable signal is Low. ++#define HwFIFOSTATE_WEY Hw10 // Y(G) Channel FiFO Write ERROR, 1:The full signal of Y channel FIFO and write enable signal are High, 0:The full signal of Y channel FIFO is Low, or full is High and write enable signal is Low. ++#define HwFIFOSTATE_EO Hw8 // Overlay FIFO Empty Signal, 1:The state of overlay FIFO is empty, 0:The state of overlay FIFO is non-empty. ++#define HwFIFOSTATE_EV Hw7 // V(B) Channel FiFO Empty Signal, 1:The state of V(B) channel FIFO is empty, 0:The state of V(B) channel FIFO is non-empty. ++#define HwFIFOSTATE_EU Hw6 // U(R) Channel FiFO Empty Signal, 1:The state of U(R) channel FIFO is empty, 0:The state of U(R) channel FIFO is non-empty. ++#define HwFIFOSTATE_EY Hw5 // Y(G) Channel FiFO Empty Signal, 1:The state of Y channel FIFO is empty, 0:The state of Y channel FIFO is non-empty. ++#define HwFIFOSTATE_FO Hw3 // Overlay FiFO FULL Signal, 1:The state of overlay FIFO is full, 0:The state of overlay FIFO is non-full. ++#define HwFIFOSTATE_FV Hw2 // V(B) Channel FiFO FULL Signal, 1:The state of V(B) channel FIFO is full, 0:The state of V(B) channel FIFO is non-full. ++#define HwFIFOSTATE_FU Hw1 // U(R) Channel FiFO FULL Signal, 1:The state of U(R) channel FIFO is full, 0:The state of U(R) channel FIFO is non-full. ++#define HwFIFOSTATE_FY Hw0 // Y(G) Channel FiFO FULL Signal, 1:The state of Y(G) channel FIFO is full, 0:The state of Y(G) channel FIFO is non-full. ++ ++// Interrupt & CIF Operating ++#define HwCIRQ_IEN Hw31 // Interrupt Enable 0:interrupt disable, 1:interrupt enable ++#define HwCIRQ_URV Hw30 // Update Register in VSYNC 0:Register is update without VSYNC , 1:When VSYNC is posedge, register is updated. ++#define HwCIRQ_ITY Hw29 // Interrupt Type 0:Pulse type, 1:Hold-up type when respond signal(ICR) is high ++#define HwCIRQ_ICR Hw28 // Interrupt Clear 0:.... , 1:Interrupt Clear (using ITY is Hold-up type) ++#define HwCIRQ_MVN Hw26 // Mask interrupt of VS negative edge, 0:Don't mask, 1:Mask ++#define HwCIRQ_MVP Hw25 // Mask interrupt of VS positive edge, 0:Don't mask, 1:Mask ++#define HwCIRQ_MVIT Hw24 // Mask interrupt of VCNT Interrupt, 0:Don't mask, 1:Mask ++#define HwCIRQ_MSE Hw23 // Mask interrupt of Scaler Error, 0:Don't mask, 1:Mask ++#define HwCIRQ_MSF Hw22 // Mask interrupt of Scaler finish, 0:Don't mask, 1:Mask ++#define HwCIRQ_MENS Hw21 // Mask interrupt of Encoding start, 0:Don't mask, 1:Mask ++#define HwCIRQ_MRLV Hw20 // Mask interrupt of Rolling V address, 0:Don't mask, 1:Mask ++#define HwCIRQ_MRLU Hw19 // Mask interrupt of Rolling U address, 0:Don't mask, 1:Mask ++#define HwCIRQ_MRLY Hw18 // Mask interrupt of Rolling Y address, 0:Don't mask, 1:Mask ++#define HwCIRQ_MSCF Hw17 // Mask interrupt of Capture frame, 0:Don't mask, 1:Mask ++#define HwCIRQ_MSOF Hw16 // Mask interrupt of Stored one frame, 0:Don't mask, 1:Mask ++#define HwCIRQ_VSS Hw12 // Status of vertical sync, Non-vertical sync blank area. ++#define HwCIRQ_VN Hw10 // VS negative, 0:-, 1:When VS is generated if negative edge ++#define HwCIRQ_VP Hw9 // VS positive, 0:-, 1:When VS is generated if positive edge ++#define HwCIRQ_VIT Hw8 // VCNT Interrupt, 0:-, 1:When VCNT is generated.... ++#define HwCIRQ_SE Hw7 // Scaler Error, 0:-, 1:When Scale operation is not correct. ++#define HwCIRQ_SF Hw6 // Scaler Finish, 0:-, 1:When Scale operation is finished ++#define HwCIRQ_ENS Hw5 // Encoding start status, 0:-, 1:When Y address is bigger than encoding start address, this bit is high ++#define HwCIRQ_ROLV Hw4 // Rolling V address status, 0:-, 1:If V address is move to start address, this bit is high ++#define HwCIRQ_ROLU Hw3 // Rolling U address starus, 0:-, 1:If U address is move to start address, this bit is high ++#define HwCIRQ_ROLY Hw2 // Rolling Y address starus, 0:-, 1:If Y address is move to start address, this bit is high ++#define HwCIRQ_SCF Hw1 // Stored captured frame, 0:-, 1:If Captured frame is stored, this bit is high ++#define HwCIRQ_SOF Hw0 // Stored One frame, 0-, 1:If one frame if stored, this bit is high. ++ ++// Overlay Control 1 ++#define HwOCTRL1_OCNT_MAX (Hw29|Hw28|Hw27|Hw26|Hw25|Hw24) //[28:24] Overlay Count FIFO (Hw27|Hw26|Hw25|Hw24|Hw23) ++#define HwOCTRL1_OM_BLOCK Hw16 // Overlay Method 0:Full image overlay, 1:Block image overlay , Full image overlay mode, overlay image size is equal to the input image size. ++#define HwOCTRL1_OE_EN Hw12 // Overlay enable 0:Disable, 1:Enable ++#define HwOCTRL1_XR1_100 Hw10 // XOR in AP1 is 3 (100%) 0:XOR operation, 1:100% , When AP1 is 3 and CEN & AEN is 1, We select the 100% alpha value or XOR. ++#define HwOCTRL1_XR0_100 Hw9 // XOR in AP0 is 3 (100%) 0:XOR operation, 1:100% , When AP0 is 3 and CEN & AEN is 1, We select the 100% alpha value or XOR. ++#define HwOCTRL1_AP1_25 HwZERO // Alpha Value in alpha is 1 // 25% ++#define HwOCTRL1_AP1_50 Hw6 // Alpha Value in alpha is 1 // 50% ++#define HwOCTRL1_AP1_75 Hw7 // Alpha Value in alpha is 1 // 75% ++#define HwOCTRL1_AP1_100 (Hw7|Hw6) // Alpha Value in alpha is 1 // 100% or XOR operation (for XR value) ++#define HwOCTRL1_AP0_25 HwZERO // Alpha Value in alpha is 0 // 25% ++#define HwOCTRL1_AP0_50 Hw4 // Alpha Value in alpha is 0 // 50% ++#define HwOCTRL1_AP0_75 Hw5 // Alpha Value in alpha is 0 // 75% ++#define HwOCTRL1_AP0_100 (Hw5|Hw4) // Alpha Value in alpha is 0 // 100% or XOR operation ++ // When 565RGB and AEN, alpha value is depend on AP0 value. ++#define HwOCTRL1_AEN_EN Hw2 // Alpha enable 0:Disable, 1:Enable ++#define HwOCTRL1_CEN_EN Hw0 // Chroma key enable 0:Disable, 1:Enable ++ ++// Overlay Control 2 ++#define HwOCTRL2_CONV Hw3 // Color Converter Enable 0:Disable, 1:Enable ++#define HwOCTRL2_RGB_565 HwZERO // RGB mode 565RGB ++#define HwOCTRL2_RGB_555 Hw1 // RGB mode 555RGB ++#define HwOCTRL2_RGB_444 Hw2 // RGB mode 444RGB ++#define HwOCTRL2_RGB_332 (Hw2|Hw1) // RGB mode 332RGB ++#define HwOCTRL2_MD Hw0 // Color Mode 0:YUV Color, 1:RGB color ++ ++// Overlay Control 3 -- KEY Value ++#define HwOCTRL3_KEYR_MAX 0x00FF0000 // Chroma-key value R(U), Chroea-key value in R(U) channel, Default value is 0x00 ++#define HwOCTRL3_KEYG_MAX 0x0000FF00 // Chroma-key value G(Y), Chroea-key value in G(Y) channel, Default value is 0x00 ++#define HwOCTRL3_KEYB_MAX 0x000000FF // Chroma-key value B(V), Chroea-key value in B(V) channel, Default value is 0x00 ++ ++// Overlay Control 4 -- Mask KEY Value ++#define HwOCTRL4_MKEYR_MAX 0x00FF0000 // Mask Chroma-key value R(U), Chroea-key value in R(U) channel, Default value is 0x00 ++#define HwOCTRL4_MKEYG_MAX 0x0000FF00 // Mask Chroma-key value G(Y), Chroea-key value in G(Y) channel, Default value is 0x00 ++#define HwOCTRL4_MKEYB_MAX 0x000000FF // Mask Chroma-key value B(V), Chroea-key value in B(V) channel, Default value is 0x00 ++ ++// Camera Down Scaler ++#define HwCDS_SFH_1 HwZERO // Horizontal Scale Factor, 1/1 down scale ++#define HwCDS_SFH_2 Hw4 // Horizontal Scale Factor, 1/2 down scale ++#define HwCDS_SFH_4 Hw5 // Horizontal Scale Factor, 1/4 down scale ++#define HwCDS_SFH_8 (Hw5|Hw4) // Horizontal Scale Factor, 1/8 down scale ++#define HwCDS_SFV_1 HwZERO // Vertical Scale Factor, 1/1 down scale ++#define HwCDS_SFV_2 Hw2 // Vertical Scale Factor, 1/2 down scale ++#define HwCDS_SFV_4 Hw3 // Vertical Scale Factor, 1/4 down scale ++#define HwCDS_SFV_8 (Hw3|Hw2) // Vertical Scale Factor, 1/8 down scale ++#define HwCDS_SEN_EN Hw0 // Scale enable, 0:Disable, 1:enable ++ ++// CMOSIF Capture mode1 ++#define HwCCM1_ENCNUM 0xF0000000 // Encode INT number (using CAP mode) [31:28], value area (0~15), Encode interrupt number ++#define HwCCM1_ROLNUMV 0x0F000000 // Rolling number in V (using CAP mode) [27:24], value area (0~15), Rolling number ++#define HwCCM1_ROLNUMU 0x00F00000 // Rolling number in U (using CAP mode) [23:20], value area (0~15), Rolling number ++#define HwCCM1_ROLNUMY 0x000F0000 // Rolling number in Y (using CAP mode) [19:16], value area (0~15), Rolling number ++#define HwCCM1_CB Hw10 // Capture Busy, 0:-, 1:Capture busy ++#define HwCCM1_EIT Hw9 // Encodig INT count, 0:Always 1 pulse, 1:Counting encoding INT ++#define HwCCM1_UES Hw8 // Using Encoding Start Address, 0:disable, 1:Enable ++#define HwCCM1_SKIPNUM 0x000000F0 // Skip frame number (using CAP mode) [7:4], value area (0~15), Skip frame number ++#define HwCCM1_RLV Hw3 // Rolling address V, 0:disable, 1:Enable ++#define HwCCM1_RLU Hw2 // Rolling address U, 0:disable, 1:Enable ++#define HwCCM1_RLY Hw1 // Rolling address Y, 0:disable, 1:Enable ++#define HwCCM1_CAP Hw0 // Image Capture, 0:Normal, 1:Image Capture ++ ++// CMOSIF Capture mode2 ++#define HwCCM2_VCNT 0x000000F0 // Description (Using CAP mode) [7:4], Threshold line counter in interrupt 1:16 line, 2:32 line, 3: 48 line... ++#define HwCCM2_VEN Hw0 // VCNT folling enable (Using CAP mode) 0:Normal(?) Disalbe¾Æ´Ñ°¡?, 1:Enable ++ ++// CMOSIF R2Y confiquration ++#define HwCR2Y_FMT (Hw4|Hw3|Hw2|Hw1) // FMT[4:1] 0000 -> Input format 16bit 565RGB(RGB sequence) ÀÚ¼¼ÇÑ »çÇ× 750A CIF SPEC. 1-22 ++#define HwCR2Y_EN Hw0 // R2Y Enable, 0:disable, 1:Enable ++ ++// CMOSIF Current Line Count ++#define HwCCLC_LCNT 0x0000FFFF // LCNT[15:0] Current Line Count ++ ++ ++ ++/*********************************************************************** ++* 9-2. Effect Register Define (Base Addr = 0xF0230100) ++************************************************************************/ ++#define HwCEM_BASE *(volatile unsigned long *)0xF0230100 //W/R 0x00000000 Effect mode register ++#define HwCEM ((PEFFECT)&HwCEM_BASE) ++ ++// CMOSIF Effect mode ++#define HwCEM_UVS Hw15 // UV Swap 0:u-v-u-v sequence, 1:v-u-v-u sequence ++#define HwCEM_VB Hw14 // V Bias (V channel value offset), 0:disable, 1:Enable ++#define HwCEM_UB Hw13 // U Bias (U channel value offset), 0:disable, 1:Enable ++#define HwCEM_YB Hw12 // Y Bias (Y channel value offset), 0:disable, 1:Enable ++#define HwCEM_YCS Hw11 // YC Swap 0:u-y-v-y sequence, 1:y-u-y-v sequence ++#define HwCEM_IVY Hw10 // Invert Y, 0:disable, 1:Enable ++#define HwCEM_STC Hw9 // Strong C, 0:disable, 1:Enable ++#define HwCEM_YCL Hw8 // Y Clamp (Y value clipping), 0:disable, 1:Enable ++#define HwCEM_CS Hw7 // C Select (Color filter), 0:disable, 1:Enable(Color filter) ++#define HwCEM_SKT Hw6 // Sketch Enable, 0:disable, 1:Enable ++#define HwCEM_EMM Hw5 // Emboss mode, 0:Positive emboss, 1:Negative emboss ++#define HwCEM_EMB Hw4 // Emboss, 0:disable, 1:Enable ++#define HwCEM_NEGA Hw3 // Negative mode, 0:disable, 1:Enable ++#define HwCEM_GRAY Hw2 // Gray mode, 0:disable, 1:Enable ++#define HwCEM_SEPI Hw1 // Sepia mode, 0:disable, 1:Enable ++#define HwCEM_NOR Hw0 // Normal mode, 0:Effect mode, 1:Normal mode ++ ++// CMOSIF Sepia UV Setting ++#define HwHwCSUV_SEPIA_U 0x0000FF00 // SEPIA_U[15:8] U channel threshold value for sepia ++#define HwHwCSUV_SEPIA_V 0x000000FF // SEPIA_V[7:0] V channel threshold value for sepia ++ ++// CMOSIF Color selection ++#define HwCCS_USTART 0xFF000000 // USTART [31:24] Color filter range start point of U channel ++#define HwCCS_UEND 0x00FF0000 // UEND [23:16] Color filter range end point of U channel ++#define HwCCS_VSTART 0x0000FF00 // VSTART [15:8] Color filter range start point of V channel ++#define HwCCS_VEND 0x000000FF // VEND [7:0] Color filter range end point of V channel ++ ++// CMOSIF H-filter coefficent ++#define HwCHFC_COEF0 0x00FF0000 // COEF0 [23:16] Horizontal filter coefficient0 for emboss or sketch ++#define HwCHFC_COEF1 0x0000FF00 // COEF1 [15:8] Horizontal filter coefficient1 for emboss or sketch ++#define HwCHFC_COEF2 0x000000FF // COEF2 [7:0] Horizontal filter coefficient2 for emboss or sketch ++ ++// CMOSIF Sketch threshold ++#define HwCST_THRESHOLD 0x000000FF // Sketch [7:0] Sketch threshold ++ ++// CMOSIF Clamp threshold ++#define HwCCT_THRESHOLD 0x000000FF // Clamp [7:0] Clamp threshold ++ ++// CMOSIF BIAS ++#define HwCBR_YBIAS 0x00FF0000 // Y_BIAS [23:16] Y value offset ++#define HwCBR_UBIAS 0x0000FF00 // U_BIAS [15:8] U value offset ++#define HwCBR_VBIAS 0x000000FF // V_BIAS [7:0] V value offset ++ ++// CMOSIF Image size ++#if defined (SENSOR_3M) || defined (SENSOR_5M) ++#define HwCEIS_HSIZE 0x0FFF0000 // HSIZE [26:16] Horizontal size of input image ++#else ++#define HwCEIS_HSIZE 0x07FF0000 // HSIZE [26:16] Horizontal size of input image ++#endif ++#define HwCEIS_VSIZE 0x000007FF // VSIZE [10:0] Vertical size of input image ++ ++#define HwCIC_H2H_WAIT 0xFFFF0000 // H2H_WAIT [31:16] Horizontal sync (hs)to hs wait cycle ++#define HwCIC_STB_CYCLE 0x0000FF00 // STB_CYCLE [15:8] CCIR strobe cycle, Minimum Value of STB_CYCLE is 4. ++#define HwCIC_INP_WAIT (Hw6|Hw5|Hw4) // INP_WAIT [6:4] ??????????????? ++#define HwCIC_INPR Hw3 // ??????????????? ++#define HwCIC_FA Hw2 // Flush all ++#define HwCIC_INE Hw1 // Inpath Enalbe, 0:disable, 1:Enable ++#define HwCIC_INP Hw0 // Inpath Mode, 0:Camera mode, 1:Memory mode ++ ++// Y°ªÀº 32Àüü¸¦ ´Ù ¼¼ÆÃÇϵµ·Ï ÇÏ°í U, V°ªÀº »óÀ§ 4bit´Â »ý·«Çصµ cif¿¡¼­ address¸¦ ÃßÁ¤ÇÏ´Â °ÍÀÌ °¡´ÉÇÏ´Ù. ++// HwCISA1_SRC_BASE´Â Y°ª¸¸ 4ºñÆ® ´õ Á¸ÀçÇؼ­ ±¸º°ÇØ ³õÀº °ÍÀÓ ,, ½ÇÁ¦·Î »ç¿ëÇÒ °æ¿ì ±×³É 32 address¸¦ ÇÒ´ç ÇÑ´Ù. ++// CMOSIF INPATH Source address in Y channel ++#define HwCISA1_SRC_BASE 0xF0000000 // SRC_BASE [31:28] Source base address (31 down to 28 bit assign in base address) ++#define HwCISA1_SRC_BASE_Y 0x0FFFFFFF // SRC_BASE_Y [27:0] Source base address in Y channel (27 down to 0 bit assign in bass address) ++ ++// CMOSIF INPATH Source address in U channel ++#define HwCISA2_SRC_TYPE_422SEQ0 HwZERO // 0: (4:2:2 SEQ0) ++#define HwCISA2_SRC_TYPE_422SEQ1 Hw28 // 1: (4:2:2 SEQ1) ++#define HwCISA2_SRC_TYPE_422SEPA Hw29 // 2: (4:2:2 Separate) ++#define HwCISA2_SRC_TYPE_420SEPA (Hw29|Hw28) // 3: (4:2:0 Separate) ++#define HwCISA2_SRC_BASE_U 0x0FFFFFFF // SRC_BASE_U [27:0] Source base address in U channal (27 down to 0 bit assign in base address) ++ ++// CMOSIF INPATH Source address in V channel ++#define HwCISA3_SRC_BASE_V 0x0FFFFFFF // SRC_BASE_V [27:0] Source base address in V channal (27 down to 0 bit assign in base address) ++ ++ ++// CMOSIF INPATH Source image offset ++//#define HwCISO_SRC_OFFSET_H 0x0FFF0000 // SRC_OFFSET_H [27:16] source address offset in H ++//#define HwCISO_SRC_OFFSET_V 0x00000FFF // SRC_OFFSET_V [11:0] source address offset in V ++#define HwCISO_SRC_OFFSET_Y 0x0FFF0000 // SRC_OFFSET_Y [27:16] source address offset in Y channel ++#define HwCISO_SRC_OFFSET_C 0x00000FFF // SRC_OFFSET_C [11:0] source address offset in C channel ++ ++// CMOSIF INPATH Source image size ++#define HwCISS_SRC_HSIZE 0x0FFF0000 // SRC_HSIZE [27:16] Horizontal size in source image ++#define HwCISS_SRC_VSIZE 0x00000FFF // SRC_VSIZE [11:0] Vertical size in source image ++ ++ ++// CMOSIF INPATH Destination image size ++#define HwCIDS_DST_HSIZE 0x0FFF0000 // DST_HSIZE [27:16] Horizontal size in destination image ++#define HwCIDS_DST_VSIZE 0x00000FFF // DST_VSIZE [11:0] Vertical size in destination image ++ ++// HSCALE = SRC_HSIZE*256/DST_HSIZE ++// VSCALE = SRC_VSIZE*256/DST_VSIZE ++// CMOSIF INPATH Target scale ++#define HwCIS_HSCALE 0x3FFF0000 // HSCALE [29:16] Horizontal scale factor ++#define HwCIS_VSCALE 0x00003FFF // VSCALE [13:0] Vertical scale factor ++ ++ ++ ++/*********************************************************************** ++* 9-3. Scaler Register Define (Base Addr = 0xF0230200) ++************************************************************************/ ++#define HwCSC_BASE *(volatile unsigned long *)0xF0230200 //W/R 0x00000000 Scaler configuration ++#define HwCSC ((PCIFSCALER)&HwCSC_BASE) ++ ++// Scaler configuration ++#define HwSCC_EN Hw0 // Scaler Enable 0:disable, 1:Enable ++ ++// HSCALE = SRC_HSIZE*256/DST_HSIZE ++// VSCALE = SRC_VSIZE*256/DST_VSIZE ++// Scale factor ++#define HwSCSF_HSCALE 0x3FFF0000 // HSCALE [29:16] Horizontal scale factor ++#define HwSCSF_VSCALE 0x00003FFF // VSCALE [13:0] Vertical scale factor ++ ++// Image offset ++#define HwSCSO_OFFSET_H 0x0FFF0000 // H [27:16] Horizontal offset ++#define HwSCSO_OFFSET_V 0x00000FFF // V [11:0] Vertical offset ++ ++// Source image size ++#define HwSCSS_HSIZE 0x0FFF0000 // H [27:16] Horizontal size in source image ++#define HwSCSS_VSIZE 0x00000FFF // V [11:0] Vertical size in source image ++ ++// Destination image size ++#define HwSCDS_HSIZE 0x0FFF0000 // H [27:16] Horizontal size in destination image ++#define HwSCDS_VSIZE 0x00000FFF // V [11:0] Vertical size in destination image ++ ++/*********************************************************************** ++* 10. Video and Image Quality Enhancer Register Define (Base Addr = 0xF0230200) ++************************************************************************/ ++#define HwVIQE_BASE *(volatile unsigned long *)0xF0252000 ++ ++/*********************************************************************** ++* 11. LVDS Register Define (Base Addr = 0xF0230200) ++************************************************************************/ ++#define HwDDI_CONFIG_BASE *(volatile unsigned long *)0xF0251000 ++#define HwDDI_CONFIG ((PDDICONFIG)&HwDDI_CONFIG_BASE) ++ ++// HDMI Control register ++#define HwDDIC_HDMI_CTRL_EN Hw15 ++#define HwDDIC_HDMI_CTRL_SEL_LCDC0 HwZERO ++#define HwDDIC_HDMI_CTRL_SEL_LCDC1 Hw14 ++#define HwDDIC_HDMI_CTRL_RST_HDMI Hw0 ++#define HwDDIC_HDMI_CTRL_RST_SPDIF Hw1 ++#define HwDDIC_HDMI_CTRL_RST_TMDS Hw2 ++#define HwDDIC_HDMI_CTRL_RST_NOTUSE Hw3 ++ ++// Power Down ++#define HwDDIC_PWDN_HDMI Hw8 // HDMI Interface ++#define HwDDIC_PWDN_DDIC Hw7 // DDIBUS Cache ++#define HwDDIC_PWDN_MSCL1 Hw6 // Memory Scaler 1 ++#define HwDDIC_PWDN_MSCL0 Hw5 // Memory Scaler 0 ++#define HwDDIC_PWDN_LCDSI Hw4 // LCDSI Interface ++#define HwDDIC_PWDN_LCDC1 Hw3 // LCD 1 Interface ++#define HwDDIC_PWDN_LCDC0 Hw2 // LCD 0 Interface ++#define HwDDIC_PWDN_VIQE Hw1 // Video Image Quality Enhancer ++#define HwDDIC_PWDN_CIF Hw0 // Camera Interface ++ ++// Soft Reset ++#define HwDDIC_SWRESET_HDMI Hw8 // HDMI Interface ++#define HwDDIC_SWRESET_DDIC Hw7 // DDIBUS Cache ++#define HwDDIC_SWRESET_MSCL1 Hw6 // Memory Scaler 1 ++#define HwDDIC_SWRESET_MSCL0 Hw5 // Memory Scaler 0 ++#define HwDDIC_SWRESET_LCDSI Hw4 // LCDSI Interface ++#define HwDDIC_SWRESET_LCDC1 Hw3 // LCD 1 Interface ++#define HwDDIC_SWRESET_LCDC0 Hw2 // LCD 0 Interface ++#define HwDDIC_SWRESET_VIQE Hw1 // Video Image Quality Enhancer ++#define HwDDIC_SWRESET_CIF Hw0 // Camera Interface ++ ++#define HwDDI_CACHE_BASE *(volatile unsigned long *)0xF0250000 ++#define HwDDI_CACHE ((PDDICACHE)&HwDDI_CACHE_BASE) ++ ++// DDI CACHE Control ++#define HwDDIC_CTRL_BW Hw31 ++#define HwDDIC_CTRL_CIF_DMA Hw25 ++#define HwDDIC_CTRL_VIQE_DMA2_2 Hw24 ++#define HwDDIC_CTRL_VIQE_DMA2_1 Hw23 ++#define HwDDIC_CTRL_VIQE_DMA2_0 Hw22 ++#define HwDDIC_CTRL_VIQE_DMA1_2 Hw21 ++#define HwDDIC_CTRL_VIQE_DMA1_1 Hw20 ++#define HwDDIC_CTRL_VIQE_DMA1_0 Hw19 ++#define HwDDIC_CTRL_VIQE_DMA0_2 Hw18 ++#define HwDDIC_CTRL_VIQE_DMA0_1 Hw17 ++#define HwDDIC_CTRL_VIQE_DMA0_0 Hw16 ++#define HwDDIC_CTRL_MSCL1_DMA2 Hw15 ++#define HwDDIC_CTRL_MSCL1_DMA1 Hw14 ++#define HwDDIC_CTRL_MSCL1_DMA0 Hw13 ++#define HwDDIC_CTRL_MSCL0_DMA2 Hw12 ++#define HwDDIC_CTRL_MSCL0_DMA1 Hw11 ++#define HwDDIC_CTRL_MSCL0_DMA0 Hw10 ++#define HwDDIC_CTRL_LCD1_DMA2 Hw9 ++#define HwDDIC_CTRL_LCD1_DMA1 Hw8 ++#define HwDDIC_CTRL_LCD1_DMA0_2 Hw7 ++#define HwDDIC_CTRL_LCD1_DMA0_1 Hw6 ++#define HwDDIC_CTRL_LCD1_DMA0_0 Hw5 ++#define HwDDIC_CTRL_LCD0_DMA2 Hw4 ++#define HwDDIC_CTRL_LCD0_DMA1 Hw3 ++#define HwDDIC_CTRL_LCD0_DMA0_2 Hw2 ++#define HwDDIC_CTRL_LCD0_DMA0_1 Hw1 ++#define HwDDIC_CTRL_LCD0_DMA0_0 Hw0 ++ ++// DDI CACHE Configuration ++#define HwDDIC_CFG_CIF_DMA (25) ++#define HwDDIC_CFG_VIQE_DMA2_2 (24) ++#define HwDDIC_CFG_VIQE_DMA2_1 (23) ++#define HwDDIC_CFG_VIQE_DMA2_0 (22) ++#define HwDDIC_CFG_VIQE_DMA1_2 (21) ++#define HwDDIC_CFG_VIQE_DMA1_1 (20) ++#define HwDDIC_CFG_VIQE_DMA1_0 (19) ++#define HwDDIC_CFG_VIQE_DMA0_2 (18) ++#define HwDDIC_CFG_VIQE_DMA0_1 (17) ++#define HwDDIC_CFG_VIQE_DMA0_0 (16) ++#define HwDDIC_CFG_MSCL1_DMA2 (15) ++#define HwDDIC_CFG_MSCL1_DMA1 (14) ++#define HwDDIC_CFG_MSCL1_DMA0 (13) ++#define HwDDIC_CFG_MSCL0_DMA2 (12) ++#define HwDDIC_CFG_MSCL0_DMA1 (11) ++#define HwDDIC_CFG_MSCL0_DMA0 (10) ++#define HwDDIC_CFG_LCD1_DMA2 (9) ++#define HwDDIC_CFG_LCD1_DMA1 (8) ++#define HwDDIC_CFG_LCD1_DMA0_2 (7) ++#define HwDDIC_CFG_LCD1_DMA0_1 (6) ++#define HwDDIC_CFG_LCD1_DMA0_0 (5) ++#define HwDDIC_CFG_LCD0_DMA2 (4) ++#define HwDDIC_CFG_LCD0_DMA1 (3) ++#define HwDDIC_CFG_LCD0_DMA0_2 (2) ++#define HwDDIC_CFG_LCD0_DMA0_1 (1) ++#define HwDDIC_CFG_LCD0_DMA0_0 (0) ++ ++#define HwDDIC_CFG_MASK (0x1F) ++#define HwDDIC_CFG26(X) ((X)<<16) ++#define HwDDIC_CFG27(X) ((X)<<24) ++#define HwDDIC_CFG28(X) ((X)) ++#define HwDDIC_CFG29(X) ((X)<<8) ++#define HwDDIC_CFG30(X) ((X)<<16) ++#define HwDDIC_CFG31(X) ((X)<<24) ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 7 VIDEO BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/*********************************************************************** ++* 4. VIDEO CODEC Register Define (Base Addr = 0x0xF0700000) ++************************************************************************/ ++#define HwVIDEOCODEC_BASE *(volatile unsigned long *)0xF0700000 ++ ++/*********************************************************************** ++* 5. JPEG CODEC Register Define (Base Addr = 0x0xF0710000/0xF0720000) ++************************************************************************/ ++#define HwJPEGDECODER_BASE *(volatile unsigned long *)0xF0710000 ++#define HwJPEGENCODER_BASE *(volatile unsigned long *)0xF0720000 ++#define HwVIDEOCACHE_BASE *(volatile unsigned long *)0xF0701000 ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 8 GRAPHIC BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/*********************************************************************** ++* 4. Overlay Mixer Register Define (Base Addr = 0xF0010000) ++************************************************************************/ ++#define HwOVERLAYMIXER_BASE *(volatile unsigned long *)0xF0010000 ++ ++/******************************************************************************* ++* 5-1. 2D/3D GPU ++* ++* Pixel Processor Register Map Register Define (Base Addr = 0xF0000000) ++********************************************************************************/ ++#define HwPIXELPROCESSOR_BASE *(volatile unsigned long *)0xF0000000 ++ ++/******************************************************************************* ++* 5-2. Geometry Processor Register Map Register Define (Base Addr = 0xF0000000) ++********************************************************************************/ ++#define HwGEOMETRYPROCESSOR_BASE *(volatile unsigned long *)0xF0002000 ++ ++/******************************************************************************* ++* 5-3. MMU Configuration Register Define (Base Addr = 0xF0003000) ++********************************************************************************/ ++#define HwMMUCONFIG_BASE *(volatile unsigned long *)0xF0003000 ++ ++/******************************************************************************* ++* 5-4. GRPBUS Configuration Register Define (Base Addr = 0xF0004000) ++********************************************************************************/ ++#define HwGRPBUS_BASE *(volatile unsigned long *)0xF0004000 ++ ++/******************************************************************************* ++* 5-5. GRPBUS BWRAP Register Define (Base Addr = 0xF0005000) ++********************************************************************************/ ++#define HwGRPBUSBWRAP_BASE *(volatile unsigned long *)0xF0005000 ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/include/mach/TCC89x_Structures.h b/arch/arm/mach-tcc8900/include/mach/TCC89x_Structures.h +new file mode 100644 +index 0000000..381d0cd +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/TCC89x_Structures.h +@@ -0,0 +1,3276 @@ ++/**************************************************************************** ++ * FileName : TCC89x_Structures.h ++ * Description : ++ **************************************************************************** ++* ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++* ++ ****************************************************************************/ ++ ++ ++/************************************************************************ ++* TCC89x Internal Register Definition File ++************************************************************************/ ++#ifndef __TCC89xSTRUCTURES_H__ ++#define __TCC89xSTRUCTURES_H__ ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 2 SMU & PMU_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 1. Clock Controller Register Define (Base Addr = 0xF0400000) // R/W ++************************************************************************/ ++//--------------------------------------------------------------------------------------------- ++//31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ++// |CFGEN|MODE | NCKOE/DPRD | ++//15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ++// NCKOE/DMIN | NCKOE/DMAX | NCKOE/DCDIV | | CKSEL | ++//---------------------------------------------------------------------------------------------- ++//CLK_BASE *(volatile unsigned long *)0xF0400000 ++ ++typedef struct _CKC{ ++ volatile unsigned int CLK0CTRL; // 0x00 R/W 0x2FFFF4 CPU & Bus Clock0 Control Register ++ volatile unsigned int CLK1CTRL; // 0x04 R/W 0x2FFFF4 CPU & Bus Clock1 Control Register ++ volatile unsigned int CLK2CTRL; // 0x08 R/W 0x2FFFF4 CPU & Bus Clock2 Control Register ++ volatile unsigned int CLK3CTRL; // 0x0C R/W 0x2FFFF4 CPU & Bus Clock3 Control Register ++ volatile unsigned int CLK4CTRL; // 0x10 R/W 0x2FFFF4 CPU & Bus Clock4 Control Register ++ volatile unsigned int CLK5CTRL; // 0x14 R/W 0x2FFFF4 CPU & Bus Clock5 Control Register ++ volatile unsigned int CLK6CTRL; // 0x18 R/W 0x2FFFF4 CPU & Bus Clock6 Control Register ++ volatile unsigned int CLK7CTRL; // 0x1C R/W 0x2FFFF4 CPU & Bus Clock 7Control Register ++ volatile unsigned int PLL0CFG; // 0x20 R/W 0x8010FA03 PLL0 Configuration Register ++ volatile unsigned int PLL1CFG; // 0x24 R/W 0x80009603 PLL1 Configuration Register ++ volatile unsigned int PLL2CFG; // 0x28 R/W 0x80007D03 PLL2 Configuration Register ++ volatile unsigned int PLL3CFG; // 0x2C R/W 0x80009603 PLL3 Configuration Register ++ volatile unsigned int CLKDIVC; // 0x30 R/W 0x81818181 PLL Divider Configuration Register ++ volatile unsigned int CLKDIVC1; // 0x34 R/W 0x00008181 External Clock Divider Configuration Register ++ volatile unsigned int CLKDIVC2; //- 0x38 Reserved ++ volatile unsigned int CLKDIVC3; //- 0x3C Reserved ++ volatile unsigned int SWRESETPRD; // 0x40 R/W 0x000000FF Software Reset Period Register ++ volatile unsigned int SWRESET; // 0x44 R/W 0x00000000 Software Reset Control Register ++ volatile unsigned int NOTDEFINE0[14]; //- 0x48-0x7C Reserved ++ volatile unsigned int PCLK_TCX; // 0x80 R/W 0x00014000 Timer Counter 0 Oscillator-Clock Control Register ++ volatile unsigned int PCLK_TCT; // 0x84 R/W 0x00014000 Timer Counter 0 Clock Control Register ++ volatile unsigned int PCLK_TCZ; // 0x88 R/W 0x00014000 Timer Counter 1 Clock Control Register ++ volatile unsigned int PCLK_LCD0; // 0x8C R/W 0x00014000 LCD0 Clock Control Register ++ volatile unsigned int PCLK_LCD1; // 0x90 R/W 0x00014000 LCD1 Clock Control Register ++ volatile unsigned int PCLK_LCDSI; // 0x94 R/W 0x00014000 LCDSI Clock Control Register ++ volatile unsigned int PCLK_CIFMC; // 0x98 R/W 0x00014000 Control Register for CIF Internal Clock ++ volatile unsigned int PCLK_CIFSC; // 0x9C R/W 0x00014000 Control Register for CIF Scaler Clock ++ volatile unsigned int PCLK_OUT0; // 0xA0 R/W 0x00014000 Control Register for External Clock Output 0 ++ volatile unsigned int PCLK_OUT1; // 0xA4 R/W 0x00014000 Control Register for External Clock Output 1 ++ volatile unsigned int PCLK_HDMI; // 0xA8 R/W 0x00014000 Control Register for HDMI PHY Input Clock ++ volatile unsigned int PCLK_USB11H; // 0xAC R/W 0x00014000 Control Register for USB 1.1 Host ++ volatile unsigned int PCLK_SDMMC0; // 0xB0 R/W 0x00014000 Control Register for SD/MMC Channel 0 ++ volatile unsigned int PCLK_MSTICK; // 0xB4 R/W 0x00014000 Memory Stick Clock Control Register ++ volatile unsigned int PCLK_I2C; // 0xB8 R/W 0x00014000 I2C Clock Control Register ++ volatile unsigned int PCLK_UART0; // 0xBC R/W 0x00014000 UART0 Clock Control Register ++ volatile unsigned int PCLK_UART1; // 0xC0 R/W 0x00014000 UART1 Clock Control Register ++ volatile unsigned int PCLK_UART2; // 0xC4 R/W 0x00014000 UART2 Clock Control Register ++ volatile unsigned int PCLK_UART3; // 0xC8 R/W 0x00014000 UART3 Clock Control Register ++ volatile unsigned int PCLK_UART4; // 0xCC R/W 0x00014000 UART4 Clock Control Register ++ volatile unsigned int PCLK_UART5; // 0xD0 R/W 0x00014000 UART5 Clock Control Register ++ volatile unsigned int PCLK_GPSB0; // 0xD4 R/W 0x00014000 Control Register for GPSB Channel 0 ++ volatile unsigned int PCLK_GPSB1; // 0xD8 R/W 0x00014000 Control Register for GPSB Channel 1 ++ volatile unsigned int PCLK_GPSB2; // 0xDC R/W 0x00014000 Control Register for GPSB Channel 2 ++ volatile unsigned int PCLK_GPSB3; // 0xE0 R/W 0x00014000 Control Register for GPSB Channel 3 ++ volatile unsigned int PCLK_GPSB4; // 0x0E4 R/W 0x14000000 Control Register for GPSB Channel 4 ++ volatile unsigned int PCLK_GPSB5; // 0xE8 R/W 0x00014000 Control Register for GPSB Channel 5 ++ volatile unsigned int PCLK_ADC; // 0xEC R/W 0x00014000 Control Register for ADC (Touch Screen) ++ volatile unsigned int PCLK_SPDIF; // 0xF0 R/W 0x00140000 Control Register for SPDIF ++ volatile unsigned int PCLK_EHI0; // 0xF4 R/W 0x00140000 Control Register for EHI Channel 0 ++ volatile unsigned int PCLK_EHI1; // 0x0F8 R/W 0x14000000 Control Register for EHI Channel 1 ++ volatile unsigned int PCLK_AUD; // 0xFC R/W 0x00014000 Control Register for Audio DMA ++ volatile unsigned int PCLK_CAN ; // 0x100 R/W 0x00014000 Control Register for CAN ++ volatile unsigned int NOTDEFINE1; // 0x104 R/W 0x00140000 Reserved ++ volatile unsigned int PCLK_SDMMC1; // 0x108 R/W 0x00014000 Control Register for SD/MMC Channel 1 ++ volatile unsigned int NOTDEFINE2; // 0x10C R/W 0x00014000 Reserved ++ volatile unsigned int PCLK_DAI ; // 0x110 R/W 0x00014000 Control Register for DAI (DAI Only) ++}CKC, *PCKC; ++ ++/************************************************************************ ++* 2. Vectored Priority Interrupt Controller Register Map(Base Addr = 0xF0401000) ++************************************************************************/ ++//#define HwPIC_BASE *(volatile unsigned long *)0xF0401000 ++typedef struct _PIC{ ++ volatile unsigned int IEN0; // 0x000 R/W 0x00000000 Interrupt Enable0 Register ++ volatile unsigned int IEN1; // 0x004 R/W 0x00000000 Interrupt Enable1 Register ++ volatile unsigned int CLR0; // 0x008 R/W 0x00000000 Interrupt Clear0 Register ++ volatile unsigned int CLR1; // 0x00C R/W 0x00000000 Interrupt Clear1 Register ++ volatile unsigned int STS0; // 0x010 R Unknown Interrupt Status0 Register ++ volatile unsigned int STS1; // 0x014 R Unknown Interrupt Status1 Register ++ volatile unsigned int SEL0; // 0x018 R/W 0x00000000 IRQ or FIR Selection0 Register ++ volatile unsigned int SEL1; // 0x01C R/W 0x00000000 IRQ or FIR Selection1 Register ++ volatile unsigned int SRC0; // 0x020 R Unknown Source Interrupt Status0 Register ++ volatile unsigned int SRC1; // 0x024 R Unknown Source Interrupt Status1 Register ++ volatile unsigned int MSTS0; // 0x028 R 0x00000000 Masked Status0 Register ++ volatile unsigned int MSTS1; // 0x02C R 0x00000000 Masked Status1 Register ++ volatile unsigned int TIG0; // 0x030 R/W 0x00000000 Test Interrupt Generation0 Register ++ volatile unsigned int TIG1; // 0x034 R/W 0x00000000 Test Interrupt Generation1 Register ++ volatile unsigned int POL0; // 0x038 R/W 0x00000000 Interrupt Polarity0 Register ++ volatile unsigned int POL1; // 0x03C R/W 0x00000000 Interrupt Polarity1 Register ++ volatile unsigned int IRQ0; // 0x040 R 0x00000000 IRQ Raw Status0 Register ++ volatile unsigned int IRQ1; // 0x044 R 0x00000000 IRQ Raw Status1 Register ++ volatile unsigned int FIQ0; // 0x048 R Unknown FIQ Status0 Register ++ volatile unsigned int FIQ1; // 0x04C R Unknown FIQ Status1 Register ++ volatile unsigned int MIRQ0; // 0x050 R 0x00000000 Masked IRQ Status0 Register ++ volatile unsigned int MIRQ1; // 0x054 R 0x00000000 Masked IRQ Status1 Register ++ volatile unsigned int MFIQ0; // 0x058 R 0x00000000 Masked FIQ Status0 Register ++ volatile unsigned int MFIQ1; // 0x05C R 0x00000000 Masked FIQ Status1 Register ++ volatile unsigned int MODE0; // 0x060 R/W 0x00000000 Trigger Mode0 Register ? Level or Edge ++ volatile unsigned int MODE1; // 0x064 R/W 0x00000000 Trigger Mode1 Register ? Level or Edge ++ volatile unsigned int SYNC0; // 0x068 R/W 0xFFFFFFFF Synchronization Enable0 Register ++ volatile unsigned int SYNC1; // 0x06C R/W 0xFFFFFFFF Synchronization Enable1 Register ++ volatile unsigned int WKEN0; // 0x070 R/W 0x00000000 Wakeup Event Enable0 Register ++ volatile unsigned int WKEN1; // 0x074 R/W 0x00000000 Wakeup Event Enable1 Register ++ volatile unsigned int MODEA0; // 0x078 R/W 0x00000000 Both Edge or Single Edge0 Register ++ volatile unsigned int MODEA1; // 0x07C R/W 0x00000000 Both Edge or Single Edge1 Register ++ volatile unsigned int NOTDEFINE0[32]; //- 0x80-0xFC Reserved ++ volatile unsigned int INTMSK0; // 0x100 R/W 0xFFFFFFFF Interrupt Output Masking0 Register ++ volatile unsigned int INTMSK1; // 0x104 R/W 0xFFFFFFFF Interrupt Output Masking1 Register ++ volatile unsigned int ALLMSK; // 0x108 R/W 0x00000003 All Mask Register ++}PIC, *PPIC; ++ ++//#define HwVIC_BASE *(volatile unsigned long *)0xF0401200 ++typedef struct _VIC{ ++ volatile unsigned int VAIRQ; // 0x200 R 0x800000XX IRQ Vector Register ++ volatile unsigned int VAFIQ; // 0x204 R 0x800000XX FIQ Vector Register ++ volatile unsigned int VNIRQ; // 0x208 R 0x800000XX IRQ Vector Number Register ++ volatile unsigned int VNFIQ; // 0x20C R 0x800000XX FIQ Vector Number Register ++ volatile unsigned int VCTRL; // 0x210 R/W 0x00000000 Vector Control Register ++ volatile unsigned int NOTDEFINE0[3]; // 0x214-0x218-0x21c Reserved ++ volatile unsigned int PRIO0; // 0x220 R/W 0x03020100 Priorities for Interrupt 0 ~ 3 ++ volatile unsigned int PRIO1; // 0x224 R/W 0x07060504 Priorities for Interrupt 4 ~ 7 ++ volatile unsigned int PRIO2; // 0x228 R/W 0x0B0A0908 Priorities for Interrupt 8 ~ 11 ++ volatile unsigned int PRIO3; // 0x22C R/W 0x0F0E0D0C Priorities for Interrupt 12 ~ 15 ++ volatile unsigned int PRIO4; // 0x230 R/W 0x13121110 Priorities for Interrupt 16 ~ 19 ++ volatile unsigned int PRIO5; // 0x234 R/W 0x17161514 Priorities for Interrupt 20 ~ 23 ++ volatile unsigned int PRIO6; // 0x238 R/W 0x1B1A1918 Priorities for Interrupt 24 ~ 27 ++ volatile unsigned int PRIO7; // 0x23C R/W 0x1F1E1D1C Priorities for Interrupt 28 ~ 31 ++ volatile unsigned int PRIO8; // 0x220 R/W 0x23222120 Priorities for Interrupt 32 ~ 35 ++ volatile unsigned int PRIO9; // 0x224 R/W 0x27262524 Priorities for Interrupt 36 ~ 39 ++ volatile unsigned int PRIO10; // 0x228 R/W 0x2B2A2928 Priorities for Interrupt 40 ~ 43 ++ volatile unsigned int PRIO11; // 0x22C R/W 0x2F2E2D2C Priorities for Interrupt 44 ~ 47 ++ volatile unsigned int PRIO12; // 0x230 R/W 0x33323130 Priorities for Interrupt 48 ~ 51 ++ volatile unsigned int PRIO13; // 0x234 R/W 0x37363534 Priorities for Interrupt 52 ~ 55 ++ volatile unsigned int PRIO14; // 0x238 R/W 0x3B3A3938 Priorities for Interrupt 56 ~ 59 ++ volatile unsigned int PRIO15; // 0x23C R/W 0x3F3E3D3C Priorities for Interrupt 60 ~ 63 ++ ++}VIC, *PVIC; ++ ++/*********************************************************************** ++* 3. Timer/Counter Register Map (Base Address = 0xF0403000) ++************************************************************************/ ++//#define HwTMR_BASE *(volatile unsigned long *)0xF0403000 // Timer/Counter Base Register ++typedef struct _TIMER{ ++ volatile unsigned int TCFG0; // 0x00 R/W 0x00 Timer/Counter 0 Configuration Register ++ volatile unsigned int TCNT0; // 0x04 R/W 0x0000 Timer/Counter 0 Counter Register ++ volatile unsigned int TREF0; // 0x08 R/W 0xFFFF Timer/Counter 0 Reference Register ++ volatile unsigned int TMREF0; // 0x0C R/W 0x0000 Timer/Counter 0 Middle Reference Register ++ volatile unsigned int TCFG1; // 0x10 R/W 0x00 Timer/Counter 1 Configuration Register ++ volatile unsigned int TCNT1; // 0x14 R/W 0x0000 Timer/Counter 1 Counter Register ++ volatile unsigned int TREF1; // 0x18 R/W 0xFFFF Timer/Counter 1 Reference Register ++ volatile unsigned int TMREF1; // 0x1C R/W 0x0000 Timer/Counter 1 Middle Reference Register ++ volatile unsigned int TCFG2; // 0x20 R/W 0x00 Timer/Counter 2 Configuration Register ++ volatile unsigned int TCNT2; // 0x24 R/W 0x0000 Timer/Counter 2 Counter Register ++ volatile unsigned int TREF2; // 0x28 R/W 0xFFFF Timer/Counter 2 Reference Register ++ volatile unsigned int TMREF2; // 0x2C R/W 0x0000 Timer/Counter 2 Middle Reference Register ++ volatile unsigned int TCFG3; // 0x30 R/W 0x00 Timer/Counter 3 Configuration Register ++ volatile unsigned int TCNT3; // 0x34 R/W 0x0000 Timer/Counter 3 Counter Register ++ volatile unsigned int TREF3; // 0x38 R/W 0xFFFF Timer/Counter 3 Reference Register ++ volatile unsigned int TMREF3; // 0x3C R/W 0x0000 Timer/Counter 3 Middle Reference Register ++ volatile unsigned int TCFG4; // 0x40 R/W 0x00 Timer/Counter 4 Configuration Register ++ volatile unsigned int TCNT4; // 0x44 R/W 0x00000 Timer/Counter 4 Counter Register ++ volatile unsigned int TREF4; // 0x48 R/W 0xFFFFF Timer/Counter 4 Reference Register ++ volatile unsigned int NOTDEFINE0; ++ volatile unsigned int TCFG5; // 0x50 R/W 0x00 Timer/Counter 5 Configuration Register ++ volatile unsigned int TCNT5; // 0x54 R/W 0x00000 Timer/Counter 5 Counter Register ++ volatile unsigned int TREF5; // 0x58 R/W 0xFFFFF Timer/Counter 5 Reference Register ++ volatile unsigned int NOTDEFINE1; ++ volatile unsigned int TIREQ; // 0x60 R/W 0x0000 Timer/Counter n Interrupt Request Register ++ volatile unsigned int NOTDEFINE2[3]; ++ volatile unsigned int TWDCFG; // 0x70 R/W 0x0000 Reserved ++ volatile unsigned int TWDCLR; // 0x74 W - Reserved ++ volatile unsigned int NOTDEFINE3[2]; ++ volatile unsigned int TC32EN; // 0x80 R/W 0x00007FFF 32-bit Counter Enable / Pre-scale Value ++ volatile unsigned int TC32LDV; // 0x84 R/W 0x00000000 32-bit Counter Load Value ++ volatile unsigned int TC32CMP0; // 0x88 R/W 0x00000000 32-bit Counter Match Value 0 ++ volatile unsigned int TC32CMP1; // 0x8C R/W 0x00000000 32-bit Counter Match Value 1 ++ volatile unsigned int TC32PCNT; // 0x90 R/W - 32-bit Counter Current Value (pre-scale counter) ++ volatile unsigned int TC32MCNT; // 0x94 R/W - 32-bit Counter Current Value (main counter) ++ volatile unsigned int TC32IRQ; // 0x98 R/W 0x0000---- 32-bit Counter Interrupt Control ++ ++}TIMER, *PTIMER; ++ ++typedef struct _TIMERN{ ++ volatile unsigned int TCFG; // 0x000 R/W Timer/Counter Configuration Register ++ volatile unsigned int TCNT; // 0x004 R/W Timer/Counter Counter Register ++ volatile unsigned int TREF; // 0x008 R/W Timer/Counter Reference Register ++ volatile unsigned int TMREF; // 0x00C R/W Timer/Counter Middle Reference Register ++} TIMERN, *PTIMERN; ++ ++/*********************************************************************** ++* 4. PMU(POWER MANAGEMENT UNIT) Register Map (Base Address = 0xF0404000) ++************************************************************************/ ++//#define HwCONTROL *(volatile unsigned long *)0xF0404000 //R/W PMU Control Register ++#define PMU_PWROFF *(volatile unsigned long *)0xF0404018 ++typedef struct _PMU{ ++ volatile unsigned int CONTROL; // 0x00 R/W PMU Control Register ++ volatile unsigned int WKUPEN ; // 0x04 R/W Wakeup Enable Configuration Register ++ volatile unsigned int WKUPPOL ; // 0x08 R/W Wakeup Polarity Configuration Register ++ volatile unsigned int WATCHDOG; // 0x0C R/W Watchdog Control Register ++ volatile unsigned int CONFIG0 ; // 0x10 R/W Boot Configuration Register ++ volatile unsigned int USERSTS ; // 0x14 R/W Status Register ++ volatile unsigned int PWROFF ; // 0x18 R/W Power-Off Control Register ++} PMU, *PPMU; ++ ++ ++ ++/******************************************************************************* ++* 5. SMUI2C Controller Register Define (Base Addr = 0xF0405000) ++********************************************************************************/ ++//#define HwSMU_I2CMASTER0_BASE *(volatile unsigned long*)0xF0405000 ++//#define HwSMU_I2CMASTER1_BASE *(volatile unsigned long*)0xF0405040 ++//#define HwSMU_I2CICLK_BASE *(volatile unsigned long*)0xF0405080 //I2C_SCL divider Regist ++typedef struct _SMUI2CMASTER{ ++ volatile unsigned int PRES; // 0x00 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL; // 0x04 R/W 0x0000 Control Register ++ volatile unsigned int TXR; // 0x08 W 0x0000 Transmit Register ++ volatile unsigned int CMD; // 0x0C W 0x0000 Command Register ++ volatile unsigned int RXR; // 0x10 R 0x0000 Receive Register ++ volatile unsigned int SR; // 0x14 R 0x0000 Status register ++ volatile unsigned int TIME; // 0x18 R/W 0x0000 Timing Control Register ++} SMUI2CMASTER, *PSMUI2CMASTER; ++ ++typedef struct _SMUI2CICLK{ ++ volatile unsigned int ICLK; // 0x00 R/W 0xFFFF Clock Prescale register ++} SMUI2CICLK, *PSMUI2CICLK; ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 3 GPIO_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 1. GPIO Register Map (Base Address = 0xF0102000) ++************************************************************************/ ++/* ++#define HwGPIO_BASE *(volatile unsigned long *)0xF0102000 // ++#define HwGPIOA_BASE *(volatile unsigned long *)0xF0102000 // ++#define HwGPIOB_BASE *(volatile unsigned long *)0xF0102040 // ++#define HwGPIOC_BASE *(volatile unsigned long *)0xF0102080 // ++#define HwGPIOD_BASE *(volatile unsigned long *)0xF01020C0 // ++#define HwGPIOE_BASE *(volatile unsigned long *)0xF0102100 // ++#define HwGPIOF_BASE *(volatile unsigned long *)0xF0102140 // ++#define HwEINTSEL_BASE *(volatile unsigned long *)0xF0102180 // ++*/ ++typedef struct _GPIO{ ++ volatile unsigned int GPADAT; // 0x000 R/W 0x00000000 GPA Data Register ++ volatile unsigned int GPAEN; // 0x004 R/W 0x00000000 GPA Output Enable Register ++ volatile unsigned int GPASET; // 0x008 W - OR function on GPA Output Data ++ volatile unsigned int GPACLR; // 0x00C W - BIC function on GPA Output Data ++ volatile unsigned int GPAXOR; // 0x010 W - XOR function on GPA Output Data ++ volatile unsigned int GPACD0; // 0x014 W 0x55555555 Driver strength Control 0 on GPA Output Data ++ volatile unsigned int GPACD1; // 0x018 W 0x00000000 Driver strength Control 1 on GPA Output Data ++ volatile unsigned int GPAPD0; // 0x01C W 0x55555555 Pull-Up/Down function on GPA Output Data ++ volatile unsigned int GPAPD1; // 0x020 W 0x00000000 Pull-Up/Down function on GPA Output Data ++ volatile unsigned int GPAFN0; // 0x024 W 0x00000000 Port Configuration on GPA Output Data ++ volatile unsigned int GPAFN1; // 0x028 W 0x00000000 Port Configuration on GPA Output Data ++ volatile unsigned int GPAFN2; // 0x02C W 0x00000000 Port Configuration on GPA Output Data ++ volatile unsigned int GPAFN3; // 0x030 W 0x00000000 Port Configuration on GPA Output Data ++ volatile unsigned int NOTDEFINE0[3]; // 0x034-0x03C Reserved ++ volatile unsigned int GPBDAT; // 0x040 R/W 0x00000000 GPB Data Register ++ volatile unsigned int GPBEN; // 0x044 R/W 0x00000000 GPB Output Enable Register ++ volatile unsigned int GPBSET; // 0x048 W - OR function on GPB Output Data ++ volatile unsigned int GPBCLR; // 0x04C W - BIC function on GPB Output Data ++ volatile unsigned int GPBXOR; // 0x050 W - XOR function on GPB Output Data ++ volatile unsigned int GPBCD0; // 0x054 W 0x55555555 Driver strength Control 0 on GPB Output Data ++ volatile unsigned int GPBCD1; // 0x058 W 0x00000000 Driver strength Control 1 on GPB Output Data ++ volatile unsigned int GPBPD0; // 0x05C W 0x55555555 Pull-Up/Down function on GPB Output Data ++ volatile unsigned int GPBPD1; // 0x060 W 0x00000000 Pull-Up/Down function on GPB Output Data ++ volatile unsigned int GPBFN0; // 0x064 W 0x00000000 Port Configuration on GPB Output Data ++ volatile unsigned int GPBFN1; // 0x068 W 0x00000000 Port Configuration on GPB Output Data ++ volatile unsigned int GPBFN2; // 0x06C W 0x00000000 Port Configuration on GPB Output Data ++ volatile unsigned int GPBFN3; // 0x070 W 0x00000000 Port Configuration on GPB Output Data ++ volatile unsigned int NOTDEFINE1[3]; // 0x074-0x07C Reserved ++ volatile unsigned int GPCDAT; // 0x080 R/W 0x00000000 GPC Data Register ++ volatile unsigned int GPCEN; // 0x084 R/W 0x00000000 GPC Output Enable Register ++ volatile unsigned int GPCSET; // 0x088 W - OR function on GPC Output Data ++ volatile unsigned int GPCCLR; // 0x08C W - BIC function on GPC Output Data ++ volatile unsigned int GPCXOR; // 0x090 W - XOR function on GPC Output Data ++ volatile unsigned int GPCCD0; // 0x094 W 0x55555555 Driver strength Control 0 on GPC Output Data ++ volatile unsigned int GPCCD1; // 0x098 W 0x00000000 Driver strength Control 1 on GPC Output Data ++ volatile unsigned int GPCPD0; // 0x09C W 0x55555555 Pull-Up/Down function on GPC Output Data ++ volatile unsigned int GPCPD1; // 0x0A0 W 0x00000000 Pull-Up/Down function on GPC Output Data ++ volatile unsigned int GPCFN0; // 0x0A4 W 0x00000000 Port Configuration on GPC Output Data ++ volatile unsigned int GPCFN1; // 0x0A8 W 0x00000000 Port Configuration on GPC Output Data ++ volatile unsigned int GPCFN2; // 0x0AC W 0x00000000 Port Configuration on GPC Output Data ++ volatile unsigned int GPCFN3; // 0x0B0 W 0x00000000 Port Configuration on GPC Output Data ++ volatile unsigned int NOTDEFINE2[3]; // 0x0B4-0x0BC Reserved ++ volatile unsigned int GPDDAT; // 0x0C0 R/W 0x00000000 GPD Data Register ++ volatile unsigned int GPDEN; // 0x0C4 R/W 0x00000000 GPD Output Enable Register ++ volatile unsigned int GPDSET; // 0x0C8 W - OR function on GPD Output Data ++ volatile unsigned int GPDCLR; // 0x0CC W - BIC function on GPD Output Data ++ volatile unsigned int GPDXOR; // 0x0D0 W - XOR function on GPD Output Data ++ volatile unsigned int GPDCD0; // 0x0D4 W 0x55555555 Driver strength Control 0 on GPD Output Data ++ volatile unsigned int GPDCD1; // 0x0D8 W 0x00000000 Driver strength Control 1 on GPD Output Data ++ volatile unsigned int GPDPD0; // 0x0DC W 0x55555555 Pull-Up/Down function on GPD Output Data ++ volatile unsigned int GPDPD1; // 0x0E0 W 0x00000000 Pull-Up/Down function on GPD Output Data ++ volatile unsigned int GPDFN0; // 0x0E4 W 0x00000000 Port Configuration on GPD Output Data ++ volatile unsigned int GPDFN1; // 0x0E8 W 0x00000000 Port Configuration on GPD Output Data ++ volatile unsigned int GPDFN2; // 0x0EC W 0x00000000 Port Configuration on GPD Output Data ++ volatile unsigned int GPDFN3; // 0x0F0 W 0x00000000 Port Configuration on GPD Output Data ++ volatile unsigned int NOTDEFINE3[3]; // 0x0F4-0x0FC Reserved ++ volatile unsigned int GPEDAT; // 0x100 R/W 0x00000000 GPE Data Register ++ volatile unsigned int GPEEN; // 0x104 R/W 0x00000000 GPE Output Enable Register ++ volatile unsigned int GPESET; // 0x108 W - OR function on GPE Output Data ++ volatile unsigned int GPECLR; // 0x10C W - BIC function on GPE Output Data ++ volatile unsigned int GPEXOR; // 0x110 W - XOR function on GPE Output Data ++ volatile unsigned int GPECD0; // 0x114 W 0x55555555 Driver strength Control 0 on GPE Output Data ++ volatile unsigned int GPECD1; // 0x118 W 0x00000000 Driver strength Control 1 on GPE Output Data ++ volatile unsigned int GPEPD0; // 0x11C W 0x55555555 Pull-Up/Down function on GPE Output Data ++ volatile unsigned int GPEPD1; // 0x120 W 0x00000000 Pull-Up/Down function on GPE Output Data ++ volatile unsigned int GPEFN0; // 0x124 W 0x00000000 Port Configuration on GPE Output Data ++ volatile unsigned int GPEFN1; // 0x128 W 0x00000000 Port Configuration on GPE Output Data ++ volatile unsigned int GPEFN2; // 0x12C W 0x00000000 Port Configuration on GPE Output Data ++ volatile unsigned int GPEFN3; // 0x130 W 0x00000000 Port Configuration on GPE Output Data ++ volatile unsigned int NOTDEFINE4[3]; // 0x134-0x13C Reserved ++ volatile unsigned int GPFDAT; // 0x140 R/W 0x00000000 GPF Data Register ++ volatile unsigned int GPFEN; // 0x144 R/W 0x00000000 GPF Output Enable Register ++ volatile unsigned int GPFSET; // 0x148 W - OR function on GPF Output Data ++ volatile unsigned int GPFCLR; // 0x14C W - BIC function on GPF Output Data ++ volatile unsigned int GPFXOR; // 0x150 W - XOR function on GPF Output Data ++ volatile unsigned int GPFCD0; // 0x154 W 0x55555555 Driver strength Control 0 on GPF Output Data ++ volatile unsigned int GPFCD1; // 0x158 W 0x00000000 Driver strength Control 1 on GPF Output Data ++ volatile unsigned int GPFPD0; // 0x15C W 0x55555555 Pull-Up/Down function on GPF Output Data ++ volatile unsigned int GPFPD1; // 0x160 W 0x00000000 Pull-Up/Down function on GPF Output Data ++ volatile unsigned int GPFFN0; // 0x164 W 0x00000000 Port Configuration on GPF Output Data ++ volatile unsigned int GPFFN1; // 0x168 W 0x00000000 Port Configuration on GP Output Data ++ volatile unsigned int GPFFN2; // 0x16C W 0x00000000 Port Configuration on GPF Output Data ++ volatile unsigned int GPFFN3; // 0x170 W 0x00000000 Port Configuration on GPF Output Data ++ volatile unsigned int NOTDEFINE5[4]; // 0x174-0x17C Reserved ++ volatile unsigned int EINTSEL0; // 0x184 R/W 0x00000000 External Interrupt Select Register 01 ++ volatile unsigned int EINTSEL1; // 0x188 R/W 0x00000000 External Interrupt Select Register 1 ++ volatile unsigned int EINTSEL2; // 0x18C R/W 0x00000000 External Interrupt Select Register 2 ++ volatile unsigned int MON; // 0x190 R/W 0x00000000 System Monitor Enable Register ++ volatile unsigned int ECID0; // 0x194 R/W 0x00000000 CID output Register ++ volatile unsigned int ECID1; // 0x198 R - CID serial input Register ++ volatile unsigned int ECID2; // 0x19C R - CID parallel input 0 Register ++ volatile unsigned int ECID3; // 0x1A0 R - CID parallel input 1 Register ++}GPIO, *PGPIO; ++ ++typedef struct _GPION{ ++ volatile unsigned int GPDAT; // 0x000 R/W GPA Data Register ++ volatile unsigned int GPEN; // 0x004 R/W GPA Output Enable Register ++ volatile unsigned int GPSET; // 0x008 W OR function on GPA Output Data ++ volatile unsigned int GPCLR; // 0x00C W BIC function on GPA Output Data ++ volatile unsigned int GPXOR; // 0x010 W XOR function on GPA Output Data ++ volatile unsigned int GPCD0; // 0x014 W Driver strength Control 0 on GPA Output Data ++ volatile unsigned int GPCD1; // 0x018 W Driver strength Control 1 on GPA Output Data ++ volatile unsigned int GPPD0; // 0x01C W Pull-Up/Down function on GPA Output Data ++ volatile unsigned int GPPD1; // 0x020 W Pull-Up/Down function on GPA Output Data ++ volatile unsigned int GPFN0; // 0x024 W Port Configuration on GPA Output Data ++ volatile unsigned int GPFN1; // 0x028 W Port Configuration on GPA Output Data ++ volatile unsigned int GPFN2; // 0x02C W Port Configuration on GPA Output Data ++ volatile unsigned int GPFN3; // 0x030 W Port Configuration on GPA Output Data ++} GPION, *PGPION; ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 4 CORE & MEMORY BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 3. DRAM CONTROLLER Register Map (Base Address = 0xF0301000) ++************************************************************************/ ++/* ++#define HwDRAM_BASE *(volatile unsigned long *)0xF0301000 // ++#define HwDRAMM0_BASE *(volatile unsigned long *)0xF0301000 // ++#define HwDRAMM1_BASE *(volatile unsigned long *)0xF0302000 // ++#define HwDRAMMISC_BASE *(volatile unsigned long *)0xF0303000 // ++#define HwDRAMPHY_BASE *(volatile unsigned long *)0xF0304000 // ++#define HwDRAMMEMBUS_BASE *(volatile unsigned long *)0xF0305004 // ++*/ ++typedef struct _DRAM{ ++ volatile unsigned int STAT; // 0x000 RO - Status Register ++ volatile unsigned int CMD; // 0x004 WO - Command Register ++ volatile unsigned int DCMD; // 0x008 WO - Direct COmmnad Register ++ volatile unsigned int CFG; // 0x00C R/W 0x00010020 Configuration Register ++ volatile unsigned int REF; // 0x010 R/W 0x00000A60 Refresh Period Register ++ volatile unsigned int CAS; // 0x014 R/W 0x00000006 CAS Latency Register ++ volatile unsigned int DQSS; // 0x018 R/W 0x00000001 t_dqss Register ++ volatile unsigned int MRD; // 0x01C R/W 0x00000002 t_mrd Register ++ volatile unsigned int RAS; // 0x020 R/W 0x00000007 t_ras Register ++ volatile unsigned int RC; // 0x024 R/W 0x0000000B t_rc Register ++ volatile unsigned int RCD; // 0x028 R/W 0x0000001D t_rcd Register ++ volatile unsigned int RFC; // 0x02C R/W 0x000000212 t_rfc Register ++ volatile unsigned int RP; // 0x030 R/W 0x0000001D t_rp Register ++ volatile unsigned int RRD; // 0x034 R/W 0x00000002 t_rrd Register ++ volatile unsigned int WR; // 0x038 R/W 0x00000003 t_wr Register ++ volatile unsigned int WTR; // 0x03C R/W 0x00000002 t_wtr Register ++ volatile unsigned int XP; // 0x040 R/W 0x00000001 t_xp Register ++ volatile unsigned int XSR; // 0x044 R/W 0x0000000A t_xsr Register ++ volatile unsigned int ESR; // 0x048 R/W 0x00000014 t_esr Register ++ volatile unsigned int CFG2; // 0x04C R/W - Memory_cfg2 Register ++ volatile unsigned int CFG3; // 0x050 R/W 0x00000007 Memory_cfg3 Register ++ volatile unsigned int NOTDEFINE0[43]; // - 0x054- 0x0FC Reserved ++ volatile unsigned int ID0; // 0x100 R/W 0x00000000 AXI ID0 configuration Register ++ volatile unsigned int ID1; // 0x104 R/W 0x00000000 AXI ID1 configuration Register ++ volatile unsigned int ID2; // 0x108 R/W 0x00000000 AXI ID2 configuration Register ++ volatile unsigned int ID3; // 0x10C R/W 0x00000000 AXI ID3 configuration Register ++ volatile unsigned int ID4; // 0x110 R/W 0x00000000 AXI ID4 configuration Register ++ volatile unsigned int ID5; // 0x114 R/W 0x00000000 AXI ID5 configuration Register ++ volatile unsigned int ID6; // 0x118 R/W 0x00000000 AXI ID6 configuration Register ++ volatile unsigned int ID7; // 0x11C R/W 0x00000000 AXI ID7 configuration Register ++ volatile unsigned int ID8; // 0x120 R/W 0x00000000 AXI ID8 configuration Register ++ volatile unsigned int ID9; // 0x124 R/W 0x00000000 AXI ID9 configuration Register ++ volatile unsigned int ID10; // 0x128 R/W 0x00000000 AXI ID10 configuration Register ++ volatile unsigned int ID11; // 0x12C R/W 0x00000000 AXI ID11 configuration Register ++ volatile unsigned int ID12; // 0x130 R/W 0x00000000 AXI ID12 configuration Register ++ volatile unsigned int ID13; // 0x134 R/W 0x00000000 AXI ID13 configuration Register ++ volatile unsigned int ID14; // 0x138 R/W 0x00000000 AXI ID14 configuration Register ++ volatile unsigned int ID15; // 0x13C R/W 0x00000000 AXI ID15 configuration Register ++ volatile unsigned int NOTDEFINE1[48]; // - 0x140- 0x1FC Reserved ++ volatile unsigned int CH0; // 0x200 R/W 0x0000FF00 CHIP ID0 configuration Register ++ volatile unsigned int CH1; // 0x204 R/W 0x0000FF00 CHIP ID1 configuration Register ++ volatile unsigned int CH2; // 0x208 R/W 0x0000FF00 CHIP ID2 configuration Register ++ volatile unsigned int CH3; // 0x20C R/W 0x0000FF00 CHIP ID3 configuration Register ++}DRAM, *PDRAM; ++ ++typedef struct _DRAMMX{ ++ volatile unsigned int M0STAT; // 0x000 RO - Status Register ++ volatile unsigned int M0CMD; // 0x004 WO - Command Register ++ volatile unsigned int M0DCMD; // 0x008 WO - Direct COmmnad Register ++ volatile unsigned int M0CFG; // 0x00C R/W 0x00010020 Configuration Register ++ volatile unsigned int M0REF; // 0x010 R/W 0x00000A60 Refresh Period Register ++ volatile unsigned int M0CAS; // 0x014 R/W 0x00000006 CAS Latency Register ++ volatile unsigned int M0DQSS; // 0x018 R/W 0x00000001 t_dqss Register ++ volatile unsigned int M0MRD; // 0x01C R/W 0x00000002 t_mrd Register ++ volatile unsigned int M0RAS; // 0x020 R/W 0x00000007 t_ras Register ++ volatile unsigned int M0RC; // 0x024 R/W 0x0000000B t_rc Register ++ volatile unsigned int M0RCD; // 0x028 R/W 0x0000001D t_rcd Register ++ volatile unsigned int M0RFC; // 0x02C R/W 0x000000212 t_rfc Register ++ volatile unsigned int M0RP; // 0x030 R/W 0x0000001D t_rp Register ++ volatile unsigned int M0RRD; // 0x034 R/W 0x00000002 t_rrd Register ++ volatile unsigned int M0WR; // 0x038 R/W 0x00000003 t_wr Register ++ volatile unsigned int M0WTR; // 0x03C R/W 0x00000002 t_wtr Register ++ volatile unsigned int M0XP; // 0x040 R/W 0x00000001 t_xp Register ++ volatile unsigned int M0XSR; // 0x044 R/W 0x0000000A t_xsr Register ++ volatile unsigned int M0ESR; // 0x048 R/W 0x00000014 t_esr Register ++ volatile unsigned int M0CFG2; // 0x04C R/W - Memory_cfg2 Register ++ volatile unsigned int M0CFG3; // 0x050 R/W 0x00000007 Memory_cfg3 Register ++ volatile unsigned int NOTDEFINE0[43]; // - 0x054- 0x0FC Reserved ++ volatile unsigned int M0ID0; // 0x100 R/W 0x00000000 AXI ID0 configuration Register ++ volatile unsigned int M0ID1; // 0x104 R/W 0x00000000 AXI ID1 configuration Register ++ volatile unsigned int M0ID2; // 0x108 R/W 0x00000000 AXI ID2 configuration Register ++ volatile unsigned int M0ID3; // 0x10C R/W 0x00000000 AXI ID3 configuration Register ++ volatile unsigned int M0ID4; // 0x110 R/W 0x00000000 AXI ID4 configuration Register ++ volatile unsigned int M0ID5; // 0x114 R/W 0x00000000 AXI ID5 configuration Register ++ volatile unsigned int M0ID6; // 0x118 R/W 0x00000000 AXI ID6 configuration Register ++ volatile unsigned int M0ID7; // 0x11C R/W 0x00000000 AXI ID7 configuration Register ++ volatile unsigned int M0ID8; // 0x120 R/W 0x00000000 AXI ID8 configuration Register ++ volatile unsigned int M0ID9; // 0x124 R/W 0x00000000 AXI ID9 configuration Register ++ volatile unsigned int M0ID10; // 0x128 R/W 0x00000000 AXI ID10 configuration Register ++ volatile unsigned int M0ID11; // 0x12C R/W 0x00000000 AXI ID11 configuration Register ++ volatile unsigned int M0ID12; // 0x130 R/W 0x00000000 AXI ID12 configuration Register ++ volatile unsigned int M0ID13; // 0x134 R/W 0x00000000 AXI ID13 configuration Register ++ volatile unsigned int M0ID14; // 0x138 R/W 0x00000000 AXI ID14 configuration Register ++ volatile unsigned int M0ID15; // 0x13C R/W 0x00000000 AXI ID15 configuration Register ++ volatile unsigned int NOTDEFINE1[48]; // - 0x140- 0x1FC Reserved ++ volatile unsigned int M0CH0; // 0x200 R/W 0x0000FF00 CHIP ID0 configuration Register ++ volatile unsigned int M0CH1; // 0x204 R/W 0x0000FF00 CHIP ID1 configuration Register ++ volatile unsigned int M0CH2; // 0x208 R/W 0x0000FF00 CHIP ID2 configuration Register ++ volatile unsigned int M0CH3; // 0x20C R/W 0x0000FF00 CHIP ID3 configuration Register ++ volatile unsigned int NOTDEFINE2[892]; // - 0x1210- 0x1FFC Reserved ++ //0xF0302000 ++ volatile unsigned int M1STAT; // 0x000 RO - Status Register ++ volatile unsigned int M1CMD; // 0x004 WO - Command Register ++ volatile unsigned int M1DCMD; // 0x008 WO - Direct COmmnad Register ++ volatile unsigned int M1CFG; // 0x00C R/W 0x00010020 Configuration Register ++ volatile unsigned int M1REF; // 0x010 R/W 0x00000A60 Refresh Period Register ++ volatile unsigned int M1CAS; // 0x014 R/W 0x00000006 CAS Latency Register ++ volatile unsigned int M1DQSS; // 0x018 R/W 0x00000001 t_dqss Register ++ volatile unsigned int M1MRD; // 0x01C R/W 0x00000002 t_mrd Register ++ volatile unsigned int M1RAS; // 0x020 R/W 0x00000007 t_ras Register ++ volatile unsigned int M1RC; // 0x024 R/W 0x0000000B t_rc Register ++ volatile unsigned int M1RCD; // 0x028 R/W 0x0000001D t_rcd Register ++ volatile unsigned int M1RFC; // 0x02C R/W 0x000000212 t_rfc Register ++ volatile unsigned int M1RP; // 0x030 R/W 0x0000001D t_rp Register ++ volatile unsigned int M1RRD; // 0x034 R/W 0x00000002 t_rrd Register ++ volatile unsigned int M1WR; // 0x038 R/W 0x00000003 t_wr Register ++ volatile unsigned int M1WTR; // 0x03C R/W 0x00000002 t_wtr Register ++ volatile unsigned int M1XP; // 0x040 R/W 0x00000001 t_xp Register ++ volatile unsigned int M1XSR; // 0x044 R/W 0x0000000A t_xsr Register ++ volatile unsigned int M1ESR; // 0x048 R/W 0x00000014 t_esr Register ++ volatile unsigned int M1CFG2; // 0x04C R/W - Memory_cfg2 Register ++ volatile unsigned int M1CFG3; // 0x050 R/W 0x00000007 Memory_cfg3 Register ++ volatile unsigned int NOTDEFINE3[43]; // - 0x054- 0x0FC Reserved ++ volatile unsigned int M1ID0; // 0x100 R/W 0x00000000 AXI ID0 configuration Register ++ volatile unsigned int M1ID1; // 0x104 R/W 0x00000000 AXI ID1 configuration Register ++ volatile unsigned int M1ID2; // 0x108 R/W 0x00000000 AXI ID2 configuration Register ++ volatile unsigned int M1ID3; // 0x10C R/W 0x00000000 AXI ID3 configuration Register ++ volatile unsigned int M1ID4; // 0x110 R/W 0x00000000 AXI ID4 configuration Register ++ volatile unsigned int M1ID5; // 0x114 R/W 0x00000000 AXI ID5 configuration Register ++ volatile unsigned int M1ID6; // 0x118 R/W 0x00000000 AXI ID6 configuration Register ++ volatile unsigned int M1ID7; // 0x11C R/W 0x00000000 AXI ID7 configuration Register ++ volatile unsigned int M1ID8; // 0x120 R/W 0x00000000 AXI ID8 configuration Register ++ volatile unsigned int M1ID9; // 0x124 R/W 0x00000000 AXI ID9 configuration Register ++ volatile unsigned int M1ID10; // 0x128 R/W 0x00000000 AXI ID10 configuration Register ++ volatile unsigned int M1ID11; // 0x12C R/W 0x00000000 AXI ID11 configuration Register ++ volatile unsigned int M1ID12; // 0x130 R/W 0x00000000 AXI ID12 configuration Register ++ volatile unsigned int M1ID13; // 0x134 R/W 0x00000000 AXI ID13 configuration Register ++ volatile unsigned int M1ID14; // 0x138 R/W 0x00000000 AXI ID14 configuration Register ++ volatile unsigned int M1ID15; // 0x13C R/W 0x00000000 AXI ID15 configuration Register ++ volatile unsigned int NOTDEFINE4[48]; // - 0x140- 0x1FC Reserved ++ volatile unsigned int M1CH0; // 0x200 R/W 0x0000FF00 CHIP ID0 configuration Register ++ volatile unsigned int M1CH1; // 0x204 R/W 0x0000FF00 CHIP ID1 configuration Register ++ volatile unsigned int M1CH2; // 0x208 R/W 0x0000FF00 CHIP ID2 configuration Register ++ volatile unsigned int M1CH3; // 0x20C R/W 0x0000FF00 CHIP ID3 configuration Register ++}DRAMMX, *PDRAMMX; ++ ++typedef struct _DRAMPHY{ ++ volatile unsigned int REG0; // 0x400 R/W 0x00000000 PHY Mode Control Register ++ volatile unsigned int REG1; // 0x404 R/ RW 0x00000018 DLL Control & Status Register ++ volatile unsigned int REG2; // 0x408 R/W 0x00000000 DLL Phase Detector configuration Register ++ volatile unsigned int REG3; // 0x40C R/W 0x00000000 Gate Control Register ++ volatile unsigned int REG4; // 0x410 R/W 0x00000000 Read Data Slice 0 Control Register ++ volatile unsigned int REG5; // 0x414 R/W 0x00000000 Read Data Slice 1 Control Register ++ volatile unsigned int REG6; // 0x418 RO 0x00000000 Read Data Slice 2 Control Register ++ volatile unsigned int REG7; // 0x41C R/W 0x00000000 Read Data Slice 3 Control Register ++ volatile unsigned int REG8; // 0x420 R/W 0x00000000 CLK Delay Register ++ volatile unsigned int REG9; // 0x424 R/W 0x00000000 DLL Force Lock Value Register ++ volatile unsigned int REG10; // 0x428 R/W 0x00000000 ZQ Calibration Control Register ++ volatile unsigned int REG11; // 0x42C RO 0x00000000 ZQ Calibration Status Register ++ volatile unsigned int REG12; // 0x430 R/W 0x00000000 Read Delay Register ++}DRAMPHY, *PDRAMPHY; ++ ++typedef struct _DRAMMISC{ ++ volatile unsigned int M0CFG0; //0x00 R/W 0x80400000 SDR/DDR SDRAM Controller Configuration Register 0 ++ volatile unsigned int M0CFG1; //0x04 R/RW 0x00000018 SDR/DDR SDRAM Controller Configuration Register 1 ++ volatile unsigned int NOTDEFINE0[2]; // 0x08-0x0C Reserved ++ volatile unsigned int M1CFG0; //0x10 R/W 0x80000000 DDR2 SDRAM Controller Configuration Register 0 ++ volatile unsigned int M1CFG1; //0x14 R/W 0x00000000 DDR2 SDRAM Controller Configuration Register 1 ++ volatile unsigned int NOTDEFINE1[2]; // - 0x18- 0x1C Reserved ++ volatile unsigned int COMMON; //0x20 R/W 0x00010103 Common Control Register ++ volatile unsigned int PHYCTRL; //0x24 R/W 0x00000000 SDRAM PHY Control Register ++ volatile unsigned int PHYTSTS; //0x28 RO 0x00000000 SDRAM PHY Status Register ++ volatile unsigned int IOCFG; //0x2C R/W 0x00000000 SDRAM IO Control Register ++}DRAMMISC, *PDRAMMISC; ++ ++typedef struct _DRAMMEMBUS{ ++ volatile unsigned int CKDOWN; //0x04 RW 0x00000000 Clock Enable control over memory bus com-ponents ++}DRAMMEMBUS, *PDRAMMEMBUS; ++ ++/************************************************************************ ++* 4-1. MISC CORE BUS CONFIGURATION REGISTERS (Base Addr = 0xF0101000) ++************************************************************************/ ++//#define HwCORECFG_BASE *(volatile unsigned long *)0xF0101000 ************************************************************************/ ++typedef struct _MISCCOREBUS{ ++ volatile unsigned int CORECFG; //R/W 0x90000000 Core Bus Configuration Register ++}MISCCOREBUS, *PMISCCOREBUS; ++ ++/************************************************************************ ++* 4-2. Virtual MMU Table Register Define (Base Addr = 0xF7000000) ++************************************************************************/ ++//#define HwVMT_BASE *(volatile unsigned long *)0x20000000 // VMT Base Regiseter ++//#define HwREGION_BASE *(volatile unsigned long *)0xF7000000 // R/W, Configuration Register for Region 0 ++ ++typedef struct _VMTREGION{ ++ volatile unsigned int REGION0; // 0x00 R/W - Configuration Register for Region 0 ++ volatile unsigned int REGION1; // 0x04 R/W - Configuration Register for Region 1 ++ volatile unsigned int REGION2; // 0x08 R/W - Configuration Register for Region 2 ++ volatile unsigned int REGION3; // 0x0C R/W - Configuration Register for Region 3 ++ volatile unsigned int REGION4; // 0x10 R/W - Configuration Register for Region 4 ++ volatile unsigned int REGION5; // 0x14 R/W - Configuration Register for Region 5 ++ volatile unsigned int REGION6; // 0x18 R/W - Configuration Register for Region 6 ++ volatile unsigned int REGION7; // 0x1C R/W - Configuration Register for Region 7 ++}VMTREGION, *PVMTREGION; ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 5 IO BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/******************************************************************************* ++* 4. Memory Stick Host Controller Register Define (Base Addr = 0xF0590000) ++********************************************************************************/ ++//#define HwSMSHC_BASE *(volatile unsigned long*)0xF0590000 ++//#define HwSMSHCPORTCFG_BASE *(volatile unsigned long*)0xF05F1000 ++typedef struct _SMSHC{ ++ volatile unsigned int MS_CONTROL_PROGRAMCOUNTREG; // 0x00 // R/W 0x0070_1000 ++ volatile unsigned int MS_SYSTEMREG; // 0x04 // R/W 0x0800_XXXX ++ volatile unsigned int MS_FLAGREG; // 0x08 // R 0x4000_XXXX ++ volatile unsigned int MS_MEMORY_CONTROLREG; // 0x0C // R/W 0x0001_7000 ++ volatile unsigned int MS_GENERALREG01; // 0x10 // R/W 0x8000_9000 ++ volatile unsigned int MS_GENERALREG23; // 0x14 // R/W 0xA000_B000 ++ volatile unsigned int MS_GENERALREG45; // 0x18 // R/W 0xC000_D000 ++ volatile unsigned int MS_TIMERREG; // 0x1C // R 0xE000XXXX ++ volatile unsigned int MS_INSTRUCTIONREG; // 0x20 // R/W 0xXXXX_XXXX ++ volatile unsigned int MS_GENERALDATAFIFO; // 0x24 // R/W 0x0000_0000 ++ volatile unsigned int MS_PAGEBUFFER; // 0x28 // R/W 0xXXXX_XXXX ++ volatile unsigned int MS_VERSIONREG; // 0x2C // R 0xXXXX_XXXX ++ volatile unsigned int MS_MSHC_COMMANDREG; // 0x30 // R/W 0x0000_XXXX ++ volatile unsigned int MS_MSHC_DATAREG; // 0x34 // R/W 0x0000_0000 ++ volatile unsigned int MS_MSHC_STATUSREG; // 0x38 // R 0x1000_XXXX ++ volatile unsigned int MS_MSHC_SYSTEMREG; // 0x3C // R/W 0x20A5_XXXX ++ volatile unsigned int MS_MSHC_USERCUSTOMREG; // 0x40 // R 0x0220_XXXX ++ volatile unsigned int MS_MSHC_FIFOCTRLREG; // 0x44 // R/W 0x0001_XXXX ++ volatile unsigned int NOTDEFINE0; // ++ volatile unsigned int MS_MSHC_DMACTRLREG; // 0x4C // R/W 0x0000_XXXX ++}SMSHC, *PSMSHC; ++ ++typedef struct _SMSHCPORTCFG{ ++ volatile unsigned int MS_PORTCFG; // 0xF05F1000 // R/W 0x00000000 ++ volatile unsigned int MS_PORTDLY; // 0xF05F1004 // R/W 0x00000000 ++}SMSHCPORTCFG, *PSMSHCPORTCFG; ++ ++/******************************************************************************* ++* 5. SD/SDIO/MMC/CE-ATA Host Controller Register Define (Base Addr = 0xF0590000) ++********************************************************************************/ ++/* ++#define HwSDCORE0SLOT0_BASE *(volatile unsigned long*)0xF05A0000 // Core 0 Slot 0 ++#define HwSDCORE0SLOT1_BASE *(volatile unsigned long*)0xF05A0100 // Core 0 Slot 1 ++#define HwSDCORE1SLOT2_BASE *(volatile unsigned long*)0xF05A0200 // Core 1 Slot 2 ++#define HwSDCORE1SLOT3_BASE *(volatile unsigned long*)0xF05A0300 // Core 1 Slot 3 ++#define HwSDCHCTRL_BASE *(volatile unsigned long*)0xF05A0800 // Channel Control Register ++*/ ++typedef struct _SDHOST{ ++ volatile unsigned short SDMA; // 0x000 R/W 0x0000 SDMA System Address ++ volatile unsigned short NOTDEFINE0; // 0x002 ++ volatile unsigned short BSIZE; // 0x004 R/W 0x0000 Block Size ++ volatile unsigned short BCNT; // 0x006 R/W 0x0000 Block Count ++ volatile unsigned short ARG; // 0x008 R/W 0x0000 Argument ++ volatile unsigned short NOTDEFINE1; // 0x00A ++ volatile unsigned short TMODE; // 0x00C R/W 0x0000 Transfer Mode ++ volatile unsigned short CMD; // 0x00E R/W 0x0000 Command ++ volatile unsigned short RESP0; // 0x010 R 0x0000 Response0 ++ volatile unsigned short RESP1; // 0x012 R 0x0000 Response1 ++ volatile unsigned short RESP2; // 0x014 R 0x0000 Response2 ++ volatile unsigned short RESP3; // 0x016 R 0x0000 Response3 ++ volatile unsigned short RESP4; // 0x018 R 0x0000 Response4 ++ volatile unsigned short RESP5; // 0x01A R 0x0000 Response5 ++ volatile unsigned short RESP6; // 0x01C R 0x0000 Response6 ++ volatile unsigned short RESP7; // 0x01E R 0x0000 Response7 ++ volatile unsigned short DATAL; // 0x020 R/W - Buffer Data Port(Low) ++ volatile unsigned short DATAH; // 0x022 R/W - Buffer Data Port(High) ++ volatile unsigned short STATEL; // 0x024 R 0x0000 Present State(Low) ++ volatile unsigned short STATEH; // 0x026 R 0x0000 Present State(High) ++ volatile unsigned short CONTL; // 0x028 R/W 0x0000 Power Control / Host Control ++ volatile unsigned short CONTH; // 0x02A R/W 0x0000 Wakeup Control / Block Gap Control ++ volatile unsigned short CLK; // 0x02C R/W 0x0000 Clock Control ++ volatile unsigned short TIME; // 0x02E R/W 0x0000 Software Reset / Timeout Control ++ volatile unsigned short STSL; // 0x030 R 0x0000 Normal Interrupt Status(Low) ++ volatile unsigned short STSH; // 0x032 R 0x0000 Normal Interrupt Status(High) ++ volatile unsigned short STSENL; // 0x034 R/W 0x0000 Normal Interrupt Status Enable(Low) ++ volatile unsigned short STSENH; // 0x036 R/W 0x0000 Normal Interrupt Status Enable(High) ++ volatile unsigned short INTENL; // 0x038 R/W 0x0000 Normal Interrupt Signal Enable(Low) ++ volatile unsigned short INTENH; // 0x03A R/W 0x0000 Normal Interrupt Signal Enable(High) ++ volatile unsigned short CMD12ERR; // 0x03C R 0x0000 Auto CMD12 Error Status ++ volatile unsigned short NOTDEFINE2; // 0x03E ++ volatile unsigned short CAPL; // 0x040 R 0x30B0 Capabilities(Low) ++ volatile unsigned short CAPH; // 0x042 R 0x69EF Capabilities(High) ++ volatile unsigned short NOTDEFINE3[2]; // 0x044, 0x046 ++ volatile unsigned short CURL; // 0x048 R 0x0001 Maximum Current Capabilities(Low) ++ volatile unsigned short CURH; // 0x04A R 0x0000 Maximum Current Capabilities(High) ++ volatile unsigned short NOTDEFINE4[2]; // 0x04C, 0x04E ++ volatile unsigned short FORCEL; // 0x050 W 0x0000 Force event for AutoCmd12 Error ++ volatile unsigned short FORCEH; // 0x052 W 0x0000 Force event for Error Interrupt Status ++ volatile unsigned short AUDIO_DMAERR; // 0x054 R/W 0x0000 AUDIO DMA Error Status ++ volatile unsigned short NOTDEFINE5; // 0x056 ++ volatile unsigned short ADDR0; // 0x058 R/W 0x0000 AUDIO DMA Address[15:0] ++ volatile unsigned short ADDR1; // 0x05A R/W 0x0000 AUDIO DMA Address[31:16] ++ volatile unsigned short ADDR2; // 0x05C R/W 0x0000 AUDIO DMA Address[47:32] ++ volatile unsigned short ADDR3; // 0x05E R/W 0x0000 AUDIO DMA Address[63:48] ++ volatile unsigned short NOTDEFINE6[78]; // 0x060~0x0FA ++ volatile unsigned short SLOT; // 0x0FC R 0x0000 Slot Interrupt Status ++ volatile unsigned short VERSION; // 0x0FE R 0x0002 Host Controller Version ++}SDHOST, *PSDHOST; ++ ++typedef struct _SDCHCTRL{ ++ volatile unsigned int SDPORTCTRL; // 0x00 R/W 0x0000 SD/MMC port control register ++ volatile unsigned int SDPORTDLY0; // 0x04 R/W 0x0000 SD/MMC output delay control register ++ volatile unsigned int SDPORTDLY1; // 0x08 R/W 0x0000 SD/MMC output delay control register ++ volatile unsigned int SDPORTDLY2; // 0x0C R/W 0x0000 SD/MMC output delay control register ++ volatile unsigned int SDPORTDLY3; // 0x10 R/W 0x0000 SD/MMC output delay control register ++}SDCHCTRL, *PSDCHCTRL; ++ ++ ++/******************************************************************************* ++* 6. NAND Flash Controller(NFC) Register Define (Base Addr = 0xF05B0000) ++********************************************************************************/ ++//#define HwNFC_BASE *(volatile unsigned long*)0xF05B0000 ++ ++typedef struct _NFC{ ++ volatile unsigned int NFC_CMD; // 0x000 W NAND Flash Command Register ++ volatile unsigned int NFC_LADDR; // 0x004 W NAND Flash Linear Address Register ++ volatile unsigned int NFC_BADDR; // 0x008 W NAND Flash Block Address Register ++ volatile unsigned int NFC_SADDR; // 0x00C W NAND Flash Signal Address Register ++ volatile unsigned int NFC_WDATA; // 0x01x R/W NAND Flash Word Data Register ++ volatile unsigned int NOTDEFINE0[3]; // 0x01x R/W NAND Flash Word Data Register ++ volatile unsigned int NFC_LDATA; // 0x02x/3x R/W NAND Flash Linear Data Register ++ volatile unsigned int NOTDEFINE1[7]; // 0x01x R/W NAND Flash Word Data Register ++ volatile unsigned int NFC_SDATA; // 0x040 R/W NAND Flash Single Data Register ++ volatile unsigned int NOTDEFINE2[3]; // 0x044 Not Used ++ volatile unsigned int NFC_CTRL; // 0x050 R/W NAND Flash Control Register ++ volatile unsigned int NFC_PSTART; // 0x054 W NAND Flash Program Start Register ++ volatile unsigned int NFC_RSTART; // 0x058 W NAND Flash Read Start Register ++ volatile unsigned int NFC_DSIZE; // 0x05C R/W NAND Flash Data Size Register ++ volatile unsigned int NFC_IREQ; // 0x060 R/W NAND Flash Interrupt Request Register ++ volatile unsigned int NFC_RST; // 0x064 W NAND Flash Controller Reset Register ++ volatile unsigned int NFC_CTRL1; // 0x068 R/W NAND Flash Control Register 1 ++ volatile unsigned int NOTDEFINE3; // 0x06C Not Used ++ volatile unsigned int NFC_MDATA[4]; // 0x07x R/W NAND Flash Multiple Data Register ++}NFC, *PNFC; ++ ++/******************************************************************************* ++* 7. Static Memory Controller(SMC) Register Define (Base Addr = 0xF05F0000) ++********************************************************************************/ ++//#define HwSMC_BASE *(volatile unsigned long*)0xF05F0000 ++typedef struct _SMC{ ++ volatile unsigned int STATUS; // 0x00 R/W Unknown Status Register ++ volatile unsigned int NOTDEFINE0[7]; ++ volatile unsigned int CSNCFG0; // 0x20 R 0x4b40_3183 External Chip Select0 Config Register ++ volatile unsigned int CSNCFG1; // 0x24 R/W 0x4b40_1104 External Chip Select1 Config Register ++ volatile unsigned int CSNCFG2; // 0x28 W 0x4b40_4082 External Chip Select2 Config Register ++ volatile unsigned int CSNCFG3; // 0x2C R/W 0x4b40_20C5 External Chip Select3 Config. Register ++ volatile unsigned int CSNOFFSET; // 0x30 R/W 0x0 Wapping Address Mode OFFSET Register ++ volatile unsigned int INDIRADDR; // 0x34 R/W 0x0 Indirect Address ++}SMC, *PSMC; ++ ++/******************************************************************************* ++* 8. External Device Interface (EDI) Register Define (Base Addr = 0xF05F6000) ++********************************************************************************/ ++//#define HwEDI_BASE *(volatile unsigned long*)0xF05F6000 ++ ++typedef struct _EDI{ ++ volatile unsigned int EDI_CTRL; // 0x00 R/W 0x00000000 EDI Control Register. ++ volatile unsigned int EDI_CSNCFG0; // 0x04 R/W 0x00543210 EDI CSN Configuration Register 0. ++ volatile unsigned int EDI_CSNCFG1; // 0x08 R/W 0x00BA9876 EDI CSN Configuration Register 1. ++ volatile unsigned int NOTDEFINE0[2]; // Reserved 0x0C R/W - - ++ volatile unsigned int EDI_RDYCFG; // 0x14 R/W 0x76543210 EDI Ready Configuration Register ++ volatile unsigned int NOTDEFINE1[2]; // Reserved 0x18 R/W 0x00000000 EDI Time-Out Configuration Register 0 ++ volatile unsigned int EDI_REQOFF; // 0x20 R/W 0x00000000 EDI Request OFF Flag register ++}EDI, *PEDI; ++ ++/******************************************************************************* ++* 9. IDE Controller Register Define (Base Addr = 0xF0520000) ++********************************************************************************/ ++//#define HwIDE_BASE *(volatile unsigned long*)0xF05F6000 ++ ++typedef struct _IDE{ ++ volatile unsigned int CS00; // 0x00 R/W - PIO CS0n Access Register ++ volatile unsigned int CS01; // 0x04 ++ volatile unsigned int CS02; // 0x08 ++ volatile unsigned int CS03; // 0x0C ++ volatile unsigned int CS04; // 0x10 ++ volatile unsigned int CS05; // 0x14 ++ volatile unsigned int CS06; // 0x18 ++ volatile unsigned int CS07; // 0x1C ++ volatile unsigned int CS10; // 0x20 R/W - PIO CS1n Access Register ++ volatile unsigned int CS11; // 0x24 ++ volatile unsigned int CS12; // 0x28 ++ volatile unsigned int CS13; // 0x2C ++ volatile unsigned int CS14; // 0x30 ++ volatile unsigned int CS15; // 0x34 ++ volatile unsigned int CS16; // 0x38 ++ volatile unsigned int CS17; // 0x3C ++ volatile unsigned int PIOCTRL; // 0x40 R/W 0x00600000 PIO Mode Control Register ++ volatile unsigned int UDMACTRL; // 0x44 R/W 0x00000000 UDMA Mode Control Register ++ volatile unsigned int IDMACTRL; // 0x48 R/W 0x00000000 IDMA Control Register ++ volatile unsigned int IDMASA; // 0x4C R/W 0x00000000 IDMA Source Address Register ++ volatile unsigned int IDMASP; // 0x50 R/W 0x00000000 IDMA Source Parameter Register ++ volatile unsigned int IDMACSA; // 0x54 R 0x00000000 IDMA Current Source Address Register ++ volatile unsigned int IDMADA; // 0x58 R/W 0x00000000 IDMA Destination Address Register ++ volatile unsigned int IDMADP; // 0x5C R/W 0x00000000 IDMA Destination Parameter Register ++ volatile unsigned int IDMACDA; // 0x60 R 0x00000000 IDMA Current Destination Address Register ++ volatile unsigned int IDEINT; // 0x64 R/W 0x0000_0000 IDE Interrupt Register ++ volatile unsigned int UDMATCNT; // 0x68 R/W 0x00FF_FFFF UDMA Transfer Counter Register ++ volatile unsigned int UDMAIN; // 0x6C R - UDMA-IN Access Register ++ volatile unsigned int UDMAOUT; // 0x70 W - UDMA-OUT Access register ++ volatile unsigned int UDMACRC; // 0x74 R 0x0000_4ABA UDMA CRC Register ++ volatile unsigned int UDMACTCNT; // 0x78 R 0x00FF_FFFF UDMA Current Transfer Counter Register ++}IDE, *PIDE; ++ ++ ++/******************************************************************************* ++* 10. SATA Interface Register Define (Base Addr = 0xF0560000) ++********************************************************************************/ ++//#define HwSATA_BASE *(volatile unsigned long*)0xF0560000 ++ ++typedef struct _SATA{ ++ volatile unsigned int CDR0; // 0x00 16 RO/WO - Data register in PIO mode Dependencies: Read-only for PIO read/receive operation, write-only for PIO write/transmit operation ++ volatile unsigned int CDR1; // 0x04 8/8/8 RO/WO/WO 0xFF/0x00/0x00 Error register Feature Register(currnet value) Feature Expanded Register(previouis value) ++ volatile unsigned int CDR2; // 0x08 8/8 R/W 0xFF Sector count register (current value) Sector count expanded register (previous value) ++ volatile unsigned int CDR3; // 0x0C 8/8 R/W 0xFF Sector number register (current value) Sector number expanded register (previous value) ++ volatile unsigned int CDR4; // 0x10 8/8 R/W 0xFF Cylinder low register (current value) Cylinder low expanded register (previous value) ++ volatile unsigned int CDR5; // 0x14 8/8 R/W 0xFF Cylinder high register (current value) Cylinder high expanded register (previous value) ++ volatile unsigned int CDR6; // 0x18 8 R/W 0xEF Device/ Head register ++ volatile unsigned int CDR7; // 0x1C 8/8 RO/WO 0x7F/0x00 Status register Dependencies: Value is 0x7F on power-up, then 0x80 when device presence is detected via PHY READY condition. Command register ++ volatile unsigned int CLR0; // 0x20 8/8 RO/WO 0x7F/0x00 Alternative status register Dependencies: Value is 0x7F on power-up, then 0x80 when device presence is detected via PHY READY condition. Device control register ++ volatile unsigned int SCR0; // 0x24 32 RO 0x0 SStatus Register ++ volatile unsigned int SCR1; // 0x28 32 R/W 0x0 SError Register ++ volatile unsigned int SCR2; // 0x2C 32 R/W 0x0 SControl Register ++ volatile unsigned int SCR3; // 0x30 32 R/W 0x0 SActive Register ++ volatile unsigned int SCR4; // 0x34 32 R/W 0x0 Snotification Register ++ volatile unsigned int SCR5; // 0x38 ++ volatile unsigned int SCR6; // 0x3C ++ volatile unsigned int SCR7; // 0x40 ++ volatile unsigned int SCR8; // 0x44 ++ volatile unsigned int SCR9; // 0x48 ++ volatile unsigned int SCR10; // 0x4C ++ volatile unsigned int SCR11; // 0x50 ++ volatile unsigned int SCR12; // 0x54 ++ volatile unsigned int SCR13; // 0x58 ++ volatile unsigned int SCR14; // 0x5C ++ volatile unsigned int SCR15; // 0x60 See description 0x0 Reserved for SATA Dependencies: Reads to these locations return zeros; writes have no effect ++ volatile unsigned int FPTAGR; // 0x64 32 RO 0x0 First Party DMA tag Register ++ volatile unsigned int FPBOR; // 0x68 32 RO 0x0 First Party DMA buffer offset Register ++ volatile unsigned int FPTCR; // 0x6C 32 RO 0x0 First Party DMA transfer count Register ++ volatile unsigned int DMACR; // 0x70 32 R/W 0x0 DMA Control Register ++ volatile unsigned int DBTSR; // 0x74 32 R/W 0x0014 _0010 DMA Burst Transaction Size register ++ volatile unsigned int INTPR; // 0x78 32 R/W 0x0 Interrupt Pending Register ++ volatile unsigned int INTMR; // 0x7C 32 RO 0x0 Interrupt Mask Register ++ volatile unsigned int ERRMR; // 0x80 32 RO 0x0 Error Mask Register ++ volatile unsigned int LLCR; // 0x84 32 R/W 0x0000 _0007 Link Layer Control Register ++ volatile unsigned int NOTDEFINE0[222]; //0x88 ~ 0x3FC ++ volatile unsigned int DMADR[256]; // 0x400-0x7FC FIFO Location in DMA mode ++}SATA, *PSATA; ++ ++ ++/******************************************************************************* ++* 11-1. Audio DMA Controller Register Define (Base Addr = 0xF0533000) ++********************************************************************************/ ++//#define HwADMA_BASE *(volatile unsigned long*)0xF0533000 ++ ++typedef struct _ADMA{ ++ volatile unsigned int RxDaDar; // 0x00 R/W 0x00000000 DAI Rx (Right) Data Destination Address ++ volatile unsigned int RxDaParam; // 0x04 R/W 0x00000000 DAI Rx Parameters ++ volatile unsigned int RxDaTCnt; // 0x08 R/W 0x00000000 DAI Rx Transmission Counter Register ++ volatile unsigned int RxDaCdar; // 0x0C R 0x00000000 DAI Rx (Right) Data Current Destination Address ++ volatile unsigned int RxCdDar; // 0x10 R/W 0x00000000 CDIF(SPDIF) Rx (Right) Data Destination Address ++ volatile unsigned int RxCdParam; // 0x14 R/W 0x00000000 CDIF(SPDIF) Rx Parameters ++ volatile unsigned int RxCdTCnt; // 0x18 R/W 0x00000000 CDIF(SPDIF) Rx Transmission Counter Register ++ volatile unsigned int RxCdCdar; // 0x1C R 0x00000000 CDIF(SPDIF) Rx (Right) Data Current Destination Address ++ volatile unsigned int NOTDEFINE0[2]; ++ volatile unsigned int RxDaDarL; // 0x28 R/W 0x00000000 DAI Rx Left Data Destination Address ++ volatile unsigned int RxDaCdarL; // 0x2C R 0x00000000 DAI Rx Left Data Current Destination Address ++ volatile unsigned int RxCdDarL; // 0x30 R/W 0x00000000 CDIF(SPDIF) Rx Left Data Destination Address ++ volatile unsigned int RxCdCdarL; // 0x34 R 0x00000000 CDIF(SPDIF) Rx Left Data Current Destination Address ++ volatile unsigned int TransCtrl; // 0x38 R/W 0x0000AA00 DMA Transfer Control Register ++ volatile unsigned int RptCtrl; // 0x3C R/W 0x00000000 DMA Repeat Control Register ++ volatile unsigned int TxDaSar; // 0x40 R/W 0x00000000 DAI Tx (Right) Data Source Address ++ volatile unsigned int TxDaParam; // 0x44 R/W 0x00000000 DAI Tx Parameters ++ volatile unsigned int TxDaTCnt; // 0x48 R/W 0x00000000 DAI Tx Transmission Counter Register ++ volatile unsigned int TxDaCsar; // 0x4C R 0x00000000 DAI Tx (Right) Data Current Source Address ++ volatile unsigned int TxSpSar; // 0x50 R/W 0x00000000 SPDIF Tx (Right) Data Source Address ++ volatile unsigned int TxSpParam; // 0x54 R/W 0x00000000 SPDIF Tx Parameters ++ volatile unsigned int TxSpTCnt; // 0x58 R/W 0x00000000 SPDIF Tx Transmission Counter Register ++ volatile unsigned int TxSpCsar; // 0x5C R 0x00000000 SPDIF Tx (Right) Data Current Source Address ++ volatile unsigned int NOTDEFINE1[2]; ++ volatile unsigned int TxDaSarL; // 0x68 R/W 0x00000000 DAI Tx Left Data Source Address ++ volatile unsigned int TxDaCsarL; // 0x6C R 0x00000000 DAI Tx Left Data Current Source Address ++ volatile unsigned int TxSpSarL; // 0x70 R/W 0x00000000 SPDIF Tx Left Data Source Address ++ volatile unsigned int TxSpCsarL; // 0x74 R 0x00000000 SPDIF Tx Left Data Current Source address ++ volatile unsigned int ChCtrl; // 0x78 R/W 0x00008000 DMA Channel Control Register ++ volatile unsigned int IntStatus; // 0x7C R/W 0x00000000 DMA Interrupt Status Register ++ volatile unsigned int GIntReq; // 0x80 R/W 0x00000000 General Interrupt Request ++ volatile unsigned int GIntStatus; // 0x84 R 0x00000000 General Interrupt Status ++ volatile unsigned int NOTDEFINE2[6]; ++ volatile unsigned int RxDaDar1; // 0x100 R/W 0x00000000 DAI1 Rx (Right) Data Destination Address ++ volatile unsigned int RxDaDar2; // 0x104 R/W 0x00000000 DAI2 Rx (Right) Data Destination Address ++ volatile unsigned int RxDaDar3; // 0x108 R/W 0x00000000 DAI3 Rx (Right) Data Destination Address ++ volatile unsigned int RxDaCar1; // 0x10C R 0x00000000 DAI1 Rx (Right) Data Current Destination Address ++ volatile unsigned int RxDaCar2; // 0x110 R 0x00000000 DAI2 Rx (Right) Data Current Destination Address ++ volatile unsigned int RxDaCar3; // 0x114 R 0x00000000 DAI3 Rx (Right) Data Current Destination Address ++ volatile unsigned int RxDaDarL1; // 0x118 R/W 0x00000000 DAI1 Rx Left Data Destination Address ++ volatile unsigned int RxDaDarL2; // 0x11C R/W 0x00000000 DAI2 Rx Left Data Destination Address ++ volatile unsigned int RxDaDarL3; // 0x120 R/W 0x00000000 DAI3 Rx Left Data Destination Address ++ volatile unsigned int RxDaCarL1; // 0x124 R 0x00000000 DAI1 Rx Left Data Current Destination Address ++ volatile unsigned int RxDaCarL2; // 0x128 R 0x00000000 DAI2 Rx Left Data Current Destination Address ++ volatile unsigned int RxDaCarL3; // 0x12C R 0x00000000 DAI3 Rx Left Data Current Destination Address ++ volatile unsigned int TxDaSar1; // 0x130 R/W 0x00000000 DAI1 Tx (Right) Data Source Address ++ volatile unsigned int TxDaSar2; // 0x134 R/W 0x00000000 DAI2 Tx (Right) Data Source Address ++ volatile unsigned int TxDaSar3; // 0x138 R/W 0x00000000 DAI3 Tx (Right) Data Source Address ++ volatile unsigned int TxDaCsar1; // 0x13C R 0x00000000 DAI1 Tx (Right) Data Current Source Address ++ volatile unsigned int TxDaCsar2; // 0x140 R 0x00000000 DAI2 Tx (Right) Data Current Source Address ++ volatile unsigned int TxDaCsar3; // 0x144 R 0x00000000 DAI3 Tx (Right) Data Current Source Address ++ volatile unsigned int TxDaDarL1; // 0x148 R/W 0x00000000 DAI1 Tx Left Data Source Address ++ volatile unsigned int TxDaDarL2; // 0x14C R/W 0x00000000 DAI2 Tx Left Data Source Address ++ volatile unsigned int TxDaDarL3; // 0x150 R/W 0x00000000 DAI3 Tx Left Data Source Address ++ volatile unsigned int TxDaCarL1; // 0x154 R 0x00000000 DAI1 Tx Left Data Current Source Address ++ volatile unsigned int TxDaCarL2; // 0x158 R 0x00000000 DAI2 Tx Left Data Current Source Address ++ volatile unsigned int TxDaCarL3; // 0x15C R 0x00000000 DAI3 Tx Left Data Current Source Address ++}ADMA, *PADMA; ++ ++ ++/******************************************************************************* ++* 11-2. DAI Register Define (Base Addr = 0xF0534000) ++********************************************************************************/ ++//#define HwADMA_DAIBASE *(volatile unsigned long*)0xF0534000 ++ ++typedef struct _ADMADAI{ ++ volatile unsigned int DADIR0; // 0x00 R - Digital Audio Input Register 0 ++ volatile unsigned int DADIR1; // 0x04 R - Digital Audio Input Register 1 ++ volatile unsigned int DADIR2; // 0x08 R - Digital Audio Input Register 2 ++ volatile unsigned int DADIR3; // 0x0C R - Digital Audio Input Register 3 ++ volatile unsigned int DADIR4; // 0x10 R - Digital Audio Input Register 4 ++ volatile unsigned int DADIR5; // 0x14 R - Digital Audio Input Register 5 ++ volatile unsigned int DADIR6; // 0x18 R - Digital Audio Input Register 6 ++ volatile unsigned int DADIR7; // 0x1C R - Digital Audio Input Register 7 ++ volatile unsigned int DADOR0; // 0x20 R/W - Digital Audio Output Register 0 ++ volatile unsigned int DADOR1; // 0x24 R/W - Digital Audio Output Register 1 ++ volatile unsigned int DADOR2; // 0x28 R/W - Digital Audio Output Register 2 ++ volatile unsigned int DADOR3; // 0x2C R/W - Digital Audio Output Register 3 ++ volatile unsigned int DADOR4; // 0x30 R/W - Digital Audio Output Register 4 ++ volatile unsigned int DADOR5; // 0x34 R/W - Digital Audio Output Register 5 ++ volatile unsigned int DADOR6; // 0x38 R/W - Digital Audio Output Register 6 ++ volatile unsigned int DADOR7; // 0x3C R/W - Digital Audio Output Register 7 ++ volatile unsigned int DAMR; // 0x40 R/W 0x00000000 Digital Audio Mode Register ++ volatile unsigned int DAVC; // 0x44 R/W 0x0000 Digital Audio Volume Control Register ++ volatile unsigned int MCCR0; // 0x48 R/W 0x00000000 Multi Channel Control Register 0 ++ volatile unsigned int MCCR1; // 0x4C R/W 0x00000000 Multi Channel Control Register 1 ++}ADMADAI, *PADMADAI; ++ ++ ++ ++/******************************************************************************* ++* 11-3. CDIF Register Define (Base Addr = 0xF0534000) ++********************************************************************************/ ++//#define HwADMA_CDIFBASE *(volatile unsigned long*)0xF0534080 ++ ++typedef struct _ADMACDIF{ ++ volatile unsigned int CDDI_0; // 0x80 R CD Digital Audio Input Register 0 ++ volatile unsigned int CDDI_1; // 0x84 R CD Digital Audio Input Register 1 ++ volatile unsigned int CDDI_2; // 0x88 R CD Digital Audio Input Register 2 ++ volatile unsigned int CDDI_3; // 0x8C R CD Digital Audio Input Register 3 ++ volatile unsigned int CDDI_4; // 0x90 R CD Digital Audio Input Register 4 ++ volatile unsigned int CDDI_5; // 0x94 R CD Digital Audio Input Register 5 ++ volatile unsigned int CDDI_6; // 0x98 R CD Digital Audio Input Register 6 ++ volatile unsigned int CDDI_7; // 0x9C R CD Digital Audio Input Register 7 ++ volatile unsigned int CICR; // 0xA0 R/W 0x0000 CD Interface Control Register ++}ADMACDIF, *PADMACDIF; ++ ++ ++/******************************************************************************* ++* 11-4. ADMA_SPDIF Register Define (Base Addr = 0xF0535000/0xF0535800) ++********************************************************************************/ ++//#define HwADMA_SPDIFTXBASE *(volatile unsigned long*)0xF0535000 ++//#define HwADMA_SPDIFRXBASE *(volatile unsigned long*)0xF0535800 ++ ++typedef struct _ADMASPDIFTX{ ++ volatile unsigned int TxVersion; // 0x00 R 0x00003111 Version Register ++ volatile unsigned int TxConfig; // 0x04 R/W 0x00000000 Configuration Register ++ volatile unsigned int TxChStat; // 0x08 R/W 0x00000000 Channel Status Control Register ++ volatile unsigned int TxIntMask; // 0x0C R/W 0x00000000 Interrupt Mask Register ++ volatile unsigned int TxIntStat; // 0x10 R/W 0x00000000 Interrupt Status Register ++ volatile unsigned int NOTDEFINE0[27]; ++ volatile unsigned int UserData[24]; // 0x80~0xDC W - User Data Buffer ++ volatile unsigned int NOTDEFINE1[8]; ++ volatile unsigned int ChStatus[24]; // 0x100~0x15C W - Channel Status Buffer ++ volatile unsigned int NOTDEFINE2[40]; ++ volatile unsigned int TxBuffer[128]; // 0x200~0x23C W - Transmit Data Buffer ++ volatile unsigned int DMACFG; // 0x400 R/W 0x00000007 Additional Configuration for DMA ++ //volatile unsigned int NOTDEFINE4[159]; ++ //volatile unsigned int CSBUDB[24]; // 0x680~0x6DC W - Merged Window for CSB/UDB ++}ADMASPDIFTX, *PADMASPDIFTX; ++ ++typedef union _RXCAP{ ++ volatile unsigned int RxCapCtln[16]; // 0x840~0x87C(even) W 0x00000000 Channel Status Capture Control Register ++ volatile unsigned int RxCapn[16]; // 0x840~0x87C(odd) W 0x00000000 Captured Channel Status / user bit ++}RXCAP; ++ ++typedef struct _ADMASPDIFRX{ ++ volatile unsigned int RxVersion; // 0x800 R 0x00080111 Version Register ++ volatile unsigned int RxConfig; // 0x804 R/W 0x00000000 Configuration Register ++ volatile unsigned int RxStatus; // 0x808 R 0x00000000 Signal Status Buffer ++ volatile unsigned int RxIntMask; // 0x80C R/W 0x00000000 Interrupt Mask Register ++ volatile unsigned int RxIntStat; // 0x810 R/W 0x00000000 Interrupt Status register ++ volatile unsigned int NOTDEFINE0[11]; ++ RXCAP RxCap; ++ //volatile unsigned int RxCapCtln[16]; // 0x840~0x87C(even) W 0x00000000 Channel Status Capture Control Register ++ //volatile unsigned int RxCapn[16]; // 0x840~0x87C(odd) W 0x00000000 Captured Channel Status / user bit ++ volatile unsigned int RxBuffer[8]; // 0xA00~0xA1C W - Receive Data Buffer ++}ADMASPDIFRX, *PADMASPDIFRX; ++ ++ ++/******************************************************************************* ++* 12-1. DAI Register Define (Base Addr = 0xF0537000 ++********************************************************************************/ ++//#define HwDAI_BASE *(volatile unsigned long*)0xF0537000 ++typedef struct _DAI{ ++ volatile unsigned int DADI_L0; // 0x00 R - Digital Audio Left Input Register 0 ++ volatile unsigned int DADI_R0; // 0x04 R - Digital Audio Right Input Register 0 ++ volatile unsigned int DADI_L1; // 0x08 R - Digital Audio Left Input Register 1 ++ volatile unsigned int DADI_R1; // 0x0C R - Digital Audio Right Input Register 1 ++ volatile unsigned int DADI_L2; // 0x10 R - Digital Audio Left Input Register 2 ++ volatile unsigned int DADI_R2; // 0x14 R - Digital Audio Right Input Register 2 ++ volatile unsigned int DADI_L3; // 0x18 R - Digital Audio Left Input Register 3 ++ volatile unsigned int DADI_R3; // 0x1C R - Digital Audio Right Input Register 3 ++ volatile unsigned int DADO_L0; // 0x20 R/W - Digital Audio Left Output Register 0 ++ volatile unsigned int DADO_R0; // 0x24 R/W - Digital Audio Right Output Register 0 ++ volatile unsigned int DADO_L1; // 0x28 R/W - Digital Audio Left Output Register 1 ++ volatile unsigned int DADO_R1; // 0x2C R/W - Digital Audio Right Output Register 1 ++ volatile unsigned int DADO_L2; // 0x30 R/W - Digital Audio Left Output Register 2 ++ volatile unsigned int DADO_R2; // 0x34 R/W - Digital Audio Right Output Register 2 ++ volatile unsigned int DADO_L3; // 0x38 R/W - Digital Audio Left Output Register 3 ++ volatile unsigned int DADO_R3; // 0x3C R/W - Digital Audio Right Output Register 3 ++ volatile unsigned int DAMR; // 0x40 R/W 0x00000000 Digital Audio Mode Register ++ volatile unsigned int DAVC; // 0x44 R/W 0x0000 Digital Audio Volume Control Register ++}DAI, *PDAI; ++ ++/******************************************************************************* ++* 12-2. CDIF Register Define (Base Addr = 0xF0537000 ++********************************************************************************/ ++//#define HwCDIF_BASE *(volatile unsigned long*)0xF0537080 ++typedef struct _CDIF{ ++ volatile unsigned int CDDI_0; // 0x80 R CD Digital Audio Input Register 0 ++ volatile unsigned int CDDI_1; // 0x84 R CD Digital Audio Input Register 1 ++ volatile unsigned int CDDI_2; // 0x88 R CD Digital Audio Input Register 2 ++ volatile unsigned int CDDI_3; // 0x8C R CD Digital Audio Input Register 3 ++ volatile unsigned int CICR; // 0x90 R/W 0x0000 CD Interface Control Register ++}CDIF, *PCDIF; ++ ++ ++/******************************************************************************* ++* 13. SPDIF Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++//#define HwSPDIF_BASE *(volatile unsigned long*)0xF0538000 ++typedef struct _SPDIF{ ++ volatile unsigned int TxVersion; // 0x00 R Version Register ++ volatile unsigned int TxConfig; // 0x04 R/W Configuration Register ++ volatile unsigned int TxChStat; // 0x08 R/W Channel Status Control Register ++ volatile unsigned int TxIntMask; // 0x0C R/W Interrupt Mask Register ++ volatile unsigned int TxIntStat; // 0x10 R/W Interrupt Status Register ++ volatile unsigned int UserData[24]; // 0x80~0xDC W - User Data Buffer ++ volatile unsigned int ChStatus[24]; // 0x100~0x15C W - Channel Status Buffer ++ volatile unsigned int TxBuffer[128]; // 0x200~0x3FC W - Transmit Data Buffer ++ volatile unsigned int DMACFG; // 0x400 R/W - Additional Configuration for DMA ++}SPDIF, *PSPDIF; ++ ++ ++/******************************************************************************* ++* 14-1. USB1.1 HOST Controller & Transceiver (Base Addr = 0xF0500000) ++********************************************************************************/ ++//#define HwUSBHOST_BASE *(volatile unsigned long*)0xF0500000 ++typedef struct _USBHOST11{ ++ volatile unsigned int HcRevision; // 0x00 R 0x00000010 ++ volatile unsigned int HcControl; // 0x04 R/W 0x00000000 ++ volatile unsigned int HcCommandStatus; // 0x08 R 0x00000000 ++ volatile unsigned int HcInterruptStatus; // 0x0C R 0x00000000 ++ volatile unsigned int HcInterruptEnable; // 0x10 R/W 0x00000000 ++ volatile unsigned int HcInterruptDisable; // 0x14 W 0x00000000 ++ volatile unsigned int HcHCCA; // 0x18 R/W 0x00000000 ++ volatile unsigned int HcPeriodCurrentED; // 0x1C R 0x00000000 ++ volatile unsigned int HcControlHeadED; // 0x20 R/W 0x00000000 ++ volatile unsigned int HcControlCurrentED; // 0x24 R/W 0x00000000 ++ volatile unsigned int HcBulkHeadED; // 0x28 R/W 0x00000000 ++ volatile unsigned int HcBulkCurrentED; // 0x2C R/W 0x00000000 ++ volatile unsigned int HcDoneHead; // 0x30 R 0x00000000 ++ volatile unsigned int HcRmInterval; // 0x34 R/W 0x00002EDF ++ volatile unsigned int HcFmRemaining; // 0x38 R/W 0x00000000 ++ volatile unsigned int HcFmNumber; // 0x3C R/W 0x00000000 ++ volatile unsigned int HcPeriodStart; // 0x40 R/W 0x00000000 ++ volatile unsigned int HcLSThreshold; // 0x44 R/W 0x00000628 ++ volatile unsigned int HcRhDescriptorA; // 0x48 R/W 0x02001202 ++ volatile unsigned int HcRhDescriptorB; // 0x4C R/W 0x00000000 ++ volatile unsigned int HcRhStatus; // 0x50 R/W 0x00000000 ++ volatile unsigned int HcRhPortStatus1; // 0x54 R/W 0x00000100 ++ volatile unsigned int HcRhPortStatus2; // 0x58 R/W 0x00000100 ++}USBHOST11, *PUSBHOST11; ++ ++ ++/******************************************************************************* ++* 14-2. USB1.1 HOST Configuration Register (Base Addr = 0xF05F5000) ++********************************************************************************/ ++//#define HwUSBHOSTCFG_BASE *(volatile unsigned long*)0xF05F5000 ++typedef struct _USBHOST11CFG{ ++ volatile unsigned int NOTDEFINE0; ++ volatile unsigned int USB11H; // 0x4 R/W 0x00000010 USB1.1 Host Configuration register ++}USBHOST11CFG, *PUSBHOST11CFG; ++ ++ ++/******************************************************************************* ++* 15-1. USB2.0 OTG Controller Define (Base Addr = 0xF0550000) ++********************************************************************************/ ++//#define HwUSB20OTG_BASE *(volatile unsigned long*)0xF0550000 ++typedef struct _USB20OTG{ ++ // Core Global CSR Map ++ volatile unsigned int GOTGCTL; // 0x000 R/W OTG Control and Status Register ++ volatile unsigned int GOTGINT; // 0x004 OTG Interrupt Register ++ volatile unsigned int GAHBCFG; // 0x008 Core AHB Configuration Register ++ volatile unsigned int GUSBCFG; // 0x00C Core USB Configuration register ++ volatile unsigned int GRSTCTL; // 0x010 Core Reset Register ++ volatile unsigned int GINTSTS; // 0x014 Core Interrupt Register ++ volatile unsigned int GINTMSK; // 0x018 Core Interrupt Mask Register ++ volatile unsigned int GRXSTSR; // 0x01C Receive Status Debug Read register(Read Only) ++ volatile unsigned int GRXSTSP; // 0x020 Receive Status Read /Pop register(Read Only) ++ volatile unsigned int GRXFSIZ; // 0x024 Receive FIFO Size Register ++ volatile unsigned int GNPTXFSIZ; // 0x028 Non-periodic Transmit FIFO Size register ++ volatile unsigned int GNPTXSTS; // 0x02C Non-periodic Transmit FIFO/Queue Status register (Read Only) ++ volatile unsigned int NOTDEFINE0[3]; // 0x030~ Reserved ++ volatile unsigned int GUID; // 0x03C User ID Register ++ volatile unsigned int NOTDEFINE1; // 0x040 Reserved ++ volatile unsigned int GHWCFG1; // 0x044 User HW Config1 Register(Read Only) ++ volatile unsigned int GHWCFG2; // 0x048 User HW Config2 Register(Read Only) ++ volatile unsigned int GHWCFG3; // 0x04C User HW Config3 Register(Read Only) ++ volatile unsigned int GHWCFG4; // 0x050 User HW Config4 Register(Read Only) ++ volatile unsigned int NOTDEFINE2[43]; // 0x054~ Reserved ++ volatile unsigned int HPTXFSIZ; // 0x100 Host Periodic Transmit FIFO Size Register ++ volatile unsigned int DIEPTXFn[15]; // 0x104~ Device IN Endpoint Transmit FIFO Size register ++ volatile unsigned int NOTDEFINE3[176]; // 0x140~ Reserved ++ // Host Mode CSR Map ++ volatile unsigned int HCFG; // 0x400 Host Configuration Register ++ volatile unsigned int HFIR; // 0x404 Host Frame Interval Register ++ volatile unsigned int HFNUM; // 0x408 Host Frame Number/Frame Time Remaining register ++ volatile unsigned int NOTDEFINE4; // 0x40C Reserved ++ volatile unsigned int HPTXSTS; // 0x410 Host Periodic Transmit FIFO/Queue Status Register ++ volatile unsigned int HAINT; // 0x414 Host All Channels Interrupt Register ++ volatile unsigned int HAINTMSK; // 0x418 Host All Channels Interrupt Mask register ++ volatile unsigned int NOTDEFINE5[9]; // 0x41C~ Not Used ++ volatile unsigned int HPRT; // 0x440 Host Port Control and Status register ++ volatile unsigned int NOTDEFINE6[47]; // 0x444~ Reserved ++ volatile unsigned int HCCHARn; // 0x500 Host Channel 0 Characteristics Register ++ volatile unsigned int HCSPLTn; // 0x504 Host Channel 0 Split Control Register ++ volatile unsigned int HCINTn; // 0x508 Host Channel 0 Interrupt Register ++ volatile unsigned int HCINTMSKn; // 0x50C Host Channel 0 Interrupt Mask Register ++ volatile unsigned int HCTSIZn; // 0x510 Host Channel 0 Transfer Size Register ++ volatile unsigned int HCDMAn; // 0x514 Host Channel 0 DMA Address Register ++ volatile unsigned int NOTDEFINE7[2]; // 0x518~ Reserved ++ volatile unsigned int HCH1[8]; // 0x520~ Host Channel 1 Registers ++ volatile unsigned int HCH2[8]; // 0x540~ Host Channel 2 Registers ++ volatile unsigned int HCH3[8]; // 0x560~ Host Channel 3 Registers ++ volatile unsigned int HCH4[8]; // 0x580~ Host Channel 4 Registers ++ volatile unsigned int HCH5[8]; // 0x5A0~ Host Channel 5 Registers ++ volatile unsigned int HCH6[8]; // 0x5C0~ Host Channel 6 Registers ++ volatile unsigned int HCH7[8]; // 0x5E0~ Host Channel 7 Registers ++ volatile unsigned int HCH8[8]; // 0x600~ Host Channel 8 Registers ++ volatile unsigned int HCH9[8]; // 0x620~ Host Channel 9 Registers ++ volatile unsigned int HCH10[8]; // 0x640~ Host Channel 10 Registers ++ volatile unsigned int HCH11[8]; // 0x660~ Host Channel 11 Registers ++ volatile unsigned int HCH12[8]; // 0x680~ Host Channel 12 Registers ++ volatile unsigned int HCH13[8]; // 0x6A0~ Host Channel 13 Registers ++ volatile unsigned int HCH14[8]; // 0x6C0~ Host Channel 14 Registers ++ volatile unsigned int HCH15[8]; // 0x6E0~ Host Channel 15 Registers ++ volatile unsigned int NOTDEFINE8[64]; // 0x700~ Reserved ++ // Device Mode CSR Map ++ volatile unsigned int DCFG; // 0x800 Device Configuration Register ++ volatile unsigned int DCTL; // 0x804 Device Control Register ++ volatile unsigned int DSTS; // 0x808 Device Status Register (Read Only) ++ volatile unsigned int NOTDEFINE9; // 0x80C Reserved ++ volatile unsigned int DIEPMSK; // 0x810 Device IN Endpoint Common Interrupt Mask Register ++ volatile unsigned int DOEPMSK; // 0x814 Device OUT Endpoint Common Interrupt Mask register ++ volatile unsigned int DAINT; // 0x818 Device All Endpoints Interrupt Register ++ volatile unsigned int DAINTMSK; // 0x81C Device All Endpoints Interrupt Mask Register ++ volatile unsigned int NOTDEFINE10[2]; // 0x820~ Reserved ++ volatile unsigned int DVBUSDIS; // 0x828 Device VBUS Discharge Time Register ++ volatile unsigned int DVBUSPULSE; // 0x82C Device VBUS Pulsing Time register ++ volatile unsigned int DTHRCTL; // 0x830 Device Threshold Control register ++ volatile unsigned int DIEPEMPMSK; // 0x834 Device IN Endpoint FIFO Empty Interrupt Mask register ++ volatile unsigned int NOTDEFINE11[50]; // 0x838~ Reserved ++ ++ volatile unsigned int DIEPCTL0; // 0x900 Device Control IN Endpoint 0 Control Register ++ volatile unsigned int NOTDEFINE12; // 0x904 Reserved ++ volatile unsigned int DIEPINT0; // 0x908 Device IN Endpoint 0 Interrupt Register ++ volatile unsigned int NOTDEFINE13; // 0x90C Reserved ++ volatile unsigned int DIEPTSIZ0; // 0x910 Device IN Endpoint 0 Transfer Size register ++ volatile unsigned int DIEPDMA0; // 0x914 Device IN Endpoint 0 DMA Address Register ++ volatile unsigned int DTXFSTS0; // 0x918 Device IN Endpoint Transmit FIFO Status Register ++ volatile unsigned int NOTDEFINE14; // 0x91C Reserved ++ ++ volatile unsigned int DEVINENDPT[15][8]; // 0x920~ Device IN Endpoint 1~15 Registers ++ volatile unsigned int DOEPCTL0; // 0xB00 Device Control OUT Endpoint 0 Control register ++ volatile unsigned int NOTDEFINE15; // 0xB04 Reserved ++ volatile unsigned int DOEPINT0; // 0xB08 Device OUT Endpoint 0 Interrupt Register ++ volatile unsigned int NOTDEFINE16; // 0xB0C Reserved ++ volatile unsigned int DOEPTSIZ0; // 0xB10 Device OUT Endpoint 0 Transfer Size Register ++ volatile unsigned int DOEPDMA0; // 0xB14 Device OUT Endpoint 0 DMA Address register ++ volatile unsigned int NOTDEFINE17[2]; // 0xB18~ Reserved ++ volatile unsigned int DEVOUTENDPT[15][8]; // 0xB20~ Device OUT Endpoint 1~15 Registers ++ volatile unsigned int NOTDEFINE18[64]; // 0xD00~ Reserved ++ // Power and Clock Gating CSR Map ++ volatile unsigned int PCGCR; // 0xE00 Power and Clock Gating Control Register ++ volatile unsigned int NOTDEFINE19[127]; // 0xE04~ Reserved ++ // Data FIFO(DFIFO) Access Register Map ++ volatile unsigned int DFIFOENDPT[16][1024]; // 0x1000~ Device IN Endpoint 0~16/Host Out Channel 0~16: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT0[1024]; // 0x1000~ Device IN Endpoint 0/Host Out Channel 0: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT1[1024]; // 0x2000~ Device IN Endpoint 1/Host Out Channel 1: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT2[1024]; // 0x3000~ Device IN Endpoint 2/Host Out Channel 2: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT3[1024]; // 0x4000~ Device IN Endpoint 3/Host Out Channel 3: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT4[1024]; // 0x5000~ Device IN Endpoint 4/Host Out Channel 4: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT5[1024]; // 0x6000~ Device IN Endpoint 5/Host Out Channel 5: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT6[1024]; // 0x7000~ Device IN Endpoint 6/Host Out Channel 6: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT7[1024]; // 0x8000~ Device IN Endpoint 7/Host Out Channel 7: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT8[1024]; // 0x9000~ Device IN Endpoint 8/Host Out Channel 8: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT9[1024]; // 0xA000~ Device IN Endpoint 9/Host Out Channel 9: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT10[1024]; // 0xB000~ Device IN Endpoint 10/Host Out Channel 10: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT11[1024]; // 0xC000~ Device IN Endpoint 11/Host Out Channel 11: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT12[1024]; // 0xD000~ Device IN Endpoint 12/Host Out Channel 12: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT13[1024]; // 0xE000~ Device IN Endpoint 13/Host Out Channel 13: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT14[1024]; // 0xF000~ Device IN Endpoint 14/Host Out Channel 14: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT15[1024]; // 0x10000~ Device IN Endpoint 15/Host Out Channel 15: DFIFO Write/Read Access ++}USB20OTG, *PUSB20OTG; ++ ++typedef struct _USBOTG{ ++ // Core Global CSR Map ++ volatile unsigned int GOTGCTL; // 0x000 R/W OTG Control and Status Register ++ volatile unsigned int GOTGINT; // 0x004 OTG Interrupt Register ++ volatile unsigned int GAHBCFG; // 0x008 Core AHB Configuration Register ++ volatile unsigned int GUSBCFG; // 0x00C Core USB Configuration register ++ volatile unsigned int GRSTCTL; // 0x010 Core Reset Register ++ volatile unsigned int GINTSTS; // 0x014 Core Interrupt Register ++ volatile unsigned int GINTMSK; // 0x018 Core Interrupt Mask Register ++ volatile unsigned int GRXSTSR; // 0x01C Receive Status Debug Read register(Read Only) ++ volatile unsigned int GRXSTSP; // 0x020 Receive Status Read /Pop register(Read Only) ++ volatile unsigned int GRXFSIZ; // 0x024 Receive FIFO Size Register ++ volatile unsigned int GNPTXFSIZ; // 0x028 Non-periodic Transmit FIFO Size register ++ volatile unsigned int GNPTXSTS; // 0x02C Non-periodic Transmit FIFO/Queue Status register (Read Only) ++ volatile unsigned int NOTDEFINE0[3]; // 0x030~ Reserved ++ volatile unsigned int GUID; // 0x03C User ID Register ++ volatile unsigned int NOTDEFINE1; // 0x040 Reserved ++ volatile unsigned int GHWCFG1; // 0x044 User HW Config1 Register(Read Only) ++ volatile unsigned int GHWCFG2; // 0x048 User HW Config2 Register(Read Only) ++ volatile unsigned int GHWCFG3; // 0x04C User HW Config3 Register(Read Only) ++ volatile unsigned int GHWCFG4; // 0x050 User HW Config4 Register(Read Only) ++ volatile unsigned int NOTDEFINE2[43]; // 0x054~ Reserved ++ volatile unsigned int HPTXFSIZ; // 0x100 Host Periodic Transmit FIFO Size Register ++ volatile unsigned int DIEPTXFn[15]; // 0x104~ Device IN Endpoint Transmit FIFO Size register ++ volatile unsigned int NOTDEFINE3[176]; // 0x140~ Reserved ++ // Host Mode CSR Map ++ volatile unsigned int HCFG; // 0x400 Host Configuration Register ++ volatile unsigned int HFIR; // 0x404 Host Frame Interval Register ++ volatile unsigned int HFNUM; // 0x408 Host Frame Number/Frame Time Remaining register ++ volatile unsigned int NOTDEFINE4; // 0x40C Reserved ++ volatile unsigned int HPTXSTS; // 0x410 Host Periodic Transmit FIFO/Queue Status Register ++ volatile unsigned int HAINT; // 0x414 Host All Channels Interrupt Register ++ volatile unsigned int HAINTMSK; // 0x418 Host All Channels Interrupt Mask register ++ volatile unsigned int NOTDEFINE5[9]; // 0x41C~ Not Used ++ volatile unsigned int HPRT; // 0x440 Host Port Control and Status register ++ volatile unsigned int NOTDEFINE6[47]; // 0x444~ Reserved ++ volatile unsigned int HCCHARn; // 0x500 Host Channel 0 Characteristics Register ++ volatile unsigned int HCSPLTn; // 0x504 Host Channel 0 Split Control Register ++ volatile unsigned int HCINTn; // 0x508 Host Channel 0 Interrupt Register ++ volatile unsigned int HCINTMSKn; // 0x50C Host Channel 0 Interrupt Mask Register ++ volatile unsigned int HCTSIZn; // 0x510 Host Channel 0 Transfer Size Register ++ volatile unsigned int HCDMAn; // 0x514 Host Channel 0 DMA Address Register ++ volatile unsigned int NOTDEFINE7[2]; // 0x518~ Reserved ++ volatile unsigned int HCH1[8]; // 0x520~ Host Channel 1 Registers ++ volatile unsigned int HCH2[8]; // 0x540~ Host Channel 2 Registers ++ volatile unsigned int HCH3[8]; // 0x560~ Host Channel 3 Registers ++ volatile unsigned int HCH4[8]; // 0x580~ Host Channel 4 Registers ++ volatile unsigned int HCH5[8]; // 0x5A0~ Host Channel 5 Registers ++ volatile unsigned int HCH6[8]; // 0x5C0~ Host Channel 6 Registers ++ volatile unsigned int HCH7[8]; // 0x5E0~ Host Channel 7 Registers ++ volatile unsigned int HCH8[8]; // 0x600~ Host Channel 8 Registers ++ volatile unsigned int HCH9[8]; // 0x620~ Host Channel 9 Registers ++ volatile unsigned int HCH10[8]; // 0x640~ Host Channel 10 Registers ++ volatile unsigned int HCH11[8]; // 0x660~ Host Channel 11 Registers ++ volatile unsigned int HCH12[8]; // 0x680~ Host Channel 12 Registers ++ volatile unsigned int HCH13[8]; // 0x6A0~ Host Channel 13 Registers ++ volatile unsigned int HCH14[8]; // 0x6C0~ Host Channel 14 Registers ++ volatile unsigned int HCH15[8]; // 0x6E0~ Host Channel 15 Registers ++ volatile unsigned int NOTDEFINE8[64]; // 0x700~ Reserved ++ // Device Mode CSR Map ++ volatile unsigned int DCFG; // 0x800 Device Configuration Register ++ volatile unsigned int DCTL; // 0x804 Device Control Register ++ volatile unsigned int DSTS; // 0x808 Device Status Register (Read Only) ++ volatile unsigned int NOTDEFINE9; // 0x80C Reserved ++ volatile unsigned int DIEPMSK; // 0x810 Device IN Endpoint Common Interrupt Mask Register ++ volatile unsigned int DOEPMSK; // 0x814 Device OUT Endpoint Common Interrupt Mask register ++ volatile unsigned int DAINT; // 0x818 Device All Endpoints Interrupt Register ++ volatile unsigned int DAINTMSK; // 0x81C Device All Endpoints Interrupt Mask Register ++ volatile unsigned int NOTDEFINE10[2]; // 0x820~ Reserved ++ volatile unsigned int DVBUSDIS; // 0x828 Device VBUS Discharge Time Register ++ volatile unsigned int DVBUSPULSE; // 0x82C Device VBUS Pulsing Time register ++ volatile unsigned int DTHRCTL; // 0x830 Device Threshold Control register ++ volatile unsigned int DIEPEMPMSK; // 0x834 Device IN Endpoint FIFO Empty Interrupt Mask register ++ volatile unsigned int NOTDEFINE11[50]; // 0x838~ Reserved ++ ++ //volatile unsigned int DIEPCTL0; // 0x900 Device Control IN Endpoint 0 Control Register ++ //volatile unsigned int NOTDEFINE12; // 0x904 Reserved ++ //volatile unsigned int DIEPINT0; // 0x908 Device IN Endpoint 0 Interrupt Register ++ //volatile unsigned int NOTDEFINE13; // 0x90C Reserved ++ //volatile unsigned int DIEPTSIZ0; // 0x910 Device IN Endpoint 0 Transfer Size register ++ //volatile unsigned int DIEPDMA0; // 0x914 Device IN Endpoint 0 DMA Address Register ++ //volatile unsigned int DTXFSTS0; // 0x918 Device IN Endpoint Transmit FIFO Status Register ++ //volatile unsigned int NOTDEFINE14; // 0x91C Reserved ++ ++ volatile unsigned int DEVINENDPT[16][8]; // 0x900~ Device IN Endpoint 1~15 Registers ++ ++ //volatile unsigned int DOEPCTL0; // 0xB00 Device Control OUT Endpoint 0 Control register ++ //volatile unsigned int NOTDEFINE15; // 0xB04 Reserved ++ //volatile unsigned int DOEPINT0; // 0xB08 Device OUT Endpoint 0 Interrupt Register ++ //volatile unsigned int NOTDEFINE16; // 0xB0C Reserved ++ //volatile unsigned int DOEPTSIZ0; // 0xB10 Device OUT Endpoint 0 Transfer Size Register ++ //volatile unsigned int DOEPDMA0; // 0xB14 Device OUT Endpoint 0 DMA Address register ++ //volatile unsigned int NOTDEFINE17[2]; // 0xB18~ Reserved ++ ++ volatile unsigned int DEVOUTENDPT[16][8]; // 0xB00~ Device OUT Endpoint 1~15 Registers ++ volatile unsigned int NOTDEFINE18[64]; // 0xD00~ Reserved ++ ++ // Power and Clock Gating CSR Map ++ volatile unsigned int PCGCR; // 0xE00 Power and Clock Gating Control Register ++ volatile unsigned int NOTDEFINE19[127]; // 0xE04~ Reserved ++ // Data FIFO(DFIFO) Access Register Map ++ volatile unsigned int DFIFOENDPT[16][1024]; // 0x1000~ Device IN Endpoint 0~16/Host Out Channel 0~16: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT0[1024]; // 0x1000~ Device IN Endpoint 0/Host Out Channel 0: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT1[1024]; // 0x2000~ Device IN Endpoint 1/Host Out Channel 1: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT2[1024]; // 0x3000~ Device IN Endpoint 2/Host Out Channel 2: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT3[1024]; // 0x4000~ Device IN Endpoint 3/Host Out Channel 3: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT4[1024]; // 0x5000~ Device IN Endpoint 4/Host Out Channel 4: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT5[1024]; // 0x6000~ Device IN Endpoint 5/Host Out Channel 5: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT6[1024]; // 0x7000~ Device IN Endpoint 6/Host Out Channel 6: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT7[1024]; // 0x8000~ Device IN Endpoint 7/Host Out Channel 7: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT8[1024]; // 0x9000~ Device IN Endpoint 8/Host Out Channel 8: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT9[1024]; // 0xA000~ Device IN Endpoint 9/Host Out Channel 9: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT10[1024]; // 0xB000~ Device IN Endpoint 10/Host Out Channel 10: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT11[1024]; // 0xC000~ Device IN Endpoint 11/Host Out Channel 11: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT12[1024]; // 0xD000~ Device IN Endpoint 12/Host Out Channel 12: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT13[1024]; // 0xE000~ Device IN Endpoint 13/Host Out Channel 13: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT14[1024]; // 0xF000~ Device IN Endpoint 14/Host Out Channel 14: DFIFO Write/Read Access ++ //volatile unsigned int DFIFOENDPT15[1024]; // 0x10000~ Device IN Endpoint 15/Host Out Channel 15: DFIFO Write/Read Access ++}USBOTG, *PUSBOTG; ++/******************************************************************************* ++* 15-2. USB OTG Configuration Register Define (Base Addr = 0xF05F5000) ++********************************************************************************/ ++//#define HwUSBOTGCFG_BASE *(volatile unsigned long*)0xF05F5000 ++typedef struct _USBOTGCFG{ ++ volatile unsigned int OTGCR; // 0x000 R/W USBOTG Configuration Register ++ volatile unsigned int OTGID; // 0x004 R/W USBOTG ID Register ++ volatile unsigned int NOTUSED[8]; // 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24 ++ volatile unsigned int UPCR0; // 0x028 R/W USB PHY Configuration Register0 ++ volatile unsigned int UPCR1; // 0x02C R/W USB PHY Configuration Register1 ++ volatile unsigned int UPCR2; // 0x030 R/W USB PHY Configuration Register2 ++ volatile unsigned int UPCR3; // 0x034 R/W USB PHY Configuration Register3 ++}USBOTGCFG, *PUSBOTGCFG; ++ ++/******************************************************************************* ++* 15-3. USB PHY Configuration Register Define (Base Addr = 0xF05F5028) ++********************************************************************************/ ++//#define HwUSBPHYCFG_BASE *(volatile unsigned long*)0xF05F5028 ++typedef struct _USBPHYCFG ++{ ++ volatile unsigned int UPCR0; // 0x028 R/W USB PHY Configuration Register0 ++ volatile unsigned int UPCR1; // 0x02C R/W USB PHY Configuration Register1 ++ volatile unsigned int UPCR2; // 0x030 R/W USB PHY Configuration Register2 ++ volatile unsigned int UPCR3; // 0x034 R/W USB PHY Configuration Register3 ++}USBPHYCFG, *PUSBPHYCFG; ++ ++ ++/******************************************************************************* ++* 16. External Host Interface Register Define (Base Addr = 0xF0570000/0xF0580000) ++********************************************************************************/ ++//#define HwEHICS0_BASE *(volatile unsigned long*)0xF0570000 ++//#define HwEHICS1_BASE *(volatile unsigned long*)0xF0580000 ++ ++typedef struct _EHI{ ++ volatile unsigned int EHST; //0x00 R/W R/W 0x00000080 Status register ++ volatile unsigned int EHIINT; //0x04 R/W R/W 0x00000000 Internal interrupt control register ++ volatile unsigned int EHEINT; //0x08 R/W R/W 0x00000000 External interrupt control register ++ volatile unsigned int EHA; //0x0C R R/W 0x00000000 Address register ++ volatile unsigned int EHAM; //0x10 R/W R 0x00000000 Address masking register ++ volatile unsigned int EHD; //0x14 R/W R/W 0x00000000 Data register ++ volatile unsigned int EHSEM; //0x18 R/W R/W 0x00000000 Semaphore register ++ volatile unsigned int EHCFG; //0x1C R/W R/W 0x00000000 Configuration registers ++ volatile unsigned int EHIND; //0x20 R W 0x00000000 Index register ++ volatile unsigned int EHRWCS; //0x24 R R/W 0x00000000 Read/Write Control/Status register ++}EHI, *PEHI; ++ ++/******************************************************************************* ++* 17. General Purpose Serial Bus (GPSB) Register Define (Base Addr = 0xF0057000) ++********************************************************************************/ ++/* ++#define HwGPSBCH0_BASE *(volatile unsigned long*)0xF0057000 ++#define HwGPSBCH1_BASE *(volatile unsigned long*)0xF0057100 ++#define HwGPSBCH2_BASE *(volatile unsigned long*)0xF0057200 ++#define HwGPSBCH3_BASE *(volatile unsigned long*)0xF0057300 ++#define HwGPSBCH4_BASE *(volatile unsigned long*)0xF0057400 ++#define HwGPSBCH5_BASE *(volatile unsigned long*)0xF0057500 ++#define HwGPSBPORTCFG_BASE *(volatile unsigned long*)0xF0057800 ++#define HwGPSBPIDTABLE_BASE *(volatile unsigned long*)0xF0057F00 ++*/ ++ ++typedef struct _GPSB{ ++ volatile unsigned int PORT; // 0x000 R/W 0x0000 Data port ++ volatile unsigned int STAT; // 0x004 R/W 0x0000 Status register ++ volatile unsigned int INTEN; // 0x008 R/W 0x0000 Interrupt enable ++ volatile unsigned int MODE; // 0x00C R/W 0x0004 Mode register ++ volatile unsigned int CTRL; // 0x010 R/W 0x0000 Control register ++ volatile unsigned int EVTCTRL; // 0x014 R/W 0x0000 Counter & Ext. Event Control ++ volatile unsigned int CCV; // 0x018 R 0x0000 Counter Current Value ++ volatile unsigned int NOTDEFINE0; ++ volatile unsigned int TXBASE; // 0x020 R/W 0x0000 TX base address register ++ volatile unsigned int RXBASE; // 0x024 R/W 0x0000 RX base address register ++ volatile unsigned int PACKET; // 0x028 R/W 0x0000 Packet register ++ volatile unsigned int DMACTR; // 0x02C R/W 0x0000 DMA control register ++ volatile unsigned int DMASTR; // 0x030 R/W 0x0000 DMA status register ++ volatile unsigned int DMAICR; // 0x034 R/W 0x0000 DMA interrupt control register ++}GPSB, *PGPSB; ++ ++ ++typedef struct _GPSBPORTCFG{ ++ volatile unsigned int PCFG0; // 0x800 R/W 0x03020100 Port Configuration Register 0 ++ volatile unsigned int PCFG1; // 0x804 R/W 0x00000504 Port Configuration Port Config Register 1 ++ volatile unsigned int CIRQST; // 0x808 R 0x0000 Channel IRQ Status Register ++}GPSBPORTCFG, *PGPSBPORTCFG; ++ ++ ++typedef struct _GPSBPIDTABLE{ ++ volatile unsigned int PIDT[0x80/4]; // 0xF00 R/W PID Table ++}GPSBPIDTABLE, *PGPSBPIDTABLE; ++ ++ ++/******************************************************************************* ++* 18. The Transport Stream Interface (TSIF) Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++//#define HwTSIF_BASE *(volatile unsigned long*)0xF053B000 ++//#define HwTSIFPORTSEL_BASE *(volatile unsigned long*)0xF053B800 ++ ++typedef struct _TSIF{ ++ volatile unsigned int TSDI; //0x00 R 0x0000 TSIF Input Data Register ++ volatile unsigned int TSCR; //0x04 R/W 0x0000 TSIF Control Register ++ volatile unsigned int TSPID; //0x08 R/W 0x0000 TSIF PID Register ++ volatile unsigned int TSCTRL; //0x10 R/W 0x0000 TSIF Interrupt Control Register ++ volatile unsigned int TSSTS; //0x10(14) R 0x0000 TSIF Interrupt Status Register(Test) ++}TSIF, *PTSIF; ++ ++typedef struct _TSIFPORTSEL{ ++ volatile unsigned int TSCHS; //0x800 R/W 0x0000 TSIF Channel(Port) Select Register ++}TSIFPORTSEL, *PTSIFPORTSEL; ++ ++/******************************************************************************* ++* 19. GPS Interface Register Define (Base Addr = ) ++********************************************************************************/ ++ ++ ++/******************************************************************************* ++* 20. Remote Control Interface Register Define (Base Addr = 0xF05F3000) ++********************************************************************************/ ++//#define HwREMOCON_BASE *(volatile unsigned long*)0xF05F3000 ++ ++typedef struct _REMOTECON{ ++ volatile unsigned int TXADDR; // 0x00 R/W 0x0000 IR Data Transfer Address ++ volatile unsigned int CMD; // 0x04 R/W 0x0000 Command Register ++ volatile unsigned int CTRL; // 0x08 R/W 0x0000 Control Register ++ volatile unsigned int STA; // 0x0C W 0x0000 Status register ++ volatile unsigned int NOTDEFINE0[13]; ++ volatile unsigned int CLKDIV; // 0x40 R 0x0000 Clock Divide Register ++}REMOTECON, *PREMOTECON; ++ ++ ++/******************************************************************************* ++* 21. I2C Controller Register Define (Base Addr = 0xF0530000) ++********************************************************************************/ ++/* ++#define HwI2CMASTER0_BASE *(volatile unsigned long*)0xF0530000 ++#define HwI2CMASTER1_BASE *(volatile unsigned long*)0xF0530040 ++#define HwI2CSLAVE_BASE *(volatile unsigned long*)0xF0530080 ++#define HwI2CSTATUS_BASE *(volatile unsigned long*)0xF05300C0 ++*/ ++ ++typedef struct _I2CMASTER{ ++ volatile unsigned int PRES; // 0x00 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL; // 0x04 R/W 0x0000 Control Register ++ volatile unsigned int TXR; // 0x08 W 0x0000 Transmit Register ++ volatile unsigned int CMD; // 0x0C W 0x0000 Command Register ++ volatile unsigned int RXR; // 0x10 R 0x0000 Receive Register ++ volatile unsigned int SR; // 0x14 R 0x0000 Status register ++ volatile unsigned int TIME; // 0x18 R/W 0x0000 Timing Control Register ++}I2CMASTER, *PI2CMASTER; ++ ++typedef struct _I2C{ ++ volatile unsigned int PRES0; // 0x00 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL0; // 0x04 R/W 0x0000 Control Register ++ volatile unsigned int TXR0; // 0x08 W 0x0000 Transmit Register ++ volatile unsigned int CMD0; // 0x0C W 0x0000 Command Register ++ volatile unsigned int RXR0; // 0x10 R 0x0000 Receive Register ++ volatile unsigned int SR0; // 0x14 R 0x0000 Status register ++ volatile unsigned int TIME0; // 0x18 R/W 0x0000 Timing Control Register ++ volatile unsigned int NOTUSING[9]; // 1c, 20, 24,28,2c,30,34,38,3c, ++ volatile unsigned int PRES1; // 0x40 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL1; // 0x44 R/W 0x0000 Control Register ++ volatile unsigned int TXR1; // 0x48 W 0x0000 Transmit Register ++ volatile unsigned int CMD1; // 0x4C W 0x0000 Command Register ++ volatile unsigned int RXR1; // 0x50 R 0x0000 Receive Register ++ volatile unsigned int SR1; // 0x54 R 0x0000 Status register ++ volatile unsigned int TIME1; // 0x58 R/W 0x0000 Timing Control Register ++ volatile unsigned int NOTUSING1[26]; ++ volatile unsigned int IRQSTR; // 0xC0 R 0x00000000 IRQ Status Register ++}I2C, *PI2C; ++ ++typedef struct _SMUI2C{ ++ volatile unsigned int PRES0; // 0x00 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL0; // 0x04 R/W 0x0000 Control Register ++ volatile unsigned int TXR0; // 0x08 W 0x0000 Transmit Register ++ volatile unsigned int CMD0; // 0x0C W 0x0000 Command Register ++ volatile unsigned int RXR0; // 0x10 R 0x0000 Receive Register ++ volatile unsigned int SR0; // 0x14 R 0x0000 Status register ++ volatile unsigned int TIME0; // 0x18 R/W 0x0000 Timing Control Register ++ volatile unsigned int NOTUSING[9]; // 1c, 20, 24,28,2c,30,34,38,3c, ++ volatile unsigned int PRES1; // 0x40 R/W 0xFFFF Clock Prescale register ++ volatile unsigned int CTRL1; // 0x44 R/W 0x0000 Control Register ++ volatile unsigned int TXR1; // 0x48 W 0x0000 Transmit Register ++ volatile unsigned int CMD1; // 0x4C W 0x0000 Command Register ++ volatile unsigned int RXR1; // 0x50 R 0x0000 Receive Register ++ volatile unsigned int SR1; // 0x54 R 0x0000 Status register ++ volatile unsigned int TIME1; // 0x58 R/W 0x0000 Timing Control Register ++ volatile unsigned int NOTUSING1[10]; ++ volatile unsigned int IRQSTR; // 0x80 R 0x00000000 IRQ Status Register ++}SMUI2C, *PSMUI2C; ++ ++typedef struct _I2CSLAVE{ ++ volatile unsigned int PORT; // 0x80 R/W - Data Access port (TX/RX FIFO) ++ volatile unsigned int CTL; // 0x84 R/W 0x00000000 Control register ++ volatile unsigned int ADDR; // 0x88 W 0x00000000 Address register ++ volatile unsigned int INT; // 0x8C W 0x00000000 Interrupt Enable Register ++ volatile unsigned int STAT; // 0x90 R 0x00000000 Status Register ++ volatile unsigned int NOTDEFINE0[2]; ++ volatile unsigned int MBF; // 0x9C R/W 0x00000000 Buffer Valid Flag ++ volatile unsigned int MB0; // 0xA0 R/W 0x00000000 Data Buffer 0 (Byte 3 ~ 0) ++ volatile unsigned int MB1; // 0xA4 R/W 0x00000000 Data Buffer 1 (Byte 7 ~ 4) ++}I2CSLAVE, *PI2CSLAVE; ++ ++typedef struct _I2CSTATUS{ ++ volatile unsigned int IRQSTR; // 0xC0 R 0x00000000 IRQ Status Register ++}I2CSTATUS, *PI2CSTATUS; ++ ++ ++/******************************************************************************* ++* 22. UART Controller Register Define (Base Addr = 0xF0538000) ++********************************************************************************/ ++/* ++#define HwUARTCH0_BASE *(volatile unsigned long*)0xF0532000 ++#define HwUARTCH1_BASE *(volatile unsigned long*)0xF0532100 ++#define HwUARTCH2_BASE *(volatile unsigned long*)0xF0532200 ++#define HwUARTCH3_BASE *(volatile unsigned long*)0xF0532300 ++#define HwUARTCH4_BASE *(volatile unsigned long*)0xF0532400 ++#define HwUARTCH5_BASE *(volatile unsigned long*)0xF0532500 ++#define HwUARTPORTMUX_BASE *(volatile unsigned long*)0xF0532600 ++*/ ++typedef union _UARTREG1{ ++ volatile unsigned int RBR; // 0x00 R Unknown Receiver Buffer Register(DLAB = 0) ++ volatile unsigned int THR; // 0x00 W 0x00 Transmitter Holding Register (DLAB=0) ++ volatile unsigned int DLL; // 0x00 R/W 0x00 Divisor Latch (LSB) (DLAB=1) ++}UARTREG1; ++ ++typedef union _UARTREG2{ ++ volatile unsigned int IER; // 0x04 R/W 0x00 Interrupt Enable Register (DLAB=0) ++ volatile unsigned int DLM; // 0x04 R/W 0x00 Divisor Latch (MSB) (DLAB=1) ++}UARTREG2; ++ ++typedef union _UARTREG3{ ++ volatile unsigned int IIR; // 0x08 R Unknown Interrupt Ident. Register (DLAB=0) ++ volatile unsigned int FCR; // 0x08 W 0xC0 FIFO Control Register (DLAB=1) ++}UARTREG3; ++ ++typedef struct _UART{ ++/* ++ volatile unsigned int RBR; // 0x00 R Unknown Receiver Buffer Register(DLAB = 0) ++ volatile unsigned int THR; // 0x00 W 0x00 Transmitter Holding Register (DLAB=0) ++ volatile unsigned int DLL; // 0x00 R/W 0x00 Divisor Latch (LSB) (DLAB=1) ++ volatile unsigned int IER; // 0x04 R/W 0x00 Interrupt Enable Register (DLAB=0) ++ volatile unsigned int DLM; // 0x04 R/W 0x00 Divisor Latch (MSB) (DLAB=1) ++ volatile unsigned int IIR; // 0x08 R Unknown Interrupt Ident. Register (DLAB=0) ++ volatile unsigned int FCR; // 0x08 W 0xC0 FIFO Control Register (DLAB=1) ++*/ ++ UARTREG1 REG1; ++ UARTREG2 REG2; ++ UARTREG3 REG3; ++ volatile unsigned int LCR; // 0x0C R/W 0x03 Line Control Register ++ volatile unsigned int MCR; // 0x10 R/W 0x00 MODEM Control Register ++ volatile unsigned int LSR; // 0x14 R Unknown Line Status Register ++ volatile unsigned int MSR; // 0x18 R Unknown MODEM Status Register ++ volatile unsigned int SCR; // 0x1C R/W 0x00 Scratch Register ++ volatile unsigned int AFT; // 0x20 R/W 0x00 AFC Trigger Level Register ++ volatile unsigned int UCR; // 0x24 R/W 0x00 UART Control register ++ volatile unsigned int NOTDEFINE0[6]; ++ volatile unsigned int SRBR; // 0x40 R Unknown Rx Buffer Register ++ volatile unsigned int STHR; // 0x44 W 0x00 Transmitter Holding Register ++ volatile unsigned int SDLL; // 0x48 R/W 0x00 Divisor Latch (LSB) ++ volatile unsigned int SDLM; // 0x4C R/W 0x00 Divisor Latch (MSB) ++ volatile unsigned int SIER; // 0x50 R/W 0x00 Interrupt Enable register ++ volatile unsigned int NOTDEFINE1[3]; ++ volatile unsigned int SCCR; // 0x60 R/W 0x00 Smart Card Control Register ++ volatile unsigned int STC; // 0x64 R/W 0x00 Smart Card TX Count register ++ volatile unsigned int NOTDEFINE2[6]; ++ volatile unsigned int IRCFG; // 0x80 R/W 0x00 IRDA Configuration Register ++}UART, *PUART; ++ ++ ++typedef struct _UARTPORTMUX{ ++ volatile unsigned int CHSEL; // 0x00 R/W 0x3210 Channel Selection Register ++ volatile unsigned int CHST; // 0x00 R 0x0000 Channel Status Register ++}UARTPORTMUX, *PUARTPORTMUX; ++ ++ ++/******************************************************************************* ++* 23. CAN Controller Register Define (Base Addr = 0xF0531000) ++********************************************************************************/ ++//#define HwCAN_BASE 0xF0531000 ++ ++typedef struct _CANCTRL{ ++ volatile unsigned int CANCTRLREG; // CAN Control Register 0x00 0x0001 ++ volatile unsigned int CANSTATUS; // Status Register 0x04 0x0000 ++ volatile unsigned int CANERRORCNT; // Error Counter 0x08 0x0000 Read only ++ volatile unsigned int CANBITTIMING; // Bit Timing Register 0x0C 0x2301 Write enabled by CCE ++ volatile unsigned int CANINTREG; // Interrupt Register 0x10 0x0000 Read only ++ volatile unsigned int CANTESTREG; // Test Register 0x14 0x00 & 0br0000000 1) Write enabled by Test ++ volatile unsigned int CANBRPEXTREG; // Extenstion Register 0x18 0x0000 Write enabled by CCE ++ volatile unsigned int NOTDEFINE0; // __reserved 0x1C 3) ++ volatile unsigned int CANIF1CMDREQ; // Command Request 0x20 0x0001 ++ volatile unsigned int CANIF1CMDMSK; // Command Mask 0x24 0x0000 ++ volatile unsigned int CANIF1MSK1; // IF1 Mask1 0x28 0xFFFF ++ volatile unsigned int CANIF1MSK2; // IF1 Mask2 0x2C 0xFFFF ++ volatile unsigned int CANIF1ARBIT1; // IF1 Arbitration 1 0x30 0x0000 ++ volatile unsigned int CANIF1ARBIT2; // IF1 Arbitration 2 0x34 0x0000 ++ volatile unsigned int CANIF1MSGCTL; // IF1 Message Control 0x38 0x0000 ++ volatile unsigned int CANIF1DTA1; // IF1 Data A 1 0x3C 0x0000 ++ volatile unsigned int CANIF1DTA2; // IF1 Data A 2 0x40 0x0000 ++ volatile unsigned int CANIF1DTB1; // IF1 Data B 1 0x44 0x0000 ++ volatile unsigned int CANIF1DTB2; // IF1 Data B 2 0x48 0x0000 ++ volatile unsigned int NOTDEFINE1[13]; // __reserved 0x50-0x7C 3) ++ volatile unsigned int CANIF2CMDREQ; // Command Request 0x80 0x0001 ++ volatile unsigned int CANIF2CMDMSK; // Command Mask 0x84 0x0000 ++ volatile unsigned int CANIF2MSK1; // IF1 Mask1 0x88 0xFFFF ++ volatile unsigned int CANIF2MSK2; // IF1 Mask2 0x8C 0xFFFF ++ volatile unsigned int CANIF2ARBIT1; // IF1 Arbitration 1 0x90 0x0000 ++ volatile unsigned int CANIF2ARBIT2; // IF1 Arbitration 2 0x94 0x0000 ++ volatile unsigned int CANIF2MSGCTL; // IF1 Message Control 0x98 0x0000 ++ volatile unsigned int CANIF2DTA1; // IF1 Data A 1 0x9C 0x0000 ++ volatile unsigned int CANIF2DTA2; // IF1 Data A 2 0xA0 0x0000 ++ volatile unsigned int CANIF2DTB1; // IF1 Data B 1 0xA4 0x0000 ++ volatile unsigned int CANIF2DTB2; // IF1 Data B 2 0xA8 0x0000 ++ volatile unsigned int NOTDEFINE2[20]; // __reserved 0xAC-0xFC 3) ++ volatile unsigned int CANTRSREQ1; // Transmission Requrest 1 0x100 0x0000 Read only ++ volatile unsigned int CANTRSREQ2; // Transmission Request 2 0x104 0x0000 Read only ++ volatile unsigned int NOTDEFINE3[5]; // __reserved 0x108-0x11C 3) ++ volatile unsigned int CANNEWDT1; // New Data 1 0x120 0x0000 Read only ++ volatile unsigned int CANNEWDT2; // New Data 2 0x124 0x0000 Read only ++ volatile unsigned int NOTDEFINE4[5]; // __reserved 0x128-0x13C 3) ++ volatile unsigned int CANINTPEND1; // Interrupt Pending 1 0x140 0x0000 Read only ++ volatile unsigned int CANINTPEND2; // Interrupt Pending 2 0x144 0x0000 Read only ++ volatile unsigned int NOTDEFINE5[5]; // __reserved 0x148-0x15C 3) ++ volatile unsigned int CANMSGVALID1; // Message Valid 1 0x160 0x0000 Read only ++ volatile unsigned int CANMSGVALID3; // Message Valid 2 0x164 0x0000 Read only ++ volatile unsigned int NOTDEFINE6[5]; // __reserved 0x168-0x17C ++ ++}CANCTRL, *PCANCTRL; ++ ++ ++ ++ ++/******************************************************************************* ++* 24. DMA Controller Register Define (Base Addr = 0xF0540000) ++********************************************************************************/ ++/* ++#define HwGDMA0_BASE *(volatile unsigned long *)0xF0540000 ++#define HwGDMA1_BASE *(volatile unsigned long *)0xF0540100 ++#define HwGDMA2_BASE *(volatile unsigned long *)0xF0540200 ++#define HwGDMA3_BASE *(volatile unsigned long *)0xF0540300 ++*/ ++typedef struct _GDMACTRL{ ++ volatile unsigned int ST_SADR0; // 0x00 R/W 0x00000000 Start Address of Source Block ++ volatile unsigned int SPARAM0; // 0x04 R/W 0x00000000 Parameter of Source Block ++ volatile unsigned int NOTDEFINE0; // 0x08 ++ volatile unsigned int C_SADR0; // 0x0C R 0x00000000 Current Address of Source Block ++ volatile unsigned int ST_DADR0; // 0x10 R/W 0x00000000 Start Address of Destination Block ++ volatile unsigned int DPARAM0; // 0x14 R/W 0x00000000 Parameter of Destination Block ++ volatile unsigned int NOTDEFINE1; // 0x18 ++ volatile unsigned int C_DADR0; // 0x1C R 0x00000000 Current Address of Destination Block ++ volatile unsigned int HCOUNT0; // 0x20 R/W 0x00000000 Initial and Current Hop count ++ volatile unsigned int CHCTRL0; // 0x24 R/W 0x00000000 Channel Control Register ++ volatile unsigned int RPTCTRL0; // 0x28 R/W 0x00000000 Repeat Control Register ++ volatile unsigned int EXTREQ0; // 0x2C R/W 0x00000000 External DMA Request Register ++ volatile unsigned int ST_SADR1; // 0x30 R/W 0x00000000 Start Address of Source Block ++ volatile unsigned int SPARAM1; // 0x34 R/W 0x00000000 Parameter of Source Block ++ volatile unsigned int NOTDEFINE2; // 0x38 ++ volatile unsigned int C_SADR1; // 0x3C R 0x00000000 Current Address of Source Block ++ volatile unsigned int ST_DADR1; // 0x40 R/W 0x00000000 Start Address of Destination Block ++ volatile unsigned int DPARAM1; // 0x44 R/W 0x00000000 Parameter of Destination Block ++ volatile unsigned int NOTDEFINE3; // 0x48 ++ volatile unsigned int C_DADR1; // 0x4C R 0x00000000 Current Address of Destination Block ++ volatile unsigned int HCOUNT1; // 0x50 R/W 0x00000000 Initial and Current Hop count ++ volatile unsigned int CHCTRL1; // 0x54 R/W 0x00000000 Channel Control Register ++ volatile unsigned int RPTCTRL1; // 0x58 R/W 0x00000000 Repeat Control Register ++ volatile unsigned int EXTREQ1; // 0x5C R/W 0x00000000 External DMA Request Register ++ volatile unsigned int ST_SADR2; // 0x60 R/W 0x00000000 Start Address of Source Block ++ volatile unsigned int SPARAM2; // 0x64/ R/W 0x00000000 Parameter of Source Block ++ volatile unsigned int NOTDEFINE4; // 0x68 ++ volatile unsigned int C_SADR2; // 0x6C R 0x00000000 Current Address of Source Block ++ volatile unsigned int ST_DADR2; // 0x70 R/W 0x00000000 Start Address of Destination Block ++ volatile unsigned int DPARAM2; // 0x74/ R/W 0x00000000 Parameter of Destination Block ++ volatile unsigned int NOTDEFINE5; // 0x78 ++ volatile unsigned int C_DADR2; // 0x7C R 0x00000000 Current Address of Destination Block ++ volatile unsigned int HCOUNT2; // 0x80 R/W 0x00000000 Initial and Current Hop count ++ volatile unsigned int CHCTRL2; // 0x84 R/W 0x00000000 Channel Control Register ++ volatile unsigned int RPTCTRL2; // 0x88 R/W 0x00000000 Repeat Control Register ++ volatile unsigned int EXTREQ2; // 0x8C R/W 0x00000000 External DMA Request Register ++ volatile unsigned int CHCONFIG; // 0x90 R/W 0x00000000 Channel Configuration Register ++}GDMACTRL, *PGDMACTRL; ++ ++ ++typedef struct _GDMANCTRL{ ++ volatile unsigned int ST_SADR; // 0x000 R/W Start Address of Source Block ++ volatile unsigned int SPARAM[2]; // 0x004~ R/W Parameter of Source Block ++ volatile unsigned int C_SADR; // 0x00C R Current Address of Source Block ++ volatile unsigned int ST_DADR; // 0x010 R/W Start Address of Destination Block ++ volatile unsigned int DPARAM[2]; // 0x014~ R/W Parameter of Destination Block ++ volatile unsigned int C_DADR; // 0x01C R Current Address of Destination Block ++ volatile unsigned int HCOUNT; // 0x020 R/W Initial and Current Hop count ++ volatile unsigned int CHCTRL; // 0x024 R/W Channel Control Register ++ volatile unsigned int RPTCTRL; // 0x028 R/W Repeat Control Register ++ volatile unsigned int EXTREQ; // 0x02C R/W External DMA Request Register ++} GDMANCTRL, *PGDMANCTRL; ++ ++/******************************************************************************* ++* 25. Real Time Clock(RTC) Register Define (Base Addr = 0xF05F2000) ++********************************************************************************/ ++//#define HwRTC_BASE *(volatile unsigned long*)0xF05F2000 ++ ++typedef struct _RTC{ ++ volatile unsigned int RTCCON; // 0x00 R/W 0x00 RTC Control Register ++ volatile unsigned int INTCON; // 0x04 R/W - RTC Interrupt Control Register ++ volatile unsigned int RTCALM; // 0x08 R/W - RTC Alarm Control Register ++ volatile unsigned int ALMSEC; // 0x0C R/W - Alarm Second Data Register ++ ++ volatile unsigned int ALMMIN; // 0x10 R/W - Alarm Minute Data Register ++ volatile unsigned int ALMHOUR; // 0x14 R/W - Alarm Hour Data Register ++ volatile unsigned int ALMDATE; // 0x18 R/W - Alarm Date Data Register ++ volatile unsigned int ALMDAY; // 0x1C R/W - Alarm Day of Week Data Register ++ ++ volatile unsigned int ALMMON; // 0x20 R/W - Alarm Month Data Register ++ volatile unsigned int ALMYEAR; // 0x24 R/W - Alarm Year Data Register ++ volatile unsigned int BCDSEC; // 0x28 R/W - BCD Second Register ++ volatile unsigned int BCDMIN; // 0x2C R/W - BCD Minute Register ++ ++ volatile unsigned int BCDHOUR; // 0x30 R/W - BCD Hour Register ++ volatile unsigned int BCDDATE; // 0x34 R/W - BCD Date Register ++ volatile unsigned int BCDDAY; // 0x38 R/W - BCD Day of Week Register ++ volatile unsigned int BCDMON; // 0x3C R/W - BCD Month Register ++ ++ volatile unsigned int BCDYEAR; // 0x40 R/W - BCD Year Register ++ volatile unsigned int RTCIM; // 0x44 R/W - RTC Interrupt Mode Register ++ volatile unsigned int RTCPEND; // 0x48 R/W - RTC Interrupt Pending Register ++ volatile unsigned int RTCSTR; // 0x48 R/W - RTC Interrupt Pending Register ++}RTC, *PRTC; ++ ++ ++/******************************************************************************* ++* 26. TouchScreen ADC (TSADC) Register Define (Base Addr = 0xF05F4000) ++********************************************************************************/ ++//#define HwTSADC_BASE *(volatile unsigned long*)0xF05F4000 ++typedef struct _TSADC{ ++ volatile unsigned int ADCCON; // 0x00 R/W 0x00003FC4 ADC Control Register ++ volatile unsigned int ADCTSC; // 0x04 R/W 0x00000058 ADC Touch Screen Control Register ++ volatile unsigned int ADCDLY; // 0x08 R/W 0x000000FF ADC Start or Interval Delay Register ++ volatile unsigned int ADCDAT0; // 0x0C R - ADC Conversion Data Register ++ volatile unsigned int ADCDAT1; // 0x10 R - ADC Conversion Data Register ++ volatile unsigned int ADCUPDN; // 0x14 R/W 0x00000000 Stylus Up or Down Interrupt Register ++ volatile unsigned int ADCCLRINT; // 0x18 W - Clear ADC Interrrupt ++ volatile unsigned int NOTDEFINE0; // 0x1C - - Reserved ++ volatile unsigned int ADCCLRUPDN; // 0x20 W - Clear Pen UP/DOWN Interrupt ++}TSADC, *PTSADC; ++ ++ ++/******************************************************************************* ++* 27. Error Correction Code Register Define (Base Addr = 0xF0539000) ++********************************************************************************/ ++//#define HwECC_BASE *(volatile unsigned long*)0xF0539000 ++//#define HwECCERRADDR_BASE *(volatile unsigned long*)0xF0539050 ++ ++//================================================================================= ++// ECC Code Register ++//================================================================================= ++typedef struct _ECC{ ++ volatile unsigned int ECC_CTRL; // 0x000 R/W ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x004 R/W Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x008 R/W Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x00C R/W ECC Clear ++ volatile unsigned int ECC_CODE0; // 0x010 R/W 1st ECC Code Register ++ volatile unsigned int ECC_CODE1; // 0x014 R/W 2nd ECC Code Register ++ volatile unsigned int ECC_CODE2; // 0x018 R/W 3rd ECC Code Register ++ volatile unsigned int ECC_CODE3; // 0x01C R/W 4th ECC Code Register ++ volatile unsigned int ECC_CODE4; // 0x020 R/W 5th ECC Code Register ++ volatile unsigned int ECC_CODE5; // 0x024 R/W 6th ECC Code Register ++ volatile unsigned int ECC_CODE6; // 0x028 R/W 7th ECC Code Register ++ volatile unsigned int ECC_CODE7; // 0x02C R/W 8th ECC Code Register ++ volatile unsigned int ECC_CODE8; // 0x030 R/W 9th ECC Code Register ++ volatile unsigned int ECC_CODE9; // 0x034 R/W 10th ECC Code Register ++ volatile unsigned int ECC_CODE10; // 0x038 R/W 11th ECC Code Register ++ volatile unsigned int ECC_CODE11; // 0x03C R/W 12th ECC Code Register ++ volatile unsigned int ECC_CODE12; // 0x040 R/W 13th ECC Code Register ++ volatile unsigned int ECC_CODE13; // 0x044 R/W 14th ECC Code Register ++ volatile unsigned int ECC_CODE14; // 0x048 R/W 15th ECC Code Register ++ volatile unsigned int ECC_CODE15; // 0x04C R/W 16th ECC Code register ++ volatile unsigned int ECC_EADDR0; // 0x050 R ECC Error Address Register0 ++ volatile unsigned int ECC_EADDR1; // 0x054 R ECC Error Address Register1 ++ volatile unsigned int ECC_EADDR2; // 0x058 R ECC Error Address Register2 ++ volatile unsigned int ECC_EADDR3; // 0x05C R ECC Error Address Register3 ++ volatile unsigned int ECC_EADDR4; // 0x060 R ECC Error Address Register4 ++ volatile unsigned int ECC_EADDR5; // 0x064 R ECC Error Address Register5 ++ volatile unsigned int ECC_EADDR6; // 0x068 R ECC Error Address Register6 ++ volatile unsigned int ECC_EADDR7; // 0x06C R ECC Error Address Register7 ++ volatile unsigned int ECC_EADDR8; // 0x070 R ECC Error Address Register8 ++ volatile unsigned int ECC_EADDR9; // 0x074 R ECC Error Address Register9 ++ volatile unsigned int ECC_EADDR10; // 0x078 R ECC Error Address Register10 ++ volatile unsigned int ECC_EADDR11; // 0x07C R ECC Error Address Register11 ++ volatile unsigned int ECC_EADDR12; // 0x080 R ECC Error Address Register12 ++ volatile unsigned int ECC_EADDR13; // 0x084 R ECC Error Address Register13 ++ volatile unsigned int ECC_EADDR14; // 0x088 R ECC Error Address Register14 ++ volatile unsigned int ECC_EADDR15; // 0x08C R ECC Error Address Register15 ++ volatile unsigned int ERRNUM; // 0x090 R ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x094 R/W ECC Interrupt Control Register ++}ECC, *PECC; ++ ++typedef struct _SLCECC{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int SECC_0; // 0x10 R/W 0x00000000 1st SLC ECC Code Register ++ volatile unsigned int SECC_1; // 0x14 R/W 0x00000000 2nd SLC ECC Code Register ++ volatile unsigned int SECC_2; // 0x18 R/W 0x00000000 3rd SLC ECC Code Register ++ volatile unsigned int SECC_3; // 0x1C R/W 0x00000000 4th SLC ECC Code Register ++ volatile unsigned int SECC_4; // 0x20 R/W 0x00000000 5th SLC ECC Code Register ++ volatile unsigned int SECC_5; // 0x24 R/W 0x00000000 6th SLC ECC Code Register ++ volatile unsigned int SECC_6; // 0x28 R/W 0x00000000 7th SLC ECC Code Register ++ volatile unsigned int SECC_7; // 0x2C R/W 0x00000000 8th SLC ECC Code Register ++ volatile unsigned int SECC_8; // 0x30 R/W 0x00000000 9th SLC ECC Code Register ++ volatile unsigned int SECC_9; // 0x34 R/W 0x00000000 10th SLC ECC Code Register ++ volatile unsigned int SECC_10; // 0x38 R/W 0x00000000 11th SLC ECC Code Register ++ volatile unsigned int SECC_11; // 0x3C R/W 0x00000000 12th SLC ECC Code Register ++ volatile unsigned int SECC_12; // 0x40 R/W 0x00000000 13th SLC ECC Code Register ++ volatile unsigned int SECC_13; // 0x44 R/W 0x00000000 14th SLC ECC Code Register ++ volatile unsigned int SECC_14; // 0x48 R/W 0x00000000 15th SLC ECC Code Register ++ volatile unsigned int SECC_15; // 0x4C R/W 0x00000000 16th SLC ECC Code register ++ ++}SLCECC, *PSLCECC; ++ ++typedef struct _MLCECC4{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int MECC4_0; // 0x10 R/W 0x00000000 1st MLC ECC4 Code Register ++ volatile unsigned int MECC4_1; // 0x14 R/W 0x00000000 2nd MLC ECC4 Code register ++ ++}MLCECC4, *PMLCECC4; ++ ++typedef struct _MLCECC8{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int MECC8_0; // 0x10 R/W 0x00000000 1st MLC ECC8 Code Register ++ volatile unsigned int MECC8_1; // 0x14 R/W 0x00000000 2nd MLC ECC8 Code Register ++ volatile unsigned int MECC8_2; // 0x18 R/W 0x00000000 3rd MLC ECC8 Code Register ++ volatile unsigned int MECC8_3; // 0x1C R/W 0x00000000 4th MLC ECC8 Code Register ++}MLCECC8, *PMLCECC8; ++ ++ ++typedef struct _MLCECC12{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int MECC12_0; // 0x10 R/W 0x00000000 1st MLC ECC12 Code Register ++ volatile unsigned int MECC12_1; // 0x14 R/W 0x00000000 2nd MLC ECC12 Code Register ++ volatile unsigned int MECC12_2; // 0x18 R/W 0x00000000 3rd MLC ECC12 Code Register ++ volatile unsigned int MECC12_3; // 0x1C R/W 0x00000000 4th MLC ECC12 Code Register ++ volatile unsigned int MECC12_4; // 0x20 R/W 0x00000000 5th MLC ECC12 Code Register ++}MLCECC12, *PMLCECC12; ++ ++ ++typedef struct _MLCECC14{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int MECC14_0; // 0x10 R/W 0x00000000 1st MLC ECC14 Code Register ++ volatile unsigned int MECC14_1; // 0x14 R/W 0x00000000 2nd MLC ECC14 Code Register ++ volatile unsigned int MECC14_2; // 0x18 R/W 0x00000000 3rd MLC ECC14 Code Register ++ volatile unsigned int MECC14_3; // 0x1C R/W 0x00000000 4th MLC ECC14 Code Register ++ volatile unsigned int MECC14_4; // 0x20 R/W 0x00000000 5th MLC ECC14 Code Register ++ volatile unsigned int MECC14_5; // 0x24 R/W 0x00000000 6th MLC ECC14 Code Register ++}MLCECC14, *PMLCECC14; ++ ++ ++typedef struct _MLCECC16{ ++ volatile unsigned int ECC_CTRL; // 0x00 R/W 0x00000000 ECC Control Register ++ volatile unsigned int ECC_BASE; // 0x04 R/W 0x00000000 Base Address for ECC Calculation ++ volatile unsigned int ECC_MASK; // 0x08 R/W 0x00000000 Address mask for ECC area. ++ volatile unsigned int ECC_CLEAR; // 0x0C R/W ECC Clear ++ volatile unsigned int MECC16_0; // 0x10 R/W 0x00000000 1st MLC ECC16 Code Register ++ volatile unsigned int MECC16_1; // 0x14 R/W 0x00000000 2nd MLC ECC16 Code Register ++ volatile unsigned int MECC16_2; // 0x18 R/W 0x00000000 3rd MLC ECC16 Code Register ++ volatile unsigned int MECC16_3; // 0x1C R/W 0x00000000 4th MLC ECC16 Code Register ++ volatile unsigned int MECC16_4; // 0x20 R/W 0x00000000 5th MLC ECC16 Code Register ++ volatile unsigned int MECC16_5; // 0x24 R/W 0x00000000 6th MLC ECC16 Code Register ++ volatile unsigned int MECC16_6; // 0x28 R/W 0x00000000 7th MLC ECC16 Code Register ++}MLCECC16, *PMLCECC16; ++ ++//================================================================================= ++// ECC Error Address Register ++//================================================================================= ++typedef struct _SLCECCERRADDR{ ++ volatile unsigned int SECC_EADDR0; // 0x50 R 0x00000000 SLC ECC Error Address Register0 ++ volatile unsigned int SECC_EADDR1; // 0x54 R 0x00000000 SLC ECC Error Address Register1 ++ volatile unsigned int SECC_EADDR2; // 0x58 R 0x00000000 SLC ECC Error Address Register2 ++ volatile unsigned int SECC_EADDR3; // 0x5C R 0x00000000 SLC ECC Error Address Register3 ++ volatile unsigned int SECC_EADDR4; // 0x60 R 0x00000000 SLC ECC Error Address Register4 ++ volatile unsigned int SECC_EADDR5; // 0x64 R 0x00000000 SLC ECC Error Address Register5 ++ volatile unsigned int SECC_EADDR6; // 0x68 R 0x00000000 SLC ECC Error Address Register6 ++ volatile unsigned int SECC_EADDR7; // 0x6C R 0x00000000 SLC ECC Error Address Register7 ++ volatile unsigned int SECC_EADDR8; // 0x70 R 0x00000000 SLC ECC Error Address Register8 ++ volatile unsigned int SECC_EADDR9; // 0x74 R 0x00000000 SLC ECC Error Address Register9 ++ volatile unsigned int SECC_EADDR10; // 0x78 R 0x00000000 SLC ECC Error Address Register10 ++ volatile unsigned int SECC_EADDR11; // 0x7C R 0x00000000 SLC ECC Error Address Register11 ++ volatile unsigned int SECC_EADDR12; // 0x80 R 0x00000000 SLC ECC Error Address Register12 ++ volatile unsigned int SECC_EADDR13; // 0x84 R 0x00000000 SLC ECC Error Address Register13 ++ volatile unsigned int SECC_EADDR14; // 0x88 R 0x00000000 SLC ECC Error Address Register14 ++ volatile unsigned int SECC_EADDR15; // 0x8C R 0x00000000 SLC ECC Error Address Register15 ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}SLCECCERRADDR, *PSLCECCERRADDR; ++ ++ ++typedef struct _MLCECC4ERRADDR{ ++ volatile unsigned int MECC4_EADDR0; // 0x50 R 0x00000000 MLC ECC Error Address Register0 ++ volatile unsigned int MECC4_EADDR1; // 0x54 R 0x00000000 MLC ECC Error Address Register1 ++ volatile unsigned int MECC4_EADDR2; // 0x58 R 0x00000000 MLC ECC Error Address Register2 ++ volatile unsigned int MECC4_EADDR3; // 0x5C R 0x00000000 MLC ECC Error Address Register3 ++ volatile unsigned int NOTDEFINE0[12]; ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}MLCECC4ERRADDR, *PMLCECC4ERRADDR; ++ ++ ++typedef struct _MLCECC8ERRADDR{ ++ volatile unsigned int MECC8_EADDR0; // 0x50 R 0x00000000 MLC ECC8 Error Address Register0 ++ volatile unsigned int MECC8_EADDR1; // 0x54 R 0x00000000 MLC ECC8 Error Address Register1 ++ volatile unsigned int MECC8_EADDR2; // 0x58 R 0x00000000 MLC ECC8 Error Address Register2 ++ volatile unsigned int MECC8_EADDR3; // 0x5C R 0x00000000 MLC ECC8 Error Address Register3 ++ volatile unsigned int MECC8_EADDR4; // 0x60 R 0x00000000 MLC ECC8 Error Address Register4 ++ volatile unsigned int MECC8_EADDR5; // 0x64 R 0x00000000 MLC ECC8 Error Address Register5 ++ volatile unsigned int MECC8_EADDR6; // 0x68 R 0x00000000 MLC ECC8 Error Address Register6 ++ volatile unsigned int MECC8_EADDR7; // 0x6C R 0x00000000 MLC ECC8 Error Address Register7 ++ volatile unsigned int NOTDEFINE0[8]; ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}MLCECC8ERRADDR, *PMLCECC8ERRADDR; ++ ++ ++typedef struct _MLCECC12ERRADDR{ ++ volatile unsigned int MECC12_EADDR0; // 0x50 R 0x00000000 MLC ECC12 Error Address Register0 ++ volatile unsigned int MECC12_EADDR1; // 0x54 R 0x00000000 MLC ECC12 Error Address Register1 ++ volatile unsigned int MECC12_EADDR2; // 0x58 R 0x00000000 MLC ECC12 Error Address Register2 ++ volatile unsigned int MECC12_EADDR3; // 0x5C R 0x00000000 MLC ECC12 Error Address Register3 ++ volatile unsigned int MECC12_EADDR4; // 0x60 R 0x00000000 MLC ECC12 Error Address Register4 ++ volatile unsigned int MECC12_EADDR5; // 0x64 R 0x00000000 MLC ECC12 Error Address Register5 ++ volatile unsigned int MECC12_EADDR6; // 0x68 R 0x00000000 MLC ECC12 Error Address Register6 ++ volatile unsigned int MECC12_EADDR7; // 0x6C R 0x00000000 MLC ECC12 Error Address Register7 ++ volatile unsigned int MECC12_EADDR8; // 0x70 R 0x00000000 MLC ECC12 Error Address Register8 ++ volatile unsigned int MECC12_EADDR9; // 0x74 R 0x00000000 MLC ECC12 Error Address Register9 ++ volatile unsigned int MECC12_EADDR10; // 0x78 R 0x00000000 MLC ECC12 Error Address Register10 ++ volatile unsigned int MECC12_EADDR11; // 0x7C R 0x00000000 MLC ECC12 Error Address Register11 ++ volatile unsigned int NOTDEFINE0[4]; ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}MLCECC12ERRADDR, *PMLCECC12ERRADDR; ++ ++typedef struct _MLCECC14ERRADDR{ ++ volatile unsigned int MECC14_EADDR0; // 0x50 R 0x00000000 MLC ECC14 Error Address Register0 ++ volatile unsigned int MECC14_EADDR1; // 0x54 R 0x00000000 MLC ECC14 Error Address Register1 ++ volatile unsigned int MECC14_EADDR2; // 0x58 R 0x00000000 MLC ECC14 Error Address Register2 ++ volatile unsigned int MECC14_EADDR3; // 0x5C R 0x00000000 MLC ECC14 Error Address Register3 ++ volatile unsigned int MECC14_EADDR4; // 0x60 R 0x00000000 MLC ECC14 Error Address Register4 ++ volatile unsigned int MECC14_EADDR5; // 0x64 R 0x00000000 MLC ECC14 Error Address Register5 ++ volatile unsigned int MECC14_EADDR6; // 0x68 R 0x00000000 MLC ECC14 Error Address Register6 ++ volatile unsigned int MECC14_EADDR7; // 0x6C R 0x00000000 MLC ECC14 Error Address Register7 ++ volatile unsigned int MECC14_EADDR8; // 0x70 R 0x00000000 MLC ECC14 Error Address Register8 ++ volatile unsigned int MECC14_EADDR9; // 0x74 R 0x00000000 MLC ECC14 Error Address Register9 ++ volatile unsigned int MECC14_EADDR10; // 0x78 R 0x00000000 MLC ECC14 Error Address Register10 ++ volatile unsigned int MECC14_EADDR11; // 0x7C R 0x00000000 MLC ECC14 Error Address Register11 ++ volatile unsigned int MECC14_EADDR12; // 0x80 R 0x00000000 MLC ECC14 Error Address Register12 ++ volatile unsigned int MECC14_EADDR13; // 0x84 R 0x00000000 MLC ECC14 Error Address Register13 ++ volatile unsigned int NOTDEFINE0[2]; ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}MLCECC14ERRADDR, *PMLCECC14ERRADDR; ++ ++typedef struct _MLCECC16ERRADDR{ ++ volatile unsigned int MECC16_EADDR0; // 0x50 R 0x00000000 MLC ECC16 Error Address Register0 ++ volatile unsigned int MECC16_EADDR1; // 0x54 R 0x00000000 MLC ECC16 Error Address Register1 ++ volatile unsigned int MECC16_EADDR2; // 0x58 R 0x00000000 MLC ECC16 Error Address Register2 ++ volatile unsigned int MECC16_EADDR3; // 0x5C R 0x00000000 MLC ECC16 Error Address Register3 ++ volatile unsigned int MECC16_EADDR4; // 0x60 R 0x00000000 MLC ECC16 Error Address Register4 ++ volatile unsigned int MECC16_EADDR5; // 0x64 R 0x00000000 MLC ECC16 Error Address Register5 ++ volatile unsigned int MECC16_EADDR6; // 0x68 R 0x00000000 MLC ECC16 Error Address Register6 ++ volatile unsigned int MECC16_EADDR7; // 0x6C R 0x00000000 MLC ECC16 Error Address Register7 ++ volatile unsigned int MECC16_EADDR8; // 0x70 R 0x00000000 MLC ECC16 Error Address Register8 ++ volatile unsigned int MECC16_EADDR9; // 0x74 R 0x00000000 MLC ECC16 Error Address Register9 ++ volatile unsigned int MECC16_EADDR10; // 0x78 R 0x00000000 MLC ECC16 Error Address Register10 ++ volatile unsigned int MECC16_EADDR11; // 0x7C R 0x00000000 MLC ECC16 Error Address Register11 ++ volatile unsigned int MECC16_EADDR12; // 0x80 R 0x00000000 MLC ECC16 Error Address Register12 ++ volatile unsigned int MECC16_EADDR13; // 0x84 R 0x00000000 MLC ECC16 Error Address Register13 ++ volatile unsigned int MECC16_EADDR14; // 0x88 R 0x00000000 MLC ECC16 Error Address Register14 ++ volatile unsigned int MECC16_EADDR15; // 0x8C R 0x00000000 MLC ECC16 Error Address Register15 ++ volatile unsigned int ERRNUM; // 0x90 R 0x00000000 ECC Error Number ++ volatile unsigned int ECC_IREQ; // 0x94 R/W 0x00000000 ECC Interrupt Control Register ++}MLCECC16ERRADDR, *PMLCECC16ERRADDR; ++ ++ ++/******************************************************************************* ++* 28. Multi-Protocol Encapsulation Forward Error Correction (MPEFEC) ++* Register Define (Base Addr = 0xF0510000) ++********************************************************************************/ ++//#define HwMPEFEC_BASE *(volatile unsigned long*)0xF0510000 ++ ++typedef struct _MPEFEC{ ++ volatile unsigned int MERR; // 0x00 R/W 0x00000000 MPE_FEC Enable/ RESET [1] -> MPE_FEC Enable [0] -> MPE_FEC RESET ++ volatile unsigned int MSR; // 0x04 W 0x00000000 MPE_FEC Start (Auto clear) ++ volatile unsigned int MFRNR; // 0x08 R/W 0x03FF03FF [25:16] active row number -1 : MPE Frame Áß ¸î°³ÀÇ row´ÜÀ§·Î MEPFEC¸¦ µ¿ÀÛ½ÃÅ°´ÂÁö ¼³Á¤ ÇÔ [9:0] MPE Frame ÀÇ row -1 °³¼ö ++ volatile unsigned int MDSAR; // 0x0C R/W 0x00000000 Datagram ÀÌ ÀúÀåµÇ¾î ÀÖ´Â memoryÀÇ start address Memory Data Source Address ++ volatile unsigned int EFR; // 0x10 R/W 0x00000000 Erasure flag ÀÌ ÀúÀåµÇ¾îÀÖ´Â memoryÀÇ start address ++ volatile unsigned int MCR; // 0x14 R/W 0x00014000 MPE_FEC Control [25] ->Ç×»ó 0 À̾î¾ß ÇÔ [24] -> erasure_on(erasure»ç¿ë 1¡¯b1) [22:16] -> eras_thres(erasure°¡eras_thresº¸´Ù Å©¸é erasure ¸¦ »ç¿ëÇÏÁö¾ÊÀ½) [15:8] -> stuffing_len [6:0] -> puncturing_len ++ volatile unsigned int MSTR; // 0x18 R 0x00000000 MPE_FEC Status [1] -> mpe_done [0] -> mpe_over ++ volatile unsigned int MIER; // 0x1C R 0x00000000 MPE_FEC IRQ Enable [1] -> mpe_done IRQ Enable [0] -> mpe_over IRQ Enable ++ volatile unsigned int MICR; // 0x20 W 0x00000000 MPE_FEC IRQ_clear [1] -> mpe_done IRQ clear [0] -> mpe_over IRQ clear ++ volatile unsigned int MARR; // 0x24 R/W 0x03FF0000 MPE Frame Áß ¸î¹ø° row ºÎÅÍ MPEFEC ¸¦ ÇÒ °ÍÀÎÁö ¼³Á¤ÇÔ [9:0] start row number [25:16] end row number ++ volatile unsigned int ECNT; // 0x28 R/W 0x00000000 MPEFECs º¹±¸µÈ Error °³¼ö ++ volatile unsigned int NOTDEFINE0[3]; // 0x34-0x3C R/W Reserved ++}MPEFEC, *PMPEFEC; ++ ++ ++/******************************************************************************* ++* 29. IOBUS Configuration Register Define (Base Addr = 0xF05F5000) ++********************************************************************************/ ++//#define HwIOBUSCFG_BASE *(volatile unsigned long*)0xF05F5000 ++ ++typedef struct _IOBUSCFG{ ++ volatile unsigned int USBOTG; // 0x00 Refer to USB OTG Configuration Register (OTGCR) in 15.2 register Description for USB 2.0 OTG Controller USB OTG Configuration register (OTGCR)USB OTG Configuration Register (OTGCR)USB OTG Configuration register (OTGCR)USB OTG Configuration Register (OTGCR)USB OTG Configuration Register (OTGCR). ++ volatile unsigned int USB11H; // 0x04 Refer to USB 1.1 Host Configuration Register (USB11H) in 14.2 register Description for USB 1.1 Host Controller & Transceiver¡± ++ volatile unsigned int IOBAPB; // 0x08 IOBUS APB wait counter register ++ volatile unsigned int STORAGE; // 0x0C Storage Device Configuration Register ++ volatile unsigned int HCLKEN0; // 0x10 IOBUS AHB clock enable Register 0 ++ volatile unsigned int HCLKEN1; // 0x14 IOBUS AHB clock enable Register 1 ++ volatile unsigned int HCLKMEN; // 0x18 DMA AHB clock mask enable Register ++ volatile unsigned int NOTDEFINE0; // 0x1C Reserved ++ volatile unsigned int HRSTEN0; // 0x20 IOBUS AHB Hreset Control register 0 ++ volatile unsigned int HRSTEN1; // 0x24 IOBUS AHB Hreset Control register 1 ++ volatile unsigned int USBOTG0; // 0x28 Refer to USB PHY Configuration Register0 (UPCR0) in 15.2 register Description for USB 2.0 OTG Controller ++ volatile unsigned int USBOTG1; // 0x2C Refer to USB PHY Configuration Register1 (UPCR1) in 15.2 register Description for USB 2.0 OTG Controller ++ volatile unsigned int USBOTG2; // 0x30 Refer to USB PHY Configuration Register2 (UPCR2) in 15.2 register Description for USB 2.0 OTG Controller ++ volatile unsigned int USBOTG3; // 0x34 Refer to USB PHY Configuration Register3 (UPCR3) in 15.2 register Description for USB 2.0 OTG Controller ++ volatile unsigned int IO_A2X; // 0x38 IOBUS AHB2AXI Control Register ++}IOBUSCFG, *PIOBUSCFG; ++ ++ ++ ++/************************************************************************ ++* Channel 0 Memory Controller Register Define (Base Addr = 0xF1000000) ++************************************************************************/ ++//#define HwEMC_BASE *(volatile unsigned long *)0xF1000000 // External Memory Controller Base Register ++typedef struct _EMC{ ++ volatile unsigned int SDCFG; // 0x00 R/W 0x6A484C00 SDRAM Configuration Register ++ volatile unsigned int SDFSM; // 0x04 R 0x00000000 SDRAM FSM Status Register ++ volatile unsigned int MCFG; // 0x08 R/W 0x01000042 Miscellaneous Configuration Register ++ volatile unsigned int TST; // 0x0C W 0x00000000 Should not write to this ? it¡¯s for TEST ++ volatile unsigned int CSCFG0; // 0x10 R/W 0x468AC809 External Chip Select 0 Config. Register (CSN_CS0) ++ volatile unsigned int NOTDEFINE0[2]; // 0x14 R/W 0x508AD01A Reserved - 0x18 R/W 0x608AD03A Reserved ++ volatile unsigned int CSCFG3; // 0x1C R/W 0x728AD01A External Chip Select 3 Config. Register (CSN_NOR) ++ volatile unsigned int CLKCFG; // 0x20 R/W 0x00000A05 Memory Controller Version & Periodic Clock Enable Count Register ++ volatile unsigned int SDCMD; // 0x24 R/W - SDRAM Command Write Register ++ volatile unsigned int SDCFG1; // 0x28 R/W 0xFFFFFFFF Extra SDRAM Configuration Register ++}EMC, *PEMC; ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 6 DDI_BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/************************************************************************ ++* 4. LCD INTERFACE Register Define (Base Addr = 0xF0200000) ++************************************************************************/ ++//#define HwLCDC0_BASE *(volatile unsigned long *)0xF0200000 // LCDC0 Control Base Register ++//#define HwLCDC1_BASE *(volatile unsigned long *)0xF0204000 // LCDC1 Control Base Register ++ ++typedef struct _LCDC{ ++ volatile unsigned int LCTRL; // 0x00 R/W 0x00000000 LCD Control Register ++ volatile unsigned int LBC; // 0x04 R/W 0x00000000 LCD Background Color Register ++ volatile unsigned int LCLKDIV; // 0x08 R/W 0x00000000 LCD Clock Divider Register ++ volatile unsigned int LHTIME1; // 0x0C R/W 0x00000000 LCD Horizontal Timing Register 1 ++ volatile unsigned int LHTIME2; // 0x10 R/W 0x00000000 LCD Horizontal Timing Register 2 ++ volatile unsigned int LVTIME1; // 0x14 R/W 0x00000000 LCD Vertical Timing Register 1 ++ volatile unsigned int LVTIME2; // 0x18 R/W 0x00000000 LCD Vertical Timing Register 2 ++ volatile unsigned int LVTIME3; // 0x1C R/W 0x00000000 LCD Vertical Timing Register 3 ++ volatile unsigned int LVTIME4; // 0x20 R/W 0x00000000 LCD Vertical Timing Register 4 ++ volatile unsigned int LLUTR; // 0x24 R/W 0x00000000 LCD Lookup Register for Red ++ volatile unsigned int LLUTG; // 0x28 R/W 0x00000000 LCD Lookup Register for Green ++ volatile unsigned int LLUTB; // 0x2C R/W 0x00000000 LCD Lookup Register for Blue ++ volatile unsigned int LDP7L; // 0x30 R/W 0x4d2b3401 LCD Modulo 7 Dithering Pattern (low) ++ volatile unsigned int LDP7H; // 0x34 R/W 0x0000003f LCD Modulo 7 Dithering Pattern (high) ++ volatile unsigned int LDP5; // 0x38 R/W 0x1d0b0610 LCD Modulo 5 Dithering Pattern Register ++ volatile unsigned int LDP4; // 0x3C R/W 0x00000768 LCD Modulo 4 Dithering Pattern Register ++ volatile unsigned int LDP3; // 0x40 R/W 0x00000034 LCD 3-bit Dithering Pattern Register ++ volatile unsigned int LCP1; // 0x44 R/W 0x000000ff LCD Clipping Register1 ++ volatile unsigned int LCP2; // 0x48 R/W 0x000000ff LCD Clipping Register2 ++ volatile unsigned int LDS; // 0x4C R/W 0x00000000 LCD Display Size Register ++ volatile unsigned int LSTATUS; // 0x50 R/CLR 0x00000000 LCD Status Register ++ volatile unsigned int LIM; // 0x54 R/W 0x0000001f LCD Interrupt Register. ++ volatile unsigned int LGR0; // 0x58 R/W 0x00000000 LCD Gamma Correction Register 0 for Red Color ++ volatile unsigned int LGR1; // 0x5C R/W 0x00000000 LCD Gamma Correction Register 1 for Red Color ++ volatile unsigned int LGG0; // 0x60 R/W 0x00000000 LCD Gamma Correction Register 0 for Green Color ++ volatile unsigned int LGG1; // 0x64 R/W 0x00000000 LCD Gamma Correction Register 1 for Green Color ++ volatile unsigned int LGB0; // 0x68 R/W 0x00000000 LCD Gamma Correction Register 0 for Blue Color ++ volatile unsigned int LGB1; // 0x6C R/W 0x00000000 LCD Gamma Correction Register 1 for Blue Color ++ volatile unsigned int LENH; // 0x70 R/W 0x00000020 LCD Color Enhancement Register ++ volatile unsigned int NOTDEFINE0; // 0x74 ++ volatile unsigned int LI0C; // 0x78 R/W 0x00000000 LCD Image 0 Control Register ++ volatile unsigned int LI0P; // 0x7C R/W 0x00000000 LCD Image 0 Position Register ++ volatile unsigned int LI0S; // 0x80 R/W 0x00000000 LCD Image 0 Size Register ++ volatile unsigned int LI0BA0; // 0x84 R/W 0x00000000 LCD Image 0 Base Address 0 Register. ++ volatile unsigned int LI0CA; // 0x88 R/W 0x00000000 LCD Image 0 Current Address Register. ++ volatile unsigned int LI0BA1; // 0x8C R/W 0x00000000 LCD Image 0 Base Address 1 Register ++ volatile unsigned int LI0BA2; // 0x90 R/W 0x00000000 LCD Image 0 Base Address 2 Register ++ volatile unsigned int LI0O; // 0x94 R/W 0x00000000 LCD Image 0 Offset Register ++ volatile unsigned int LI0SR; // 0x98 R/W 0x00000000 LCD Image 0 Scale ratio ++ volatile unsigned int LI0A; // 0x9C R/W 0x00000000 LCD Image 0 Alpha Configuration Register ++ volatile unsigned int LI0KR; // 0xA0 R/W 0x00000000 LCD Image 0 Keying Register for RED or LUMA(Y) ++ volatile unsigned int LI0KG; // 0xA4 R/W 0x00000000 LCD Image 0 Keying Register for BLUE or CHROMA(Cb) ++ volatile unsigned int LI0KB; // 0xA8 R/W 0x00000000 LCD Image 0 Keying Register for GREEN or CHROMA(Cr) ++ volatile unsigned int LI0EN; // 0xAC R/W 0x00000000 LCD Image 0 Enhancement Register ++ volatile unsigned int LI1C; // 0xB0 R/W 0x00000000 LCD Image 1 Control Register ++ volatile unsigned int LI1P; // 0xB4 R/W 0x00000000 LCD Image 1 Position Register ++ volatile unsigned int LI1S; // 0xB8 R/W 0x00000000 LCD Image 1 Size Register ++ volatile unsigned int LI1BA0; // 0xBC R/W 0x00000000 LCD Image 1 Base Address 0 Register. ++ volatile unsigned int LI1CA; // 0xC0 R/W 0x00000000 LCD Image 1 Current Address Register. ++ volatile unsigned int LI1BA1; // 0xC4 R/W 0x00000000 Not Used ++ volatile unsigned int LI1BA2; // 0xC8 R/W 0x00000000 Not Used ++ volatile unsigned int LI1O; // 0xCC R/W 0x00000000 LCD Image 1 Offset Register ++ volatile unsigned int LI1SR; // 0xD0 R/W 0x00000000 LCD Image 1 Scale ratio- ++ volatile unsigned int LI1A; // 0xD4 R/W 0x00000000 LCD Image 1 Alpha Configuration Register ++ volatile unsigned int LI1KR; // 0xD8 R/W 0x00000000 LCD Image 1 Keying Register for RED or LUMA(Y) ++ volatile unsigned int LI1KG; // 0xDC R/W 0x00000000 LCD Image 1 Keying Register for BLUE or CHROMA(Cb) ++ volatile unsigned int LI1KB; // 0xE0 R/W 0x00000000 LCD Image 1 Keying Register for GREEN or CHROMA(Cr) ++ volatile unsigned int LI1EN; // 0xE4 R/W 0x00000000 LCD Image 1 Enhancement Register ++ volatile unsigned int LI2C; // 0xE8 R/W 0x00000000 LCD Image 2 Control Register ++ volatile unsigned int LI2P; // 0xEC R/W 0x00000000 LCD Image 2 Position Register ++ volatile unsigned int LI2S; // 0xF0 R/W 0x00000000 LCD Image 2 Size Register ++ volatile unsigned int LI2BA0; // 0xF4 R/W 0x00000000 LCD Image 2 Base Address 0 Register. ++ volatile unsigned int LI2CA; // 0xF8 R/W 0x00000000 LCD Image 2 Current Address Register. ++ volatile unsigned int LI2BA1; // 0xFC R/W 0x00000000 Not Used ++ volatile unsigned int LI2BA2; // 0x100 R/W 0x00000000 Not Used ++ volatile unsigned int LI2O; // 0x104 R/W 0x00000000 LCD Image 2 Offset Register ++ volatile unsigned int LI2SR; // 0x108 R/W 0x00000000 LCD Image 2 Scale ratio ++ volatile unsigned int LI2A; // 0x10C R/W 0x00000000 LCD Image 2 Alpha Register ++ volatile unsigned int LI2KR; // 0x110 R/W 0x00000000 LCD Image 2 Keying Register for RED or LUMA(Y) ++ volatile unsigned int LI2KG; // 0x114 R/W 0x00000000 LCD Image 2 Keying Register for BLUE or CHROMA(Cb) ++ volatile unsigned int LI2KB; // 0x118 R/W 0x00000000 LCD Image 2 Keying Register for GREEN or CHROMA(Cr) ++ volatile unsigned int LI2EN; // 0x11C R/W 0x00000000 LCD Image 2 Enhancement Register ++ volatile unsigned int LUTIDX; // 0x120 Lookup Table index Register ++ ++}LCDC, *PLCDC; ++ ++ ++//#define HwLCDLUT0_BASE *(volatile unsigned long *)0xF0200400 // LCD LUT 0 Base Register ++//#define HwLCDLUT1_BASE *(volatile unsigned long *)0xF0204400 // LCD LUT 1 Base Register ++ ++typedef struct _LUT_TYPE{ ++ volatile unsigned char BCr; // [7:0] ++ volatile unsigned char GCb; // [15:8] ++ volatile unsigned char RY; // [23:16] ++ volatile unsigned char dummy; // [31:24]] ++}LUT_TYPE, *PLUT_TYPE; ++ ++typedef struct _LCDLUT{ ++ volatile LUT_TYPE LUTDAT[256]; // 0x400 ~ 0x7FF ++}LCDLUT, *PLCDLUT; ++ ++ ++/************************************************************************ ++* 5. LCD System Interface Register Define (Base Addr = 0xF020C400) ++************************************************************************/ ++//#define HwLCDSI_BASE *(volatile unsigned long *)0xF020C400 // LCDSI Base Register ++ ++typedef struct _LCDSI0{ ++ volatile unsigned int CTRL0; // 0x400 R/W 0x00000000 Control register for LCDSI ++}LCDSI0, *PLCDSI0; ++ ++typedef struct _LCDSI1{ ++ volatile unsigned int CTRL1; // 0x800 R/W 0xA0229011 Control register for nCS0 when RS=0(for core access) ++ volatile unsigned int CTRL2; // 0x804 R/W 0xA0429021 Control register for nCS0 when RS=1(for core access) ++ volatile unsigned int CTRL3; // 0x808 R/W 0xA0129009 Control register for nCS1 when RS=0(for core access) ++ volatile unsigned int CTRL4; // 0x80C R/W 0xA0229011 Control register for nCS1 when RS=1(for core access) ++ volatile unsigned int CS0RS0; // 0x810 R/W -if this register is read or written, reading or writing operations are generated on nCS0 while RS = 0. ++ volatile unsigned int NOTDEFINE0; // 0x814 ++ volatile unsigned int CS0RS1; // 0x818 R/W -if this register is read or written, reading or writing operations are generated on nCS0 while RS = 1. ++ volatile unsigned int NOTDEFINE1; // 0x81C ++ volatile unsigned int CS1RS0; // 0x820 R/W -if this register is read or written, reading or writing operations are generated on nCS1 while RS = 0. ++ volatile unsigned int NOTDEFINE2; // 0x824 ++ volatile unsigned int CS1RS1; // 0x828 R/W -if this register is read or written, reading or writing operations are generated on nCS1 while RS = 1. ++ volatile unsigned int NOTDEFINE3; // 0x82C ++ volatile unsigned int CTRL5; // 0x830 R/W 0xA0229011 Control register for nCS0 when RS=0(for lcd access) ++ volatile unsigned int CTRL6; // 0x834 R/W 0xA0429021 Control register for nCS0 when RS=1(for lcd access) ++ volatile unsigned int CTRL7; // 0x838 R/W 0xA0129009 Control register for nCS1 when RS=0(for lcd access) ++ volatile unsigned int CTRL8; // 0x83C R/W 0xA0229011 Control register for nCS1 when RS=1(for lcd access) ++}LCDSI1, *PLCDSI1; ++ ++ ++/*********************************************************************** ++* 6. Memory to Memory Scaler Register Define (Base Addr = 0xF0210000/0xF0220000) ++************************************************************************/ ++//#define HwM2MSCALER1_BASE *(volatile unsigned long *)0xF0251000 ++//#define HwM2MSCALER1_BASE *(volatile unsigned long *)0xF0252000 ++typedef struct _M2MSCALER{ ++ volatile unsigned int SRCBASEY; // 0x000 R/W 0x00000000 Scaler source base address for Y ++ volatile unsigned int SRCBASEU; // 0x004 R/W 0x00000000 Scaler source base address for U (Cb) ++ volatile unsigned int SRCBASEV; // 0x008 R/W 0x00000000 Scaler source base address for V (Cr) ++ volatile unsigned int SRCSIZE; // 0x00c R/W 0x00000000 Source image size register ++ volatile unsigned int SRCOFF; // 0x010 R/W 0x00000000 Source image line offset register ++ volatile unsigned int SRCCFG; // 0x014 R/W 0x00000000 Source image configuration register ++ volatile unsigned int NOTDEFINE0[2]; ++ volatile unsigned int DSTBASEY; // 0x020 R/W 0x00000000 Scaler destination base address for Y ++ volatile unsigned int DSTBASEU; // 0x024 R/W 0x00000000 Scaler destination base address for U (Cb) ++ volatile unsigned int DSTBASEV; // 0x028 R/W 0x00000000 Scaler destination base address for V (Cr) ++ volatile unsigned int DSTSIZE; // 0x02c R/W 0x00000000 Destination image size register ++ volatile unsigned int DSTOFF; // 0x030 R/W 0x00000000 Destination image line offset register ++ volatile unsigned int DSTCFG; // 0x034 R/W 0x00000000 Destination image configuration register ++ volatile unsigned int NOTDEFINE1[2]; ++ volatile unsigned int MSCINF; // 0x040 R/W 0x00000000 Scaling information register ++ volatile unsigned int MSCCTR; // 0x044 R/W 0x00000000 Scaler control register ++ volatile unsigned int MSCSTR; // 0x048 R/W 0x00000000 Scaler status register ++ volatile unsigned int HSTROBE; // 0x04C R/W 0x000A0002 Horizontal Strobe Timing Control Register ++ volatile unsigned int DSTRMCNT; // 0x050 R/W 0x00000000 Destination Rolling Status Register ++ volatile unsigned int CRCNT; // 0x054 R 0x00000000 Destination Rolling Status Register ++ volatile unsigned int CLIP0; // 0x058 R/W 0x00000000 RGB-to-YCbCr Clipping Configuration Register 0 ++ volatile unsigned int CLIP1; // 0x05C R/W 0x000000FF RGB-to-YCbCr Clipping Configuration Register 1 ++ volatile unsigned int VSTROBE; // 0x060 R/W 0x0000000A Vertical Strobe Timing Control Register ++}M2MSCALER, *PM2MSCALER; ++ ++ ++/************************************************************************ ++* 7. NTSC/PAL ENCODER Composite Output Register Define (Base Addr = 0xF9000000) ++************************************************************************/ ++//#define HwTVE_BASE *(volatile unsigned long *)0xF9000000 // TV Encoder Base Register ++typedef struct _NTSCPAL{ ++ volatile unsigned int STATA; //0x00 ++ volatile unsigned int ECMDA; //0x04 ++ volatile unsigned int ECMDB; //0x08 ++ volatile unsigned int GLK; //0x0C ++ volatile unsigned int SCH; //0x10 ++ volatile unsigned int HUE; //0x14 ++ volatile unsigned int SAT; //0x18 ++ volatile unsigned int CONT; //0x1C ++ volatile unsigned int BRIGHT; //0x20 ++ volatile unsigned int FSC_ADJM; //0x24 ++ volatile unsigned int FSC_ADJL; //0x28 ++ volatile unsigned int ECMDC; //0x2C ++ volatile unsigned int NOTDEFINE0[4]; //0x30, 34, 38, 3C ++ volatile unsigned int DACSEL; //0x40 ++ volatile unsigned int NOTDEFINE1[3]; //0x44, 48, 4C ++ volatile unsigned int DACPD; //0x50 ++ volatile unsigned int NOTDEFINE2[11]; //0x54, 58, 5C, 60, 64, 68, 6C, 70, 74, 78, 7C ++ volatile unsigned int ICNTL; //0x80 ++ volatile unsigned int HVOFFST; //0x84 ++ volatile unsigned int HOFFST; //0x88 ++ volatile unsigned int VOFFST; //0x8C ++ volatile unsigned int HSVSO; //0x90 ++ volatile unsigned int HSOE; //0x94 ++ volatile unsigned int HSOB; //0x98 ++ volatile unsigned int VSOB; //0x9C ++ volatile unsigned int VSOE; //0xA0 ++}NTSCPAL, *PNTSCPAL; ++ ++typedef struct _NTSCPALOP{ ++ volatile unsigned int VENCON; //0xF9080000 ++ volatile unsigned int VENCIF; //0xF9080004 ++}NTSCPALOP, *PNTSCPALOP; ++ ++/************************************************************************ ++* 8. HDMI Register Define (Base Addr = 0xF0254000) ++************************************************************************/ ++//#define HwHDMICTRL_BASE *(volatile unsigned long *)0xF0254000 //Controller register base address ++typedef struct _HDMICTRL{ ++ volatile unsigned int INTC_CON; // 0x0000 R/W Interrupt Control Register 0x00 ++ volatile unsigned int INTC_FLAG; // 0x0004 R/W Interrupt Flag Register 0x00 ++ volatile unsigned int AESKEY_VALID; // 0x0008 R aeskey_valid Register 0x00 ++ volatile unsigned int HPD; // 0x000C R HPD signal 0x00 ++}HDMICTRL, *PHDMICTRL; ++ ++//#define HwHDMICORE_BASE *(volatile unsigned long *)0xF0255000 ++typedef struct _HDMICORE{ ++ volatile unsigned int HDMI_CON_0; // 0x0000 R/W HDMI system control register 0 0x00 ++ volatile unsigned int HDMI_CON_1; // 0x0004 R/W HDMI system control register 1 0x00 ++ volatile unsigned int HDMI_CON_2; // 0x0008 R/W HDMI system control register 2 0x00 ++ volatile unsigned int NOTDEFINE_; // 0x000C ++ volatile unsigned int STATUS; // 0x0010 R/W HDMI system status register 0x00 ++ volatile unsigned int PHY_STATUS; // 0x0014 R PHY status register 0x00 ++ volatile unsigned int NOTDEFINE0[2]; // 0x18, 0x1C ++ volatile unsigned int STATUS_EN; // 0x0020 R/W HDMI system status enable register 0x00 ++ volatile unsigned int NOTDEFINE1[3]; // 0x24, 0x28, 0x2C ++ volatile unsigned int HPD; // 0x0030 R/W HPD control register 0x00 ++ volatile unsigned int NOTDEFINE2[3]; // 0x34, 0x38, 0x3C ++ volatile unsigned int MODE_SEL; // 0x0040 R/W HDMI/DVI mode selection 0x00 ++ volatile unsigned int ENC_EN; // 0x0044 R/W HDCP encryption enable register 0x00 ++ volatile unsigned int NOTDEFINE3[2]; // 0x48, 0x4C ++//Video Related Registers ++ volatile unsigned int BLUE_SCREEN_0; // 0x0050 R/W Pixel values for blue screen 0x00 ++ volatile unsigned int BLUE_SCREEN_1; // 0x0054 R/W Pixel values for blue screen 0x00 ++ volatile unsigned int BLUE_SCREEN_2; // 0x0058 R/W Pixel values for blue screen 0x00 ++ volatile unsigned int NOTDEFINE4; // 0x5C ++ volatile unsigned int HDMI_YMAX; // 0x0060 R/W Maximum Y (or "R,G,B)" pixel value 0x00 ++ volatile unsigned int HDMI_YMIN; // 0x0064 R/W Minimum Y (or "R,G,B)" pixel value 0x00 ++ volatile unsigned int HDMI_CMAX; // 0x0068 R/W Maximum Cb/Cr pixel value 0x00 ++ volatile unsigned int HDMI_CMIN; // 0x006C R/W Minimum Cb/Cr pixel value 0x00 ++ volatile unsigned int NOTDEFINE5[12]; // 0x70~0x9C ++ volatile unsigned int H_BLANK[2]; // 0x00A0 ,0x00A4 R/W Horizontal blanking setting 0x00 ++ volatile unsigned int NOTDEFINE6[2]; // 0xA8 0xAC ++ volatile unsigned int V_BLANK[3]; // 0x00B0,0x00B4, 0x00B8 R/W Vertical blanking setting 0x00 ++ volatile unsigned int NOTDEFINE7[2]; // 0xB8 0xBC ++ volatile unsigned int H_V_LINE[3]; // 0x00C0,0x00C4, 0x00C8 R/W Horizontal line & vertical line setting 0x00 ++ volatile unsigned int NOTDEFINE8[6]; // 0xCC, 0xD0, 0xD4, 0xD8, 0xDC, 0xE0 ++ volatile unsigned int VSYNC_POL; // 0x00E4 R/W Vertical sync polarity control register 0x00 ++ volatile unsigned int INT_PRO_MODE ; // 0x00E8 R/W Interlace/Progressive control register 0x00 ++ volatile unsigned int NOTDEFINE9[9]; // 0xEC, 0xF0, 0xF4, 0xF8, 0xFC, 0x100, 0x104, 0x108, 0x10C ++ volatile unsigned int V_BLANK_F[3]; // 0x0110,0x0114, 0x0118 R/W Vertical blanking setting for bottom field 0x00 ++ volatile unsigned int NOTDEFINE10; // 0x011C ++ volatile unsigned int H_SYNC_GEN[3] ; // 0x0120,0x0124 ,0x0128 R/W Horizontal sync generation setting 0x00 ++ volatile unsigned int NOTDEFINE11; // 0x012C ++ volatile unsigned int V_SYNC_GEN1[3]; // 0x0130,0x0134,0x0138 R/W Vertical sync generation for top field or frame 0x01 ++ volatile unsigned int NOTDEFINE12; // 0x013C ++ volatile unsigned int V_SYNC_GEN2[3]; // 0x0140,0x0144,0x0148 R/W Vertical sync generation for bottom field - vertical position 0x01 ++ volatile unsigned int NOTDEFINE13; // 0x014C ++ volatile unsigned int V_SYNC_GEN3[3]; // 0x0150,0x0154,0x0158 R/W Vertical sync generation for bottom field - horizontal position 0x01 ++ volatile unsigned int NOTDEFINE14; // 0x015C ++//Audio Related Registers ++ volatile unsigned int ASP_CON; // 0x0160 R/W ASP packet control register 0x00 ++ volatile unsigned int ASP_SP_FLAT; // 0x0164 R/W ASP packet sp_flat bit control 0x00 ++ volatile unsigned int NOTDEFINE15[2]; // 0x0168,0x016C ++ volatile unsigned int ASP_CHCFG[4]; // 0x0170,0x0174,0x0178,0x017C R/W ASP audio channel configuration 0x04 ++ volatile unsigned int ACR_CON; // 0x0180 R/W ACR packet control register 0x00 ++ volatile unsigned int ACR_MCTS[3]; // 0x0184,0x0188,0x018C R/W Measured CTS value 0x01 ++ volatile unsigned int ACR_CTS[3]; // 0x0190,0x0194,0x0198 R/W CTS value for fixed CTS transmission mode. 0xe8 ++ volatile unsigned int NOTDEFINE16; // 0x019C ++ volatile unsigned int ACR_N[3]; // 0x01A0,0x01A4,0x01A8 R/W N value for ACR packet 0xe8 ++ volatile unsigned int NOTDEFINE17; // 0x01AC ++ volatile unsigned int ACR_LSB2; // 0x01B0 R/W Alternate LSB for fixed CTS transmission mode 0x00 ++ volatile unsigned int ACR_TXCNT; // 0x01B4 R/W Number of ACR packet transmission per frame 0x1f ++ volatile unsigned int ACR_TXINTERVAL; // 0x01B8 R/W Interval for ACR packet transmission 0x63 ++ volatile unsigned int ACR_CTS_OFFSET; // 0x01BC R/W CTS offset for measured CTS mode 0x00 ++//Packet Related Registers ++ volatile unsigned int GCP_CON ; // 0x01C0 R/W ACR packet control register 0x00 ++ volatile unsigned int NOTDEFINE18[3]; // 0x01C4,0x01C8,0x01CC, ++ volatile unsigned int GCP_BYTE[3]; // 0x01D0,0x01D4,0x01D8 R/W GCP packet body 0x00 ++ volatile unsigned int NOTDEFINE19; // 0x01DC, ++ volatile unsigned int ACP_CON; // 0x01E0 R/W ACP packet control register 0x00 ++ volatile unsigned int NOTDEFINE20[3]; // 0x01E4,0x01E8,0x01EC, ++ volatile unsigned int ACP_TYPE; // 0x01F0 R/W ACP packet header 0x00 ++ volatile unsigned int NOTDEFINE21[3]; // 0x01F4,0x01F8,0x01FC, ++ volatile unsigned int ACP_DATA[17]; // 0x0200~0x0240 R/W ACP packet body 0x00 ++ volatile unsigned int NOTDEFINE22[3]; // 0x0244,0x0248,0x024C, ++ volatile unsigned int ISRC_CON; // 0x0250 R/W ACR packet control register 0x00 ++ volatile unsigned int NOTDEFINE23[4]; // 0x0254,0x0258,0x025C,0x0260 ++ volatile unsigned int ISRC1_HEADER1; // 0x0264 R/W ISCR1 packet header 0x00 ++ volatile unsigned int NOTDEFINE24[2]; // 0x0268,0x026C, ++ volatile unsigned int ISRC1_DATA[16]; // 0x0270~0x02AC R/W ISRC1 packet body 0x00 ++ volatile unsigned int ISRC2_DATA[16]; // 0x02B0~0x02EC R/W ISRC2 packet body 0x00 ++ volatile unsigned int NOTDEFINE25[4]; // 0x02F0,0x02F4,0x02F8,0x2FC ++ ++ volatile unsigned int AVI_CON; // 0x0300 R/W AVI packet control register 0x00 ++ volatile unsigned int NOTDEFINE26[3]; // 0x0304,0x0308,0x030c ++ volatile unsigned int AVI_CHECK_SUM; // 0x0310 R/W AVI packet checksum 0x00 ++ volatile unsigned int NOTDEFINE27[3]; // 0x0314,0x0318,0x031c ++ volatile unsigned int AVI_BYTE[13]; // 0x0320~0x0350 R/W AVI packet body 0x00 ++ volatile unsigned int NOTDEFINE28[3]; // 0x0354,0x0358,0x035c ++ volatile unsigned int AUI_CON; // 0x0360 R/W AUI packet control register 0x00 ++ volatile unsigned int NOTDEFINE29[3]; // 0x0364,0x0368,0x036c ++ volatile unsigned int AUI_CHECK_SUM; // 0x0370 R/W AUI packet checksum 0x00 ++ volatile unsigned int NOTDEFINE30[3]; // 0x0374,0x0378,0x037c ++ volatile unsigned int AUI_BYTE[5]; // 0x0380~0x0390 R/W AUI packet body 0x00 ++ volatile unsigned int NOTDEFINE31[3]; // 0x0394,0x0398,0x039c ++ ++ volatile unsigned int MPG_CON; // 0x03A0 R/W ACR packet control register 0x00 ++ volatile unsigned int NOTDEFINE32[3]; // 0x03A4,0x03A8,0x03Ac ++ volatile unsigned int MPG_CHECK_SUM; // 0x03B0 R/W MPG packet checksum 0x00 ++ volatile unsigned int NOTDEFINE33[3]; // 0x03B4,0x03B8,0x03Bc ++ ++ volatile unsigned int MPG_BYTE[5]; // 0x03C0~0x03D0 R/W MPG packet body 0x00 ++ volatile unsigned int NOTDEFINE34[11]; // 0x03D4,0x03D8,0x03Dc ++ // 0x03E0, ++ // 0x03F ++ volatile unsigned int SPD_CON; // 0x0400 R/W SPD packet control register 0x00 ++ volatile unsigned int NOTDEFINE35[3]; // 0x0344,0x0348,0x034c ++ volatile unsigned int SPD_HEADER0; // 0x0410~ R/W SPD packet header 0x00 ++ volatile unsigned int SPD_HEADER1; // 0x0414 R/W SPD packet header 0x00 ++ volatile unsigned int SPD_HEADER2; // 0x0418 R/W SPD packet header 0x00 ++ volatile unsigned int NOTDEFINE36; // 0x041C ++ volatile unsigned int SPD_DATA[28]; // 0x0420~0x048C R/W SPD packet body 0x00 ++ ++//HDCP Related Registes ++ volatile unsigned int GAMUT_CON; // 0x0500 R/W GAMUT packet control register 0x00 ++ volatile unsigned int GAMUT_HEADER0; // 0x0504 R/W GAMUT packet header 0x00 ++ volatile unsigned int GAMUT_HEADER1; // 0x0508 R/W GAMUT packet header 0x00 ++ volatile unsigned int GAMUT_HEADER2; // 0x050C R/W GAMUT packet header 0x00 ++ volatile unsigned int GAMUT_DATA[28]; // 0x0510~0x057C R/W GAMUT packet body 0x00 ++ volatile unsigned int NOTDEFINE37[16]; // 0x0580~ ++ // 0x0590,~ ++ // 0x05A0~ ++ // 0x05B0~ ++ volatile unsigned int DC_CONTROL; // 0x05C0 R/W Deep Color Control Register 0x00 ++ volatile unsigned int VIDEO_PATTERN_GEN; // 0x05C4 R/W Video Pattern Generation Register 0x00 ++ volatile unsigned int HPD_GEN ; // 0x05C8 R/W HPD Duration value register 0x01 ++ volatile unsigned int NOTDEFINE38[113]; // 0x05CC ++ // 0x05D0, ++ // 0x05E0 ++ // 0x05F0 ++ ++ volatile unsigned int HDCP_SHA1[20]; // 0x0600~0x064C R/W SHA-1 value from repeater 0x00 ++ volatile unsigned int HDCP_KSV_LIST[5]; // 0x0650~0x0660 R/W KSV list from repeater 0x00 ++ ++ volatile unsigned int HDCP_KSV_LIST_CON; // 0x0664 R/W KSV list control 0x00 ++ volatile unsigned int NOTDEFINE39[2]; // 0x0668,0x066C ++ volatile unsigned int HDCP_SHA_RESULT; // 0x0670 R/W SHA-1 checking result register 0x00 ++ volatile unsigned int NOTDEFINE40[3]; // 0x0674,0x0678,0x067c ++ volatile unsigned int HDCP_CTRL1; // 0x0680 R/W HDCP control register1 0x00 ++ volatile unsigned int HDCP_CTRL2; // 0x0684 R/W HDCP control register2 0x00 ++ volatile unsigned int NOTDEFINE41[2]; // 0x0688,0x068c ++ volatile unsigned int HDCP_CHECK_RESULT; // 0x0690 R/W Ri and Pj value checking result 0x00 ++ volatile unsigned int NOTDEFINE42[3]; // 0x0394,0x0398,0x039c ++ volatile unsigned int HDCP_BKSV[5]; // 0x06A0~0x06B0 R/W KSV of Rx 0x00 ++ volatile unsigned int NOTDEFINE43[3]; // 0x06B4,0x06B8,0x06Bc ++ ++ volatile unsigned int HDCP_AKSV[5]; //0x06C0~ 0x06D0 R/W KSV of Tx 0x00 ++ volatile unsigned int NOTDEFINE44[3]; // 0x06D4,0x06D8,0x06Dc ++ volatile unsigned int HDCP_An[8]; // 0x06E0~ 0x06FC R/W An value 0x00 ++ volatile unsigned int HDCP_BCAPS; // 0x0700 R/W BCAPS from Rx 0x00 ++ volatile unsigned int NOTDEFINE45[3]; // 0x0704,0x0708,0x070c ++ volatile unsigned int HDCP_BSTATUS_0; // 0x0710 R/W BSTATUS from Rx 0x00 ++ volatile unsigned int HDCP_BSTATUS_1; // 0x0714 R/W BSTATUS from Rx 0x00 ++ volatile unsigned int NOTDEFINE46[10]; // 0x0718,0x071c ++ // 0x0720, ++ // 0x0730 ++ volatile unsigned int HDCP_Ri_0; // 0x0740 R/W Ri value of Tx 0x00 ++ volatile unsigned int HDCP_Ri_1; // 0x0744 R/W Ri value of Tx 0x00 ++ volatile unsigned int NOTDEFINE47[13]; // 0x0748 ++ // 0x0750, ++ // 0x0760, ++ // 0x0770 ++ volatile unsigned int HDCP_I2C_INT; // 0x0780 R/W I2C interrupt flag 0x00 ++ volatile unsigned int NOTDEFINE48[3]; // 0x0784,0x0788,0x078c ++ ++ volatile unsigned int HDCP_AN_INT; // 0x0790 R/W An value ready interrupt flag 0x00 ++ volatile unsigned int NOTDEFINE49[3]; // 0x0794,0x0798,0x079c ++ ++ volatile unsigned int HDCP_WATCGDOG_INT; // 0x07A0 R/W Wachdog interrupt flag 0x00 ++ volatile unsigned int NOTDEFINE50[3]; // 0x07A4,0x07A8,0x07Ac ++ ++ volatile unsigned int HDCP_Ri_INT; // 0x07B0 R/W Ri value update interrupt flag 0x00 ++ volatile unsigned int NOTDEFINE51[7]; // 0x07B4,0x07B8,0x07Bc ++ // 0x07C0, ++ volatile unsigned int HDCP_Ri_Compare_0; // 0x07D0 R/W HDCP Ri Interrupt Frame number index register 0 0x80 ++ volatile unsigned int HDCP_Ri_Compare_1; // 0x07D4 R/W HDCP Ri Interrupt Frame number index register 1 0x7f ++ volatile unsigned int NOTDEFINE52[2]; // 0x07D8,0x07Dc ++ ++ volatile unsigned int HDCP_Frame_Count; // 0x07E0 R Current value of the frame count index in the hardware 0x00 ++}HDMICORE, *PHDMICORE; ++ ++//AES register base address ++//fHDMIAES_BASE *(volatile unsigned long *)0xF0256000 //AES register base address ++typedef struct _HDMIAES{ ++ volatile unsigned int AES_START; // 0x0000 R/W AES_START 0x00 ++ volatile unsigned int NOTDEFINE0[7]; // 0x0004,0x0008,0x000c ++ // 0x0010, ++ volatile unsigned int AES_DATA_SIZE_L; // 0x0020 R/W AES_DATA_SIZE_L 0x20 ++ volatile unsigned int AES_DATA_SIZE_H; // 0x0024 R/W AES_DATA_SIZE_H 0x01 ++ volatile unsigned int NOTDEFINE1[6]; // 0x0028,0x002c ++ // 0x0030 ++ volatile unsigned int AES_DATA; // 0x0040 W AES_DATA - ++}HDMIAES, *PHDMIAES; ++ ++//SPDIF Receiver register base address ++//#define HwHDMISPDIF_BASE *(volatile unsigned long *)0xF0257000 ++typedef struct _HDMISPDIF{ ++ volatile unsigned int SPDIFIN_CLK_CTRL; // 0x0000 R/W SPDIFIN Clock Control Register 0x02 ++ volatile unsigned int SPDIFIN_OP_CTRL; // 0x0004 R/W SPDIFIN Operation Control Register 1 0x00 ++ volatile unsigned int SPDIFIN_IRQ_MASK; // 0x0008 R/W SPDIFIN Interrupt Request Mask Register 0x00 ++ volatile unsigned int SPDIFIN_IRQ_STATUS; // 0x000C R/W SPDIFIN Interrupt Request Status Register 0x00 ++ volatile unsigned int SPDIFIN_CONFIG_1; // 0x0010 R/W SPDIFIN Configuration Register 1 0x02 ++ volatile unsigned int SPDIFIN_CONFIG_2; // 0x0014 R/W SPDIFIN Configuration Register 2 0x00 ++ volatile unsigned int NOTDEFINE0[2]; // 0x0018 0x001C - Reserved - ++ volatile unsigned int SPDIFIN_USER_VALUE_1; // 0x0020 R SPDIFIN User Value Register 1 0x00 ++ volatile unsigned int SPDIFIN_USER_VALUE_2; // 0x0024 R SPDIFIN User Value Register 2 0x00 ++ volatile unsigned int SPDIFIN_USER_VALUE_3; // 0x0028 R SPDIFIN User Value Register 3 0x00 ++ volatile unsigned int SPDIFIN_USER_VALUE_4; // 0x002C R SPDIFIN User Value Register 4 0x00 ++ volatile unsigned int SPDIFIN_CH_STATUS_0_1; // 0x0030 R SPDIFIN Channel Status Register 0-1 0x00 ++ volatile unsigned int SPDIFIN_CH_STATUS_0_2; // 0x0034 R SPDIFIN Channel Status Register 0-2 0x00 ++ volatile unsigned int SPDIFIN_CH_STATUS_0_3; // 0x0038 R SPDIFIN Channel Status Register 0-3 0x00 ++ volatile unsigned int SPDIFIN_CH_STATUS_0_4; // 0x003C R SPDIFIN Channel Status Register 0-4 0x00 ++ volatile unsigned int SPDIFIN_CH_STATUS_1; // 0x0040 R SPDIFIN Channel Status Register 1 0x00 ++ volatile unsigned int NOTDEFINE1; // 0x0044 - Reserved - ++ volatile unsigned int SPDIFIN_FRAME_PERIOD_1; // 0x0048 R SPDIFIN Frame Period Register 1 0x00 ++ volatile unsigned int SPDIFIN_FRAME_PERIOD_2; // 0x004C R SPDIFIN Frame Period Register 2 0x00 ++ volatile unsigned int SPDIFIN_Pc_INFO_1; // 0x0050 R SPDIFIN Pc Info Register 1 0x00 ++ volatile unsigned int SPDIFIN_Pc_INFO_2; // 0x0054 R SPDIFIN Pc Info Register 2 0x00 ++ volatile unsigned int SPDIFIN_Pd_INFO_1; // 0x0058 R SPDIFIN Pd Info Register 1 0x00 ++ volatile unsigned int SPDIFIN_Pd_INFO_2; // 0x005C R SPDIFIN Pd Info Register 2 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_0_1; // 0x0060 R SPDIFIN Data Buffer Register 0_1 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_0_2; // 0x0064 R SPDIFIN Data Buffer Register 0_2 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_0_3; // 0x0068 R SPDIFIN Data Buffer Register 0_3 0x00 ++ volatile unsigned int SPDIFIN_USER_BUF_0; // 0x006C R SPDIFIN User Buffer Register 0 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_1_1; // 0x0070 R SPDIFIN Data Buffer Register 1_1 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_1_2; // 0x0074 R SPDIFIN Data Buffer Register 1_2 0x00 ++ volatile unsigned int SPDIFIN_DATA_BUF_1_3; // 0x0078 R SPDIFIN Data Buffer Register 1_3 0x00 ++ volatile unsigned int SPDIFIN_USER_BUF_1; // 0x007C R SPDIFIN User Buffer Register 1 0x00 ++}HDMISPDIF, *PHDMISPDIF; ++ ++//I2S Receiver register base address ++//#define HwHDMII2S_BASE *(volatile unsigned long *)0xF0258000 ++typedef struct _HDMII2S{ ++ volatile unsigned int I2S_CLK_CON; // 0x0000 R/W I2S Clock Enable Register 0x00 ++ volatile unsigned int I2S_CON_1; // 0x0004 R/W I2S Control Register 1 0x00 ++ volatile unsigned int I2S_CON_2; // 0x0008 R/W I2S Control Register 2 0x00 ++ volatile unsigned int I2S_PIN_SEL_0; // 0x000C R/W I2S Input Pin Selection Register 0 0x77 ++ volatile unsigned int I2S_PIN_SEL_1; // 0x0010 R/W I2S Input Pin Selection Register 1 0x77 ++ volatile unsigned int I2S_PIN_SEL_2; // 0x0014 R/W I2S Input Pin Selection Register 2 0x77 ++ volatile unsigned int I2S_PIN_SEL_3; // 0x0018 R/W I2S Input Pin Selection Register 3 0x07 ++ volatile unsigned int I2S_DSD_CON; // 0x001C R/W I2S DSD Control Register 0x02 ++ volatile unsigned int I2S_MUX_CON; // 0x0020 R/W I2S In/Mux Control Register 0x60 ++ volatile unsigned int I2S_CH_ST_CON; // 0x0024 R/W I2S Channel Status Control Register 0x00 ++ volatile unsigned int I2S_CH_ST_0; // 0x0028 R/W I2S Channel Status Block 0 0x00 ++ volatile unsigned int I2S_CH_ST_1; // 0x002C R/W I2S Channel Status Block 1 0x00 ++ volatile unsigned int I2S_CH_ST_2; // 0x0030 R/W I2S Channel Status Block 2 0x00 ++ volatile unsigned int I2S_CH_ST_3; // 0x0034 R/W I2S Channel Status Block 3 0x00 ++ volatile unsigned int I2S_CH_ST_4; // 0x0038 R/W I2S Channel Status Block 4 0x00 ++ volatile unsigned int I2S_CH_ST_SH_0; // 0x003C R I2S Channel Status Block Shadow Register 0 0x00 ++ volatile unsigned int I2S_CH_ST_SH_1; // 0x0040 R I2S Channel Status Block Shadow Register 1 0x00 ++ volatile unsigned int I2S_CH_ST_SH_2; // 0x0044 R I2S Channel Status Block Shadow Register 2 0x00 ++ volatile unsigned int I2S_CH_ST_SH_3; // 0x0048 R I2S Channel Status Block Shadow Register 3 0x00 ++ volatile unsigned int I2S_CH_ST_SH_4; // 0x004C R I2S Channel Status Block Shadow Register 4 0x00 ++ volatile unsigned int I2S_VD_DATA; // 0x0050 R/W I2S Audio Sample Validity Register 0x00 ++ volatile unsigned int I2S_MUX_CH; // 0x0054 R/W I2S Channel Enable Register 0x03 ++ volatile unsigned int I2S_MUX_CUV; // 0x0058 R/W I2S CUV Enable Register 0x03 ++ volatile unsigned int I2S_IRQ_MASK; // 0x005C R/W I2S Interrupt Request Mask Register 0x03 ++ volatile unsigned int I2S_IRQ_STATUS; // 0x0060 R/W I2S Interrupt Request Status Register 0x00 ++ volatile unsigned int I2S_CH0_L_0; // 0x0064 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_L_1; // 0x0068 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_L_2; // 0x006C R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_L_3; // 0x0070 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_R_0; // 0x0074 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_R_1; // 0x0078 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_R_2; // 0x007C R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH0_R_3; // 0x0080 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_L_0; // 0x0084 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_L_1; // 0x0088 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_L_2; // 0x008C R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_L_3; // 0x0090 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_R_0; // 0x0094 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_R_1; // 0x0098 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_R_2; // 0x009C R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH1_R_3; // 0x00A0 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_L_0; // 0x00A4 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_L_1; // 0x00A8 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_L_2; // 0x00AC R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_L_3; // 0x00B0 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_R_0; // 0x00B4 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_R_1; // 0x00B8 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH2_R_2; // 0x00BC R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_Ch2_R_3; // 0x00C0 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_L_0; // 0x00C4 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_L_1; // 0x00C8 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_L_2; // 0x00CC R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_R_0; // 0x00D0 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_R_1; // 0x00D4 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CH3_R_2; // 0x00D8 R I2S PCM Output Data Register 0x00 ++ volatile unsigned int I2S_CUV_L_R; // 0x00DC R I2S CUV Output Data Register 0x00 ++}HDMII2S, *PHDMII2S; ++ ++ //CEC register base address ++//#define HwHDMICEC_BASE *(volatile unsigned long *)0xF0259000 ++typedef struct _HDMICEC{ ++ volatile unsigned int CEC_TX_STATUS_0; // 0x0000 R CEC Tx status register 0. 0x00 ++ volatile unsigned int CEC_TX_STATUS_1; // 0x0004 R CEC Tx status register 1. Number of blocks transferred. 0x00 ++ volatile unsigned int CEC_RX_STATUS_0; // 0x0008 R CEC Rx status register 0. 0x00 ++ volatile unsigned int CEC_RX_STATUS_1; // 0x000C R CEC Rx status register 1. Number of blocks received. 0x00 ++ volatile unsigned int CEC_INTR_MASK; // 0x0010 R/W CEC interrupt mask register 0x00 ++ volatile unsigned int CEC_INTR_CLEAR; // 0x0014 R/W CEC interrupt clear register 0x00 ++ volatile unsigned int NOTDEFINE0[2]; // 0x0018 0x001C - Reserved - ++ volatile unsigned int CEC_LOGIC_ADDR; // 0x0020 R/W HDMI Tx logical address register 0x0F ++ volatile unsigned int NOTDEFINE1[3]; // 0x0024 0x0028, 0x002C - Reserved - ++ volatile unsigned int CEC_DIVISOR_0; // 0x0030 R/W Clock divisor for 0.05ms period count ([7:0] of 32-bit) 0x00 ++ volatile unsigned int CEC_DIVISOR_1; // 0x0034 R/W Clock divisor for 0.05ms period count ([15:8] of 32-bit) 0x00 ++ volatile unsigned int CEC_DIVISOR_2; // 0x0038 R/W Clock divisor for 0.05ms period count ([23:16] of 32-bit) 0x00 ++ volatile unsigned int CEC_DIVISOR_3; // 0x003C R/W Clock divisor for 0.05ms period count ([31:24] of 32-bit) 0x00 ++//CEC Tx related Registers ++ volatile unsigned int CEC_TX_CTRL; // 0x0040 R/W CEC Tx control register 0x10 ++ volatile unsigned int CEC_TX_BYTE_NUM; // 0x0044 R/W Number of blocks in a message to be transferred 0x00 ++ volatile unsigned int NOTDEFINE2[6]; // 0x0048 0x004C - Reserved - ++ // 0x0050 ++ volatile unsigned int CEC_TX_STATUS_2; // 0x0060 R CEC Tx status register 2 0x00 ++ volatile unsigned int CEC_TX_STATUS_3; // 0x0064 R CEC Tx status register 3 0x00 ++ volatile unsigned int NOTDEFINE3[6]; // 0x0068 0x006C - Reserved - ++ // 0x0070 ++ volatile unsigned int NOTDEFINE4[3]; // 0x0074 0x0078, 0x007C - Reserved - ++ volatile unsigned int CEC_TX_BUFFER[16]; // 0x0080 ~ 0x00BC R/W Byte #0 ~ #15 of CEC message to be transferred. (#0 is transferred 1st ) 0x00 ++//CEC Rx related Registers ++ volatile unsigned int CEC_RX_CTRL; // 0x00C0 R/W CEC Rx control register 0x00 ++ volatile unsigned int NOTDEFINE5[7]; // 0x00C4 0x00C8, 0x00CC - Reserved - ++ // 0x00D0 ++ volatile unsigned int CEC_RX_STATUS_2; // 0x00E0 R CEC Rx status register 2 0x00 ++ volatile unsigned int CEC_RX_STATUS_3; // 0x00E4 R CEC Rx status register 3eived 1st ) 0x00 ++ volatile unsigned int NOTDEFINE6[2]; // 0x00E8, 0x00EC - Reserved - ++ volatile unsigned int CEC_RX_BUFFER[16]; // 0x0100 ~ 0x013C R Byte #0 ~ #15 of CEC message received (#0 is received 1st ) 0x00 ++}HDMICEC, *PHDMICEC; ++ ++/*********************************************************************** ++* 9-1. Camera Interface Register Define (Base Addr = 0xF0230000) ++************************************************************************/ ++//#define HwCIF_BASE *(volatile unsigned long *)0xF0230000 // CIF Base Register ++typedef struct _CIF{ ++ volatile unsigned int ICPCR1; // 0x00 W/R 0x00000000 Input Image Color/Pattern Configuration Register 1 ++ volatile unsigned int CCIR656FCR1; // 0x04 W/R 0x06ff0000 CCIR656 Format Configuration Register 1 ++ volatile unsigned int CCIR656FCR2; // 0x08 W/R 0x010b CCIR656 Format Configuration Register 2 ++ volatile unsigned int IIS; // 0x0C W/R 0x00000000 Input Image Size ++ volatile unsigned int IIW1; // 0x10 W/R 0x00000000 Input Image Windowing 1 ++ volatile unsigned int IIW2; // 0x14 W/R 0x00000000 Input Image Windowing 2 ++ volatile unsigned int CDCR1; // 0x18 W/R 0x0003 DMA Configuration Register 1 ++ volatile unsigned int CDCR2; // 0x1C W/R 0x00000000 DMA Configuration Register 2 ++ volatile unsigned int CDCR3; // 0x20 W/R 0x00000000 DMA Configuration Register 3 ++ volatile unsigned int CDCR4; // 0x24 W/R 0x00000000 DMA Configuration Register 4 ++ volatile unsigned int CDCR5; // 0x28 W/R 0x00000000 DMA Configuration Register 5 ++ volatile unsigned int CDCR6; // 0x2C W/R 0x00000000 DMA Configuration Register 6 ++ volatile unsigned int CDCR7; // 0x30 W/R 0x00000000 DMA Configuration Register 7 ++ volatile unsigned int CDCR8; // 0x34 W/R 0x00000000 DMA Configuration Register 7 ++ volatile unsigned int FIFOSTATE; // 0x38 R 0x00000000 FIFO Status Register ++ volatile unsigned int CIRQ; // 0x3C W/R 0x00000000 Interrupt & Status register ++ volatile unsigned int OCTRL1; // 0x40 W/R 0x37000000 Overlay Control 1 ++ volatile unsigned int OCTRL2; // 0x44 W/R 0x00000000 Overlay Control 2 ++ volatile unsigned int OCTRL3; // 0x48 W/R 0x00000000 Overlay Control 3 ++ volatile unsigned int OCTRL4; // 0x4C W/R 0x00000000 Overlay Control 4 ++ volatile unsigned int OIS; // 0x50 W/R 0x00000000 Overlay Image Size ++ volatile unsigned int OIW1; // 0x54 W/R 0x00000000 Overlay Image Windowing 1 ++ volatile unsigned int OIW2; // 0x58 W/R 0x00000000 Overlay Image Windowing 2 ++ volatile unsigned int COBA; // 0x5C W/R 0x00000000 Overlay Base Address ++ volatile unsigned int COBO; // 0x60 W/R 0x00000000 Overlay Base Address Offset ++ volatile unsigned int CDS; // 0x64 W/R 0x00000000 Camera Down Scaler ++ volatile unsigned int CCM1; // 0x68 W/R 0x00000000 Capture Mode Configuration 1 ++ volatile unsigned int CCM2; // 0x6C W/R 0x00000000 Capture Mode Configuration 2 ++ volatile unsigned int CESA; // 0x70 W/R 0x00000000 Point Encoding Start Address ++ volatile unsigned int CR2Y; // 0x74 W/R 0x00000000 RGB2YUV Format converter Configuration ++ volatile unsigned int CCYA; // 0x78 R - Current Y Address ++ volatile unsigned int CCUA; // 0x7C R - Current U Address ++ volatile unsigned int CCVA; // 0x80 R - Current V Address ++ volatile unsigned int CCLC; // 0x84 R Current Line count ++}CIF, *PCIF; ++ ++/*********************************************************************** ++* 9-2. Effect Register Define (Base Addr = 0xF0230100) ++************************************************************************/ ++//#define HwCEM_BASE *(volatile unsigned long *)0xF0230100 //W/R 0x00000000 Effect mode register ++ ++typedef struct _EFFECT{ ++ volatile unsigned int CEM; // 0x00 W/R 0x00000000 Effect mode register ++ volatile unsigned int CSUV; // 0x04 W/R 0x00000000 Sepia UV setting ++ volatile unsigned int CCS; // 0x08 W/R 0x00000000 Color selection register ++ volatile unsigned int CHFC; // 0x0C W/R 0x00000000 H-filter coefficent0 ++ volatile unsigned int CST; // 0x10 W/R 0x00000000 Sketch threshold register ++ volatile unsigned int CCT; // 0x14 W/R 0x00000000 Clamp threshold register ++ volatile unsigned int CBR; // 0x18 W/R 0x00000000 BIAS register ++ volatile unsigned int CEIS; // 0x1C W/R 0x00000000 Image size register ++ volatile unsigned int NOTDEFINE0[8]; // 0x20, 24, 28, 2C, 30, 34, 38, 3C, ++ volatile unsigned int INPATH_CTRL; // 0x40 W/R 0x00000000 Inpath configuration ++ volatile unsigned int CISA1; // 0x44 W/R 0x00000000 Source address in Y channel ++ volatile unsigned int CISA2; // 0x48 W/R 0x00000000 Source address in U channel ++ volatile unsigned int CISA3; // 0x4C W/R 0x00000000 Source address in V channel ++ volatile unsigned int CISS; // 0x50 W/R 0x00000000 Source image size ++ volatile unsigned int CISO; // 0x54 W/R 0x00000000 Source image offset ++ volatile unsigned int CIDS; // 0x58 W/R 0x00000000 Destination image size ++ volatile unsigned int CIS; // 0x5C W/R 0x00000000 Target scale ++}EFFECT, *PEFFECT; ++ ++/*********************************************************************** ++* 9-3. Scaler Register Define (Base Addr = 0xF0230200) ++************************************************************************/ ++//#define HwCSC_BASE *(volatile unsigned long *)0xF0230200 //W/R 0x00000000 Scaler configuration ++typedef struct _CIFSCALER{ ++ volatile unsigned int CSC; // 0x00 W/R 0x00000000 Scaler configuration ++ volatile unsigned int CSSF; // 0x04 W/R 0x00000000 Scale factor ++ volatile unsigned int CSSO; // 0x08 W/R 0x00000000 Image offset ++ volatile unsigned int CSSS; // 0x0C W/R 0x00000000 Source image size ++ volatile unsigned int CSDS; // 0x10 W/R 0x00000000 Destination image size ++}CIFSCALER, *PCIFSCALER; ++ ++ ++ ++/*********************************************************************** ++* 10. Video and Image Quality Enhancer Register Define (Base Addr = 0xF0230200) ++************************************************************************/ ++//#define HwVIQE_BASE *(volatile unsigned long *)0xF0252000 ++typedef struct _VIQE{ ++ volatile unsigned int CTRL; // 0x000 R/W 0x00000000 VIQE General Control Register ++ volatile unsigned int SIZE; // 0x004 R/W 0x00000000 VIQE SIZE Register ++ volatile unsigned int TIMEGEN; // 0x008 R/W 0x00000000 VIQE Time Generator Register ++ volatile unsigned int LUMADLY; // 0x00C R/W 0x00000000 VIQE Luma Delay Register ++ volatile unsigned int IMGCONF; // 0x010 R/W 0x00000000 VIQE Image Configuration Register ++ volatile unsigned int IMGFMT; // 0x014 R/W 0x00000000 VIQE Image Format Register ++ volatile unsigned int MISCC; // 0x018 R/W 0x00000000 VIQE Misc, Control Register ++ volatile unsigned int FRMC; // 0x01C R/W 0x00000000 VIQE Frame Control Register ++ volatile unsigned int INT; // 0x020 R/W 0x00000000 VIQE Interrupt Register ++ volatile unsigned int INTMASK; // 0x024 R/W 0x00000000 VIQE Interrupt Mask register ++ volatile unsigned int NOTDEFINE0[5]; ++ volatile unsigned int VERSION; // 0x03c R 0x4d2b3401 VIQE Version register ++ volatile unsigned int NOTDEFINE1[16]; ++ volatile unsigned int DI_CTRL; // 0x080 R/W 0x00000000 De-interlacer Control Register ++ volatile unsigned int DI_ENGINE0; // 0x084 R/W 0x00000000 De-interlacer Engine 0 Register ++ volatile unsigned int DI_ENGINE1; // 0x088 R/W 0x00000000 De-interlacer Engine 1 Register ++ volatile unsigned int PD_THRES0; // 0x08C R/W 0x00000000 De-interlacer Pulldown Threshold 0 Register ++ volatile unsigned int PD_THRES1; // 0x090 R/W 0x00000000 De-interlacer Pulldown Threshold 1 Register ++ volatile unsigned int PD_JUDDER; // 0x094 R/W 0x00000000 De-interlacer Pulldown Judder Register ++ volatile unsigned int DI_MISCC; // 0x098 R/W 0x00000000 De-interlacer Misc. Control register ++ volatile unsigned int NOTDEFINE2; ++ volatile unsigned int DI_STATUS; // 0x0A0 R De-interlacer Status Register ++ volatile unsigned int PD_STATUS; // 0x0A4 R De-interlacer Pulldown Status Register ++ volatile unsigned int DI_REGION0; // 0x0A8 R/W 0x00000000 De-interlacer Region 0 Register ++ volatile unsigned int DI_REGION1; // 0x0AC R/W 0x00000000 De-interlacer Region 1 register ++ volatile unsigned int NOTDEFINE3[3]; ++ volatile unsigned int DI_INT; // 0x0BC R/W 0x00000000 De-interlacer Interrupt Register ++ volatile unsigned int NOTDEFINE4[16]; ++ ++ volatile unsigned int DN_C_H_Y0; // 0x100 R/W 0xbfffffa4 Temporal De-noiser horizontal coefficient #0 in luminance ++ volatile unsigned int DN_C_H_Y1; // 0x104 R/W 0x15556aaa Temporal De-noiser horizontal coefficient #1 in luminance ++ volatile unsigned int DN_C_V_Y0; // 0x108 R/W 0xaaaaaaa4 Temporal De-noiser vertical coefficient #0 in luminance ++ volatile unsigned int DN_C_V_Y1; // 0x10C R/W 0x15556aaa Temporal De-noiser vertical coefficient #1 in luminance ++ volatile unsigned int DN_C_T_Y0; // 0x110 R/W 0xaaaaaaa4 Temporal De-noiser temporal coefficient #0 in luminance ++ volatile unsigned int DN_C_T_Y1; // 0x114 R/W 0x15556aaa Temporal De-noiser temporal coefficient #1 in luminance ++ volatile unsigned int DN_C_H_C0; // 0x118 R/W 0xbfffffa4 Temporal De-noiser horizontal coefficient #0 in chrominance ++ volatile unsigned int DN_C_H_C1; // 0x11C R/W 0x15556aaa Temporal De-noiser horizontal coefficient #1 in chrominance ++ volatile unsigned int DN_C_V_C0; // 0x120 R/W 0xaaaaaaa4 Temporal De-noiser vertical coefficient #0 in chrominance ++ volatile unsigned int DN_C_V_C1; // 0x124 R/W 0x15556aaa Temporal De-noiser vertical coefficient #1 in chrominance ++ volatile unsigned int DN_C_T_C0; // 0x128 R/W 0xaaaaaaa4 Temporal De-noiser temporal coefficient #0 in chrominance ++ volatile unsigned int DN_C_T_C1; // 0x12C R/W 0x15556aaa Temporal De-noiser temporal coefficient #1 in chrominance ++ volatile unsigned int DN_STATE0_TEM; // 0x130 R/W 0x00000000 Temporal De-noiser count states and int. mask ++ volatile unsigned int DN_STATE1_TEM; // 0x134 R - Temporal De-noiser count states ++ volatile unsigned int DN_DIV_IMG_TEM; // 0x138 R/W 0x00000168 Temporal De-noiser image divide ++ volatile unsigned int NOTDEFINE5; ++ volatile unsigned int DN_C_SPA_Y0; // 0x140 R/W 0x12320e0a Spatial De-noiser coefficient #0 in luminance ++ volatile unsigned int DN_C_SPA_Y1; // 0x144 R/W 0x373c051d Spatial De-noiser coefficient #1 in luminance ++ volatile unsigned int DN_C_SPA_Y2; // 0x148 R/W 0x4a0640ff Spatial De-noiser coefficient #2 in luminance ++ volatile unsigned int DN_C_SPA_Y3; // 0x14C R/W 0x003100fb Spatial De-noiser coefficient #3 in luminance ++ volatile unsigned int DN_C_SPA_C0; // 0x150 R/W 0x12190805 Spatial De-noiser coefficient #0 in chrominance ++ volatile unsigned int DN_C_SPA_C1; // 0x154 R/W 0x373c0507 Spatial De-noiser coefficient #1 in chrominance ++ volatile unsigned int DN_C_SPA_C2; // 0x158 R/W 0x4a0640ff Spatial De-noiser coefficient #2 in chrominance ++ volatile unsigned int DN_C_SPA_C3; // 0x15C R/W 0x003100fb Spatial De-noiser coefficient #3 in chrominance ++ volatile unsigned int DN_FIFOSTATE; // 0x160 R/W 0x00000000 De-noiser FIFO states ++ volatile unsigned int DN_STATE0_SPA; // 0x164 R/W 0x00000000 Spatial De-noiser count states and int.mask ++ volatile unsigned int DN_STATE1_SPA; // 0x168 R - Spatial De-noiser count states ++ volatile unsigned int DN_CTRL; // 0x16C R/W 0x00000000 De-noiser FIFO and coefficient ctrl ++ volatile unsigned int DN_DIV_IMG_SPA; // 0x170 R/W 0x00000168 Spatial De-noiser image divide ++ volatile unsigned int NOTDEFINE6[3]; ++ ++ volatile unsigned int RD_IMG0_BASE0; // 0x180 R/W 0x00000000 RDMA image #0 base address in Y channel ++ volatile unsigned int RD_IMG0_BASE1; // 0x184 R/W 0x00000000 RDMA image #0 base address in U channel ++ volatile unsigned int RD_IMG0_BASE2; // 0x188 R/W 0x00000000 RDMA image #0 base address in V channel ++ volatile unsigned int RD_IMG0_OFS; // 0x18C R/W 0x00000000 RDMA image #0 address offset ++ volatile unsigned int RD_IMG1_BASE0; // 0x190 R/W 0x00000000 RDMA image #1 base address in Y channel ++ volatile unsigned int RD_IMG1_BASE1; // 0x194 R/W 0x00000000 RDMA image #1 base address in U channel ++ volatile unsigned int RD_IMG1_BASE2; // 0x198 R/W 0x00000000 RDMA image #1 base address in V channel ++ volatile unsigned int RD_IMG1_OFS; // 0x19C R/W 0x00000000 RDMA image #1 address offset ++ volatile unsigned int RD_IMG2_BASE0_0; // 0x1A0 R/W 0x00000000 RDMA decomp. data #0 base address in Y channel ++ volatile unsigned int RD_IMG2_BASE1_0; // 0x1A4 R/W 0x00000000 RDMA decomp. data #0 base address in U channel ++ volatile unsigned int RD_IMG2_BASE2_0; // 0x1A8 R/W 0x00000000 RDMA decomp. data #0 base address in V channel ++ volatile unsigned int RD_IMG2_BASE0_1; // 0x1AC R/W 0x00000000 RDMA decomp. data #1 base address in Y channel ++ volatile unsigned int RD_IMG2_BASE1_1; // 0x1B0 R/W 0x00000000 RDMA decomp. data #1 base address in U channel ++ volatile unsigned int RD_IMG2_BASE2_1; // 0x1B4 R/W 0x00000000 RDMA decomp. data #1 base address in V channel ++ volatile unsigned int RD_CUR_ADDR0; // 0x1B8 R - RDMA image #0 current address ++ volatile unsigned int RD_CUR_ADDR1; // 0x1BC R - RDMA image #1 current address ++ volatile unsigned int RD_CUR_ADDR2; // 0x1C0 R - RDMA decomp. data current address ++ volatile unsigned int RD_FIFOSTATE; // 0x1C4 R/W 0x00000000 RDMA FIFO States ++ volatile unsigned int RD_LINE_STATE0; // 0x1C8 R - RDMA count states #0 ++ volatile unsigned int RD_LINE_STATE1; // 0x1CC R/W 0x00000000 RDMA count states #1 ++ volatile unsigned int RD_CTRL; // 0x1D0 R/W 0x00000000 RDMA control register ++ volatile unsigned int RD_COMP_PL0; // 0x1D4 R/W 0x00000000 RDMA decomp. data number in Y channel ++ volatile unsigned int RD_COMP_PL1; // 0x1D8 R/W 0x00000000 RDMA decomp. data number in C channel ++ volatile unsigned int NOTDEFINE7[9]; ++ ++ volatile unsigned int CD_BASE0_0; // 0x200 R/W 0x00000000 Comp. DMA #0 base address in Y channel ++ volatile unsigned int CD_BASE1_0; // 0x204 R/W 0x00000000 Comp. DMA #0 base address in U channel ++ volatile unsigned int CD_BASE2_0; // 0x208 R/W 0x00000000 Comp. DMA #0 base address in V channel ++ volatile unsigned int CD_BASE0_1; // 0x20C R/W 0x00000000 Comp. DMA #1 base address in Y channel ++ volatile unsigned int CD_BASE1_1; // 0x210 R/W 0x00000000 Comp. DMA #1 base address in U channel ++ volatile unsigned int CD_BASE2_1; // 0x214 R/W 0x00000000 Comp. DMA #1 base address in V channel ++ volatile unsigned int CD_CUR_ADDR; // 0x218 R - Comp. DMA current address ++ volatile unsigned int CD_STATE; // 0x21C R/W 0x00000000 Comp. DMA states ++ volatile unsigned int CD_CTRL; // 0x220 R/W 0x00000000 Comp. DMA control register ++ volatile unsigned int NOTDEFINE8[3]; ++ volatile unsigned int CD_HUFF_CNT0; // 0x230 R - Comp. DMA compressed data count in Y channel ++ volatile unsigned int CD_HUFF_CNT1; // 0x234 R - Comp. DMA compressed data count in U channel ++ volatile unsigned int CD_HUFF_CNT2; // 0x238 R Comp. DMA compressed data count in V channel ++ volatile unsigned int NOTDEFINE9[17]; ++ ++ volatile unsigned int OD_BASE0; // 0x280 R/W 0x00000000 ODMA base address in Y channel ++ volatile unsigned int OD_BASE1; // 0x284 R/W 0x00000000 ODMA base address in U channel ++ volatile unsigned int OD_BASE2; // 0x288 R/W 0x00000000 ODMA base address in V channel ++ volatile unsigned int OD_SIZE; // 0x28C R/W 0x00000000 ODMA image size ++ volatile unsigned int OD_OFS; // 0x290 R/W 0x00000000 ODMA address offset ++ volatile unsigned int OD_CFG; // 0x294 R/W 0x00000000 ODMA image type ++ volatile unsigned int NOTDEFINE10[3]; ++ volatile unsigned int OD_CTRL; // 0x2A4 R/W 0x00000000 ODMA control register ++ volatile unsigned int OD_STATE; // 0x2A8 R/W 0x00000000 ODMA States ++ volatile unsigned int NOTDEFINE11[85]; ++ ++ volatile unsigned int GM_CTRL; // 0x400 R/W 0x00000000 Gamut-mapper Control Register ++ volatile unsigned int GM_STATUS; // 0x404 R/W 0x00000000 Gamut-mapper Status Register ++ volatile unsigned int GM_REGION0; // 0x408 R/W 0x00000000 Gamut-mapper Region 0 Register ++ volatile unsigned int GM_REGION1; // 0x40C R/W 0x00000000 Gamut-mapper Region 1 register ++ volatile unsigned int NOTDEFINE12[3]; ++ volatile unsigned int GM_INT; // 0x41C R/W 0x00000000 Gamut-mapper Interrupt Register ++ volatile unsigned int NOTDEFINE13[120]; ++ ++ volatile unsigned int HI_CTRL; // 0x600 R/W 0x00000000 Histogram Control Register ++ volatile unsigned int HI_STATUS; // 0x604 R/W 0x00000000 Histogram Status Register ++ volatile unsigned int HI_CONFIG; // 0x608 R/W 0x00000000 Histogram Configuration Register ++ volatile unsigned int HI_REGION0; // 0x60C R/W 0x00000000 Histogram Region 0 Register ++ volatile unsigned int HI_REGION1; // 0x610 R/W 0x00000000 Histogram Region 1 register ++ volatile unsigned int NOTDEFINE14[2]; ++ volatile unsigned int HI_INT; // 0x61C R/W 0x00000000 Histogram Interrupt Register ++ volatile unsigned int HI_SEGS[4]; // 0x620 ~ 0x62C R/W 0x00000000 Histogram Segments Register ++ volatile unsigned int HI_CDFS[4]; // 0x630 ~ 0x63C R 0x00000000 Histogram CDF Register ++ volatile unsigned int HI_CNTS[8]; // 0x640 ~ 0x65C R 0x00000000 Histogram CNT Register ++ volatile unsigned int HI_SCALE[4]; // 0x660 ~ 0x66C R/W 0x00000000 Histogram Scale Register ++ volatile unsigned int HI_LUTS[64]; // 0x700 ~ 0x7FC R/W 0x00000000 Histogram LUT Table register ++}VIQE, *PVIQE; ++ ++ ++ ++/*********************************************************************** ++* 11. DDI_CONFIG/DDI_CACHE Register Define (Base Addr = 0xF0251000) ++************************************************************************/ ++//#define HwDDI_CONFIG_BASE *(volatile unsigned long *)0xF0251000 ++//#define HwDDI_CACHE_BASE *(volatile unsigned long *)0xF0250000 ++ ++typedef struct _DDICONFIG{ ++ volatile unsigned int NTSCPAL_SEL; // 0x000 R/W 0x00000001 NTSCPAL_Encoder select ++ volatile unsigned int LVDS_CTRL; // 0x004 R/W 0x04444443 LVDS Control register ++ volatile unsigned int LVDS_TXO_SEL0; // 0x008 R/W 0x03020100 LVDS TXOUT select #0 ++ volatile unsigned int LVDS_TXO_SEL1; // 0x00C R/W 0x09080504 LVDS TXOUT select #1 ++ volatile unsigned int LVDS_TXO_SEL2; // 0x010 R/W 0x0D0C0B0A LVDS TXOUT select #2 ++ volatile unsigned int LVDS_TXO_SEL3; // 0x014 R/W 0x13121110 LVDS TXOUT select #3 ++ volatile unsigned int LVDS_TXO_SEL4; // 0x018 R/W 0x1A191514 LVDS TXOUT select #4 ++ volatile unsigned int LVDS_TXO_SEL5; // 0x01C R/W 0x0E070618 LVDS TXOUT select #5 ++ volatile unsigned int LVDS_TXO_SEL6; // 0x020 R/W 0x1B17160F LVDS TXOUT select #6 ++ volatile unsigned int LVDS_TXO_SEL7; // 0x024 R/W 0x1F1E1F1E LVDS TXOUT select #7 ++ volatile unsigned int LVDS_TXO_SEL8; // 0x028 R/W 0x001E1F1E LVDS TXOUT select #8 ++ volatile unsigned int HDMI_CTRL; // 0x02C R/W 0x00000002 HDMI Control register ++ volatile unsigned int PWDN; // 0x030 R/W 0x00000000 Power Down ++ volatile unsigned int SWRESET; // 0x034 R/W 0x00000000 Soft Reset ++ volatile unsigned int ON_THE_FLY; // 0x038 R/W 0x00000000 On-The-Fly mode ++ volatile unsigned int NOTDEFINE0; ++ volatile unsigned int HDMI_AES; // 0x040 R/W 0x00000000 HDMI AES ++ volatile unsigned int HDMI_AES_DATA0; // 0x044 RW 0x00000000 HDMI AES DATA #0 ++ volatile unsigned int HDMI_AES_DATA1; // 0x048 R/W 0x00000000 HDMI AES DATA #1 ++ volatile unsigned int HDMI_AES_HW0; // 0x050 R/W 0x00000000 HDMI AES HW #0 ++ volatile unsigned int HDMI_AES_HW1; // 0x054 R/W 0x00000000 HDMI AES HW #1 ++ volatile unsigned int HDMI_AES_HW2; // 0x058 R/W 0x00000000 HDMI AES HW #2 ++}DDICONFIG, *PDDICONFIG; ++ ++ ++// Where is DDI_CONGIF in DataSheet ?? ++ ++typedef struct _DDICACHE{ ++ volatile unsigned int DDIC_CTRL; // 0x000 R/W 0x00000000 DDI_CACHE Control ++ volatile unsigned int DDIC_CFG0; // 0x004 R/W 0x00000000 DDI_CACHE Configuration #0 ++ volatile unsigned int DDIC_CFG1; // 0x008 R/W 0x00000000 DDI_CACHE Configuration #1 ++}DDICACHE, *PDDICACHE; ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 7 VIDEO BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/*********************************************************************** ++* 4. VIDEO CODEC Register Define (Base Addr = 0x0xF0700000) ++************************************************************************/ ++//#define HwVIDEOCODEC_BASE *(volatile unsigned long*)0xF0700000 ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 7 VIDEO BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/******************************************************************************* ++* 5-1. JPEG Encoder Register Define (Base Addr = 0xF0720000) ++********************************************************************************/ ++//#define HwJPEGDECODER_BASE *(volatile unsigned long*)0xF0710000 ++//#define HwJPEGENCODER_BASE *(volatile unsigned long*)0xF0720000 ++//#define HwVIDEOCACHE_BASE *(volatile unsigned long*)0xF0701000 ++typedef struct _JPEGENCODER{ ++ volatile unsigned int NOTDEFINE0; // 0x000 ++ volatile unsigned int JP_MOD; // 0x004 R/W ALL 0x00000000 JPEG codec mode register ++ volatile unsigned int JP_INT_MASK; // 0x008 R/W ALL 0x0000001f Interrupt mask register ++ volatile unsigned int JP_INT_LEVEL; // 0x00c R/W SLV 0x000000ff FIFO interrupt level register ++ volatile unsigned int JP_TRG_MOD; // 0x010 R/W ALL 0x00000000 Polling or Interrupt mode selection register ++ volatile unsigned int NOTDEFINE1[3]; ++ volatile unsigned int R_YBUF_ADDR; // 0x020 R/W JP 0x00000000 Raw data buffer Y address register ++ volatile unsigned int R_UBUF_ADDR; // 0x024 R/W JP 0x00000000 Raw data buffer U address register ++ volatile unsigned int R_VBUF_ADDR; // 0x028 R/W JP 0x00000000 Raw data V address register ++ volatile unsigned int R_BUF_INFO; // 0x02c R/W JP 0x00000000 Raw data buffer information register ++ volatile unsigned int JP_SIZE; // 0x030 R/W JP 0x00000000 Image size information register ++ volatile unsigned int JP_CHROMA; // 0x034 R/W JP 0x00000000 Image format information register ++ volatile unsigned int JP_CBUF_ADDR; // 0x38 R/W JP 0x00000000 Coded data buffer address register ++ volatile unsigned int JP_CBUF_SIZE; // 0x03c R/W JP 0x00000fff Coded data buffer size register ++ volatile unsigned int NOTDEFINE2[12]; ++ volatile unsigned int JP_START; // 0x070 W ALL 0x00000000 Codec start command register ++ volatile unsigned int NOTDEFINE3[3]; ++ volatile unsigned int JP_SBUF_WCNT; // 0x080 R/W MST 0x00000000 Source buffer write count register ++ volatile unsigned int JP_SBUF_RCNT; // 0x084 R MST 0x00000000 Source buffer read count register ++ volatile unsigned int JP_DBUF_WCNT; // 0x088 R MST 0x00000000 Destination buffer write count register ++ volatile unsigned int JP_DBUF_RCNT; // 0x08c R/W MST 0x00000000 Destination buffer read count register ++ volatile unsigned int JP_IFIFO_ST; // 0x090 R SLV 0x00000000 Input FIFO status register ++ volatile unsigned int JP_OFIFO_ST; // 0x094 R SLV 0x00000000 Output FIFO status register ++ volatile unsigned int NOTDEFINE4[2]; ++ volatile unsigned int JP_INT_FLAG; // 0x0a0 R ALL 0x00000000 Interrupt flag register ++ volatile unsigned int JP_INT_ACK; // 0x0a4 R ALL 0x00000000 Interrupt ack register ++ volatile unsigned int NOTDEFINE5[10]; ++ volatile unsigned int JP_IFIFO_WD; // 0x0c0 W SLV 0x00000000 Input FIFO write data register ++ volatile unsigned int NOTDEFINE6[7]; ++ volatile unsigned int JP_OFIFO_RD; // 0x0e0 R SLV 0x00000000 Output FIFO read data register ++ volatile unsigned int NOTDEFINE7[7]; ++ volatile unsigned int JPC_QTAB0[64]; // 0x100 - W JPC 0x00000000 Encoder Q table 0 (64 entries) ++ volatile unsigned int JPC_QTAB1[64]; // 0x200 - W JPC 0x00000000 Encoder Q table 1 (64 entries) ++}JPEGENCODER, *PJPEGENCODER; ++ ++/******************************************************************************* ++* 5-2. JPEG Decoder Register Define (Base Addr = 0xF0710000) ++********************************************************************************/ ++typedef struct _JPEGDECODER{ ++ volatile unsigned int NOTDEFINE0; // 0x000 ++ volatile unsigned int JP_MOD; // 0x004 R/W ALL 0x00000000 JPEG codec mode register ++ volatile unsigned int JP_INT_MASK; // 0x008 R/W ALL 0x0000001f Interrupt mask register ++ volatile unsigned int JP_INT_LEVEL; // 0x00c R/W SLV 0x000000ff FIFO interrupt level register ++ volatile unsigned int JP_TRG_MOD; // 0x010 R/W ALL 0x00000000 Polling or Interrupt mode selection register ++ volatile unsigned int R_YBUF_ADDR; // 0x020 R/W JP 0x00000000 Raw data buffer Y address register ++ volatile unsigned int R_UBUF_ADDR; // 0x024 R/W JP 0x00000000 Raw data buffer U address register ++ volatile unsigned int R_VBUF_ADDR; // 0x028 R/W JP 0x00000000 Raw data V address register ++ volatile unsigned int R_BUF_INFO; // 0x02c R/W JP 0x00000000 Raw data buffer information register ++ volatile unsigned int JP_SIZE; // 0x030 R/W JP 0x00000000 Image size information register ++ volatile unsigned int JP_CHROMA; // 0x034 R/W JP 0x00000000 Image format information register ++ volatile unsigned int JP_CBUF_ADDR; // 0x38 R/W JP 0x00000000 Coded data buffer address register ++ volatile unsigned int JP_CBUF_SIZE; // 0x03c R/W JP 0x00000fff Coded data buffer size register ++ volatile unsigned int NOTDEFINE1[4]; ++ volatile unsigned int JPD_TBL_ID; // 0x050 R/W JPD 0x00000000 Decoder table index register ++ volatile unsigned int JPD_RST_INTV; // 0x054 R/W JPD 0x00000000 Decoder reset interval register ++ volatile unsigned int JPD_OUT_SCL; // 0x058 R/W JPD 0x00000000 Decoder output scaling register ++ volatile unsigned int NOTDEFINE2[5]; ++ volatile unsigned int JP_START; // 0x070 W ALL 0x00000000 Codec start command register ++ volatile unsigned int NOTDEFINE3[3]; ++ volatile unsigned int JP_SBUF_WCNT; // 0x080 R/W MST 0x00000000 Source buffer write count register ++ volatile unsigned int JP_SBUF_RCNT; // 0x084 R MST 0x00000000 Source buffer read count register ++ volatile unsigned int JP_DBUF_WCNT; // 0x088 R MST 0x00000000 Destination buffer write count register ++ volatile unsigned int JP_DBUF_RCNT; // 0x08c R/W MST 0x00000000 Destination buffer read count register ++ volatile unsigned int JP_IFIFO_ST; // 0x090 R SLV 0x00000000 Input FIFO status register ++ volatile unsigned int JP_OFIFO_ST; // 0x094 R SLV 0x00000000 Output FIFO status register ++ volatile unsigned int NOTDEFINE4[2]; ++ volatile unsigned int JP_INT_FLAG; // 0x0a0 R ALL 0x00000000 Interrupt flag register ++ volatile unsigned int JP_INT_ACK; // 0x0a4 R ALL 0x00000000 Interrupt ack register ++ volatile unsigned int NOTDEFINE5[6]; ++ volatile unsigned int JP_IFIFO_WD; // 0x0c0 W SLV 0x00000000 Input FIFO write data register ++ volatile unsigned int NOTDEFINE6[7]; ++ volatile unsigned int JP_OFIFO_RD; // 0x0e0 R SLV 0x00000000 Output FIFO read data register ++ volatile unsigned int NOTDEFINE7[135]; ++ volatile unsigned int JPD_IQTAB0[64]; // 0x300 - W JPD 0x00000000 Decoder IQ table 0 (64 entries) ++ volatile unsigned int JPD_IQTAB1[64]; // 0x400 - W JPD 0x00000000 Decoder IQ table 1 (64 entires) ++ volatile unsigned int JPD_IQTAB2[64]; // 0x500 - W JPD 0x00000000 Decoder IQ table 2 (64 entires) ++ volatile unsigned int JPD_HT_DC0_C[16]; // 0x600 - W JPD 0x00000000 Decoder huffman table (dc0 code, 16 entreis) ++ volatile unsigned int JPD_HT_AC0_C[16]; // 0x640 - W JPD 0x00000000 Decoder huffman table (ac0 code, 16 entreis) ++ volatile unsigned int JPD_HT_DC1_C[16]; // 0x680 - W JPD 0x00000000 Decoder huffman table (dc1 code, 16 entreis) ++ volatile unsigned int JPD_HT_AC1_C[16]; // 0x6c0 - W JPD 0x00000000 Decoder huffman table (ac1 code, 16 entreis) ++ volatile unsigned int JPD_HT_DC0_A[16]; // 0x700 - W JPD 0x00000000 Decoder huffman table (dc0 addr, 16 entreis) ++ volatile unsigned int JPD_HT_AC0_A[16]; // 0x740 - W JPD 0x00000000 Decoder huffman table (ac0 addr, 16 entreis) ++ volatile unsigned int JPD_HT_DC1_A[16]; // 0x780 - W JPD 0x00000000 Decoder huffman table (dc1 addr, 16 entreis) ++ volatile unsigned int JPD_HT_AC1_A[16]; // 0x7c0 - W JPD 0x00000000 Decoder huffman table (ac1 addr, 16 entreis) ++ volatile unsigned int JPD_HT_DC0_V[12]; // 0x800 - W JPD 0x00000000 Decoder huffman table (dc0 var, 12 entreis) ++ volatile unsigned int JPD_HT_AC0_V[162]; // 0x840 - W JPD 0x00000000 Decoder huffman table (ac0 var, 162 entreis) ++ volatile unsigned int NOTDEFINE8[78]; ++ volatile unsigned int JPD_HT_DC1_V[12]; // 0xc00 - W JPD 0x00000000 Decoder huffman table (dc1 var, 12 entreis) ++ volatile unsigned int NOTDEFINE9[4]; ++ volatile unsigned int JPD_HT_AC1_V[162]; // 0xc40 - W JPD 0x00000000 Decoder huffman table (ac1 var, 162 entreis) ++}JPEGDECODER, *PJPEGDECODER; ++ ++ ++/******************************************************************************* ++* TCC8900_DataSheet_PART 8 GRAPHIC BUS_V0.00 Dec.11 2008 ++********************************************************************************/ ++/*********************************************************************** ++* 4. Overlay Mixer Register Define (Base Addr = 0xF6000000) ++************************************************************************/ ++//#define HwOVERLAYMIXER_BASE *(volatile unsigned long *)0xF6000000 ++typedef struct _OVERLAYMIXER{ ++ volatile unsigned int FCH0_SADDR0; // 0x00 R/W 0x00000000 Front-End Channel 0 Source Address 0 ++ volatile unsigned int FCH0_SADDR1; // 0x04 R/W 0x00000000 Front-End Channel 0 Source Address 1 ++ volatile unsigned int FCH0_SADDR2; // 0x08 R/W 0x00000000 Front-End Channel 0 Source Address 2 ++ volatile unsigned int FCH0_SFSIZE; // 0x0C R/W 0x00000000 Front-End Channel 0 Source Frame Pixel Size ++ volatile unsigned int FCH0_SOFF; // 0x10 R/W 0x00000000 Front-End Channel 0 Source Pixel Offset ++ volatile unsigned int FCH0_SISIZE; // 0x14 R/W 0x00000000 Front-End Channel 0 Source Image Pixel Size ++ volatile unsigned int FCH0_WOFF; // 0x18 R/W 0x00000000 Front-End Channel 0 Window Pixel Offset ++ volatile unsigned int FCH0_SCTRL; // 0x1C R/W 0x00000000 Front-End Channel 0 Control ++ volatile unsigned int FCH1_SADDR0; // 0x20 R/W 0x00000000 Front-End Channel 1 Source Address 0 ++ volatile unsigned int FCH1_SADDR1; // 0x24 R/W 0x00000000 Front-End Channel 1 Source Address 1 ++ volatile unsigned int FCH1_SADDR2; // 0x28 R/W 0x00000000 Front-End Channel 1 Source Address 2 ++ volatile unsigned int FCH1_SFSIZE; // 0x2C R/W 0x00000000 Front-End Channel 1 Source Frame Pixel Size ++ volatile unsigned int FCH1_SOFF; // 0x30 R/W 0x00000000 Front-End Channel 1 Source Pixel Offset ++ volatile unsigned int FCH1_SISIZE; // 0x34 R/W 0x00000000 Front-End Channel 1 Source Image Pixel Size ++ volatile unsigned int FCH1_WOFF; // 0x38 R/W 0x00000000 Front-End Channel 1 Window Pixel Offset ++ volatile unsigned int FCH1_SCTRL; // 0x3C R/W 0x00000000 Front-End Channel 1 Control ++ volatile unsigned int FCH2_SADDR0; // 0x40 R/W 0x00000000 Front-End Channel 1 Source Address 0 ++ volatile unsigned int FCH2_SADDR1; // 0x44 R/W 0x00000000 Front-End Channel 1 Source Address 1 ++ volatile unsigned int FCH2_SADDR2; // 0x48 R/W 0x00000000 Front-End Channel 1 Source Address 2 ++ volatile unsigned int FCH2_SFSIZE; // 0x4C R/W 0x00000000 Front-End Channel 1 Source Frame Pixel Size ++ volatile unsigned int FCH2_SOFF; // 0x50 R/W 0x00000000 Front-End Channel 1 Source Pixel Offset ++ volatile unsigned int FCH2_SISIZE; // 0x54 R/W 0x00000000 Front-End Channel 1 Source Image Pixel Size ++ volatile unsigned int FCH2_WOFF; // 0x58 R/W 0x00000000 Front-End Channel 1 Window Pixel Offset ++ volatile unsigned int FCH2_SCTRL; // 0x5C R/W 0x00000000 Front-End Channel 1 Control ++ volatile unsigned int S0_CHROMA; // 0x60 R/W 0x00000000 Source 0 Chroma-Key Parameter ++ volatile unsigned int S0_PAR; // 0x64 R/W 0x00000000 Source 0 Arithmetic Parameter ++ volatile unsigned int S1_CHROMA; // 0x68 R/W 0x00000000 Source 1 Chroma-Key Parameter ++ volatile unsigned int S1_PAR; // 0x6C R/W 0x00000000 Source 1 Arithmetic Parameter ++ volatile unsigned int S2_CHROMA; // 0x70 R/W 0x00000000 Source 2 Chroma-Key Parameter ++ volatile unsigned int S2_PAR; // 0x74 R/W 0x00000000 Source 2 Arithmetic Parameter ++ volatile unsigned int S_CTRL; // 0x78 R/W 0x00000000 Source Control Register ++ volatile unsigned int NOTDEFINE0; // 0x7C - - Reserved ++ volatile unsigned int OP0_PAT; // 0x80 R/W 0x00000000 Source Operator 0 Pattern ++ volatile unsigned int OP1_PAT; // 0x84 R/W 0x00000000 Source Operator 1 Pattern ++ volatile unsigned int OP_CTRL; // 0x88 R/W 0x00000000 Source Operation Control Register ++ volatile unsigned int NOTDEFINE1; // 0x8C - - Reserved ++ volatile unsigned int BCH_DADDR0; // 0x90 R/W 0x00000000 Back-End Channel Destination Address 0 ++ volatile unsigned int BCH_DADDR1; // 0x94 R/W 0x00000000 Back -End Channel Destination Address 1 ++ volatile unsigned int BCH_DADDR2; // 0x98 R/W 0x00000000 Back -End Channel Destination Address 2 ++ volatile unsigned int BCH_DFSIZE; // 0x9C R/W 0x00000000 Back -End Channel Destination Frame Pixel Size ++ volatile unsigned int BCH_DOFF; // 0xA0 R/W 0x00000000 Back -End Channel Destination Pixel Offset ++ volatile unsigned int BCH_DCTRL; // 0xA4 R/W 0x00000000 Back -End Channel Control ++ ++ volatile unsigned int NOTDEFINE2[2]; // 0xA8 - 0xAF - - Reserved ++ volatile unsigned int BCH_DDMAT0; // 0xB0 R/W 0x00000000 Back-End Channel Destination Dither Matrix 0 ++ volatile unsigned int BCH_DDMAT1; // 0xB4 R/W 0x00000000 Back-End Channel Destination Dither Matrix 1 ++ volatile unsigned int BCH_DDMAT2; // 0xB8 R/W 0x00000000 Back-End Channel Destination Dither Matrix 2 ++ volatile unsigned int BCH_DDMAT3; // 0xBC R/W 0x00000000 Back-End Channel Destination Dither Matrix 3 ++ volatile unsigned int OM_CTRL; // 0xC0 R/W 0x00000000 Overlay Mixer Control ++ volatile unsigned int OM_IREQ; // 0xC4 R/W 0x00000000 Overlay Mixer Interrupt Request ++ volatile unsigned int NOTDEFINE3[206]; // 0xC8 - 0x3FF - - Reserved ++ ++ volatile unsigned int FCH0_LUT[256]; // 0x400 ? 0x7FF R/W - Front-End Channel 0 Lookup Table ++ volatile unsigned int FCH1_LUT[256]; // 0x800 ? 0xBFF R/W - Front-End Channel 1 Lookup Table ++ volatile unsigned int FCH2_LUT[256]; // 0xC00 ? 0xFFF R/W - Front-End Channel 2 Lookup Table ++}OVERLAYMIXER, *POVERLAYMIXER; ++ ++ ++/******************************************************************************* ++* 5-1. 2D/3D GPU ++* ++* Pixel Processor Register Map Register Define (Base Addr = 0xF0000000) ++********************************************************************************/ ++// #define HwPIXELPROCESSOR_BASE *(volatile unsigned long *)0xF0000000 ++typedef struct _GPUPIXELPROCESSOR{ ++ volatile unsigned int REND_LIST_ADDR; // 0x0000 R/W 0x00000000 Renderer List Address ++ volatile unsigned int REND_RSW_BASE; // 0x0004 R/W 0x00000000 Renderer State Word Base Address ++ volatile unsigned int REND_VERTEX_BASE; // 0x0008 R/W 0x00000000 Renderer Vertex Base Address ++ volatile unsigned int FEATURE_ENABLE; // 0x000C R/W 0x00000002 Feature Enable ++ volatile unsigned int Z_CLEAR_VALUE; // 0x0010 R/W 0x00000009 Z Clear Value ++ volatile unsigned int STENCIL_CLEAR_VALUE; // 0x0014 R/W 0x00000000 Stencil Clear value ++ volatile unsigned int ABGR_CLEAR_VALUE_0; // 0x0018 R/W 0x00000000 ABGR Clear Value 0 ++ volatile unsigned int ABGR_CLEAR_VALUE_1; // 0x001C R/W 0x00000000 ABGR Clear Value 1 ++ volatile unsigned int ABGR_CLEAR_VALUE_2; // 0x0020 R/W 0x00000000 ABGR Clear Value 2 ++ volatile unsigned int ABGR_CLEAR_VALUE_3; // 0x0024 R/W 0x00000000 ABGR Clear Value 3 ++ volatile unsigned int BOUNDING_BOX_LEFT_RIGHT; // 0x0028 R/W 0x00000000 Bounding Box left Right ++ volatile unsigned int BOUNDING_BOX_BOTTOM; // 0x002C R/W 0x00000000 Bounding Box Bottom ++ volatile unsigned int FS_STACK_ADDR; // 0x0030 R/W 0x00000000 FS Stack Address ++ volatile unsigned int FS_STACK_SIZE_AND_INIT_VAL; // 0x0034 R/W 0x00000000 FS Stack Size and Initial Value ++ volatile unsigned int ORIGIN_OFFSET_X; // 0x0040 R/W 0x00000000 Origin Offset X ++ volatile unsigned int ORIGIN_OFFSET_Y; // 0x0044 R/W 0x00000000 Origin Offset Y ++ volatile unsigned int SUBPIXEL_SPECIFIER; // 0x0048 R/W 0x00000075 Subpixel Specifier ++ volatile unsigned int TIEBREAK_MODE; // 0x004C R/W 0x00000000 Tiebreak mode Register ++ volatile unsigned int NOTDEFINE0[44]; ++ volatile unsigned int WB0_SOURCE_SELECT; // 0x0100 R/W 0x00000000 WB0 Source Select ++ volatile unsigned int WB0_TARGET_ADDR; // 0x0104 R/W 0x00000000 WB0 Target Addres ++ volatile unsigned int WB0_TARGET_PIXEL_FORMAT; // 0x0108 R/W 0x00000000 WB0 Target Pixel Format ++ volatile unsigned int WB0_TARGET_AA_FORMAT; // 0x010C R/W 0x00000000 WB0 Target AA Format ++ volatile unsigned int WB0_TARGET_LAYOUT; // 0x0110 R/W 0x00000000 WB0 Target Layout ++ volatile unsigned int WB0_TARGET_SCANLINE_LENGTH; // 0x0114 R/W 0x00000000 WB0 Target Scanline length ++ volatile unsigned int WB0_TARGET_FLAGS; // 0x0118 R/W 0x00000000 WB0 Target Flags ++ volatile unsigned int WB0_MRT_ENABLE; // 0x011C R/W 0x00000000 WB0 MRT Enagle ++ volatile unsigned int WB0_MRT_OFFSET; // 0x0120 R/W 0x00000000 WB0 MRT Offset ++ volatile unsigned int WB0_GLOBAL_TEST_ENABLE; // 0x0124 R/W 0x00000000 WB0 Global Test Enable ++ volatile unsigned int WB0_GLOBAL_TEST_REF_VALUE; // 0x0128 R/W 0x00000000 WB0 Global Test Reference ++ volatile unsigned int WB0_GLOBAL_TEST_CMP_FUNC; // 0x012C R/W 0x00000000 WB0 Global Test Compare Function ++ volatile unsigned int NOTDEFINE1[52]; ++ volatile unsigned int WB1_SOURCE_SELECT; // 0x0200 R/W 0x00000000 WB1 Source Select ++ volatile unsigned int WB1_TARGET_ADDR; // 0x0204 R/W 0x00000000 WB1 Target Addres ++ volatile unsigned int WB1_TARGET_PIXEL_FORMAT; // 0x0208 R/W 0x00000000 WB1 Target Pixel Format ++ volatile unsigned int WB1_TARGET_AA_FORMAT; // 0x020C R/W 0x00000000 WB1 Target AA Format ++ volatile unsigned int WB1_TARGET_LAYOUT; // 0x0210 R/W 0x00000000 WB1 Target Layout ++ volatile unsigned int WB1_TARGET_SCANLINE_LENGTH; // 0x0214 R/W 0x00000000 WB1 Target Scanline length ++ volatile unsigned int WB1_TARGET_FLAGS; // 0x0218 R/W 0x00000000 WB1 Target Flags ++ volatile unsigned int WB1_MRT_ENABLE; // 0x021C R/W 0x00000000 WB1 MRT Enagle ++ volatile unsigned int WB1_MRT_OFFSET; // 0x0220 R/W 0x00000000 WB1 MRT Offset ++ volatile unsigned int WB1_GLOBAL_TEST_ENABLE; // 0x0224 R/W 0x00000000 WB1 Global Test Enable ++ volatile unsigned int WB1_GLOBAL_TEST_REF_VALUE; // 0x0228 R/W 0x00000000 WB1 Global Test Reference ++ volatile unsigned int WB1_GLOBAL_TEST_CMP_FUNC; // 0x022C R/W 0x00000000 WB1 Global Test Compare Function ++ volatile unsigned int NOTDEFINE2[52]; ++ volatile unsigned int WB2_SOURCE_SELECT; // 0x0300 R/W 0x00000000 WB2 Source Select ++ volatile unsigned int WB2_TARGET_ADDR; // 0x0304 R/W 0x00000000 WB2 Target Addres ++ volatile unsigned int WB2_TARGET_PIXEL_FORMAT; // 0x0308 R/W 0x00000000 WB2 Target Pixel Format ++ volatile unsigned int WB2_TARGET_AA_FORMAT; // 0x030C R/W 0x00000000 WB2 Target AA Format ++ volatile unsigned int WB2_TARGET_LAYOUT; // 0x0310 R/W 0x00000000 WB2 Target Layout ++ volatile unsigned int WB2_TARGET_SCANLINE_LENGTH; // 0x0314 R/W 0x00000000 WB2 Target Scanline length ++ volatile unsigned int WB2_TARGET_FLAGS; // 0x0318 R/W 0x00000000 WB2 Target Flags ++ volatile unsigned int WB2_MRT_ENABLE; // 0x031C R/W 0x00000000 WB2 MRT Enagle ++ volatile unsigned int WB2_MRT_OFFSET; // 0x0320 R/W 0x00000000 WB2 MRT Offset ++ volatile unsigned int WB2_GLOBAL_TEST_ENABLE; // 0x0324 R/W 0x00000000 WB2 Global Test Enable ++ volatile unsigned int WB2_GLOBAL_TEST_REF_VALUE; // 0x0328 R/W 0x00000000 WB2 Global Test Reference ++ volatile unsigned int WB2_GLOBAL_TEST_CMP_FUNC; // 0x032C R/W 0x00000000 WB2 Global Test Compare Function ++ volatile unsigned int NOTDEFINE3[820]; ++ volatile unsigned int VERSION; // 0x1000 R 0xC8070005 Version ++ volatile unsigned int CURRENT_REND_LIST_ADDR; // 0x1004 R/W 0x00000000 Current Renderer List Address ++ volatile unsigned int STATUS; // 0x1008 R/W 0x00000000 Status ++ volatile unsigned int CTRL_MGMT; // 0x100C W N/A Control Management ++ volatile unsigned int INT_RAWSTAT; // 0x1020 R/W 0x00000000 Interrupt Rawstat ++ volatile unsigned int INT_CLEAR; // 0x1024 W N/A Interrupt Clear ++ volatile unsigned int INT_MASK; // 0x1028 RW 0x00001FF Interrupt Mask ++ volatile unsigned int INT_STATUS; // 0x102c R 0x00000000 Interrupt Status ++ volatile unsigned int WRITE_BOUNDARY_ENABLE; // 0x1040 R/W 0x00000000 Write Boundary Enable ++ volatile unsigned int WRITE_BOUNDARY_LOW; // 0x1044 R/W 0x00000000 Write Boundary Low ++ volatile unsigned int WRITE_BOUNDARY_HIGH; // 0x1048 R/W 0x00000000 Write Boundary High ++ volatile unsigned int WRITE_BOUNDARY_ADDRESS; // 0x104C R 0x00000000 Write Boundary Address ++ volatile unsigned int BUS_ERROR_STATUS; // 0x1050 R 0x00000000 Bus Error Status ++ volatile unsigned int WATCHDOG_DISABLE; // 0x1060 R/W 0x00000000 Watchdog Disable ++ volatile unsigned int WATCHDOG_TIMEOUT; // 0x1064 R/W 0x000F4240 Watchdog Timeout ++ volatile unsigned int PERF_CNT_0_ENABLE; // 0x1080 R/W 0x00000000 Performance Counter 0 Enable ++ volatile unsigned int PERF_CNT_0_SRC; // 0x1084 R/W 0x00000000 Performance Counter 0 SRC ++ volatile unsigned int PERF_CNT_0_LIMIT; // 0x1088 R/W 0x00000000 Performance Counter 0 Limit ++ volatile unsigned int PERF_CNT_0_VALUE; // 0x108C R/W 0x00000000 Performance Counter 0 Value ++ volatile unsigned int PERF_CNT_1_ENABLE; // 0x10A0 R/W 0x00000000 Performance Counter 1 Enable ++ volatile unsigned int PERF_CNT_1_SRC; // 0x10A4 R/W 0x00000000 Performance Counter 1 SRC ++ volatile unsigned int PERF_CNT_1_LIMIT; // 0x10A8 R/W 0x00000000 Performance Counter 1 Limit ++ volatile unsigned int PERF_CNT_1_VALUE; // 0x10AC R/W 0x00000000 Performance Counter 1 Value ++}GPUPIXELPROCESSOR,*PGPUPIXELPROCESSOR; ++ ++/******************************************************************************* ++* 5-2. Geometry Processor Register Map Register Define (Base Addr = 0xF0000000) ++********************************************************************************/ ++//#define HwGEOMETRYPROCESSOR_BASE *(volatile unsigned long *)0xF0002000 ++typedef struct _GPUGEOMETRYPROCESSOR{ ++ volatile unsigned int CONTR_REG_VSCL_START_ADDR; // 0x2000 R/W 0x00000000 Control Register VSCL Start Address ++ volatile unsigned int CONTR_REG_VSCL_END_ADDR; // 0x2004 R/W 0x00000000 Control Register VSCL End Address ++ volatile unsigned int CONTR_REG_PLBCL_START_ADDR; // 0x2008 R/W 0x00000000 Control Register PLBCL Start Address ++ volatile unsigned int CONTR_REG_PLBCL_END_ADDR; // 0x200C R/W 0x00000000 Control Register PLBCL End Address ++ volatile unsigned int CONTR_REG_PLB_ALLOC_START_ADDR; // 0x2010 R/W 0x00000000 Control Register PLB Allocate Start Address ++ volatile unsigned int CONTR_REG_PLB_ALLOC_END_ADDR; // 0x2014 R/W 0x00000000 Control Register PLB Allocate End Address ++ volatile unsigned int CONTR_REG_CMD; // 0x2020 W N/A Control Register Command ++ volatile unsigned int CONTR_REG_INT_RAWSTAT; // 0x2024 R/W 0x00000000 Control Register Interrupt Rawstat ++ volatile unsigned int CONTR_REG_INT_CLEAR; // 0x2028 W N/A Control Register Interrupt Clear ++ volatile unsigned int CONTR_REG_INT_MASK; // 0x202C R/W 0x00000000 Control Register Interrupt Mask ++ volatile unsigned int CONTR_REG_INT_STAT; // 0x2030 R 0x00000000 Control Register Interrupt Status ++ volatile unsigned int CONTR_REG_WRITE_BOUND_LOW; // 0x2034 R/W 0x00000000 Control Register Write Boundary Low ++ volatile unsigned int CONTR_REG_WRITE_BOUND_HIGH; // 0x2038 R/W 0xFFFFFF00 Control Register Write Boundary High ++ volatile unsigned int CONTR_REG_PERF_CNT_0_ENABLE; // 0x203C R/W 0x00000000 Control Register Performance Counter 0 Enable ++ volatile unsigned int CONTR_REG_PERF_CNT_1_ENABLE; // 0x2040 R/W 0x00000000 Control Register Performance Counter 1 Enable ++ volatile unsigned int CONTR_REG_PERF_CNT_0_SRC; // 0x2044 R/W 0x00000000 Control Register Performance Counter 0 Source ++ volatile unsigned int CONTR_REG_PERF_CNT_1_SRC; // 0x2048 R/W 0x00000000 Control Register Performance Counter 1 Source ++ volatile unsigned int CONTR_REG_PERF_CNT_0_VAL; // 0x204C R 0x00000000 Control Register Performance Counter 0 Value ++ volatile unsigned int CONTR_REG_PERF_CNT_1_VAL; // 0x2050 R 0x00000000 Control Register Performance Counter 1 Value ++ volatile unsigned int CONTR_REG_PERF_CNT_0_LIMIT; // 0x2054 R/W 0x00000000 Control Register Performance Counter 0 Limit ++ volatile unsigned int CONTR_REG_PERF_CNT_1_LIMIT; // 0x2058 R/W 0x00000000 Control Register Performance Counter 1 Limit ++ volatile unsigned int CONTR_REG_STATUS; // 0x2068 R 0x00000000 Control Register Status ++ volatile unsigned int CONTR_REG_VERSION; // 0x206C R 0x0A070005 Control Register VERSION ++ volatile unsigned int CONTR_REG_VSCL_INITIAL_ADDR; // 0x2080 R 0x00000000 Control Register VSCL Initial Address ++ volatile unsigned int CONTR_REG_PLBCL_INITIAL_ADDR; // 0x2084 R 0x00000000 Control Register PLBCL Initial Address ++ volatile unsigned int CONTR_REG_WRITE_BOUNDARY_ERROR_ADDR;// 0x2088 R 0x00000000 Control Register Write Error Address ++ volatile unsigned int CONTR_REG_AXI_BUS_ERROR_STAT; // 0x2094 R 0x00000000 Control AXI Bus Error Status ++ volatile unsigned int CONTR_REG_WATCHDOG_DISABLE; // 0x20A0 R/W 0x00000000 Control Register Watchdog Disable ++ volatile unsigned int CONTR_REG_WATCHDOG_TIMEOUT; // 0x20A4 R/W 0x000F4240 Control Register Watchdog Timeout ++}GPUGEOMETRYPROCESSOR, *PGPUGEOMETRYPROCESSOR; ++ ++ ++// MaliGP2 PLB Configuration Register Map ++//#define HwPLBCFG_BASE *(volatile unsigned long*)0xFFFFFFFF ++typedef struct _GPUPLBCFG{ ++ volatile unsigned char PLB_CONF_REG_VERTEX_ARRAY_ADDR; // 0x0100 W 0x00000000 PLB Configuration Register Vertex Array Address ++ volatile unsigned char PLB_CONF_REG_INDEX_ARRAY_ADDR; // 0x0101 W 0x00000000 PLB Configuration Register Index Array Address ++ volatile unsigned char PLB_CONF_REG_POINT_SIZE_ADDR; // 0x0102 W 0x00000000 PLB Configuration Register Point Size Address ++ volatile unsigned char PLB_CONF_REG_HEAP_START_ADDR; // 0x0103 W 0x00000000 PLB Configuration Register Heap Start Address ++ volatile unsigned char PLB_CONF_REG_HEAP_END_ADDR; // 0x0104 W 0x00000000 PLB Configuration Register Heap End Address ++ volatile unsigned char PLB_CONF_REG_VIEWPORT_TO; // 0x0105 W 0x00000000 PLB Configuration Register Viewport Top ++ volatile unsigned char PLB_CONF_REG_VIEWPORT_BOTTOM; // 0x0106 W 0x00000000 PLB Configuration Register Viewport Bottom ++ volatile unsigned char PLB_CONF_REG_VIEWPORT_LEFT; // 0x0107 W 0x00000000 PLB Configuration Register Viewport Left ++ volatile unsigned char PLB_CONF_REG_VIEWPORT_RIGHT; // 0x0108 W 0x00000000 PLB Configuration Register Viewport Right ++ volatile unsigned char PLB_CONF_REG_SCREENSIZE; // 0x0109 W 0x00000000 PLB Configuration Register Screen Size ++ volatile unsigned char PLB_CONF_REG_OFFSET_VERTEX_ARRAY;// 0x010A W 0x00000000 PLB Configuration Register Offset Vertex Array ++ volatile unsigned char PLB_CONF_REG_PARAMS; // 0x010B W 0x00000000 PLB Configuration Register Parameters ++ volatile unsigned char PLB_CONF_REG_TILE_SIZE; // 0x010C W 0x00000000 PLB Configuration Register Tile Size ++ volatile unsigned char PLB_CONF_REG_POchar_SIZE; // 0x010D W 0x00000000 PLB Configuration Register Pochar Size ++ volatile unsigned char PLB_CONF_REG_Z_NEAR; // 0x010E W 0x00000000 PLB Configuration Register Z Near ++ volatile unsigned char PLB_CONF_REG_Z_FAR; // 0x010F W 0x3F800000 PLB Configuration Register Z Far ++}GPUPLBCFG, *PGPUPLBCFG; ++ ++ ++// MaliGP2 Vertex Shader Register Map ++//#define HwGPUVERTEXSHADER_BASE *(volatile unsigned long*)0xFFFFFFFF ++typedef union _VSCFGREG1{ ++ //volatile unsigned char VS_CONF_REG_INP_ADDR[32]; // 0x0000-0x001E W 0x00000000 VS Configuration Register Input Address ++ //volatile unsigned char VS_CONF_REG_INP_SPEC[32]; // 0x0001-0x001F W 0x0000003F VS Configuration Register Input Specifier ++ volatile unsigned char ADDR[32]; // 0x0000-0x001E W 0x00000000 VS Configuration Register Input Address ++ volatile unsigned char SPEC[32]; // 0x0001-0x001F W 0x0000003F VS Configuration Register Input Specifier ++}VSCFGREG; ++/* ++typedef union _VSCFGREG2{ ++ volatile unsigned char ADDR[32]; // 0x0020-0x003E W 0x00000000 VS Configuration Register Output Address ++ volatile unsigned char SPEC[32]; // 0x0021-0x003F W 0x0000003F VS Configuration Register Output Specifier ++}VSCFGREG2; ++*/ ++typedef struct _GPUVERTEXSHADER{ ++ VSCFGREG VS_CONF_REG_INP; ++ VSCFGREG VS_CONF_REG_OUTP; ++ volatile unsigned char VS_CONF_REG_PROG_PARAM; // 0x0040 W 0x00000000 VS Configuration Register Program Parameter Create ++ volatile unsigned char VS_CONF_REG_PREFETCH; // 0x0041 W 0x00000000 VS Configuration Register Prefetch ++ volatile unsigned char VS_CONF_REG_OPMOD; // 0x0042 W 0x0F000000 VS Configuration Register OPMOD ++ volatile unsigned char VS_CONF_REG_VERTICES_ALT_STRIDE; // 0x0043 W 0x00000000 VS Configuration Register Vertices Alternative Stride ++ volatile unsigned char VS_CONF_REG_INPUT_ALT_STRIDE_0; // 0x0044 W 0x00000000 VS Configuration Register Input Alternative Stride 0 ++ volatile unsigned char VS_CONF_REG_INPUT_ALT_STRIDE_1; // 0x0045 W 0x00000000 VS Configuration Register Input Alternative Stride 1 ++ volatile unsigned char VS_CONF_REG_INPUT_ALT_STRIDE_2; // 0x0046 W 0x00000000 VS Configuration Register Input Alternative Stride 2 ++ volatile unsigned char VS_CONF_REG_INPUT_ALT_STRIDE_3; // 0x0047 W 0x00000000 VS Configuration Register Input Alternative Stride 3 ++ volatile unsigned char VS_CONF_REG_OUTPUT_ALT_STRIDE_0; // 0x0048 W 0x00000000 VS Configuration Register Output Alternative Stride 0 ++ volatile unsigned char VS_CONF_REG_OUTPUT_ALT_STRIDE_1; // 0x0049 W 0x00000000 VS Configuration Register Output Alternative Stride 1 ++ volatile unsigned char VS_CONF_REG_OUTPUT_ALT_STRIDE_2; // 0x004A W 0x00000000 VS Configuration Register Output Alternative Stride 2 ++ volatile unsigned char VS_CONF_REG_OUTPUT_ALT_STRIDE_3; // 0x004B W 0x00000000 VS Configuration Register Output Alternative Stride 3 ++}GPUVERTEXSHADER, *PGPUVERTEXSHADER; ++ ++ ++/******************************************************************************* ++* 5-3. MMU Configuration Register Define (Base Addr = 0xF0003000) ++********************************************************************************/ ++//#define HwMMUCONFIG_BASE *(volatile unsigned long *)0xF0003000 ++typedef struct _GPUMMUCONFIG{ ++ volatile unsigned int MMU_DTE_ADDR; // 0x3000 R/W 0x00000000 MMU Current Page Table Address ++ volatile unsigned int MMU_STATUS; // 0x3004 R 0x00000018 MMU Status ++ volatile unsigned int MMU_COMMAND; // 0x3008 W N/A MMU Command ++ volatile unsigned int MMU_PAGE_FAULT_ADDR; // 0x300C R 0x00000000 MMU Logical Address of Last Page Fault ++ volatile unsigned int MMU_ZAP_ONE_LINE; // 0x3010 W N/A MMU Zap Cache Line ++ volatile unsigned int MMU_INT_RAWSTA; // 0x3014 R/W 0x00000000 MMU Raw Interrupt Status ++ volatile unsigned int MMU_INT_CLEAR; // 0x3018 W N/A MMU Interrupt Clear ++ volatile unsigned int MMU_INT_MASK; // 0x301C R/W 0x00000000 MMU Interrupt Mask ++ volatile unsigned int MMU_INT_STATUS; // 0x3020 R 0x00000000 MMU Interrup Status ++}GPUMMUCONFIG, *PGPUMMUCONFIG; ++ ++/******************************************************************************* ++* 5-4. GRPBUS Configuration Register Define (Base Addr = 0xF0004000) ++********************************************************************************/ ++//#define HwGRPBUS_BASE *(volatile unsigned long *)0xF0004000 ++typedef struct _GPUGRPBUSCONFIG{ ++ volatile unsigned int GRPBUS_PWRDOWN; // 0x0000 R/W 0x00000000 Graphics bus power down ++ volatile unsigned int GRPBUS_SWRESET; // 0x0004 R/W 0x00000000 Graphics bus software reset ++ volatile unsigned int GRPBUS_MALI_IDLE; // 0x0008 R/W 0x00000002 Mali idle configration ++}GPUGRPBUSCONFIG, *PGPUGRPBUSCONFIG; ++ ++/******************************************************************************* ++* 5-5. GRPBUS BWRAP Register Define (Base Addr = 0xF0005000) ++********************************************************************************/ ++//#define HwGRPBUSBWRAP_BASE *(volatile unsigned long *)0xF0005000 ++typedef struct _GPUGRPBUSBWRAP{ ++ volatile unsigned int GRPBUS_BWRAPCTRL; // 0x0000 R/W 0x00000000 Graphics bus bwrap control ++}GPUGRPBUSBWRAP, *PGPUGRPBUSBWRAP; ++ ++ ++ ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/include/mach/bsp_cfg.h b/arch/arm/mach-tcc8900/include/mach/bsp_cfg.h +new file mode 100644 +index 0000000..9b972a9 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/bsp_cfg.h +@@ -0,0 +1,32 @@ ++/**************************************************************************** ++* FileName : bsp_cfg.h ++* Description : ++**************************************************************************** ++* ++* TCC Version : 1.0 ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************/ ++ ++#ifndef __BSP_CFG_H__ ++#define __BSP_CFG_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++//loglevel option ++#define TC_LOG_OPTION (TC_ERROR | TC_LOG ) ++#define TC_LOG_LEVEL(a) ((TC_LOG_OPTION)&(a)) ++ ++#if defined(_LINUX_) ++# define tc_debug pr_debug ++#endif ++ ++// ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // __BSP_CFG_H__ +diff --git a/arch/arm/mach-tcc8900/include/mach/common.h b/arch/arm/mach-tcc8900/include/mach/common.h +new file mode 100644 +index 0000000..7359670 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/common.h +@@ -0,0 +1,36 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/common.h ++ * ++ * Author: ++ * Created: June 10, 2008 ++ * Description: Header for code common to all Telechips TCC8900/TCC83x machines. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __ARCH_ARM_MACH_TCC8900_COMMON_H ++#define __ARCH_ARM_MACH_TCC8900_COMMON_H ++ ++struct sys_timer; ++ ++extern struct sys_timer tcc8900_timer; ++ ++#endif /* __ARCH_ARM_MACH_TCC8900_COMMON_H */ +diff --git a/arch/arm/mach-tcc8900/include/mach/ddr.h b/arch/arm/mach-tcc8900/include/mach/ddr.h +new file mode 100644 +index 0000000..7895bfe +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/ddr.h +@@ -0,0 +1,95 @@ ++/*************************************************************************************** ++* FileName : ddr2.h ++* Description : TCBOOT DDR Configuration File ++**************************************************************************************** ++* ++* TCC Board Support Package ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************************/ ++ ++ ++#ifndef __DDR_CONFIG_H__ ++#define __DDR_CONFIG_H__ ++ ++/*********************************************************** ++* DRAM config ++* CS BANK CAS_Latency CAS/RAS Size MaxClock PartNumber Vendor ++* [DDR2] ++* DRAM_TYPE1 : 1, 2, 5, 10/13 (16bit x 64 x 2) 128MB, 330Mhz K4T51163QG-HCE6(EVB 0.1) SAMSUNG ++* DRAM_TYPE2 : 1, 2, 6, 10/13 (16bit x 64 x 4) 128MB, 400Mhz H5PS5162FPR S2C- 415A (EVB 1.0), HYNIX ++* H5PS5162FFR S6C-915A HYNIX ++* DRAM_TYPE3 : 1, 3, 5, 10/13 (16bit x 128 x 2) 256MB, 400Mhz K4T1G164QE-HCE7 SAMSUNG ++* 330Mhz K4T1G164QQ-HCE6 SAMSUNG ++* DRAM_TYPE4 : 1, 3, 6, 10/13 (16bit x 128 x 2) 256MB, 400Mhz K4T1G1643QG-HCF7 SAMSUNG ++* ++* [TEST Only] ++* DRAM_TYPE5 : 1, 2, 5, 10/14 (8bit x 64 x 4) 256MB, 330Mhz E5108AG-6E-E ELPIDA ++* DRAM_TYPE6 : 2, 2, 6, 10/13 (16bit x 64 x 4) 256MB, 400Mhz H5PS5162FFR S6C-915A HYNIX ++* [MDDR] ++* DRAM_TYPE7 : 1, 2, 3, 10/13 (16bit x 64 x 2) 128MB, 166Mhz H5MS516DFR J3M-919A HYNIX ++* DRAM_TYPE8 : 1, 2, 3, 10/14 (16bit x 128 x 2) 256MB, 166Mhz H5MS1G62MFP J3M-902A HYNIX ++************************************************************/ ++/*--------------* ++ * DDR Type * ++ *--------------*/ ++//#define DRAM_TYPE1 ++//#define DRAM_TYPE2 ++#define DRAM_TYPE3 ++//#define DRAM_TYPE4 ++//#define DRAM_TYPE5 ++//#define DRAM_TYPE6 ++//#define DRAM_TYPE7 ++//#define DRAM_TYPE8 ++ ++#if defined(DRAM_TYPE1) ++# define DRAM_DDR2 ++# define DRAM_BANK2 ++# define DRAM_CAS5 ++#endif ++ ++#if defined(DRAM_TYPE2) ++# define DRAM_DDR2 ++# define DRAM_BANK2 ++# define DRAM_CAS6 ++#endif ++ ++#if defined(DRAM_TYPE3) ++# define DRAM_DDR2 ++# define DRAM_BANK3 ++# define DRAM_CAS5 ++#endif ++ ++#if defined(DRAM_TYPE4) ++# define DRAM_DDR2 ++# define DRAM_BANK3 ++# define DRAM_CAS6 ++#endif ++ ++#if defined(DRAM_TYPE5) ++# define DRAM_DDR2 ++# define DRAM_BANK2 ++# define DRAM_CAS5 ++#endif ++ ++#if defined(DRAM_TYPE6) ++# define DRAM_DDR2 ++# define DRAM_BANK2 ++# define DRAM_CAS6 ++#endif ++ ++#if defined(DRAM_TYPE7) ++# define DRAM_MDDR ++# define DRAM_BANK2 ++# define DRAM_CAS3 ++#endif ++ ++#if defined(DRAM_TYPE8) ++# define DRAM_MDDR ++# define DRAM_BANK2 ++# define DRAM_CAS3 ++#endif ++ ++#endif /* __DDR_CONFIG_H__ */ ++/************* end of file *************************************************************/ +diff --git a/arch/arm/mach-tcc8900/include/mach/debug-macro.S b/arch/arm/mach-tcc8900/include/mach/debug-macro.S +new file mode 100644 +index 0000000..dccd599 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/debug-macro.S +@@ -0,0 +1,40 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/debug-macro.S ++ * ++ * Based on: linux/arch/arm/kernel/debug.S by Ben Dooks ++ * Author: ++ * Created: February 10, 2009 ++ * Description: Debugging macro include header ++ * ++ * Copyright (C) 1994-1999 Russell King ++ * Copyright (C) 2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++ .macro addruart,rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 @ MMU enabled? ++ moveq \rx, #0xf0000000 @ physical base address ++ movne \rx, #0xf0000000 @ virtual base ++ orr \rx, \rx, #0x00530000 @ debug port UART0 ++ orr \rx, \rx, #0x2000 @ debug port UART0 0xf00532000 ++ .endm ++ ++ .macro senduart,rd,rx ++ strb \rd, [\rx] ++ .endm ++ ++ .macro busyuart,rd,rx ++ .endm ++ ++ .macro waituart,rd,rx ++1001: ++ ldr \rd, [\rx, #0x14] ++ tst \rd, #0x20 ++ ++ beq 1001b ++ .endm +diff --git a/arch/arm/mach-tcc8900/include/mach/dma.h b/arch/arm/mach-tcc8900/include/mach/dma.h +new file mode 100644 +index 0000000..c4c9d3c +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/dma.h +@@ -0,0 +1,27 @@ ++/* ++ * arch/arm/mach-tcc8900/include/mach/dma.h ++ * ++ * Written by ++ * Modified: March 10, 2009 ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/entry-macro.S b/arch/arm/mach-tcc8900/include/mach/entry-macro.S +new file mode 100644 +index 0000000..7ddbfda +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/entry-macro.S +@@ -0,0 +1,66 @@ ++/* ++ * include/asm-arm/arch-tcc8900/entry-macro.S ++ * ++ * Author : ++ * Created: Feb 10, 2009 ++ * Description: Low-level IRQ helper macros for OMAP-based platforms ++ * ++ * Copyright (C) 2009 Telechips ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++#include ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ /* tcc8900 dependent code */ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ldr \base, =0xF0401000 @ load base address of IRQ registers ++ ++ /* A intr */ ++ ldr \irqstat, [\base, #0x50] /* MIRQ0 */ ++ cmp \irqstat, #0 ++ bne 1001f /* jump to check A-intr */ ++ ++ /* B intr */ ++ ldr \irqstat, [\base, #0x54] /* MIRQ1 */ ++ cmp \irqstat, #0 ++ beq 1002f /* jump to exit macro. cannot find the intr number. (something wrong) */ ++ ++ /* get B-intr num */ ++ mov \irqnr, #0 @@ start here B ++1102: ands \tmp, \irqstat, #1 ++ moveq \irqstat, \irqstat, LSR #1 ++ addeq \irqnr, \irqnr, #1 ++ beq 1102b ++ add \irqnr, \irqnr, #32 ++ b 1002f ++ ++ ++ /* get A-intr num */ ++1001: mov \irqnr, #0 @@ start here A ++1101: ands \tmp, \irqstat, #1 ++ moveq \irqstat, \irqstat, LSR #1 ++ addeq \irqnr, \irqnr, #1 ++ beq 1101b ++ @@ work out which irq (if any) we got ++ ++ @@ ADD Register #2 ++ ++ ++1002: /* exit */ ++ @@ exit here, Z flag unset if IRQ ++ .endm ++ ++ .macro irq_prio_table ++ .endm +diff --git a/arch/arm/mach-tcc8900/include/mach/globals.h b/arch/arm/mach-tcc8900/include/mach/globals.h +new file mode 100644 +index 0000000..a98b52e +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/globals.h +@@ -0,0 +1,443 @@ ++/**************************************************************************** ++* FileName : globals.h ++* Description : ++**************************************************************************** ++* ++* TCC Version : 1.0 ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************/ ++ ++//using only global defines, macros.. etc - If you want using this file contact to RYU ++ ++#ifndef __GLOBALS_H__ ++#define __GLOBALS_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++//Log Level ++#define TC_ERROR 0x00000001 ++#define TC_LOG 0x00000002 ++#define TC_TRACE 0x00000004 ++#define TC_DEBUG 0x00000008 ++ ++ //system info ++#define IOCTL_PLATFORM_TYPE (L"PLATFORM_TYPE") ++#define IOCTL_PLATFORM_OEM (L"PLATFORM_OEM") ++ ++//------------------------------------------------------------------------------ ++// Define: IOCTL_PROCESSOR_VENDOR/NAME/CORE ++// ++// Defines the processor information ++// ++ ++#define IOCTL_PROCESSOR_VENDOR (L"Telechips") ++#define IOCTL_PROCESSOR_NAME (L"TCC89X") ++#define IOCTL_PROCESSOR_CORE (L"ARM11") ++ ++//------------------------------------------------------------------------------ ++// ++// Define: IOCTL_PROCESSOR_INSTRUCTION_SET ++// ++// Defines the processor instruction set information ++// ++#define IOCTL_PROCESSOR_INSTRUCTION_SET (0) ++#define IOCTL_PROCESSOR_CLOCK_SPEED 266*1000 ++ ++//macro defines ++/************************************************************************************************ ++* MACRO * ++************************************************************************************************/ ++#ifndef BITSET ++#define BITSET(X, MASK) ( (X) |= (unsigned int)(MASK) ) ++#endif ++#ifndef BITSCLR ++#define BITSCLR(X, SMASK, CMASK) ( (X) = ((((unsigned int)(X)) | ((unsigned int)(SMASK))) & ~((unsigned int)(CMASK))) ) ++#endif ++#ifndef BITCSET ++#define BITCSET(X, CMASK, SMASK) ( (X) = ((((unsigned int)(X)) & ~((unsigned int)(CMASK))) | ((unsigned int)(SMASK))) ) ++#endif ++#ifndef BITCLR ++#define BITCLR(X, MASK) ( (X) &= ~((unsigned int)(MASK)) ) ++#endif ++#ifndef BITXOR ++#define BITXOR(X, MASK) ( (X) ^= (unsigned int)(MASK) ) ++#endif ++#ifndef ISZERO ++#define ISZERO(X, MASK) ( ! (((unsigned int)(X)) & ((unsigned int)(MASK))) ) ++#endif ++ ++#ifndef ENABLE ++#define ENABLE 1 ++#endif ++#ifndef DISABLE ++#define DISABLE 0 ++#endif ++ ++#ifndef ON ++#define ON 1 ++#endif ++#ifndef OFF ++#define OFF 0 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#define HwVMT_SZ(X) (((X)-1)*Hw12) ++ #define SIZE_4GB 32 ++ #define SIZE_2GB 31 ++ #define SIZE_1GB 30 ++ #define SIZE_512MB 29 ++ #define SIZE_256MB 28 ++ #define SIZE_128MB 27 ++ #define SIZE_64MB 26 ++ #define SIZE_32MB 25 ++ #define SIZE_16MB 24 ++ #define SIZE_8MB 23 ++ #define SIZE_4MB 22 ++ #define SIZE_2MB 21 ++ #define SIZE_1MB 20 ++ #define HwVMT_REGION_AP_ALL (Hw11+Hw10) ++ #define HwVMT_DOMAIN(X) ((X)*Hw5) ++ #define HwVMT_REGION_EN Hw9 // Region Enable Register ++ #define HwVMT_CACHE_ON Hw3 // Cacheable Register ++ #define HwVMT_CACHE_OFF HwZERO ++ #define HwVMT_BUFF_ON Hw2 // Bufferable Register ++ #define HwVMT_BUFF_OFF HwZERO ++ ++ #define HwVMT_REGION0_EN Hw9 // Region Enable Register ++ #define HwVMT_REGION0_CA Hw3 // Cacheable Register ++ #define HwVMT_REGION0_BU Hw2 // Bufferable Register ++ ++/************************************************************************************************ ++* ENUM * ++************************************************************************************************/ ++/***************************************CLOCK****************************************************/ ++ enum ++ { ++ IDLE_PRIORITY = 0, // Don't Return IDLE_PRIORITY ++ LOW_PRIORITY, ++ MID_PRIORITY, ++ HIGH_PRIORITY, ++ MAX_PRIORITY, ++ ++ CLOCK_PRIORITY_NUM, ++ //}stCKC_PRIORITY; ++ }; ++ ++//CKC Enum ++ enum{ /* CLKCTRL Clock Source */ ++ DIRECTPLL0=0, ++ DIRECTPLL1, ++ DIRECTPLL2, ++ DIRECTPLL3, ++ DIRECTXIN, ++ DIVIDPLL0, ++ DIVIDPLL1, ++ DIRECTXTIN, ++ }; ++ ++ enum{ /* Peri. Clock Source */ ++ PCDIRECTPLL0=0, ++ PCDIRECTPLL1, ++ PCDIRECTPLL2, ++ PCDIRECTPLL3, ++ PCDIRECTXIN, ++ PCDIVIDPLL0, ++ PCDIVIDPLL1, ++ PCDIVIDPLL2, ++ PCDIVIDPLL3, ++ PCDIRECTXTIN, ++ PCEXITERNAL, // 10 ++ PCDIVIDXIN_HDMITMDS, ++ PCDIVIDXTIN_HDMIPCLK, ++ PCHDMI, // 27Mhz ++ PCSATA, // 25Mhz ++ PCUSBPHY, // 48Mhz ++ }; ++ ++ enum{ /* Peri. Clock Source */ ++ PDCO = 0, ++ PDIVIDER, ++ }; ++ ++ enum {/* Peri. Name */ ++ PERI_TCX = 0, ++ PERI_TCT, ++ PERI_TCZ, ++ PERI_LCD0, ++ PERI_LCD1, ++ PERI_LCDSI, ++ PERI_CIFMC, ++ PERI_CIFSC, ++ PERI_OUT0, ++ PERI_OUT1, ++ PERI_HDMI, ++ PERI_USB11H, ++ PERI_SDMMC0, ++ PERI_MSTICK, ++ PERI_I2C, ++ PERI_UART0, ++ PERI_UART1, ++ PERI_UART2, ++ PERI_UART3, ++ PERI_UART4, ++ PERI_UART5, ++ PERI_GPSB0, ++ PERI_GPSB1, ++ PERI_GPSB2, ++ PERI_GPSB3, ++ PERI_GPSB4, ++ PERI_GPSB5, ++ PERI_ADC, ++ PERI_SPDIF, ++ PERI_EHI0, ++ PERI_EHI1, ++ PERI_AUD, ++ PERI_CAN, ++ PERI_Reserved0, ++ PERI_SDMMC1, ++ PERI_Reserved1, ++ PERI_DAI, ++ }; ++ ++ enum{/*for PWROFF Register*/ ++ PMU_VIDEODAC = 0, ++ PMU_HDMIPHY, ++ PMU_LVDSPHY, ++ PMU_USBNANOPHY, ++ PMU_SATAPHY, ++ PMU_MEMORYBUS, ++ PMU_VIDEOBUS, ++ PMU_DDIBUS, ++ PMU_GRAPHICBUS, ++ PMU_IOBUS, ++ }; ++ ++ enum{/* for SWRESET */ ++ RESET_CPU = 0, ++ RESET_DDIBUS, ++ RESET_MEMBUS, ++ RESET_GRAPBUS, ++ RESET_IOBUS, ++ RESET_VIDEOBUS, ++ RESET_VIDEOCORE, ++ RESET_SMU, ++ }; ++ ++ enum {/* clock divider (div+1) */ ++ CLKDIV0 = 0, ++ CLKDIV2 , ++ CLKDIV3 , ++ CLKDIV4 , ++ CLKDIVNONCHANGE, ++ }; ++ ++ enum { ++ CLKCTRL0 = 0, //FCORE_CPU ++ CLKCTRL1, //FBUS_DDI ++ CLKCTRL2, //FMEM_BUS ++ CLKCTRL3, //FBUS_GRP ++ CLKCTRL4, //FBUS_IOB ++ CLKCTRL5, //FBUS_VBUS ++ CLKCTRL6, //FBUS_VCODEC ++ CLKCTRL7, //FBUS_SMU ++ }; ++ ++ enum { ++ NORMAL_MD = 0, ++ DYNAMIC_MD, ++ }; ++ ++ enum { ++ RB_USB11H = 0, ++ RB_USB20OTG, ++ RB_IDECONTROLLER, ++ RB_DMACONTROLLER , ++ RB_SDMMCCONTROLLER , ++ RB_SATAHCONTROLLER , ++ RB_MEMORYSTICKCONTROLLER , ++ RB_I2CCONTROLLER , ++ RB_NFCCONTROLLER , ++ RB_EXTHCONTROLLER0 , ++ RB_EXTHCONTROLLER1 , //10 ++ RB_UARTCONTROLLER0 , ++ RB_UARTCONTROLLER1 , ++ RB_UARTCONTROLLER2 , ++ RB_UARTCONTROLLER3 , ++ RB_UARTCONTROLLER4 , ++ RB_UARTCONTROLLER5 , ++ RB_GPSBCONTROLLER0 , ++ RB_GPSBCONTROLLER1 , ++ RB_GPSBCONTROLLER2 , ++ RB_GPSBCONTROLLER3 , //20 ++ RB_GPSBCONTROLLER4 , ++ RB_GPSBCONTROLLER5 , ++ RB_DAICDIFCONTROLLER , ++ RB_ECCCONTROLLER , ++ RB_SPDIFTXCONTROLLER, ++ RB_RTCCONTROLLER , ++ RB_TSADCCONTROLLER, ++ RB_GPSCONTROLLER , ++ RB_RESERVEDCONTROLLER, ++ RB_CANCONTROLLER, ++ RB_ADMACONTROLLER, // 31 ++ ++ RB_MPE_FECCONTROLLER, ++ RB_TSIFCONTROLLER, ++ RB_SRAMCONTROLLER, ++ ++ RB_ALLPERIPERALS, ++ ++ }; ++ ++ enum{ /* Fmbus Step */ ++ FMBUS_141Mhz=0, ++ FMBUS_145Mhz, ++ FMBUS_150Mhz, ++ FMBUS_160Mhz, ++ FMBUS_170Mhz, ++ FMBUS_180Mhz, ++ FMBUS_190Mhz, ++ FMBUS_200Mhz, ++ FMBUS_210Mhz, ++ FMBUS_220Mhz, ++ FMBUS_230Mhz, ++ FMBUS_240Mhz, ++ FMBUS_250Mhz, ++ FMBUS_260Mhz, ++ FMBUS_270Mhz, ++ FMBUS_280Mhz, ++ FMBUS_290Mhz, ++ FMBUS_300Mhz, ++ FMBUS_312Mhz, ++ FMBUS_320Mhz, ++ FMBUS_330Mhz, ++ ++ FMBUS_STEPMAX, ++ }; ++ ++ enum{ /* ddi Power Down Field */ ++ DDIPWDN_CIF = 0, ++ DDIPWDN_VIQE, ++ DDIPWDN_LCDC0, ++ DDIPWDN_LCDC1, ++ DDIPWDN_LCDSI, ++ DDIPWDN_MSCL0, ++ DDIPWDN_MSCL1, ++ DDIPWDN_DDIC, ++ DDIPWDN_HDMI, ++ DDIPWDN_STEPMAX, ++ }; ++ ++ enum{ /* ETC Power Down Field */ ++ ETC_USBPHYOFF = 0, ++ ETC_USBPHYON, ++ ETC_3DGPUOFF, ++ ETC_3DGPUON, ++ ETC_OVERLAYMIXEROFF, ++ ETC_OVERLAYMIXERON , ++ ++ ETC_STEPMAX, ++ ++ }; ++ ++#define ETCMASK_USBPHYOFF 0x00000001 ++#define ETCMASK_USBPHYON 0x00000002 ++#define ETCMASK_3DGPUOFF 0x00000004 ++#define ETCMASK_3DGPUON 0x00000008 ++#define ETCMASK_OVERLAYMIXEROFF 0x00000010 ++#define ETCMASK_OVERLAYMIXERON 0x00000020 ++ ++/***************************************Interrup****************************************************/ ++enum { ++ IRQ_TC0 =0, // 0 0x0 Timer 0 interrupt enable ++ IRQ_TC1, // 1 0x0 Timer 1 interrupt enable ++ IRQ_SMUI2C, // 2 0x0 SMU_I2C interrupt enable ++ IRQ_EI0, // 3 0x0 External interrupt 0 enable ++ IRQ_EI1, // 4 0x0 External interrupt 1 enable ++ IRQ_EI2, // 5 0x0 External interrupt 2 enable ++ IRQ_EI3, // 6 0x0 External interrupt 3 enable ++ IRQ_EI4, // 7 0x0 External interrupt 4 enable ++ IRQ_EI5, // 8 0x0 External interrupt 5 enable ++ IRQ_EI6, // 9 0x0 External interrupt 6 enable ++ IRQ_EI7, // 10 0x0 External interrupt 7 enable ++ IRQ_EI8, // 11 0x0 External interrupt 8 enable ++ IRQ_EI9, // 12 0x0 External interrupt 9 enable ++ IRQ_EI10, // 13 0x0 External interrupt 10 enable ++ IRQ_EI11, // 14 0x0 External interrupt 11 enable ++ IRQ_SC0, // 15 0x0 Mem-to-Mem scaler 0 interrupt enable ++ IRQ_SC1, // 16 0x0 Mem-to-Mem scaler 0 interrupt enable ++ IRQ_CAM, // 17 0x0 Camera interrupt enable ++ IRQ_LCD0, // 18 0x0 LCD controller 0 interrupt enable ++ IRQ_LCD1, // 19 0x0 LCD controller 1 interrupt enable ++ IRQ_VIPET, // 20 0x0 VIPET controller interrupt enable Note: the interrupt request signal is active low. 21 JPGE RW 0x0 JPEG Encoder interrupt enable ++ IRQ_JPGE, // 21 0x0 JPEG Decoder interrupt enable ++ IRQ_JPGD, // 22 0x0 JPEG Decoder interrupt enable ++ IRQ_VCDC, // 23 0x0 Video CODEC interrupt enable ++ IRQ_3DPP, // 24 0x0 3D Pixel Processor interrupt enable ++ IRQ_3DGP, // 25 0x0 3D Geometry Processor interrupt enable ++ IRQ_3DMMU, // 26 0x0 3D MMU interrupt enable ++ IRQ_G2D, // 27 0x0 Graphic Engine 2D Hardware Interrupt Enable ++ IRQ_TSADC, // 28 0x0 TSADC interrupt enable ++ IRQ_DMA, // 29 0x0 DMA controller interrupt enable ++ IRQ_ECC, // 30 0x0 ECC interrupt enable ++ IRQ_EHI0, // 31 0x0 External interrupt 0 enable ++ IRQ_EHI1, // 32 0x0 External interrupt 1 enable ++ IRQ_CAN, // 33 0x0 CAN interrupt enable ++ IRQ_HDMI, // 34 0x0 HDMI interrupt enable ++ IRQ_SATA, // 35 0x0 SATA Host interrupt enable ++ IRQ_GPSB, // 36 0x0 GPSB Interrupt Enable ++ IRQ_HDD, // 37 0x0 HDD controller interrupt enable ++ IRQ_I2C, // 38 0x0 I2C interrupt enable ++ IRQ_MPEFEC, // 39 0x0 MPEFEC interrupt enable ++ IRQ_MS, // 40 0x0 Memory Stick interrupt enable ++ IRQ_NFC, // 41 0x0 Nand flash controller interrupt enable ++ IRQ_RMT, // 42 0x0 Remote Control interrupt enable ++ IRQ_RTC, // 43 0x0 RTC interrupt enable ++ IRQ_SD0, // 44 0x0 SD/MMC 0 interrupt enable ++ IRQ_SD1, // 45 0x0 SD/MMC 1 interrupt enable ++ IRQ_SPDTX, // 46 0x0 SPDIF transmitter interrupt enable ++ IRQ_UART, // 47 0x0 UART interrupt enable ++ IRQ_UOTG, // 48 0x0 USB 2.0 OTG interrupt enable ++ IRQ_U11H, // 49 0x0 USB 1.1 host interrupt enable ++ IRQ_GPS0, // 50 0x0 GPS RTC expired interrupt enable ++ IRQ_GPS1, // 51 0x0 GPS TCXO expired interrupt enable ++ IRQ_GPS2, // 52 0x0 GPS AGPS interrupt enable ++ IRQ_TSIF0, // 53 0x0 TS interface 0 interrupt enable ++ IRQ_TSIF1, // 54 0x0 TS interface 1 interrupt enable ++ IRQ_CDRX, // 55 0x0 CDIF receive interrupt enable ++ IRQ_DAIRX, // 56 0x0 DAI receive interrupt enable ++ IRQ_DAITX, // 57 0x0 DAI transmit interrupt enable ++ IRQ_ADMA, // 58 0x0 AUDIO DMA interrupt enable ++ IRQ_AUDIO, // 59 0x0 AUDIO interrupt enable ++ IRQ_APMU, // 60 0x0 ARM System Metrics interrupt enable Note: the interrupt request signal is active low. ++ IRQ_AIRQ, // 61 0x0 Non secure ARM DMA interrupt enable Note: the interrupt request signal is active low. ++ IRQ_ASIRQ, // 62 0x0 Secure ARM DMA select interrupt enable Note: the interrupt request signal is active low. ++ IRQ_AEIRQ, // 63 0x0 Not maskable error ARM DMA interrupt enable Note: the interrupt request signal is active low. ++}; ++ ++typedef struct _rtctime { ++ unsigned int wYear; ++ unsigned int wMonth; ++ unsigned int wDayOfWeek; ++ unsigned int wDay; ++ unsigned int wHour; ++ unsigned int wMinute; ++ unsigned int wSecond; ++ unsigned int wMilliseconds; ++} rtctime; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // __GLOBALS_H__ +diff --git a/arch/arm/mach-tcc8900/include/mach/gpio.h b/arch/arm/mach-tcc8900/include/mach/gpio.h +new file mode 100644 +index 0000000..f973bac +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/gpio.h +@@ -0,0 +1,711 @@ ++/* ++ * arch/arm/mach-tcc8900/include/mach/gpio.h ++ * ++ * Written by ++ * Modified: March 10, 2009 ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include ++#include ++#include ++ ++/* configure GPIO ports A..F */ ++#define TCC_GPIOREG(x) ((x) + HWGPIO_BASE) ++ ++/* GPIO */ ++#define TCC_GPIONO(bank,offset) ((bank) + (offset)) ++ ++#define TCC_GPIO_BANKA (32*0) ++#define TCC_GPIO_BANKB (32*1) ++#define TCC_GPIO_BANKC (32*2) ++#define TCC_GPIO_BANKD (32*3) ++#define TCC_GPIO_BANKE (32*4) ++#define TCC_GPIO_BANKF (32*5) ++ ++#define TCC_GPIO_INPUT (0) ++#define TCC_GPIO_OUTPUT (1) ++#define TCC_GPIO_BASE(pin) ((pin & ~31) >> 5) ++#define TCC_GPIO_OFFSET(pin) (pin & 31) ++ ++/* GPA : 16 in/out port */ ++#define TCC_GPADAT TCC_GPIOREG(0x00) ++#define TCC_GPAEN TCC_GPIOREG(0x04) ++#define TCC_GPASET TCC_GPIOREG(0x08) ++#define TCC_GPACLR TCC_GPIOREG(0x0C) ++#define TCC_GPAXOR TCC_GPIOREG(0x10) ++#define TCC_GPACD0 TCC_GPIOREG(0x14) ++#define TCC_GPACD1 TCC_GPIOREG(0x18) ++#define TCC_GPAPD0 TCC_GPIOREG(0x1C) ++#define TCC_GPAPD1 TCC_GPIOREG(0x20) ++#define TCC_GPAFN0 TCC_GPIOREG(0x24) ++#define TCC_GPAFN1 TCC_GPIOREG(0x28) ++#define TCC_GPAFN2 TCC_GPIOREG(0x2C) ++#define TCC_GPAFN3 TCC_GPIOREG(0x30) ++ ++#define TCC_GPA0 TCC_GPIONO(TCC_GPIO_BANKA, 0) ++#define TCC_GPA0_GPIO (0) ++#define TCC_GPA0_SCL0 (1) ++ ++#define TCC_GPA1 TCC_GPIONO(TCC_GPIO_BANKA, 1) ++#define TCC_GPA1_GPIO (0) ++#define TCC_GPA1_SDA0 (1) ++ ++#define TCC_GPA2 TCC_GPIONO(TCC_GPIO_BANKA, 2) ++#define TCC_GPA2_GPIO (0) ++#define TCC_GPA2_CLK_OUT0 (1) ++ ++#define TCC_GPA3 TCC_GPIONO(TCC_GPIO_BANKA, 3) ++#define TCC_GPA3_GPIO (0) ++#define TCC_GPA3_CLK_OUT1 (1) ++ ++#define TCC_GPA4 TCC_GPIONO(TCC_GPIO_BANKA, 4) ++#define TCC_GPA4_GPIO (0) ++#define TCC_GPA4_WDTRSTO (1) ++#define TCC_GPA4_TCO0 (2) ++ ++#define TCC_GPA5 TCC_GPIONO(TCC_GPIO_BANKA, 5) ++#define TCC_GPA5_GPIO (0) ++#define TCC_GPA5_IRDI (1) ++#define TCC_GPA5_TCO1 (2) ++ ++#define TCC_GPA6 TCC_GPIONO(TCC_GPIO_BANKA, 6) ++#define TCC_GPA6_GPIO (0) ++#define TCC_GPA6_HDMI_CECO (1) ++#define TCC_GPA6_TCO2 (2) ++#define TCC_GPA6_EDIXA19 (6) ++ ++#define TCC_GPA7 TCC_GPIONO(TCC_GPIO_BANKA, 7) ++#define TCC_GPA7_GPIO (0) ++#define TCC_GPA7_HDMI_CECI (1) ++#define TCC_GPA7_TCO3 (2) ++#define TCC_GPA7_EDIXA20 (6) ++ ++#define TCC_GPA8 TCC_GPIONO(TCC_GPIO_BANKA, 8) ++#define TCC_GPA8_GPIO (0) ++#define TCC_GPA8_SCL1 (1) ++ ++#define TCC_GPA9 TCC_GPIONO(TCC_GPIO_BANKA, 9) ++#define TCC_GPA9_GPIO (0) ++#define TCC_GPA9_SCL1 (1) ++ ++#define TCC_GPA10 TCC_GPIONO(TCC_GPIO_BANKA, 10) ++#define TCC_GPA10_GPIO (0) ++#define TCC_GPA10_CBCLK0 (1) ++#define TCC_GPA10_CBCLK1 (2) ++ ++#define TCC_GPA11 TCC_GPIONO(TCC_GPIO_BANKA, 11) ++#define TCC_GPA11_GPIO (0) ++#define TCC_GPA11_CLRCK0 (1) ++#define TCC_GPA11_CLRCK1 (2) ++ ++#define TCC_GPA12 TCC_GPIONO(TCC_GPIO_BANKA, 12) ++#define TCC_GPA12_GPIO (0) ++#define TCC_GPA12_CDATA0 (1) ++#define TCC_GPA12_CDATA1 (2) ++ ++#define TCC_GPA13 TCC_GPIONO(TCC_GPIO_BANKA, 13) ++#define TCC_GPA13_GPIO (0) ++#define TCC_GPA13_EXTCLK1 (1) ++ ++#define TCC_GPA14 TCC_GPIONO(TCC_GPIO_BANKA, 14) ++#define TCC_GPA14_GPIO (0) ++#define TCC_GPA14_HDMI_HPD (1) ++#define TCC_GPA14_TCO4 (2) ++ ++#define TCC_GPA15 TCC_GPIONO(TCC_GPIO_BANKA, 15) ++#define TCC_GPA15_GPIO (0) ++#define TCC_GPA15_UTM_DRVVBUS (1) ++#define TCC_GPA15_TCO5 (2) ++ ++/* GPB : 32 in/out port */ ++#define TCC_GPBDAT TCC_GPIOREG(0x40) ++#define TCC_GPBEN TCC_GPIOREG(0x44) ++#define TCC_GPBSET TCC_GPIOREG(0x48) ++#define TCC_GPBCLR TCC_GPIOREG(0x4C) ++#define TCC_GPBXOR TCC_GPIOREG(0x50) ++#define TCC_GPBCD0 TCC_GPIOREG(0x54) ++#define TCC_GPBCD1 TCC_GPIOREG(0x58) ++#define TCC_GPBPD0 TCC_GPIOREG(0x5C) ++#define TCC_GPBPD1 TCC_GPIOREG(0x60) ++#define TCC_GPBFN0 TCC_GPIOREG(0x64) ++#define TCC_GPBFN1 TCC_GPIOREG(0x68) ++#define TCC_GPBFN2 TCC_GPIOREG(0x6C) ++#define TCC_GPBFN3 TCC_GPIOREG(0x70) ++ ++#define TCC_GPB0 TCC_GPIONO(TCC_GPIO_BANKB, 0) ++#define TCC_GPB0_GPIO (0) ++#define TCC_GPB0_EDIXD8 (1) ++#define TCC_GPB0_SD_D0_5 (2) ++#define TCC_GPB0_MS_D0_5 (3) ++ ++#define TCC_GPB1 TCC_GPIONO(TCC_GPIO_BANKB, 1) ++#define TCC_GPB1_GPIO (0) ++#define TCC_GPB1_EDIXD9 (1) ++#define TCC_GPB1_SD_D1_5 (2) ++#define TCC_GPB1_MS_D1_5 (3) ++ ++#define TCC_GPB2 TCC_GPIONO(TCC_GPIO_BANKB, 2) ++#define TCC_GPB2_GPIO (0) ++#define TCC_GPB2_EDIXD10 (1) ++#define TCC_GPB2_SD_D2_5 (2) ++#define TCC_GPB2_MS_D2_5 (3) ++ ++#define TCC_GPB3 TCC_GPIONO(TCC_GPIO_BANKB, 3) ++#define TCC_GPB3_GPIO (0) ++#define TCC_GPB3_EDIXD11 (1) ++#define TCC_GPB3_SD_D3_5 (2) ++#define TCC_GPB3_MS_D3_5 (3) ++ ++#define TCC_GPB4 TCC_GPIONO(TCC_GPIO_BANKB, 4) ++#define TCC_GPB4_GPIO (0) ++#define TCC_GPB4_EDIXD4 (1) ++#define TCC_GPB4_SD_D4_5 (2) ++#define TCC_GPB4_MS_D4_5 (3) ++ ++#define TCC_GPB5 TCC_GPIONO(TCC_GPIO_BANKB, 5) ++#define TCC_GPB5_GPIO (0) ++ ++#define TCC_GPB6 TCC_GPIONO(TCC_GPIO_BANKB, 6) ++#define TCC_GPB6_GPIO (0) ++ ++#define TCC_GPB7 TCC_GPIONO(TCC_GPIO_BANKB, 7) ++#define TCC_GPB7_GPIO (0) ++ ++#define TCC_GPB8 TCC_GPIONO(TCC_GPIO_BANKB, 8) ++#define TCC_GPB8_GPIO (0) ++ ++#define TCC_GPB9 TCC_GPIONO(TCC_GPIO_BANKB, 9) ++#define TCC_GPB9_GPIO (0) ++ ++#define TCC_GPB10 TCC_GPIONO(TCC_GPIO_BANKB, 10) ++#define TCC_GPB10_GPIO (0) ++ ++#define TCC_GPB11 TCC_GPIONO(TCC_GPIO_BANKB, 11) ++#define TCC_GPB11_GPIO (0) ++ ++#define TCC_GPB12 TCC_GPIONO(TCC_GPIO_BANKB, 12) ++#define TCC_GPB12_GPIO (0) ++ ++#define TCC_GPB13 TCC_GPIONO(TCC_GPIO_BANKB, 13) ++#define TCC_GPB13_GPIO (0) ++ ++#define TCC_GPB14 TCC_GPIONO(TCC_GPIO_BANKB, 14) ++#define TCC_GPB14_GPIO (0) ++ ++#define TCC_GPB15 TCC_GPIONO(TCC_GPIO_BANKB, 15) ++#define TCC_GPB15_GPIO (0) ++ ++#define TCC_GPB16 TCC_GPIONO(TCC_GPIO_BANKB, 16) ++#define TCC_GPB16_GPIO (0) ++ ++#define TCC_GPB17 TCC_GPIONO(TCC_GPIO_BANKB, 17) ++#define TCC_GPB17_GPIO (0) ++ ++#define TCC_GPB18 TCC_GPIONO(TCC_GPIO_BANKB, 18) ++#define TCC_GPB18_GPIO (0) ++ ++#define TCC_GPB19 TCC_GPIONO(TCC_GPIO_BANKB, 19) ++#define TCC_GPB19_GPIO (0) ++ ++#define TCC_GPB20 TCC_GPIONO(TCC_GPIO_BANKB, 20) ++#define TCC_GPB20_GPIO (0) ++ ++#define TCC_GPB21 TCC_GPIONO(TCC_GPIO_BANKB, 21) ++#define TCC_GPB21_GPIO (0) ++ ++#define TCC_GPB22 TCC_GPIONO(TCC_GPIO_BANKB, 22) ++#define TCC_GPB22_GPIO (0) ++ ++#define TCC_GPB23 TCC_GPIONO(TCC_GPIO_BANKB, 23) ++#define TCC_GPB23_GPIO (0) ++ ++#define TCC_GPB24 TCC_GPIONO(TCC_GPIO_BANKB, 24) ++#define TCC_GPB24_GPIO (0) ++ ++#define TCC_GPB25 TCC_GPIONO(TCC_GPIO_BANKB, 25) ++#define TCC_GPB25_GPIO (0) ++ ++#define TCC_GPB26 TCC_GPIONO(TCC_GPIO_BANKB, 26) ++#define TCC_GPB26_GPIO (0) ++ ++#define TCC_GPB27 TCC_GPIONO(TCC_GPIO_BANKB, 27) ++#define TCC_GPB27_GPIO (0) ++ ++#define TCC_GPB28 TCC_GPIONO(TCC_GPIO_BANKB, 28) ++#define TCC_GPB28_GPIO (0) ++ ++#define TCC_GPB29 TCC_GPIONO(TCC_GPIO_BANKB, 29) ++#define TCC_GPB29_GPIO (0) ++ ++#define TCC_GPB30 TCC_GPIONO(TCC_GPIO_BANKB, 30) ++#define TCC_GPB30_GPIO (0) ++ ++#define TCC_GPB31 TCC_GPIONO(TCC_GPIO_BANKB, 31) ++#define TCC_GPB31_GPIO (0) ++ ++/* GPC : 32 in/out port */ ++#define TCC_GPCDAT TCC_GPIOREG(0x80) ++#define TCC_GPCEN TCC_GPIOREG(0x84) ++#define TCC_GPCSET TCC_GPIOREG(0x88) ++#define TCC_GPCCLR TCC_GPIOREG(0x8C) ++#define TCC_GPCXOR TCC_GPIOREG(0x90) ++#define TCC_GPCCD0 TCC_GPIOREG(0x94) ++#define TCC_GPCCD1 TCC_GPIOREG(0x98) ++#define TCC_GPCPD0 TCC_GPIOREG(0x9C) ++#define TCC_GPCPD1 TCC_GPIOREG(0xA0) ++#define TCC_GPCFN0 TCC_GPIOREG(0xA4) ++#define TCC_GPCFN1 TCC_GPIOREG(0xA8) ++#define TCC_GPCFN2 TCC_GPIOREG(0xAC) ++#define TCC_GPCFN3 TCC_GPIOREG(0xB0) ++ ++#define TCC_GPC0 TCC_GPIONO(TCC_GPIO_BANKC, 0) ++#define TCC_GPC0_GPIO (0) ++ ++#define TCC_GPC1 TCC_GPIONO(TCC_GPIO_BANKC, 1) ++#define TCC_GPC1_GPIO (0) ++ ++#define TCC_GPC2 TCC_GPIONO(TCC_GPIO_BANKC, 2) ++#define TCC_GPC2_GPIO (0) ++ ++#define TCC_GPC3 TCC_GPIONO(TCC_GPIO_BANKC, 3) ++#define TCC_GPC3_GPIO (0) ++ ++#define TCC_GPC4 TCC_GPIONO(TCC_GPIO_BANKC, 4) ++#define TCC_GPC4_GPIO (0) ++ ++#define TCC_GPC5 TCC_GPIONO(TCC_GPIO_BANKC, 5) ++#define TCC_GPC5_GPIO (0) ++ ++#define TCC_GPC6 TCC_GPIONO(TCC_GPIO_BANKC, 6) ++#define TCC_GPC6_GPIO (0) ++ ++#define TCC_GPC7 TCC_GPIONO(TCC_GPIO_BANKC, 7) ++#define TCC_GPC7_GPIO (0) ++ ++#define TCC_GPC8 TCC_GPIONO(TCC_GPIO_BANKC, 8) ++#define TCC_GPC8_GPIO (0) ++ ++#define TCC_GPC9 TCC_GPIONO(TCC_GPIO_BANKC, 9) ++#define TCC_GPC9_GPIO (0) ++ ++#define TCC_GPC10 TCC_GPIONO(TCC_GPIO_BANKC, 10) ++#define TCC_GPC10_GPIO (0) ++ ++#define TCC_GPC11 TCC_GPIONO(TCC_GPIO_BANKC, 11) ++#define TCC_GPC11_GPIO (0) ++ ++#define TCC_GPC12 TCC_GPIONO(TCC_GPIO_BANKC, 12) ++#define TCC_GPC12_GPIO (0) ++ ++#define TCC_GPC13 TCC_GPIONO(TCC_GPIO_BANKC, 13) ++#define TCC_GPC13_GPIO (0) ++ ++#define TCC_GPC14 TCC_GPIONO(TCC_GPIO_BANKC, 14) ++#define TCC_GPC14_GPIO (0) ++ ++#define TCC_GPC15 TCC_GPIONO(TCC_GPIO_BANKC, 15) ++#define TCC_GPC15_GPIO (0) ++ ++#define TCC_GPC16 TCC_GPIONO(TCC_GPIO_BANKC, 16) ++#define TCC_GPC16_GPIO (0) ++ ++#define TCC_GPC17 TCC_GPIONO(TCC_GPIO_BANKC, 17) ++#define TCC_GPC17_GPIO (0) ++ ++#define TCC_GPC18 TCC_GPIONO(TCC_GPIO_BANKC, 18) ++#define TCC_GPC18_GPIO (0) ++ ++#define TCC_GPC19 TCC_GPIONO(TCC_GPIO_BANKC, 19) ++#define TCC_GPC19_GPIO (0) ++ ++#define TCC_GPC20 TCC_GPIONO(TCC_GPIO_BANKC, 20) ++#define TCC_GPC20_GPIO (0) ++ ++#define TCC_GPC21 TCC_GPIONO(TCC_GPIO_BANKC, 21) ++#define TCC_GPC21_GPIO (0) ++ ++#define TCC_GPC22 TCC_GPIONO(TCC_GPIO_BANKC, 22) ++#define TCC_GPC22_GPIO (0) ++ ++#define TCC_GPC23 TCC_GPIONO(TCC_GPIO_BANKC, 23) ++#define TCC_GPC23_GPIO (0) ++ ++#define TCC_GPC24 TCC_GPIONO(TCC_GPIO_BANKC, 24) ++#define TCC_GPC24_GPIO (0) ++ ++#define TCC_GPC25 TCC_GPIONO(TCC_GPIO_BANKC, 25) ++#define TCC_GPC25_GPIO (0) ++ ++#define TCC_GPC26 TCC_GPIONO(TCC_GPIO_BANKC, 26) ++#define TCC_GPC26_GPIO (0) ++ ++#define TCC_GPC27 TCC_GPIONO(TCC_GPIO_BANKC, 27) ++#define TCC_GPC27_GPIO (0) ++ ++#define TCC_GPC28 TCC_GPIONO(TCC_GPIO_BANKC, 28) ++#define TCC_GPC28_GPIO (0) ++ ++#define TCC_GPC29 TCC_GPIONO(TCC_GPIO_BANKC, 29) ++#define TCC_GPC29_GPIO (0) ++ ++#define TCC_GPC30 TCC_GPIONO(TCC_GPIO_BANKC, 30) ++#define TCC_GPC30_GPIO (0) ++ ++#define TCC_GPC31 TCC_GPIONO(TCC_GPIO_BANKC, 31) ++#define TCC_GPC31_GPIO (0) ++ ++/* GPD : 32 in/out port */ ++#define TCC_GPDDAT TCC_GPIOREG(0xC0) ++#define TCC_GPDEN TCC_GPIOREG(0xC4) ++#define TCC_GPDSET TCC_GPIOREG(0xC8) ++#define TCC_GPDCLR TCC_GPIOREG(0xCC) ++#define TCC_GPDXOR TCC_GPIOREG(0xD0) ++#define TCC_GPDCD0 TCC_GPIOREG(0xD4) ++#define TCC_GPDCD1 TCC_GPIOREG(0xD8) ++#define TCC_GPDPD0 TCC_GPIOREG(0xDC) ++#define TCC_GPDPD1 TCC_GPIOREG(0xE0) ++#define TCC_GPDFN0 TCC_GPIOREG(0xE4) ++#define TCC_GPDFN1 TCC_GPIOREG(0xE8) ++#define TCC_GPDFN2 TCC_GPIOREG(0xEC) ++#define TCC_GPDFN3 TCC_GPIOREG(0xF0) ++ ++#define TCC_GPD0 TCC_GPIONO(TCC_GPIO_BANKD, 0) ++#define TCC_GPD0_GPIO (0) ++ ++#define TCC_GPD1 TCC_GPIONO(TCC_GPIO_BANKD, 1) ++#define TCC_GPD1_GPIO (0) ++ ++#define TCC_GPD2 TCC_GPIONO(TCC_GPIO_BANKD, 2) ++#define TCC_GPD2_GPIO (0) ++ ++#define TCC_GPD3 TCC_GPIONO(TCC_GPIO_BANKD, 3) ++#define TCC_GPD3_GPIO (0) ++ ++#define TCC_GPD4 TCC_GPIONO(TCC_GPIO_BANKD, 4) ++#define TCC_GPD4_GPIO (0) ++ ++#define TCC_GPD5 TCC_GPIONO(TCC_GPIO_BANKD, 5) ++#define TCC_GPD5_GPIO (0) ++ ++#define TCC_GPD6 TCC_GPIONO(TCC_GPIO_BANKD, 6) ++#define TCC_GPD6_GPIO (0) ++ ++#define TCC_GPD7 TCC_GPIONO(TCC_GPIO_BANKD, 7) ++#define TCC_GPD7_GPIO (0) ++ ++#define TCC_GPD8 TCC_GPIONO(TCC_GPIO_BANKD, 8) ++#define TCC_GPD8_GPIO (0) ++ ++#define TCC_GPD9 TCC_GPIONO(TCC_GPIO_BANKD, 9) ++#define TCC_GPD9_GPIO (0) ++ ++#define TCC_GPD10 TCC_GPIONO(TCC_GPIO_BANKD, 10) ++#define TCC_GPD10_GPIO (0) ++ ++#define TCC_GPD11 TCC_GPIONO(TCC_GPIO_BANKD, 11) ++#define TCC_GPD11_GPIO (0) ++ ++#define TCC_GPD12 TCC_GPIONO(TCC_GPIO_BANKD, 12) ++#define TCC_GPD12_GPIO (0) ++ ++#define TCC_GPD13 TCC_GPIONO(TCC_GPIO_BANKD, 13) ++#define TCC_GPD13_GPIO (0) ++ ++#define TCC_GPD14 TCC_GPIONO(TCC_GPIO_BANKD, 14) ++#define TCC_GPD14_GPIO (0) ++ ++#define TCC_GPD15 TCC_GPIONO(TCC_GPIO_BANKD, 15) ++#define TCC_GPD15_GPIO (0) ++ ++#define TCC_GPD16 TCC_GPIONO(TCC_GPIO_BANKD, 16) ++#define TCC_GPD16_GPIO (0) ++ ++#define TCC_GPD17 TCC_GPIONO(TCC_GPIO_BANKD, 17) ++#define TCC_GPD17_GPIO (0) ++ ++#define TCC_GPD18 TCC_GPIONO(TCC_GPIO_BANKD, 18) ++#define TCC_GPD18_GPIO (0) ++ ++#define TCC_GPD19 TCC_GPIONO(TCC_GPIO_BANKD, 19) ++#define TCC_GPD19_GPIO (0) ++ ++#define TCC_GPD20 TCC_GPIONO(TCC_GPIO_BANKD, 20) ++#define TCC_GPD20_GPIO (0) ++ ++#define TCC_GPD21 TCC_GPIONO(TCC_GPIO_BANKD, 21) ++#define TCC_GPD21_GPIO (0) ++ ++#define TCC_GPD22 TCC_GPIONO(TCC_GPIO_BANKD, 22) ++#define TCC_GPD22_GPIO (0) ++ ++#define TCC_GPD23 TCC_GPIONO(TCC_GPIO_BANKD, 23) ++#define TCC_GPD23_GPIO (0) ++ ++#define TCC_GPD24 TCC_GPIONO(TCC_GPIO_BANKD, 24) ++#define TCC_GPD24_GPIO (0) ++ ++#define TCC_GPD25 TCC_GPIONO(TCC_GPIO_BANKD, 25) ++#define TCC_GPD25_GPIO (0) ++ ++/* GPE : 32 in/out port */ ++#define TCC_GPEDAT TCC_GPIOREG(0x100) ++#define TCC_GPEEN TCC_GPIOREG(0x104) ++#define TCC_GPESET TCC_GPIOREG(0x108) ++#define TCC_GPECLR TCC_GPIOREG(0x10C) ++#define TCC_GPEXOR TCC_GPIOREG(0x110) ++#define TCC_GPECD0 TCC_GPIOREG(0x114) ++#define TCC_GPECD1 TCC_GPIOREG(0x118) ++#define TCC_GPEPD0 TCC_GPIOREG(0x11C) ++#define TCC_GPEPD1 TCC_GPIOREG(0x120) ++#define TCC_GPEFN0 TCC_GPIOREG(0x124) ++#define TCC_GPEFN1 TCC_GPIOREG(0x128) ++#define TCC_GPEFN2 TCC_GPIOREG(0x12C) ++#define TCC_GPEFN3 TCC_GPIOREG(0x130) ++ ++#define TCC_GPE0 TCC_GPIONO(TCC_GPIO_BANKE, 0) ++#define TCC_GPE0_GPIO (0) ++ ++#define TCC_GPE1 TCC_GPIONO(TCC_GPIO_BANKE, 1) ++#define TCC_GPE1_GPIO (0) ++ ++#define TCC_GPE2 TCC_GPIONO(TCC_GPIO_BANKE, 2) ++#define TCC_GPE2_GPIO (0) ++ ++#define TCC_GPE3 TCC_GPIONO(TCC_GPIO_BANKE, 3) ++#define TCC_GPE3_GPIO (0) ++ ++#define TCC_GPE4 TCC_GPIONO(TCC_GPIO_BANKE, 4) ++#define TCC_GPE4_GPIO (0) ++ ++#define TCC_GPE5 TCC_GPIONO(TCC_GPIO_BANKE, 5) ++#define TCC_GPE5_GPIO (0) ++ ++#define TCC_GPE6 TCC_GPIONO(TCC_GPIO_BANKE, 6) ++#define TCC_GPE6_GPIO (0) ++ ++#define TCC_GPE7 TCC_GPIONO(TCC_GPIO_BANKE, 7) ++#define TCC_GPE7_GPIO (0) ++ ++#define TCC_GPE8 TCC_GPIONO(TCC_GPIO_BANKE, 8) ++#define TCC_GPE8_GPIO (0) ++ ++#define TCC_GPE9 TCC_GPIONO(TCC_GPIO_BANKE, 9) ++#define TCC_GPE9_GPIO (0) ++ ++#define TCC_GPE10 TCC_GPIONO(TCC_GPIO_BANKE, 10) ++#define TCC_GPE10_GPIO (0) ++ ++#define TCC_GPE11 TCC_GPIONO(TCC_GPIO_BANKE, 11) ++#define TCC_GPE11_GPIO (0) ++ ++#define TCC_GPE12 TCC_GPIONO(TCC_GPIO_BANKE, 12) ++#define TCC_GPE12_GPIO (0) ++ ++#define TCC_GPE13 TCC_GPIONO(TCC_GPIO_BANKE, 13) ++#define TCC_GPE13_GPIO (0) ++ ++#define TCC_GPE14 TCC_GPIONO(TCC_GPIO_BANKE, 14) ++#define TCC_GPE14_GPIO (0) ++ ++#define TCC_GPE15 TCC_GPIONO(TCC_GPIO_BANKE, 15) ++#define TCC_GPE15_GPIO (0) ++ ++#define TCC_GPE16 TCC_GPIONO(TCC_GPIO_BANKE, 16) ++#define TCC_GPE16_GPIO (0) ++ ++#define TCC_GPE17 TCC_GPIONO(TCC_GPIO_BANKE, 17) ++#define TCC_GPE17_GPIO (0) ++ ++#define TCC_GPE18 TCC_GPIONO(TCC_GPIO_BANKE, 18) ++#define TCC_GPE18_GPIO (0) ++ ++#define TCC_GPE19 TCC_GPIONO(TCC_GPIO_BANKE, 19) ++#define TCC_GPE19_GPIO (0) ++ ++#define TCC_GPE20 TCC_GPIONO(TCC_GPIO_BANKE, 20) ++#define TCC_GPE20_GPIO (0) ++ ++#define TCC_GPE21 TCC_GPIONO(TCC_GPIO_BANKE, 21) ++#define TCC_GPE21_GPIO (0) ++ ++#define TCC_GPE22 TCC_GPIONO(TCC_GPIO_BANKE, 22) ++#define TCC_GPE22_GPIO (0) ++ ++#define TCC_GPE23 TCC_GPIONO(TCC_GPIO_BANKE, 23) ++#define TCC_GPE23_GPIO (0) ++ ++#define TCC_GPE24 TCC_GPIONO(TCC_GPIO_BANKE, 24) ++#define TCC_GPE24_GPIO (0) ++ ++#define TCC_GPE25 TCC_GPIONO(TCC_GPIO_BANKE, 25) ++#define TCC_GPE25_GPIO (0) ++ ++#define TCC_GPE26 TCC_GPIONO(TCC_GPIO_BANKE, 26) ++#define TCC_GPE26_GPIO (0) ++ ++#define TCC_GPE27 TCC_GPIONO(TCC_GPIO_BANKE, 27) ++#define TCC_GPE27_GPIO (0) ++ ++#define TCC_GPE28 TCC_GPIONO(TCC_GPIO_BANKE, 28) ++#define TCC_GPE28_GPIO (0) ++ ++#define TCC_GPE29 TCC_GPIONO(TCC_GPIO_BANKE, 29) ++#define TCC_GPE29_GPIO (0) ++ ++#define TCC_GPE30 TCC_GPIONO(TCC_GPIO_BANKE, 30) ++#define TCC_GPE30_GPIO (0) ++ ++#define TCC_GPE31 TCC_GPIONO(TCC_GPIO_BANKE, 31) ++#define TCC_GPE31_GPIO (0) ++ ++/* GPF : 32 in/out port */ ++#define TCC_GPFDAT TCC_GPIOREG(0x140) ++#define TCC_GPFEN TCC_GPIOREG(0x144) ++#define TCC_GPFSET TCC_GPIOREG(0x148) ++#define TCC_GPFCLR TCC_GPIOREG(0x14C) ++#define TCC_GPFXOR TCC_GPIOREG(0x150) ++#define TCC_GPFCD0 TCC_GPIOREG(0x154) ++#define TCC_GPFCD1 TCC_GPIOREG(0x158) ++#define TCC_GPFPD0 TCC_GPIOREG(0x15C) ++#define TCC_GPFPD1 TCC_GPIOREG(0x160) ++#define TCC_GPFFN0 TCC_GPIOREG(0x164) ++#define TCC_GPFFN1 TCC_GPIOREG(0x168) ++#define TCC_GPFFN2 TCC_GPIOREG(0x16C) ++#define TCC_GPFFN3 TCC_GPIOREG(0x170) ++ ++#define TCC_GPF0 TCC_GPIONO(TCC_GPIO_BANKF, 0) ++#define TCC_GPF0_GPIO (0) ++ ++#define TCC_GPF1 TCC_GPIONO(TCC_GPIO_BANKF, 1) ++#define TCC_GPF1_GPIO (0) ++ ++#define TCC_GPF2 TCC_GPIONO(TCC_GPIO_BANKF, 2) ++#define TCC_GPF2_GPIO (0) ++ ++#define TCC_GPF3 TCC_GPIONO(TCC_GPIO_BANKF, 3) ++#define TCC_GPF3_GPIO (0) ++ ++#define TCC_GPF4 TCC_GPIONO(TCC_GPIO_BANKF, 4) ++#define TCC_GPF4_GPIO (0) ++ ++#define TCC_GPF5 TCC_GPIONO(TCC_GPIO_BANKF, 5) ++#define TCC_GPF5_GPIO (0) ++ ++#define TCC_GPF6 TCC_GPIONO(TCC_GPIO_BANKF, 6) ++#define TCC_GPF6_GPIO (0) ++ ++#define TCC_GPF7 TCC_GPIONO(TCC_GPIO_BANKF, 7) ++#define TCC_GPF7_GPIO (0) ++ ++#define TCC_GPF8 TCC_GPIONO(TCC_GPIO_BANKF, 8) ++#define TCC_GPF8_GPIO (0) ++ ++#define TCC_GPF9 TCC_GPIONO(TCC_GPIO_BANKF, 9) ++#define TCC_GPF9_GPIO (0) ++ ++#define TCC_GPF10 TCC_GPIONO(TCC_GPIO_BANKF, 10) ++#define TCC_GPF10_GPIO (0) ++ ++#define TCC_GPF11 TCC_GPIONO(TCC_GPIO_BANKF, 11) ++#define TCC_GPF11_GPIO (0) ++ ++#define TCC_GPF12 TCC_GPIONO(TCC_GPIO_BANKF, 12) ++#define TCC_GPF12_GPIO (0) ++ ++#define TCC_GPF13 TCC_GPIONO(TCC_GPIO_BANKF, 13) ++#define TCC_GPF13_GPIO (0) ++ ++#define TCC_GPF14 TCC_GPIONO(TCC_GPIO_BANKF, 14) ++#define TCC_GPF14_GPIO (0) ++ ++#define TCC_GPF15 TCC_GPIONO(TCC_GPIO_BANKF, 15) ++#define TCC_GPF15_GPIO (0) ++ ++#define TCC_GPF16 TCC_GPIONO(TCC_GPIO_BANKF, 16) ++#define TCC_GPF16_GPIO (0) ++ ++#define TCC_GPF17 TCC_GPIONO(TCC_GPIO_BANKF, 17) ++#define TCC_GPF17_GPIO (0) ++ ++#define TCC_GPF18 TCC_GPIONO(TCC_GPIO_BANKF, 18) ++#define TCC_GPF18_GPIO (0) ++ ++#define TCC_GPF19 TCC_GPIONO(TCC_GPIO_BANKF, 19) ++#define TCC_GPF19_GPIO (0) ++ ++#define TCC_GPF20 TCC_GPIONO(TCC_GPIO_BANKF, 20) ++#define TCC_GPF20_GPIO (0) ++ ++#define TCC_GPF21 TCC_GPIONO(TCC_GPIO_BANKF, 21) ++#define TCC_GPF21_GPIO (0) ++ ++#define TCC_GPF22 TCC_GPIONO(TCC_GPIO_BANKF, 22) ++#define TCC_GPF22_GPIO (0) ++ ++#define TCC_GPF23 TCC_GPIONO(TCC_GPIO_BANKF, 23) ++#define TCC_GPF23_GPIO (0) ++ ++#define TCC_GPF24 TCC_GPIONO(TCC_GPIO_BANKF, 24) ++#define TCC_GPF24_GPIO (0) ++ ++#define TCC_GPF25 TCC_GPIONO(TCC_GPIO_BANKF, 25) ++#define TCC_GPF25_GPIO (0) ++ ++#define TCC_GPF26 TCC_GPIONO(TCC_GPIO_BANKF, 26) ++#define TCC_GPF26_GPIO (0) ++ ++#define TCC_GPF27 TCC_GPIONO(TCC_GPIO_BANKF, 27) ++#define TCC_GPF27_GPIO (0) ++ ++#define gpio_set_pin(gpio, function) tcc_gpio_cfgpin(gpio, function, 0) ++#define gpio_get_pin(gpio) tcc_gpio_getcfg(gpio) ++#define gpio_pullup(gpio, to) tcc_gpio_pullup(gpio, to) ++#define gpio_get_value(gpio) tcc_gpio_getpin(gpio) ++#define gpio_set_value(gpio, value) tcc_gpio_setpin(gpio, value) ++#define gpio_direction_input(gpio) tcc_gpio_direction_input(gpio) ++#define gpio_direction_output(gpio, value) tcc_gpio_direction_output(gpio, value) ++ ++extern void tcc_gpio_cfgpin(unsigned int pin, unsigned int function, unsigned int out); ++extern unsigned int tcc_gpio_getcfg(unsigned int pin); ++extern void tcc_gpio_pullup(unsigned int pin, unsigned int to); ++extern void tcc_gpio_setpin(unsigned int pin, unsigned int to); ++extern unsigned int tcc_gpio_getpin(unsigned int pin); ++extern int tcc_gpio_direction_input(unsigned int gpio); ++extern int tcc_gpio_direction_output(unsigned int gpio, int value); ++ ++#if 0 ++static inline int gpio_request(unsigned int gpio, const char *label) ++{ ++ return 0; ++} ++ ++static inline void gpio_free(unsigned int gpio) ++{ ++ return; ++} ++#else// XXX: mhfan ++#define gpio_request(...) (0) ++#define gpio_free(...) ++#endif ++ ++#include +diff --git a/arch/arm/mach-tcc8900/include/mach/hardware.h b/arch/arm/mach-tcc8900/include/mach/hardware.h +new file mode 100644 +index 0000000..d30ef32 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/hardware.h +@@ -0,0 +1,65 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/hardware.h ++ * ++ * Rewritten by: ++ * Modifiedd: June 10, 2008 ++ * Description: Hardware definitions for TCC8900 processors and boards ++ * Author: RidgeRun, Inc. Greg Lonnon ++ * Reorganized for Linux-2.6 by Tony Lindgren ++ * and Dirk Behme ++ * ++ * Copyright (C) 2001 RidgeRun, Inc. ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * NOTE: Please put device driver specific defines into a separate header ++ * file for each driver. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __ASM_ARCH_TCC8900_HARDWARE_H ++#define __ASM_ARCH_TCC8900_HARDWARE_H ++ ++#include ++#ifndef __ASSEMBLER__ ++#include ++#endif ++#include ++ ++/* ++ * ---------------------------------------------------------------------------- ++ * Clocks ++ * ---------------------------------------------------------------------------- ++ */ ++#define CLKGEN_REG_BASE (0xfffece00) ++#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) ++#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) ++#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) ++#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) ++#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) ++#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) ++#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) ++#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) ++ ++/* DPLL control registers */ ++#define DPLL_CTL (0xfffecf00) ++ ++#endif /* __ASM_ARCH_TCC8900_HARDWARE_H */ +diff --git a/arch/arm/mach-tcc8900/include/mach/io.h b/arch/arm/mach-tcc8900/include/mach/io.h +new file mode 100644 +index 0000000..4592fa9 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/io.h +@@ -0,0 +1,73 @@ ++/* ++ * linux/include/asm-arm/arch-tcc89x/io.h ++ * ++ * Based on: linux/include/asm-arm/arch-sa1100/io.h ++ * Author : ++ * Description: IO definitions for TCC8900 processors and boards ++ * ++ * Copyright (C) 1997-1999 Russell King ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++ ++#ifndef __ASM_ARM_ARCH_IO_H__ ++#define __ASM_ARM_ARCH_IO_H__ ++ ++#include ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++/* ++ * We don't actually have real ISA nor PCI buses, but there is so many ++ * drivers out there that might just work if we fake them... ++ */ ++#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) ++#define __mem_pci(a) (a) ++ ++/* ++ * ---------------------------------------------------------------------------- ++ * I/O mapping ++ * ---------------------------------------------------------------------------- ++ */ ++#define PCIO_BASE 0 ++ ++#define IO_PHYS 0xF0000000 ++#define IO_OFFSET 0x00000000 /* Virtual IO = 0xf0000000 */ ++#define IO_SIZE 0x100000 ++#define IO_VIRT (IO_PHYS - IO_OFFSET) ++#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) ++#define io_p2v(pa) ((pa) - IO_OFFSET) ++#define io_v2p(va) ((va) + IO_OFFSET) ++ ++/* Physical value to Virtual Address */ ++#define tcc_p2v(pa) ((unsigned int)(&pa) - IO_OFFSET) ++ ++#define tcc_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) ++#define tcc_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++#define tcc_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) ++ ++#define tcc_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) ++#define tcc_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++#define tcc_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) ++ ++#endif /*__ASM_ARM_ARCH_IO_H__*/ +diff --git a/arch/arm/mach-tcc8900/include/mach/ioctl_ckcstr.h b/arch/arm/mach-tcc8900/include/mach/ioctl_ckcstr.h +new file mode 100644 +index 0000000..b521130 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/ioctl_ckcstr.h +@@ -0,0 +1,86 @@ ++/**************************************************************************** ++ * FileName : ioctl_ckcstr.h ++ * Description : ++ **************************************************************************** ++* ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++* ++ ****************************************************************************/ ++ ++ ++/************************************************************************************************ ++* Revision History * ++* * ++* Version : 1.0 : 2009, 2, 04 * ++************************************************************************************************/ ++ ++#ifndef __IOCTL_STR_H__ ++#define __IOCTL_STR_H__ ++ ++ ++//#include "bsp.h" ++ ++ ++// For CKC Controller ++typedef struct _stckcioctl{ ++ unsigned int ioctlcode; ++ //Reset or bus Enable name ++ unsigned int prbname; ++ //Peri Clock ++ unsigned int pckcname; ++ unsigned int pckcenable; ++ unsigned int pckcsource; ++ unsigned int pckcfreq; ++ //PLL Cllock ++ unsigned int pllchannel; ++ unsigned int pllvalue; ++ unsigned int P; ++ unsigned int M; ++ unsigned int S; ++ //CPU Cllock ++ unsigned int cpuvalue; ++ //BUS Cllock ++ unsigned int busvalue; ++ //mode ++ unsigned int mode; // Enable, Disable, ahalf, athird ++ ++ unsigned int priority; ++ ++ unsigned int cpudivider; ++ unsigned int pmuoffname; ++ ++ unsigned int bspmax; ++ //Fbus Clock ++ unsigned int fbusname; ++ unsigned int fbusenable; ++ unsigned int fbussource; ++ unsigned int fbusfreq; ++ ++ //DDI PWDN ++ unsigned int ddipdname; ++ ++ //ETC Block ++ unsigned int etcblock; ++ ++ ++}stckcioctl; ++ ++ ++typedef struct _stckcinfo{ ++ unsigned int currentbusfreq; ++ unsigned int currentsysfreq; ++ unsigned int currentcpufreq; ++ int pckcfreq; //return etc frequency ++ unsigned int validpll[30]; ++ int retVal; ++ unsigned int currentpriority; ++ ++ unsigned int state; ++ ++ int fbusfreq; ++ ++}stckcinfo; ++ ++#endif /* __IOCTL_STR_H__ */ +diff --git a/arch/arm/mach-tcc8900/include/mach/irqs.h b/arch/arm/mach-tcc8900/include/mach/irqs.h +new file mode 100644 +index 0000000..82efdaf +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/irqs.h +@@ -0,0 +1,158 @@ ++/* linux/include/asm-arm/arch-tcc8900/irqs.h ++ * ++ * Author: ++ * Created: Mach 10, 2009 ++ * Copyright (C) 2009- Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __ASM_ARCH_TCC_IRQS_H ++#define __ASM_ARCH_TCC_IRQS_H ++ ++/* ++ * IRQ numbers for interrupt handler ++ */ ++ ++#define INT_TC0 0 ++#define INT_TC1 1 ++#define INT_SMUI2C 2 ++#define INT_EI0 3 ++#define INT_EI1 4 ++#define INT_EI2 5 ++#define INT_EI3 6 ++#define INT_EI4 7 ++#define INT_EI5 8 ++#define INT_EI6 9 ++#define INT_EI7 10 ++#define INT_EI8 11 ++#define INT_EI9 12 ++#define INT_EI10 13 ++#define INT_EI11 14 ++#define INT_SC0 15 ++#define INT_SC1 16 ++#define INT_CAM 17 ++#define INT_LCD0 18 ++#define INT_LCD1 19 ++#define INT_VIPET 20 ++#define INT_JPGE 21 ++#define INT_JPGD 22 ++#define INT_VCDC 23 ++#define INT_3DPP 24 ++#define INT_3DGP 25 ++#define INT_3DMMU 26 ++#define INT_G2D 27 ++#define INT_TSADC 28 ++#define INT_DMA 29 ++#define INT_ECC 30 ++#define INT_EHI0 31 ++#define INT_EHI1 32 ++#define INT_CAN 33 ++#define INT_HDMI 34 ++#define INT_SATA 35 ++#define INT_GPSB 36 ++#define INT_HDD 37 ++#define INT_I2C 38 ++#define INT_MPEFEC 39 ++#define INT_MS 40 ++#define INT_NFC 41 ++#define INT_RMT 42 ++#define INT_RTC 43 ++#define INT_SD0 44 ++#define INT_SD1 45 ++#define INT_SPDTX 46 ++#define INT_UART 47 ++#define INT_UOTG 48 ++#define INT_U11H 49 ++#define INT_GPS0 50 ++#define INT_GPS1 51 ++#define INT_GPS2 52 ++#define INT_TSIF0 53 ++#define INT_TSIF1 54 ++#define INT_CDRX 55 ++#define INT_DAIRX 56 ++#define INT_DAITX 57 ++#define INT_ADMA 58 ++#define INT_AUDIO 59 ++#define INT_APMU 60 ++#define INT_AIRQ 61 ++#define INT_ASIRQ 62 ++#define INT_AEIRQ 63 ++ ++/* ++ * IRQ_UT numbers for UART[0:5] ++ */ ++#define INT_UT_BASE 64 ++#define INT_UART0 (0 + INT_UT_BASE) ++#define INT_UART1 (1 + INT_UT_BASE) ++#define INT_UART2 (2 + INT_UT_BASE) ++#define INT_UART3 (3 + INT_UT_BASE) ++#define INT_UART4 (4 + INT_UT_BASE) ++#define INT_UART5 (5 + INT_UT_BASE) ++ ++/* ++ * GPSB-IRQ numbers for GPSB0 & GPSB0 ++ */ ++#define INT_GPSB0_BASE 70 ++#define INT_GPSB0_DMA (0 + INT_GPSB0_BASE) ++#define INT_GPSB1_DMA (1 + INT_GPSB0_BASE) ++#define INT_GPSB2_DMA (2 + INT_GPSB0_BASE) ++ ++#define INT_GPSB0_CORE (3 + INT_GPSB0_BASE) ++#define INT_GPSB1_CORE (4 + INT_GPSB0_BASE) ++#define INT_GPSB2_CORE (5 + INT_GPSB0_BASE) ++#define INT_GPSB3_CORE (6 + INT_GPSB0_BASE) ++#define INT_GPSB4_CORE (7 + INT_GPSB0_BASE) ++#define INT_GPSB5_CORE (8 + INT_GPSB0_BASE) ++ ++/* ++ * DMA-IRQ numbers ++ */ ++#define INT_DMA0_BASE 79 ++#define INT_DMA0_CH0 (0 + INT_DMA0_BASE) ++#define INT_DMA0_CH1 (1 + INT_DMA0_BASE) ++#define INT_DMA0_CH2 (2 + INT_DMA0_BASE) ++#define INT_DMA1_CH0 (3 + INT_DMA0_BASE) ++#define INT_DMA1_CH1 (4 + INT_DMA0_BASE) ++#define INT_DMA1_CH2 (5 + INT_DMA0_BASE) ++#define INT_DMA2_CH0 (6 + INT_DMA0_BASE) ++#define INT_DMA2_CH1 (7 + INT_DMA0_BASE) ++#define INT_DMA2_CH2 (8 + INT_DMA0_BASE) ++#define INT_DMA3_CH0 (9 + INT_DMA0_BASE) ++#define INT_DMA3_CH1 (10 + INT_DMA0_BASE) ++#define INT_DMA3_CH2 (11 + INT_DMA0_BASE) ++ ++/* ++ * TC0-IRQ numbers for Timer/Counter 0~5 ++ */ ++#define INT_TC0_BASE 91 ++#define INT_TC0_TI0 (0 + INT_TC0_BASE) ++#define INT_TC0_TI1 (1 + INT_TC0_BASE) ++#define INT_TC0_TI2 (2 + INT_TC0_BASE) ++#define INT_TC0_TI3 (3 + INT_TC0_BASE) ++#define INT_TC0_TI4 (4 + INT_TC0_BASE) ++#define INT_TC0_TI5 (5 + INT_TC0_BASE) ++ ++/* ++ * NR_IRQ: ++ */ ++#define NR_IRQS ((INT_AEIRQ + 1)\ ++ + (INT_UART5 - INT_UT_BASE + 1)\ ++ + (INT_GPSB5_CORE - INT_GPSB0_BASE + 1)\ ++ + (INT_DMA3_CH2 - INT_DMA0_BASE + 1)\ ++ + (INT_TC0_TI5 - INT_TC0_BASE + 1)) ++ ++#endif /* ASM_ARCH_TCC_IRQS_H */ ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/memory.h b/arch/arm/mach-tcc8900/include/mach/memory.h +new file mode 100644 +index 0000000..f6a3713 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/memory.h +@@ -0,0 +1,106 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/memory.h ++ * ++ * Based on: linux/include/asm-arm/arch-intergrator/memory.h ++ * Author: Greg Lonnon ++ * Rewritten by: ++ * Modified: Feb 10, 2009 ++ * Description: Memory map for TCC8900 ++ * ++ * Copyright (C) 1999 ARM Limited ++ * Copyright (C) 2000 RidgeRun, Inc. ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define PHYS_OFFSET UL(0x40200000) ++ ++/* ++ * Free Mem Size ++ * mem=[size] ++ * size = Total RAM size - Total Reserved RAM size ++ * Total RAM size = CONFIG_RAM_XXXMB ++ * Totla Reserved RAM size = FB reserved size + Video Codec reserved size ++ */ ++#define CAL_VPU_OFFSET(ram_size, vpu_size) ( (0x40000000+ram_size) - (vpu_size*1024*1024) ) ++#if defined(CONFIG_RAM_128MB) ++ #define TCC_RAM_TOTAL_SIZE 0x08000000 ++ ++ #if defined(CONFIG_HD720p_LEVEL41) ++ #define TCC_MEM_SIZE " mem=86M" ++ #elif defined(CONFIG_HD720p_LEVEL51) ++ #define TCC_MEM_SIZE " mem=60M" ++ #elif defined(CONFIG_HD1080p_LEVEL41) ++ #define TCC_MEM_SIZE " mem=66M" ++ #elif defined(CONFIG_HD1080p_LEVEL51) ++ #error "[not support HD1080p_LEVEL51] Check menuconfig->System Type->A/V Spec" ++ #else ++ #error "[undefine A/V spec] Check menuconfig->System Type->A/V Spec" ++ #endif ++ ++ ++#elif defined(CONFIG_RAM_256MB) ++ #define TCC_RAM_TOTAL_SIZE 0x10000000 ++ ++ #if defined(CONFIG_HD720p_LEVEL41) ++ #define TCC_MEM_SIZE " mem=214M" ++ #elif defined(CONFIG_HD720p_LEVEL51) ++ #define TCC_MEM_SIZE " mem=188M" ++ #elif defined(CONFIG_HD1080p_LEVEL41) ++ #define TCC_MEM_SIZE " mem=194M" ++ #elif defined(CONFIG_HD1080p_LEVEL51) ++ #define TCC_MEM_SIZE " mem=138M" ++ #else ++ #error "[undefine A/V spec] Check menuconfig->System Type->A/V Spec" ++ #endif ++ ++#else ++ #error "[undefine MEM size] Check menuconfig->System Type->RAM Spec" ++#endif ++ ++/* ++ * Frame buffer memory define ++ */ ++#define TCC_FB0_SIZE (8*1024*1024) // 8MB ++#define TCC_FB1_SIZE (4*1024*1024) // 4MB ++#define TCC_FB2_SIZE (4*1024*1024) // 4MB ++ ++/* ++ * Size of DMA-consistent memory region. Must be multiple of 2M, ++ * between 2MB and 14MB inclusive. ++ */ ++#ifndef CONSISTENT_DMA_SIZE ++#define CONSISTENT_DMA_SIZE (SZ_2M) ++#endif ++ ++ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/ohci.h b/arch/arm/mach-tcc8900/include/mach/ohci.h +new file mode 100644 +index 0000000..6ec9451 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/ohci.h +@@ -0,0 +1,241 @@ ++/* ++ * linux/include/asm-arm/arch-tcc79x/ohci.h ++ * ++ * Author: ++ * Created: June 10, 2008 ++ * Description: ohci definition for TCC79x ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see the file COPYING, or write ++ * to the Free Software Foundation, Inc., ++ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#ifndef ASMARM_ARCH_OHCI_H ++#define ASMARM_ARCH_OHCI_H ++ ++ ++// fields and bits for uhcrev: HCI Spec Revision ++#define USBOHCI_UHCREV_OHCISPEC1_0_A 0x10 ++ ++// fields and bits for uhchcon: Control register ++#define USBOHCI_UHCCON_CBSR_MASK ( 0x3u << 0 ) ++ ++#define USBOHCI_UHCCON_CBSR_PLE ( 2u << 2 ) ++#define USBOHCI_UHCCON_CBSR_IE ( 3u << 2 ) ++#define USBOHCI_UHCCON_CBSR_CLE ( 4u << 2 ) ++#define USBOHCI_UHCCON_CBSR_BLE ( 5u << 2 ) ++ ++#define USBOHCI_UHCCON_HCFS_MASK ( 0x3u << 6 ) ++ ++#define USBOHCI_UHCCON_CBSR_IR ( 8u << 2 ) ++#define USBOHCI_UHCCON_CBSR_RWC ( 9u << 2 ) ++#define USBOHCI_UHCCON_CBSR_RWE ( 10u << 2 ) ++ ++// for the HCFS field ++#define USBOHCI_UHCCON_HCFS_USBRESET ( 0u << 6 ) ++#define USBOHCI_UHCCON_HCFS_USBRESUME ( 1u << 6 ) ++#define USBOHCI_UHCCON_HCFS_USBOPERATIONAL ( 2u << 6 ) ++#define USBOHCI_UHCCON_HCFS_USBSUSPEND ( 3u << 6 ) ++ ++ ++// fields and bits for uhccoms: Command Status ++#define USBOHCI_UHCCOMS_HCR ( 1u << 0) ++#define USBOHCI_UHCCOMS_CLF ( 1u << 1 ) ++#define USBOHCI_UHCCOMS_BLF ( 1u << 2 ) ++#define USBOHCI_UHCCOMS_OCR ( 1u << 3 ) ++ ++#define USBOHCI_UHCCOMS_SOC_MASK ( 0x3u << 16 ) ++ ++ ++ ++// fields and bits for uhcints: Interrupt Status ++// fields and bits for uhcinte: Interrupt Enable Control register ++// fields and bits for uhcintd: Interrupt Disable Control register ++#define USBOHCI_UHCINT_SO ( 1u << 0 ) ++#define USBOHCI_UHCINT_WDH ( 1u << 1 ) ++#define USBOHCI_UHCINT_SF ( 1u << 2 ) ++#define USBOHCI_UHCINT_RD ( 1u << 3 ) ++#define USBOHCI_UHCINT_UE ( 1u << 4 ) ++#define USBOHCI_UHCINT_FNO ( 1u << 5 ) ++#define USBOHCI_UHCINT_RHSC ( 1u << 6 ) ++#define USBOHCI_UHCINT_OC ( 1u << 30 ) ++#define USBOHCI_UHCINT_MIE ( 1u << 31 ) ++ ++// fields and bits for uhchcca: Host controller Communication Area ++#define USBOHCI_UHCHCCA_MASK ( 0xfffffffu << 8 ) ++ ++// fields and bits for uhcpced: Period Current Endpoint Descriptor ++#define USBOHCI_UHCPCED_MASK ( 0xffffffffu << 4 ) ++ ++// fields and bits for uhcched: Control Head Endpoint Descriptor register ++#define USBOHCI_UHCCHED_MASK ( 0xffffffffu << 4 ) ++ ++// fields and bits for uhccced: Control Current Endpoint Descriptor register ++#define USBOHCI_UHCCCED_MASK ( 0xffffffffu << 4 ) ++ ++// fields and bits for uhcbhed: Bulk Head Endpoint Descriptor register ++#define USBOHCI_UHCBHED_MASK ( 0xffffffffu << 4 ) ++ ++// fields and bits for uhcbced: Bulk Current Endpoint Descriptor register ++#define USBOHCI_UHCBCED_MASK ( 0xffffffffu << 4 ) ++ ++// fields and bits for uhcdhead: Done head register ++#define USBOHCI_UHCDHED_MASK ( 0xffffffffu << 4 ) // should be "DHTD" because its a transfer descriptor ++ ++// fields and bits for uhcfmi: Frame Interval register ++#define USBOHCI_UHCFMI_FI_MASK ( 0x3fffu << 0 ) ++#define USBOHCI_UHCFMI_FSMPS_MASK ( 0x7fffu << 16 ) ++#define USBOHCI_UHCFMI_FIT ( 1u << 31 ) ++ ++// fields and bits for uhcfmr: Frame Remaining register ++#define USBOHCI_UHCFMR_FR_MASK ( 0x3fffu << 0 ) ++#define USBOHCI_UHCFMI_FRT ( 1u << 31 ) ++ ++// fields and bits for uhcfmn: Frame Number register ++#define USBOHCI_UHCFMN_FN_MASK ( 0xffffu << 0 ) ++ ++// fields and bits for uhcpers: Periodic Start register ++#define USBOHCI_UHCPERS_PS_MASK ( 0x3fffu << 0 ) ++ ++// fields and bits for uhclst: Low Speed Threshold register ++#define USBOHCI_UHCPLST_LST_MASK ( 0xfffu << 0 ) ++ ++// fields and bits for uhcrhda: Root Hub Descriptor A register ++#define USBOHCI_UHCRHDA_NDP_MASK ( 0xffu << 0 ) ++ ++#define USBOHCI_UHCRHDA_PSM ( 1u << 8 ) ++#define USBOHCI_UHCRHDA_NPS ( 1u << 9 ) ++#define USBOHCI_UHCRHDA_DT ( 1u << 10 ) ++#define USBOHCI_UHCRHDA_OCPM ( 1u << 11 ) ++#define USBOHCI_UHCRHDA_NOCP ( 1u << 12 ) ++ ++#define USBOHCI_UHCRHDA_POTPGT_MASK ( 0xffu << 24 ) ++ ++// fields and bits for uhcrhdb: Root Hub Descriptor B register ++#define USBOHCI_UHCRHDB_DR_MASK ( 0xffffu << 0 ) ++#define USBOHCI_UHCRHDB_PPCM_MASK ( 0xffffu << 16 ) ++ ++// fields and bits for uhcrhs: Root Hub Status register ++#define USBOHCI_UHCRHS_LPS ( 1u << 0 ) // meaning on read ++#define USBOHCI_UHCRHS_CGP ( 1u << 0 ) // meaining on write ++#define USBOHCI_UHCRHS_OCI ( 1u << 1 ) ++#define USBOHCI_UHCRHS_DRWE ( 1u << 15 ) // meaning on read ++#define USBOHCI_UHCRHS_SRWE ( 1u << 15 ) // meaning on write ++#define USBOHCI_UHCRHS_LPSC ( 1u << 16 ) // meaning on read ++#define USBOHCI_UHCRHS_SGP ( 1u << 16 ) // meaning on write ++#define USBOHCI_UHCRHS_OCIC ( 1u << 17 ) ++#define USBOHCI_UHCRHS_CRWE ( 1u << 31 ) ++ ++// fields and bits for uhcrhps1: Root Hub Port 1 Status register ++// fields and bits for uhcrhps2: Root Hub Port 2 Status register ++#define USBOHCI_UHCRHPS_CCS ( 1u << 0 ) ++#define USBOHCI_UHCRHPS_PES ( 1u << 1 ) ++#define USBOHCI_UHCRHPS_PSS ( 1u << 2 ) ++#define USBOHCI_UHCRHPS_POCI ( 1u << 3 ) ++#define USBOHCI_UHCRHPS_PRS ( 1u << 4 ) ++#define USBOHCI_UHCRHPS_PPS ( 1u << 8 ) ++#define USBOHCI_UHCRHPS_LSDA ( 1u << 9 ) // meaning on read ++#define USBOHCI_UHCRHPS_CPP ( 1u << 9 ) // meaning on write ++#define USBOHCI_UHCRHPS_CSC ( 1u << 16 ) ++#define USBOHCI_UHCRHPS_PESC ( 1u << 17 ) ++#define USBOHCI_UHCRHPS_PSSC ( 1u << 18 ) ++#define USBOHCI_UHCRHPS_POCIC ( 1u << 19 ) ++#define USBOHCI_UHCRHPS_PRSC ( 1u << 20 ) ++ ++// fields and bits for uhcstat: USB Host Status ++#define USBOHCI_UHCSTAT_RWUE ( 1u << 7 ) ++#define USBOHCI_UHCSTAT_HBA ( 1u << 8 ) ++#define USBOHCI_UHCSTAT_HTA ( 1u << 10 ) ++#define USBOHCI_UHCSTAT_UPS1 ( 1u << 11 ) ++#define USBOHCI_UHCSTAT_UPS2 ( 1u << 12 ) ++#define USBOHCI_UHCSTAT_UPRI ( 1u << 13 ) ++#define USBOHCI_UHCSTAT_SBTAI ( 1u << 14 ) ++#define USBOHCI_UHCSTAT_SBMAI ( 1u << 15 ) ++ ++// fields and bits for uhchr: USB Host Reset ++// UHCHR host reset register bit positions ++#define USBOHCI_UHCHR_SSEP1 ( 1u << 10) // Sleep Standby Enable: enable/disable port1 SE receivers & power supply ++#define USBOHCI_UHCHR_SSEP0 ( 1u << 9) // Sleep Standby Enable: enable/disable port1 SE receivers & power supply ++#define USBOHCI_UHCHR_PCPL ( 1u << 7) // Power CONTROL Polarity: Control polarity of Power Enable signals output to the MAX1693EUB USB Power Switch ++#define USBOHCI_UHCHR_PSPL ( 1u << 6) // Power SENSE Polarity: Control polarity of Over-current Indicator signals input from the MAX1693EUB USB Power Switch ++#define USBOHCI_UHCHR_SSE ( 1u << 5) // Sleep Standby Enable: enable/disable both ports SE receivers & power supply ++#define USBOHCI_UHCHR_UIT ( 1u << 4) // USB Interrupt Test: Enable Interrupt Test Mode and UHCHIT register ++#define USBOHCI_UHCHR_SSDC ( 1u << 3) // Simulation Scale Down Clock: When 1, internal 1 mSec timer changes to 1 uSec to speed up simulations ++#define USBOHCI_UHCHR_CGR ( 1u << 2) // Clock Generation Reset: When 0, resets the OHCI Clock Generation block (DPLL). Used only in simulation ++#define USBOHCI_UHCHR_FHR ( 1u << 1) // Force Host controller Reset: When 1, resets OHCI core. Must be held high for 10 uSeconds, then cleared ++#define USBOHCI_UHCHR_FSBIR ( 1u << 0) // Force System Bus Interface Reset: When 1, resets the logic that interfaces to the system bus, DMA, etc. Auto clears after three system bus clocks. ++ ++// fields and bits for uhchie: USB Host Interrupt Enable ++#define USBOHCI_UHCIE_RWIE ( 1u << 7 ) ++#define USBOHCI_UHCIE_HBAIE ( 1u << 8 ) ++#define USBOHCI_UHCIE_TAIE ( 1u << 10 ) ++#define USBOHCI_UHCIE_UPS1IE ( 1u << 11 ) ++#define USBOHCI_UHCIE_UPS2IE ( 1u << 12 ) ++#define USBOHCI_UHCIE_UPRIE ( 1u << 13 ) ++ ++ ++// fields and bits for uhchit: USB Host Interrupt Test ++#define USBOHCI_UHCIT_RWIT ( 1u << 7 ) ++#define USBOHCI_UHCIT_BAT ( 1u << 8 ) ++#define USBOHCI_UHCIT_IRQT ( 1u << 9 ) ++#define USBOHCI_UHCIT_TAT ( 1u << 10 ) ++#define USBOHCI_UHCIT_UPS1T ( 1u << 11 ) ++#define USBOHCI_UHCIT_UPS2T ( 1u << 12 ) ++#define USBOHCI_UHCIT_UPRT ( 1u << 13 ) ++#define USBOHCI_UHCIT_STAT ( 1u << 14 ) ++#define USBOHCI_UHCIT_SMAT ( 1u << 15 ) ++ ++ ++ ++// root hub descriptor A information ++#define USBOHCI_UHCRHDA_PSM_PERPORT 1 ++ ++ ++#define INT_CTRL_BASE 0xF3001000 ++#define IEN_REG_OFFSET 0x0 ++#define CLR_REG_OFFSET 0x4 ++#define SEL_REG_OFFSET 0xC ++#define POL_REG_OFFSET 0x1C ++ ++#define CLK_CTRL_BASE 0xF3000000 ++#define BCLK_CTRL_OFFSET 0x18 ++#define SWRESET_CTRL_OFFSET 0x1C ++ ++#define HwBCLK *(volatile unsigned long *)(CLK_CTRL_BASE+BCLK_CTRL_OFFSET) ++ ++#define IO_CKC_BUS_UBH 0x00000001 ++#define IO_CKC_BUS_UBD 0x00000002 ++ ++ ++ ++struct device; ++ ++struct tccohci_platform_data { ++ int (*init)(struct device *); ++ void (*exit)(struct device *); ++ ++ int port_mode; ++#define USBOHCI_PPM_NPS 1 ++#define USBOHCI_PPM_GLOBAL 2 ++#define USBOHCI_PPM_PERPORT 3 ++#define USBOHCI_PPM_MIXED 4 ++ ++ int power_budget; ++}; ++ ++extern void tcc_set_ohci_info(struct tccohci_platform_data *info); ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/include/mach/reg_physical.h b/arch/arm/mach-tcc8900/include/mach/reg_physical.h +new file mode 100644 +index 0000000..529a296 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/reg_physical.h +@@ -0,0 +1,38 @@ ++/**************************************************************************** ++* FileName : reg_physical.h ++* Description : ++**************************************************************************** ++* ++* TCC Version : 1.0 ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************/ ++ ++#ifndef __REG_PHYSICAL_H__ ++#define __REG_PHYSICAL_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++#if defined(TCC89X) ++ #include "TCC89x_Physical.h" ++ #include "TCC89x_Structures.h" ++#elif defined(TCC91X) ++ #include "TCC91x_Physical.h" ++ #include "TCC91x_Structures.h" ++#elif defined(TCC92X) ++ #include "TCC92x_Physical.h" ++ #include "TCC92x_Structures.h" ++#endif ++*/ ++#include "TCC89x_Physical.h" ++#include "TCC89x_Structures.h" ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // __REG_PHYSICAL_H__ +diff --git a/arch/arm/mach-tcc8900/include/mach/system.h b/arch/arm/mach-tcc8900/include/mach/system.h +new file mode 100644 +index 0000000..2dbc2a0 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/system.h +@@ -0,0 +1,54 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/include/mach ++ * ++ * Author: ++ * Created: June 10, 2008 ++ * Description: LINUX SYSTEM FUNCTIONS for TCC83x ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see the file COPYING, or write ++ * to the Free Software Foundation, Inc., ++ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++#include ++ ++#include ++#include ++ ++#include ++ ++extern inline void tcc_idle(void); ++ ++static inline void arch_idle(void) ++{ ++ tcc_idle(); ++} ++ ++static inline void arch_reset(char mode) ++{ ++ volatile PPMU pPMU = (volatile PPMU)(tcc_p2v(HwPMU_BASE)); //0xF0404000 ++ volatile PIOBUSCFG pIOBUSCFG = (volatile PIOBUSCFG)(tcc_p2v(HwIOBUSCFG_BASE)); //0xF05F5000 ++ ++ pIOBUSCFG->HCLKEN0 = -1; ++ pIOBUSCFG->HCLKEN1 = -1; ++ ++ while (1) { ++ pPMU->WATCHDOG = (Hw31 + 0x1); ++ } ++} ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/include/mach/system_type.h b/arch/arm/mach-tcc8900/include/mach/system_type.h +new file mode 100644 +index 0000000..7941705 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/system_type.h +@@ -0,0 +1,32 @@ ++/**************************************************************************** ++* FileName : system.h ++* Description : ++**************************************************************************** ++* ++* TCC Version : 1.0 ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************/ ++ ++#ifndef __SYSTEM_H__ ++#define __SYSTEM_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ //wince ++#include ++#include ++#include ++#include ++ ++ //linux ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // __SYSTEM_H__ +\ No newline at end of file +diff --git a/arch/arm/mach-tcc8900/include/mach/tca_ckc.h b/arch/arm/mach-tcc8900/include/mach/tca_ckc.h +new file mode 100644 +index 0000000..cdb8315 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/tca_ckc.h +@@ -0,0 +1,178 @@ ++/**************************************************************************** ++ * FileName : tca_ckc.h ++ * Description : ++ **************************************************************************** ++* ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++* ++ ****************************************************************************/ ++ ++ ++/************************************************************************************************ ++* Revision History * ++* * ++* Version : 1.0 : 2009, 2, 04 * ++************************************************************************************************/ ++ ++#ifndef __TCA_CKC_H__ ++#define __TCA_CKC_H__ ++ ++//#include "bsp.h" ++ ++#if defined(_LINUX_) ++#ifndef VOLATILE ++#define VOLATILE ++#endif ++#else ++#ifndef VOLATILE ++#define VOLATILE volatile ++#endif ++#endif ++ ++/************************************************************************************************ ++* MACRO * ++************************************************************************************************/ ++ ++/************************************************************************************************ ++* DEFINE * ++************************************************************************************************/ ++/************************************************************************************************ ++* ENUM * ++************************************************************************************************/ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_init(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_init(void); ++ ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getpll(unsigned int ch) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE unsigned int tca_ckc_getpll(unsigned int ch); ++ ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getcpu(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE unsigned int tca_ckc_getcpu(void); ++ ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getbus(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE unsigned int tca_ckc_getbus(void); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setfbusctrl(unsigned int clkname,unsigned int isenable,unsigned int freq, unsigned int sor) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setfbusctrl(unsigned int clkname,unsigned int isenable,unsigned int md,unsigned int freq, unsigned int sor); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_getfbusctrl(unsigned int clkname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_getfbusctrl(unsigned int clkname); ++ ++/**************************************************************************************** ++* FUNCTION :int tca_ckc_setpll(unsigned int pll, unsigned int ch) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_setpll(unsigned int pll, unsigned int ch); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_validpll(unsigned int * pvalidpll) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_validpll(unsigned int * pvalidpll); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setpmupwroff( unsigned int periname , unsigned int isenable) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setpmupwroff( unsigned int periname , unsigned int isenable); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_getpmupwroff( unsigned int pmuoffname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_getpmupwroff( unsigned int pmuoffname); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setperi(unsigned int periname,unsigned int isenable, unsigned int freq, unsigned int sor) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setperi(unsigned int periname,unsigned int isenable, unsigned int freq, unsigned int sor); ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getperi(unsigned int periname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_getperi(unsigned int periname); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setcpu(unsigned int n) ++* DESCRIPTION : n is n/16 ++* example : CPU == PLL : n=16 - CPU == PLL/2 : n=8 ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setcpu(unsigned int n); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setswresetprd(unsigned int prd) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setswresetprd(unsigned int prd); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setswreset(unsigned int lfbusname, unsigned int mode) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setswreset(unsigned int lfbusname, unsigned int mode); ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_set_iobus_swreset(unsigned int sel) ++* DESCRIPTION : ++* ***************************************************************************************/ ++ ++extern VOLATILE unsigned int tca_ckc_set_iobus_swreset(unsigned int sel, unsigned int mode); ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_setiobus(unsigned int sel, unsigned int mode) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_setiobus(unsigned int sel, unsigned int mode); ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getiobus(unsigned int sel) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_getiobus(unsigned int sel); ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_setsmui2c(unsigned int freq) ++* DESCRIPTION : ++* ***************************************************************************************/ ++extern VOLATILE void tca_ckc_setsmui2c(unsigned int freq); ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getsmui2c(void) ++* DESCRIPTION : unit : 100Hz ++* ***************************************************************************************/ ++extern VOLATILE int tca_ckc_getsmui2c(void); ++ ++/**************************************************************************************** ++* FUNCTION : void tca_ckc_setddipwdn(unsigned int lpwdn , unsigned int lmode) ++* DESCRIPTION : Power Down Register of DDI_CONFIG ++* ***************************************************************************************/ ++extern void tca_ckc_setddipwdn(unsigned int lpwdn , unsigned int lmode); ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getddipwdn(unsigned int lpwdn) ++* DESCRIPTION : Power Down Register of DDI_CONFIG ++* ***************************************************************************************/ ++extern int tca_ckc_getddipwdn(unsigned int lpwdn); ++ ++#endif /* __TCA_CKC_H__ */ ++ ++ ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/tcc_ckc_ctrl.h b/arch/arm/mach-tcc8900/include/mach/tcc_ckc_ctrl.h +new file mode 100644 +index 0000000..aa2a10c +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/tcc_ckc_ctrl.h +@@ -0,0 +1,60 @@ ++/* linux/arch/arm/mach-tcc8900/include/mach/tcc_ckc_ctrl.h ++ ++ * Author: ++ * Created: June 10, 2008 ++ * Description: Header for code common to all Telechips TCC8900/TCC83x machines. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef _TCC_CKC_CTRL_H ++#define _TCC_CKC_CTRL_H ++ ++#include ++ ++extern int arm_changestack(void); ++extern void arm_restorestack(unsigned int rst); ++ ++extern void ckc_set_peri(struct ckc_ioctl st); ++extern int ckc_get_peri(struct ckc_ioctl st); ++extern int ckc_set_peribus(struct ckc_ioctl st); ++extern int ckc_get_peribus(struct ckc_ioctl st); ++extern void ckc_set_periswreset(struct ckc_ioctl st); ++extern void ckc_set_fbusswreset(struct ckc_ioctl st); ++extern void ckc_set_cpu(struct ckc_ioctl st); ++extern void ckc_set_smui2c(struct ckc_ioctl st); ++extern unsigned int ckc_get_cpu(struct ckc_ioctl st); ++extern unsigned int ckc_get_bus(struct ckc_ioctl st); ++extern void ckc_get_validpllinfo(struct ckc_ioctl st); ++extern void ckc_set_fbus(struct ckc_ioctl st); ++extern int ckc_get_fbus(struct ckc_ioctl st); ++extern void ckc_set_pmupower(struct ckc_ioctl st); ++extern void ckc_get_pmupower(struct ckc_ioctl st); ++extern void ckc_get_clockinfo(struct ckc_ioctl st); ++extern void ckc_set_changefbus(struct ckc_ioctl st); ++extern void ckc_set_changemem(struct ckc_ioctl st); ++extern void ckc_set_changecpu(struct ckc_ioctl st); ++extern void ckc_set_ddipwdn(struct ckc_ioctl st); ++extern void ckc_get_ddipwdn(struct ckc_ioctl st); ++extern void ckc_set_etcblock(struct ckc_ioctl st); ++ ++#endif /* _TCC_CKC_CTRL_H*/ ++ +diff --git a/arch/arm/mach-tcc8900/include/mach/tcc_pca953x.h b/arch/arm/mach-tcc8900/include/mach/tcc_pca953x.h +new file mode 100644 +index 0000000..c554f6e +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/tcc_pca953x.h +@@ -0,0 +1,210 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/include/mach/tcc_pca953x.h ++ * ++ * Author: ++ * Created: 21th March, 2009 ++ * Description: Tcc250 Driver ++ * ++ * Copyright (c) Telechips, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * =============================================================================================== ++ * USAGE ++ * ======= ++ * ++ * Use "tcc_pca953x_setup()" function for management port status. ++ * ++ * 1. read operation ++ * ++ * int tcc_pca953x_setup(int slave, int name, int direction, int value, int mode); ++ * ++ * parameters ++ * ---------- ++ * int slave - PCA953x I2C slave address ++ * int name - fixed 0 ++ * int direction - direction of port [OUTPUT/INPUT] ++ * int value - fixed 0 ++ * int mode - fixed GET_VALUE ++ * ++ * return value ++ * ------------ ++ * int rd_buf - 16bit read data returned, -1 is fail ++ * ++ * example ++ * ------- ++ * // read PCA9539_U2_SLAVE_ADDR port0 and port1 ++ * int rd_buf = tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, 0, OUTPUT, 0, GET_VALUE); ++ * ++ * 2. write operation ++ * ++ * int tcc_pca953x_setup(int slave, int name, int direction, int value, int mode); ++ * ++ * parameters ++ * ---------- ++ * int slave - PCA953x I2C slave address ++ * int name - control port name, see "Expanded GPIO port map" ++ * int direction - direction of port [OUTPUT/INPUT] ++ * int value - output mode only. set port value [HIGH/LOW] ++ * int mode - [SET_DIRECTION/SET_VALUE] or [SET_DIRECTION|SET_VALUE] ++ * ++ * return value ++ * ------------ ++ * int rd_buf - 1 is success, -1 is fail ++ * ++ * example ++ * ------- ++ * + set port direction ++ * // PCA9539_U2_SLAVE_ADDR, ETH_RST, Output mode ++ * tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, ETH_RST, OUTPUT, 0, SET_DIRECTION); ++ * ++ * + set port value (output mode only) ++ * // PCA9539_U2_SLAVE_ADDR, ETH_RST, Output High ++ * tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, ETH_RST, OUTPUT, HIGH, SET_VALUE); ++ * ++ * + set both (direction & value) ++ * // PCA9539_U2_SLAVE_ADDR, ETH_RST, Output mode, Output Low ++ * tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, ETH_RST, OUTPUT, LOW, SET_DIRECTION|SET_VALUE); ++ * ++ * 3. direct read/write ++ * + read ++ * tcc_pca953x_read(PCA9539_U2_SLAVE_ADDR, PCA9539_OUTPUT_0, &buf[0]); ++ * tcc_pca953x_read(PCA9539_U2_SLAVE_ADDR, PCA9539_OUTPUT_1, &buf[1]); ++ * printk("PCA9539_U2_SLAVE_ADDR port0(%x), port1(%x)", buf[0], buf[1]); ++ * ++ * + write each port ++ * buf[0] = PCA9539_OUTPUT_0; ++ * buf[1] = 0x12; ++ * tcc_pca953x_write(PCA9539_U2_SLAVE_ADDR, &buf[0], 2); ++ * buf[0] = PCA9539_OUTPUT_1; ++ * buf[1] = 0x34; ++ * tcc_pca953x_write(PCA9539_U2_SLAVE_ADDR, &buf[0], 2); ++ * ++ * + write all port ++ * buf[0] = PCA9539_OUTPUT_0; ++ * buf[1] = 0x12; ++ * buf[2] = 0x34; ++ * tcc_pca953x_write(PCA9539_U3_SLAVE_ADDR, &buf[0], 3); ++ * ++ * =============================================================================================== ++ */ ++#ifndef __PCA953X_H__ ++#define __PCA953X_H__ ++ ++#include ++ ++ ++/* ++ * EXPORT_SYMBOL ++ */ ++extern int tcc_pca953x_setup(int slave, int name, int direction, int value, int mode); ++extern int tcc_pca953x_read(int slave, unsigned char cmd, unsigned char *rd_buf); ++extern int tcc_pca953x_write(int slave, const unsigned char *wr_buf, int count); ++ ++/* ++ * PCA953x I2C slave address ++ */ ++#define PCA9539_U2_SLAVE_ADDR 0x77 ++#define PCA9539_U3_SLAVE_ADDR 0x74 ++#define PCA9538_U4_SLAVE_ADDR 0x70 ++ ++/* ++ * Port setup mode ++ */ ++#define GET_VALUE 0x0001 ++#define SET_DIRECTION 0x0010 ++#define SET_VALUE 0x0100 ++ ++/* ++ * Port direction & value ++ */ ++#define INPUT 1 ++#define OUTPUT 0 ++#define HIGH 1 ++#define LOW 0 ++ ++/* ++ * Expanded GPIO port map ++ */ ++/* PCA9539 U2 */ ++//PORT0 ++#define ETH_RST Hw0 // DNP : Ethernet Controller Reset ++#define DXB0_RST Hw1 // DMB, DAB Reset ++#define CAM_RST Hw2 // DNP : Camera Module Reset ++#define CAS_RST Hw3 // DNP : CAS Reset ++#define AUTH_RST Hw4 // iPod Auth Reset ++#define FM_RST Hw5 // FM Transceiver Reset ++#define RTC_RST Hw6 // DNP : RTC Reset ++#define SATA_ON Hw6 // SATA_ON ++#define BT_WAKE Hw7 // DNP : Bluetooth Wakeup ++#define HDMI_ON Hw7 // HDMI_ON ++//PORT1 ++#define DXB0_IRQ Hw8 // INPUT ++#define BT_HWAKE Hw9 // INPUT : Bluetooth Host Wakeup ++#define FM_IRQ Hw10 // INPUT : FM Receiver IRQ ++#define CP_READY Hw11 // INPUT : iPod CP Ready ++#define DXB_GP0 Hw12 // DXBGP0 ++#define CAM_FL_EN Hw13 // DNP : Camera Flash Light En/Disable ++#define LCD_BL_EN Hw13 // DNP : LCD Backlight En/Disable ++#define MUTE_CTL Hw14 // Audio Mute Control ++#define CAS_GP Hw15 // CASGP ++#define TV_SLEEP Hw15 // DNP : TV Sleep Signal ++#define HDD_RST Hw15 // DNP : HDD Reset ++ ++/* PCA9539 U3 */ ++//PORT0 ++#define ATAPI_ON Hw0 // IDE Disk Interface ++#define LCD_ON Hw1 // LCD Power ++#define LVDSIVT_ON Hw2 // LVDS Inverter ++#define CAM_ON Hw3 // Camera Module Power ++#define CODEC_ON Hw4 // External Audio CODEC ++#define FMTC_ON Hw5 // FM Transceiver ++#define SD0_ON Hw6 // SD Card Slot 0 ++#define SD1_ON Hw7 // SD Card Slot 1 ++//PORT1 ++#define BT_ON Hw8 // Bluetooth ++#define CAS_ON Hw9 // CAS ++#define CAN_ON Hw10 // CAN Interface Controller ++#define ETH_ON Hw11 // Ethernet Controller ++#define DXB_ON Hw12 // DMB, DAB Power ++#define iPOD_ON Hw13 // iPOD Connection Power ++#define PWR_GP4 Hw14 // GPIO4 Power ++#define LVDS_LP_CTRL Hw15 // LVDS LCD Controller ++ ++/* PCA9538 U4 */ ++//PORT0 ++#define DVBUS_ON Hw0 // USB Device VBUS ++#define HVBUS_ON Hw1 // USB Host VBUS ++#define HDMI_LVDS_ON Hw2 // HDMI_LVDS Interface Power ++#define PWR_GP0 Hw3 // GPIO0 Power ++#define PWR_GP2 Hw4 // GPIO2 Power ++#define PWR_GP3 Hw5 // GPIO3 Power ++#define VCORE_CTL Hw6 // Core Voltage Power ++#define PWR_GP1 Hw7 // GPIO1 Power ++ ++/* ++ * PCA953x command ++ */ ++enum pca9539_cmd ++{ ++ PCA9539_INPUT_0 = 0, ++ PCA9539_INPUT_1 = 1, ++ PCA9539_OUTPUT_0 = 2, ++ PCA9539_OUTPUT_1 = 3, ++ PCA9539_INVERT_0 = 4, ++ PCA9539_INVERT_1 = 5, ++ PCA9539_DIRECTION_0 = 6, ++ PCA9539_DIRECTION_1 = 7, ++}; ++ ++enum pca9538_cmd ++{ ++ PCA9538_INPUT_0 = 0, ++ PCA9538_OUTPUT_0 = 1, ++ PCA9538_INVERT_0 = 2, ++ PCA9538_DIRECTION_0 = 3, ++}; ++ ++#endif /*__PCA953X_H__*/ +diff --git a/arch/arm/mach-tcc8900/include/mach/timex.h b/arch/arm/mach-tcc8900/include/mach/timex.h +new file mode 100644 +index 0000000..8ff927f +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/timex.h +@@ -0,0 +1,31 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/timex.h ++ * ++ * Author: Greg Lonnon ++ * Modified: ++ * ++ * Copyright (C) 2000 RidgeRun, Inc. ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#define CLOCK_TICK_RATE (HZ * 100000UL) +diff --git a/arch/arm/mach-tcc8900/include/mach/uncompress.h b/arch/arm/mach-tcc8900/include/mach/uncompress.h +new file mode 100644 +index 0000000..f72cb50 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/uncompress.h +@@ -0,0 +1,45 @@ ++/* ++ * linux/include/asm-arm/arch-tcc83x/uncompress.h ++ * ++ * Author: ++ * Modified: ++ * Modified: June 10, 2008 ++ * Description: Serial port stubs for kernel decompress status messages ++ * ++ * 2004 (c) MontaVista Software, Inc. ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This file is licensed under the terms of the GNU General Public License ++ * version 2. This program is licensed "as is" without any warranty of any ++ * kind, whether express or implied. ++ */ ++ ++#include ++#include ++ ++unsigned int system_rev; ++ ++#define ID_MASK 0x7fff ++ ++static void putc(int c) ++{ ++ volatile u8 * uart = 0; ++ int shift = 2; ++ ++ /* ++ * Now, xmit each character ++ */ ++ while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) ++ barrier(); ++ uart[UART_TX << shift] = c; ++} ++ ++static inline void flush(void) ++{ ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_setup() ++#define arch_decomp_wdog() +diff --git a/arch/arm/mach-tcc8900/include/mach/vmalloc.h b/arch/arm/mach-tcc8900/include/mach/vmalloc.h +new file mode 100644 +index 0000000..b47ade6 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/include/mach/vmalloc.h +@@ -0,0 +1,25 @@ ++/* ++ * linux/include/asm-arm/arch-tcc8900/vmalloc.h ++ * ++ * Author: ++ * Created: Feb 10, 2009 ++ * ++ * Copyright (C) 2000 Russell King. ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (PAGE_OFFSET + 0x20000000) ++ +diff --git a/arch/arm/mach-tcc8900/io.c b/arch/arm/mach-tcc8900/io.c +new file mode 100644 +index 0000000..7ba1689 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/io.c +@@ -0,0 +1,100 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/io.c ++ * ++ * Author: ++ * Created: 10th February, 2008 ++ * Description: tcc8900 mapping code ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * The machine specific code may provide the extra mapping besides the ++ * default mapping provided here. ++ */ ++static struct map_desc tcc8900_io_desc[] __initdata = { ++ { ++ .virtual = 0xF0000000, ++ .pfn = __phys_to_pfn(0xF0000000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0100000, ++ .pfn = __phys_to_pfn(0xF0100000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0200000, ++ .pfn = __phys_to_pfn(0xF0200000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0300000, ++ .pfn = __phys_to_pfn(0xF0300000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0400000, ++ .pfn = __phys_to_pfn(0xF0400000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0500000, ++ .pfn = __phys_to_pfn(0xF0500000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0600000, ++ .pfn = __phys_to_pfn(0xF0600000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xF0700000, ++ .pfn = __phys_to_pfn(0xF0700000), ++ .length = 0x100000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = 0xEFF00000, ++ .pfn = __phys_to_pfn(0x10000000), ++ .length = 0x100000, ++ .type = MT_MEMORY_TCC ++ }, ++}; ++ ++ ++/* ++ * Maps common IO regions for tcc8900. ++ */ ++void __init tcc8900_map_common_io(void) ++{ ++ iotable_init(tcc8900_io_desc, ARRAY_SIZE(tcc8900_io_desc)); ++ ++ /* Normally devicemaps_init() would flush caches and tlb after ++ * mdesc->map_io(), but we must also do it here because of the CPU ++ * revision check below. ++ */ ++ local_flush_tlb_all(); ++ flush_cache_all(); ++} +diff --git a/arch/arm/mach-tcc8900/irq.c b/arch/arm/mach-tcc8900/irq.c +new file mode 100644 +index 0000000..8a485ff +--- /dev/null ++++ b/arch/arm/mach-tcc8900/irq.c +@@ -0,0 +1,595 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/irq.c ++ * ++ * Author: ++ * Created: 10th February, 2009 ++ * Description: Interrupt handler for Telechips TCC8900 chipset ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++// Global ++static volatile PGPIO pGPIO; ++static volatile PPIC pPIC; ++static volatile PVIC pVIC; ++static volatile PGPSBPORTCFG pPGPSBPORTCFG; ++static volatile PUARTPORTMUX pUARTPORTMUX; ++static volatile PGDMACTRL pPGDMACTRL0, pPGDMACTRL1, pPGDMACTRL2, pPGDMACTRL3; ++static volatile PTIMER pTIMER; ++ ++ ++/****************************************** ++ * Disable IRQ ++ * ++ * If mask_ack exist, this is not called. ++ *****************************************/ ++static void tcc8900_mask_irq(unsigned int irq) ++{ ++ if (irq < 32) { ++ BITCLR(pPIC->INTMSK0, (1 << irq)); ++ } else { ++ BITCLR(pPIC->INTMSK1, (1 << (irq - 32))); ++ } ++} ++ ++static void tcc8900_mask_irq_uart(unsigned int irq) ++{ ++ if (irq != INT_UART) { ++ BITCLR(pPIC->INTMSK1, Hw15); ++ } ++} ++ ++static void tcc8900_mask_irq_gpsb(unsigned int irq) ++{ ++ if (irq != INT_GPSB) { ++ BITCLR(pPIC->INTMSK1, Hw4); ++ } ++} ++ ++static void tcc8900_mask_irq_dma(unsigned int irq) ++{ ++ if (irq != INT_DMA) { ++ BITCLR(pPIC->INTMSK0, Hw29); ++ } ++} ++ ++static void tcc8900_mask_irq_tc0(unsigned int irq) ++{ ++ if (irq != INT_TC0) { ++ BITCLR(pPIC->INTMSK0, Hw0); ++ } ++} ++ ++/****************************************** ++ * Enable IRQ ++ *****************************************/ ++static void tcc8900_irq_enable(unsigned int irq) ++{ ++ if (irq < 32) { ++ BITSET(pPIC->CLR0, (1 << irq)); ++ BITSET(pPIC->IEN0, (1 << irq)); ++ BITSET(pPIC->INTMSK0, (1 << irq)); ++ } else { ++ BITSET(pPIC->CLR1, (1 << (irq - 32))); ++ BITSET(pPIC->IEN1, (1 << (irq - 32))); ++ BITSET(pPIC->INTMSK1, (1 << (irq - 32))); ++ } ++} ++ ++static void tcc8900_unmask_irq(unsigned int irq) ++{ ++ if (irq < 32) { ++ BITSET(pPIC->INTMSK0, (1 << irq)); ++ BITSET(pPIC->CLR0, (1 << irq)); ++ } else { ++ BITSET(pPIC->INTMSK1, (1 << (irq - 32))); ++ BITSET(pPIC->CLR1, (1 << (irq - 32))); ++ } ++} ++static void tcc8900_unmask_irq_uart(unsigned int irq) ++{ ++ if (irq != INT_UART) { ++ BITSET(pPIC->INTMSK1, Hw15); ++ } ++} ++static void tcc8900_unmask_irq_gpsb(unsigned int irq) ++{ ++ if (irq != INT_GPSB) { ++ BITSET(pPIC->INTMSK1, Hw4); ++ } ++} ++static void tcc8900_unmask_irq_dma(unsigned int irq) ++{ ++ if (irq != INT_DMA) { ++ BITSET(pPIC->INTMSK0, Hw29); ++ } ++} ++ ++static void tcc8900_unmask_irq_tc0(unsigned int irq) ++{ ++ if (irq != INT_TC0) { ++ BITSET(pPIC->INTMSK0, Hw0); ++ } ++} ++ ++/****************************************** ++ * Ack IRQ (Disable IRQ) ++ *****************************************/ ++ ++static void tcc8900_irq_disable(unsigned int irq) ++{ ++ if (irq < 32){ ++ BITCLR(pPIC->IEN0, (1 << irq)); ++ BITCLR(pPIC->INTMSK0, (1 << irq)); ++ } else { ++ BITCLR(pPIC->IEN1, (1 << (irq - 32))); ++ BITCLR(pPIC->INTMSK1, (1 << (irq - 32))); ++ } ++} ++ ++ ++static void tcc8900_mask_ack_irq(unsigned int irq) ++{ ++ if (irq < 32){ ++ BITCLR(pPIC->INTMSK0, (1 << irq)); ++ } else { ++ BITCLR(pPIC->INTMSK1, (1 << (irq - 32))); ++ } ++} ++ ++static void tcc8900_mask_ack_irq_uart(unsigned int irq) ++{ ++ if (irq != INT_UART) { ++ BITCLR(pPIC->INTMSK1, Hw15); ++ } ++} ++ ++static void tcc8900_mask_ack_irq_gpsb(unsigned int irq) ++{ ++ if (irq != INT_GPSB) { ++ BITCLR(pPIC->INTMSK1, Hw4); ++ } ++} ++ ++static void tcc8900_mask_ack_irq_dma(unsigned int irq) ++{ ++ if (irq != INT_DMA) { ++ BITCLR(pPIC->INTMSK0, Hw29); ++ } ++} ++ ++static void tcc8900_mask_ack_irq_tc0(unsigned int irq) ++{ ++ if (irq != INT_TC0) { ++ BITCLR(pPIC->INTMSK0, Hw0); ++ } ++} ++ ++/****************************************** ++ * wake IRQ ++ *****************************************/ ++static int tcc8900_wake_irq(unsigned int irq, unsigned int enable) ++{ ++ return 0; ++} ++ ++static int tcc8900_wake_irq_uart(unsigned int irq, unsigned int enable) ++{ ++ return 0; ++} ++ ++static int tcc8900_wake_irq_gpsb(unsigned int irq, unsigned int enable) ++{ ++ return 0; ++} ++ ++static int tcc8900_wake_irq_dma(unsigned int irq, unsigned int enable) ++{ ++ return 0; ++} ++ ++static int tcc8900_wake_irq_tc0(unsigned int irq, unsigned int enable) ++{ ++ return 0; ++} ++ ++static void tcc8900_irq_dummy(unsigned int irq) ++{ ++} ++ ++static void tcc8900_irq_uart_handler(unsigned irq, struct irq_desc *desc) ++{ ++ if (pUARTPORTMUX->CHST & Hw0) { ++ irq = INT_UART0; ++ } else if (pUARTPORTMUX->CHST & Hw1) { ++ irq = INT_UART1; ++ } else if (pUARTPORTMUX->CHST & Hw2) { ++ irq = INT_UART2; ++ } else if (pUARTPORTMUX->CHST & Hw3) { ++ irq = INT_UART3; ++ } else if (pUARTPORTMUX->CHST & Hw4) { ++ irq = INT_UART4; ++ } else if (pUARTPORTMUX->CHST & Hw5) { ++ irq = INT_UART5; ++ } else { ++ //BITSET(pPIC->INTMSK1 , Hw15); // using INTMSK ++ BITSET(pPIC->CLR1, Hw15); ++ goto out; ++ } ++ ++ desc = irq_desc + irq; ++ desc_handle_irq(irq, desc); ++out: ++ return; ++} ++ ++static void tcc8900_irq_gpsb_handler(unsigned irq, struct irq_desc *desc) ++{ ++ if (pPGPSBPORTCFG->CIRQST & Hw3) { ++ irq = INT_GPSB1_DMA; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw1) { ++ irq = INT_GPSB0_DMA; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw5) { ++ irq = INT_GPSB2_DMA; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw3) { ++ irq = INT_GPSB0_CORE; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw0) { ++ irq = INT_GPSB1_CORE; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw2) { ++ irq = INT_GPSB2_CORE; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw6) { ++ irq = INT_GPSB3_CORE; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw8) { ++ irq = INT_GPSB4_CORE; ++ } else if (pPGPSBPORTCFG->CIRQST & Hw10) { ++ irq = INT_GPSB5_CORE; ++ } else { ++ //BITSET(pPIC->INTMSK1 , Hw4); // using INTMSK ++ BITSET(pPIC->CLR1, Hw4); ++ goto out; ++ } ++ ++ desc = irq_desc + irq; ++ desc_handle_irq(irq, desc); ++out: ++ return; ++} ++ ++static void tcc8900_irq_dma_handler(unsigned irq, struct irq_desc *desc) ++{ ++ if (pPGDMACTRL0->CHCONFIG & (Hw18|Hw17|Hw16)) { ++ if (pPGDMACTRL0->CHCONFIG & Hw16) { ++ irq = INT_DMA0_CH0; ++ } else if (pPGDMACTRL0->CHCONFIG & Hw17) { ++ irq = INT_DMA0_CH1; ++ } else if (pPGDMACTRL0->CHCONFIG & Hw18) { ++ irq = INT_DMA0_CH2; ++ } else { ++ goto out1; ++ } ++ } else if (pPGDMACTRL1->CHCONFIG & (Hw18|Hw17|Hw16)) { ++ if (pPGDMACTRL1->CHCONFIG & Hw16) { ++ irq = INT_DMA1_CH0; ++ } else if (pPGDMACTRL1->CHCONFIG & Hw17) { ++ irq = INT_DMA1_CH1; ++ } else if (pPGDMACTRL1->CHCONFIG & Hw18) { ++ irq = INT_DMA1_CH2; ++ } else { ++ goto out1; ++ } ++ ++ } else if (pPGDMACTRL2->CHCONFIG & (Hw18|Hw17|Hw16)) { ++ if (pPGDMACTRL2->CHCONFIG & Hw16) { ++ irq = INT_DMA2_CH0; ++ } else if (pPGDMACTRL2->CHCONFIG & Hw17) { ++ irq = INT_DMA2_CH1; ++ } else if (pPGDMACTRL2->CHCONFIG & Hw18) { ++ irq = INT_DMA2_CH2; ++ } else { ++ goto out1; ++ } ++ ++ } else if (pPGDMACTRL3->CHCONFIG & (Hw18|Hw17|Hw16)) { ++ if (pPGDMACTRL3->CHCONFIG & Hw16) { ++ irq = INT_DMA3_CH0; ++ } else if (pPGDMACTRL3->CHCONFIG & Hw17) { ++ irq = INT_DMA3_CH1; ++ } else if (pPGDMACTRL3->CHCONFIG & Hw18) { ++ irq = INT_DMA3_CH2; ++ } else { ++ goto out1; ++ } ++ ++ } else { ++out1: ++ BITSET(pPIC->CLR0, Hw29); ++ goto out2; ++ } ++ ++ desc = irq_desc + irq; ++ desc_handle_irq(irq, desc); ++out2: ++ return; ++} ++ ++static void tcc8900_irq_tc0_handler(unsigned irq, struct irq_desc *desc) ++{ ++ if (pTIMER->TIREQ & Hw0) { ++ irq = INT_TC0_TI0; ++ } else if (pTIMER->TIREQ & Hw1) { ++ irq = INT_TC0_TI1; ++ } else if (pTIMER->TIREQ & Hw2) { ++ irq = INT_TC0_TI2; ++ } else if (pTIMER->TIREQ & Hw3) { ++ irq = INT_TC0_TI3; ++ } else if (pTIMER->TIREQ & Hw4) { ++ irq = INT_TC0_TI4; ++ } else if (pTIMER->TIREQ & Hw5) { ++ irq = INT_TC0_TI5; ++ } else { ++ //BITSET(pPIC->INTMSK1 , Hw0); // using INTMSK ++ BITSET(pPIC->CLR0, Hw0); ++ goto out; ++ } ++ ++ desc = irq_desc + irq; ++ desc_handle_irq(irq, desc); ++out: ++ return; ++} ++ ++ ++static struct irq_chip tcc8900_irq_chip = { ++ .name = "IRQ", ++ .enable = tcc8900_irq_enable, ++ .disable = tcc8900_irq_disable, ++ .ack = tcc8900_mask_ack_irq, ++ .mask_ack = tcc8900_mask_ack_irq, ++ .mask = tcc8900_mask_irq, ++ .unmask = tcc8900_unmask_irq, ++ .set_wake = tcc8900_wake_irq, ++}; ++ ++static struct irq_chip tcc8900_irq_uart_chip = { ++ .name = "IRQ_UART", ++ .enable = tcc8900_irq_dummy, ++ .disable = tcc8900_irq_dummy, ++ .ack = tcc8900_mask_ack_irq_uart, ++ .mask_ack = tcc8900_mask_ack_irq_uart, ++ .mask = tcc8900_mask_irq_uart, ++ .unmask = tcc8900_unmask_irq_uart, ++ .set_wake = tcc8900_wake_irq_uart, ++}; ++ ++static struct irq_chip tcc8900_irq_gpsb_chip = { ++ .name = "IRQ_GPSB", ++ .enable = tcc8900_irq_dummy, ++ .disable = tcc8900_irq_dummy, ++ .ack = tcc8900_mask_ack_irq_gpsb, ++ .mask_ack = tcc8900_mask_ack_irq_gpsb, ++ .mask = tcc8900_mask_irq_gpsb, ++ .unmask = tcc8900_unmask_irq_gpsb, ++ .set_wake = tcc8900_wake_irq_gpsb, ++}; ++ ++static struct irq_chip tcc8900_irq_dma_chip = { ++ .name = "IRQ_DMA", ++ .enable = tcc8900_irq_dummy, ++ .disable = tcc8900_irq_dummy, ++ .ack = tcc8900_mask_ack_irq_dma, ++ .mask_ack = tcc8900_mask_ack_irq_dma, ++ .mask = tcc8900_mask_irq_dma, ++ .unmask = tcc8900_unmask_irq_dma, ++ .set_wake = tcc8900_wake_irq_dma, ++}; ++ ++static struct irq_chip tcc8900_irq_tc0_chip = { ++ .name = "IRQ_TC0", ++ .enable = tcc8900_irq_dummy, ++ .disable = tcc8900_irq_dummy, ++ .ack = tcc8900_mask_ack_irq_tc0, ++ .mask_ack = tcc8900_mask_ack_irq_tc0, ++ .mask = tcc8900_mask_irq_tc0, ++ .unmask = tcc8900_unmask_irq_tc0, ++ .set_wake = tcc8900_wake_irq_tc0, ++}; ++ ++void __init tcc8900_irq_init(void) ++{ ++ int irqno; ++ ++ printk("%s\n", __func__); ++ ++ //reset interrupt ++ pGPIO = (volatile PGPIO)tcc_p2v(HwGPIO_BASE); ++ pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE); ++ pVIC = (volatile PVIC)tcc_p2v(HwVIC_BASE); ++ pPGPSBPORTCFG = (volatile PGPSBPORTCFG)tcc_p2v(HwGPSBPORTCFG_BASE); ++ pUARTPORTMUX = (volatile PUARTPORTMUX)tcc_p2v(HwUARTPORTMUX_BASE); ++ pPGDMACTRL0 = (volatile PGDMACTRL)tcc_p2v(HwGDMA0_BASE); ++ pPGDMACTRL1 = (volatile PGDMACTRL)tcc_p2v(HwGDMA1_BASE); ++ pPGDMACTRL2 = (volatile PGDMACTRL)tcc_p2v(HwGDMA2_BASE); ++ pPGDMACTRL3 = (volatile PGDMACTRL)tcc_p2v(HwGDMA3_BASE); ++ pTIMER = (volatile PTIMER)tcc_p2v(HwTMR_BASE); ++ ++ ++ /* ADD IOREMAP */ ++ ++ //clear IEN Field ++ BITCLR(pPIC->IEN0 , 0xFFFFFFFF); // All Interrupt Disable ++ BITCLR(pPIC->IEN1 , 0xFFFFFFFF); // All Interrupt Disable ++ ++ //clear SEL Field ++ BITSET(pPIC->SEL0 , 0xFFFFFFFF); //using IRQ ++ BITSET(pPIC->SEL1 , 0xFFFFFFFF); //using IRQ ++ ++ //clear TIG Field ++ BITCLR(pPIC->TIG0 , 0xFFFFFFFF); //Test Interrupt Disable ++ BITCLR(pPIC->TIG1 , 0xFFFFFFFF); //Test Interrupt Disable ++ ++ //clear POL Field ++ BITCLR(pPIC->POL0 , 0xFFFFFFFF); //Default ACTIVE Low ++ BITCLR(pPIC->POL1 , 0xFFFFFFFF); //Default ACTIVE Low ++ ++ //clear MODE Field ++ BITSET(pPIC->MODE0 , 0xFFFFFFFF); //Trigger Mode - Level Trigger Mode ++ BITSET(pPIC->MODE1 , 0xFFFFFFFF); //Trigger Mode - Level Trigger Mode ++ ++ //clear SYNC Field ++ BITSET(pPIC->SYNC0 , 0xFFFFFFFF); //SYNC Enable ++ BITSET(pPIC->SYNC1 , 0xFFFFFFFF); //SYNC Enable ++ ++ //clear WKEN Field ++ BITCLR(pPIC->WKEN0 , 0xFFFFFFFF); //Wakeup all disable ++ BITCLR(pPIC->WKEN1 , 0xFFFFFFFF); //Wakeup all disable ++ ++ //celar MODEA Field ++ BITCLR(pPIC->MODEA0 , 0xFFFFFFFF); //both edge - all disable ++ BITCLR(pPIC->MODEA1 , 0xFFFFFFFF); //both edge - all disable ++ ++ //clear INTMSK Field ++ BITCLR(pPIC->INTMSK0 , 0xFFFFFFFF); //not using INTMSK ++ BITCLR(pPIC->INTMSK1 , 0xFFFFFFFF); //not using INTMSK ++ ++ //clear ALLMSK Field ++ BITCSET(pPIC->ALLMSK , 0xFFFFFFFF, 0x1); //using only IRQ ++ ++ /* Install the interrupt handlers */ ++ for(irqno = INT_TC0; irqno <= INT_AEIRQ; irqno++) ++ { ++ if (irqno == INT_UART) { ++ set_irq_chip(INT_UART, &tcc8900_irq_uart_chip); ++ set_irq_chained_handler(INT_UART, tcc8900_irq_uart_handler); ++ } else if (irqno == INT_GPSB) { ++ set_irq_chip(INT_GPSB, &tcc8900_irq_gpsb_chip); ++ set_irq_chained_handler(INT_GPSB, tcc8900_irq_gpsb_handler); ++ } else if (irqno == INT_DMA) { ++ set_irq_chip(INT_DMA, &tcc8900_irq_dma_chip); ++ set_irq_chained_handler(INT_DMA, tcc8900_irq_dma_handler); ++ } else if (irqno == INT_TC0) { ++ set_irq_chip(INT_TC0, &tcc8900_irq_tc0_chip); ++ set_irq_chained_handler(INT_TC0, tcc8900_irq_tc0_handler); ++ } else { ++ set_irq_chip(irqno, &tcc8900_irq_chip); ++ set_irq_handler(irqno, handle_level_irq); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ } ++ ++ /* Install the interrupt UART Group handlers */ ++ for (irqno = INT_UART0; irqno <= INT_UART5; irqno++) { ++ set_irq_chip(irqno, &tcc8900_irq_uart_chip); ++ set_irq_handler(irqno, handle_level_irq); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ ++ /* Install the interrupt GPSB Group handlers */ ++ for (irqno = INT_GPSB0_DMA; irqno <= INT_GPSB5_CORE; irqno++) { ++ set_irq_chip(irqno, &tcc8900_irq_gpsb_chip); ++ set_irq_handler(irqno, handle_level_irq); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ ++ /* Install the interrupt DMA Group handlers */ ++ for (irqno = INT_DMA0_CH0; irqno <= INT_DMA3_CH2; irqno++) { ++ set_irq_chip(irqno, &tcc8900_irq_dma_chip); ++ set_irq_handler(irqno, handle_level_irq); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ ++ /* Install the interrupt TC0 Group handlers */ ++ for (irqno = INT_TC0_TI0; irqno <= INT_TC0_TI5; irqno++) { ++ set_irq_chip(irqno, &tcc8900_irq_tc0_chip); ++ set_irq_handler(irqno, handle_level_irq); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ ++ ++ /* IEN SET */ ++ BITSET(pPIC->IEN1, Hw15); /* UART */ ++ BITSET(pPIC->INTMSK1, Hw15); /* UART */ ++ BITSET(pPIC->IEN1, Hw4); /* GPSB */ ++ BITSET(pPIC->INTMSK1, Hw4); /* GPSB */ ++ BITSET(pPIC->IEN0, Hw29); /* DMA */ ++ BITSET(pPIC->INTMSK0, Hw29); /* DMA */ ++ BITSET(pPIC->IEN0, Hw0); /* TC0 */ ++ BITSET(pPIC->INTMSK0, Hw0); ++ ++ BITCSET(pGPIO->EINTSEL2, Hw6-Hw0, 26<<0); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1<EINTSEL2, Hw14-Hw8, 27<<8); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1<EINTSEL2, Hw22-Hw16, 28<<16); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1<EINTSEL2, Hw30-Hw24, 38<<24); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1<EINTSEL1, Hw14-Hw8, 24<<8); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1<EINTSEL1, Hw22-Hw16, 25<<16); ++ BITSET(pPIC->INTMSK0, 1<MODE0, 1<POL0, 1<MODEA0, 1< ++ * Created: October, 2009 ++ * Description: LINUX POWER MANAGEMENT FUNCTIONS ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * ++ * ChangeLog: ++ * ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include // sys_sync() ++#include ++#include ++#include // local_flush_tlb_all(), flush_cache_all(); ++ ++#include ++#include ++#include ++#include "pm.h" ++ ++#include ++ ++#define BUS_CONTROL ++ ++#define GPIOSIZE (16 * 6 + 8) ++#define SRAM_ADDR_STANDBY 0xEFF00000 ++unsigned long bkreg[GPIOSIZE]; ++ ++typedef void (* lpfunc)(int); ++static lpfunc lpSelfRefresh; ++ ++extern void IO_ARM_SaveREG(int sram_addr, unsigned int p89reg, void *); ++extern void Awake_address(void); ++extern void tca_bkl_powerup(unsigned int tmr_vaddr, unsigned int gpio_vaddr); ++ ++ ++static void tcc_gpio_default(unsigned int gpio_vaddr) ++{ ++ PGPIO pGPIO = (PGPIO)gpio_vaddr; ++ ++ /* GPC */ ++ pGPIO->GPCDAT = 0x0000000; // 0x080 R/W 0x00000000 GPC Data Register ++ pGPIO->GPCEN = 0xFFFFFFFF; // 0x084 R/W 0x00000000 GPC Output Enable Register ++ ++ //pGPIO->GPCPD1 &= ~Hw6; //pull - up remove ++ //pGPIO->GPCPD1 &= ~Hw7; //pull - down remove ++ ++ pGPIO->GPCPD0 = 0; //pull - up ++ pGPIO->GPCPD1 = 0; //pull - up ++ ++ pGPIO->GPCFN0 = 0x00000000; // 0x0A4 W 0x00000000 Port Configuration on GPC Output Data ++ pGPIO->GPCFN1 = 0x00000000; // 0x0A8 W 0x00000000 Port Configuration on GPC Output Data ++ pGPIO->GPCFN2 = 0x00000000; // 0x0AC W 0x00000000 Port Configuration on GPC Output Data ++ pGPIO->GPCFN3 = 0x00000000; // 0x0B0 W 0x00000000 Port Configuration on GPC Output Data ++ ++ /* GPD */ ++ pGPIO->GPDDAT = 0x00000000; // 0x0C0 R/W 0x00000000 GPD Data Register ++ pGPIO->GPDEN = 0x00000000; // 0x0C4 R/W 0x00000000 GPD Output Enable Register ++ pGPIO->GPDFN0 = 0x00000000; // 0x0E4 W 0x00000000 Port Configuration on GPD Output Data ++ pGPIO->GPDFN1 = 0x00000000; // 0x0E8 W 0x00000000 Port Configuration on GPD Output Data ++ pGPIO->GPDFN2 = 0x00000000; // 0x0EC W 0x00000000 Port Configuration on GPD Output Data ++ pGPIO->GPDFN3 = 0x00000000; // 0x0F0 W 0x00000000 Port Configuration on GPD Output Data ++ ++ /* GPE */ ++ pGPIO->GPEDAT = 0x00000000; // 0x100 R/W 0x00000000 GPE Data Register ++ pGPIO->GPEEN = 0x0F000000; // 0x104 R/W 0x00000000 GPE Output Enable Register ++ pGPIO->GPEFN0 = 0x00000000; // 0x124 W 0x00000000 Port Configuration on GPE Output Data ++ pGPIO->GPEFN1 = 0x00000000; // 0x128 W 0x00000000 Port Configuration on GPE Output Data ++ pGPIO->GPEFN2 = 0x00000000; // 0x12C W 0x00000000 Port Configuration on GPE Output Data ++ pGPIO->GPEFN3 = 0x00000000; // 0x130 W 0x00000000 Port Configuration on GPE Output Data ++ ++ /* GPF */ ++ pGPIO->GPFDAT = 0x00000000|Hw6; // 0x140 R/W 0x00000000 GPF Data Register ++ pGPIO->GPFEN = 0xffffffff; // 0x144 R/W 0x00000000 GPF Output Enable Register ++ pGPIO->GPFFN0 = 0x00000000; // 0x164 W 0x00000000 Port Configuration on GPF Output Data ++ pGPIO->GPFFN1 = 0x00000000; // 0x168 W 0x00000000 Port Configuration on GP Output Data ++ pGPIO->GPFFN2 = 0x00000000; // 0x16C W 0x00000000 Port Configuration on GPF Output Data ++ pGPIO->GPFFN3 = 0x00000000; // 0x170 W 0x00000000 Port Configuration on GPF Output Data ++ ++ /* EXTEND */ ++ pGPIO->EINTSEL0 = 0x00000000; // 0x184 R/W 0x00000000 External Interrupt Select Register 01 ++ pGPIO->EINTSEL1 = 0x00000000; // 0x188 R/W 0x00000000 External Interrupt Select Register 1 ++ pGPIO->EINTSEL2 = 0x00000000; // 0x18C R/W 0x00000000 External Interrupt Select Register 2 ++ pGPIO->MON = 0x00000000; // 0x190 R/W 0x00000000 System Monitor Enable Register ++ pGPIO->ECID0 = 0x00000000; // 0x194 R/W 0x00000000 CID output Register ++ pGPIO->ECID1 = 0x00000000; // 0x198 R - CID serial input Register ++ pGPIO->ECID2 = 0x00000000; // 0x19C R - CID parallel input 0 Register ++ pGPIO->ECID3 = 0x00000000; ++} ++ ++static void tcc_init_console(void) ++{ ++ PUART pUART = (PUART)tcc_p2v(HwUARTCH0_BASE); ++ PGPIO pGPIO = (PGPIO)tcc_p2v(HwGPIO_BASE); ++ ++ pUART->LCR = Hw4 | Hw2 | Hw1 | Hw0; ++ pUART->LCR &= ~Hw7; //HwUART0_LCR_DLAB_OFF; //HwUART1_LCR_DLAB_OFF; ++ pUART->REG2.IER = 0; ++ pUART->LCR |= Hw7; //HwUART0_LCR_DLAB_ON; ++ pUART->REG3.FCR = Hw5|Hw4|Hw2|Hw1|Hw0; //HwUART0_FCR_TXFR_EN | HwUART0_FCR_RXFR_EN | HwUART0_FCR_FE_EN; ++ pUART->REG1.DLL = 28; ++ pUART->REG2.DLM = 0; ++ pUART->LCR &= ~Hw7; ++ pUART->REG2.IER = Hw0; ++ ++ pGPIO->GPEEN |= (Hw1|Hw0); ++ pGPIO->GPEFN0 |= (Hw4|Hw0); // UTXD0, URXD0 ++} ++ ++static void tcc_store_gpio(unsigned int gpio_vaddr) ++{ ++ int i = 0; ++ PGPIO pGPIO = (PGPIO)gpio_vaddr; ++ ++ for(i = 0 ; i < GPIOSIZE-8 ; i++ ) { ++ switch (i % 16) { ++ case 2: ++ case 3: ++ case 4: ++ case 13: ++ case 14: ++ case 15: ++ break; ++ default: ++ bkreg[i] = *((volatile unsigned int *)(gpio_vaddr + 4 * i)); ++ break; ++ } ++ } ++ ++ bkreg[GPIOSIZE-8] = pGPIO->EINTSEL0; ++ bkreg[GPIOSIZE-8+1] = pGPIO->EINTSEL1; ++ bkreg[GPIOSIZE-8+2] = pGPIO->EINTSEL2; ++ bkreg[GPIOSIZE-8+3] = pGPIO->MON; ++ bkreg[GPIOSIZE-8+4] = pGPIO->ECID0; ++ ++ tcc_gpio_default(gpio_vaddr); ++} ++ ++static void tcc_restore_gpio(unsigned int gpio_vaddr) ++{ ++ int i = 0; ++ PGPIO pGPIO = (PGPIO)gpio_vaddr; ++ ++ for (i = 0; i < GPIOSIZE-8; i++) { ++ switch (i % 16) { ++ case 2: ++ case 3: ++ case 4: ++ case 13: ++ case 14: ++ case 15: ++ break; ++ default: ++ *((volatile unsigned int *)(gpio_vaddr + 4 * i)) = bkreg[i]; ++ break; ++ } ++ } ++ ++ pGPIO->EINTSEL0 = bkreg[GPIOSIZE-8]; ++ pGPIO->EINTSEL1 = bkreg[GPIOSIZE-8+1]; ++ pGPIO->EINTSEL2 = bkreg[GPIOSIZE-8+2]; ++ pGPIO->MON = bkreg[GPIOSIZE-8+3]; ++ pGPIO->ECID0 = bkreg[GPIOSIZE-8+4]; ++} ++ ++ ++/***************************************************************************** ++* Function Name : tca_off_sdramselfrefresh() ++* DRAM into Self Refresh ++******************************************************************************/ ++static void ddr2_self_refresh(void) ++{ ++ volatile unsigned int nCount = 0; ++ ++ *(volatile unsigned long *)0xF0102004 |= Hw2; // GPIOADAT == corebus ++ nCount = *(volatile unsigned long *)0xF0102000; ++ ++ /* Enter Self-Refresh Mode */ ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2) // Wait PL34X_STATUS_PAUSED ++ ; ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=3) // Wait PL34X_STATUS_LOWPOWER ++ ; ++ ++ /* To prevent input leakage */ ++ *(volatile unsigned long *)0xF0304400 |= 0x00000004; ++ /* DLL OFF */ ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ nCount = ((*(volatile unsigned long *)0xF030200C) & ~(0x00004000)); ++ *(volatile unsigned long *)0xF030200C = nCount| (1<<14); // Stop-MCLK Enter Self-refresh mode ++ ++ for (nCount = 1600; nCount > 0; nCount --) // Wait ++ ; ++ ++ *(volatile unsigned long *)0xF0400000 = 0x002ffff4; // CKC-CLKCTRL0 - set cpu clk to XIN ++ *(volatile unsigned long *)0xF0400004 = 0x00200014; // CKC-CLKCTRL1 - set display clk to XIN ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // CKC-CLKCTRL2 - set memory clk to XIN ++ *(volatile unsigned long *)0xF040000c = 0x00200014; // CKC-CLKCTRL3 - set graphic clk to XIN ++ *(volatile unsigned long *)0xF0400010 = 0x00200014; // CKC-CLKCTRL4 - set io clk to XIN ++ ++ *(volatile unsigned long *)0xF0400014 = 0x00200014; // CKC-CLKCTRL5 - set video bus clk to XIN ++ *(volatile unsigned long *)0xF0400018 = 0x00200014; // CKC-CLKCTRL6 - set video core clk to XIN ++ *(volatile unsigned long *)0xF040001c = 0x00200014; // CKC-CLKCTRL7 - set SMU clk to XIN ++ ++#if 0 ++*(volatile unsigned long *)0xF0404000 |= 0x00000002; // PMU-CONTROL - Power Off ++#endif ++ ++ *(volatile unsigned long *)0xF0400020 &= ~0x80000000; // CKC-PLL0CFG - PLL disable ++ *(volatile unsigned long *)0xF0400024 &= ~0x80000000; // CKC-PLL1CFG - PLL disable ++ *(volatile unsigned long *)0xF0400028 &= ~0x80000000; // CKC-PLL2CFG - PLL disable ++ *(volatile unsigned long *)0xF040002c &= ~0x80000000; // CKC-PLL3CFG - PLL disable ++ ++#if 0 ++*(volatile unsigned long *)0xF0404001 = 0x00000000; ++*(volatile unsigned long *)0xF0404002 = 0x00000000; ++*(volatile unsigned long *)0xF0404008 = 0x00000000; ++*(volatile unsigned long *)0xF0404020 = 0x00000000; ++*(volatile unsigned long *)0xF0404000 |= 0x00000002; // PMU-CONTROL - Power Off ++#endif ++ ++ while (1) { ++ *(volatile unsigned long *)0xF0102000 &= ~Hw2; ++ *(volatile unsigned long *)0xF0102000 &= ~Hw2; ++ } ++} ++ ++/***************************************************************************** ++* Function Name : suspend_mode_on() ++******************************************************************************/ ++//static void suspend_mode_on(void) ++void suspend_mode_on(void) ++{ ++ volatile unsigned int nCount = 0; ++ ++ TCC_REG *p89reg; ++ unsigned int *pVaddr; ++ unsigned int *pPaddr; ++ ++ CKC *ckc = (CKC *)tcc_p2v(HwCLK_BASE); ++ PIC *pic = (PIC *)tcc_p2v(HwPIC_BASE); ++ VIC *vic = (VIC *)tcc_p2v(HwVIC_BASE); ++ TIMER *timer = (TIMER *)tcc_p2v(HwTMR_BASE); ++ PMU *pmu = (PMU *)tcc_p2v(HwPMU_BASE); ++ GPIO *gpio = (GPIO *)tcc_p2v(HwGPIO_BASE); ++ //DRAM *dram= (DRAM *)tcc_p2v(HwDRAM_BASE); ++ //DRAMMX *drammx= (DRAMMX *)tcc_p2v(HwDRAM_BASE); ++ //DRAMPHY *dramphy= (DRAMPHY *)tcc_p2v(HwDRAMPHY_BASE); ++ //DRAMMISC *drammisc= (DRAMMISC *)tcc_p2v(HwDRAMMISC_BASE); ++ //DRAMMEMBUS *drammembus= (DRAMMEMBUS *)tcc_p2v(HwDRAMMEMBUS_BASE); ++ MISCCOREBUS *misccorebus= (MISCCOREBUS *)tcc_p2v(HwCORECFG_BASE); ++ IOBUSCFG *iobuscfg= (IOBUSCFG *)tcc_p2v(HwIOBUSCFG_BASE); ++ TSADC *tsadc = (TSADC *)tcc_p2v(HwTSADC_BASE); ++ ++ VMTREGION *vmtregion = (VMTREGION *)tcc_p2v(HwREGION_BASE); //twkwon ++ ++ //SMUI2CMASTER *smui2cmaster0 = (SMUI2CMASTER*)tcc_p2v(HwSMU_I2CMASTER0_BASE); ++ //SMUI2CMASTER *smui2cmaster1 = (SMUI2CMASTER*)tcc_p2v(HwSMU_I2CMASTER1_BASE); ++ //SMUI2CICLK *smui2ciclk = (SMUI2CICLK*)tcc_p2v(HwSMU_I2CICLK_BASE); ++ ++ DDICONFIG *ddiconfig = (DDICONFIG*)tcc_p2v(HwDDI_CONFIG_BASE); ++ DDICACHE *ddicache = (DDICACHE*)tcc_p2v(HwDDI_CACHE_BASE); ++ ++ USBHOST11 *usbhost11 = (USBHOST11*)tcc_p2v(HwUSBHOST_BASE); ++ USBHOST11CFG *usbhost11cfg = (USBHOST11CFG*)tcc_p2v(HwUSBHOSTCFG_BASE); ++ ++ //USB20OTG *usb20otg = (USB20OTG*)tcc_p2v(HwUSB20OTG_BASE); ++ //USBOTGCFG *usbotgconfig = (USBOTGCFG*)tcc_p2v(HwUSBOTGCFG_BASE); ++ //USBPHYCFG *usbphycfg = (USBPHYCFG*)tcc_p2v(HwUSBPHYCFG_BASE); ++ ++ RTC *rtc = (RTC *)tcc_p2v(HwRTC_BASE); ++ //NFC *nfc = (NFC *)tcc_p2v(HwNFC_BASE); ++ //LCDC *lcdc0 = (LCDC *)tcc_p2v(HwLCDC0_BASE); ++ //LCDC *lcdc1 = (LCDC *)tcc_p2v(HwLCDC1_BASE); ++ ++ //M2MSCALER *m2mscaler0 = (M2MSCALER *)tcc_p2v(HwM2MSCALER0_BASE); ++ //M2MSCALER *m2mscaler1 = (M2MSCALER *)tcc_p2v(HwM2MSCALER1_BASE); ++ ++ UARTPORTMUX *uartportmux = (UARTPORTMUX *)tcc_p2v(HwUARTPORTMUX_BASE); ++ ++/* ++ * BACKUP REGISTER ++ */ ++ pPaddr = ioremap_nocache(DRAM_PHYS_ADDRESS, PAGE_ALIGN(sizeof(unsigned int))); ++ pVaddr = ioremap_nocache(DRAM_VIRT_ADDRESS, PAGE_ALIGN(sizeof(unsigned int))); ++ p89reg = ioremap_nocache(DRAM_DATA_ADDRESS, PAGE_ALIGN(sizeof(TCC_REG))); ++ ++ /* backup iobus state */ ++ p89reg->backup_peri_iobus0 = *(volatile unsigned long *)0xF05F5010; ++ p89reg->backup_peri_iobus1 = *(volatile unsigned long *)0xF05F5014; ++ /* all peri io bus on */ ++ *(volatile unsigned long *)0xF05F5010 = 0xFFFFFFFF; ++ *(volatile unsigned long *)0xF05F5014 |= 0x7; ++ ++ memcpy(&p89reg->ckc, ckc, sizeof(CKC)); ++ memcpy(&p89reg->pic, pic, sizeof(PIC)); ++ memcpy(&p89reg->vic, vic, sizeof(VIC)); ++ memcpy(&p89reg->timer, timer, sizeof(TIMER)); ++ memcpy(&p89reg->pmu, pmu, sizeof(PMU)); ++ memcpy(&p89reg->gpio, gpio, sizeof(GPIO)); ++ //memcpy(&p89reg->dram, dram, sizeof(DRAM)); ++ //memcpy(&p89reg->drammx, drammx, sizeof(DRAMMX)); ++ //memcpy(&p89reg->dramphy, dramphy, sizeof(DRAMPHY)); ++ //memcpy(&p89reg->drammisc, drammisc, sizeof(DRAMMISC)); ++ //memcpy(&p89reg->drammembus, drammembus, sizeof(DRAMMEMBUS)); ++ memcpy(&p89reg->misccorebus, misccorebus, sizeof(MISCCOREBUS)); ++ memcpy(&p89reg->iobuscfg, iobuscfg, sizeof(IOBUSCFG)); ++ memcpy(&p89reg->tsadc, tsadc, sizeof(TSADC)); ++ ++ memcpy(&p89reg->vmtregion, vmtregion, sizeof(VMTREGION)); //twkwon ++ ++ //memcpy(&p89reg->smui2cmaster0, smui2cmaster0, sizeof(SMUI2CMASTER)); ++ //memcpy(&p89reg->smui2cmaster1, smui2cmaster1, sizeof(SMUI2CMASTER)); ++ //memcpy(&p89reg->smui2ciclk, smui2ciclk, sizeof(SMUI2CICLK)); ++ memcpy(&p89reg->ddiconfig, ddiconfig, sizeof(DDICONFIG)); ++ memcpy(&p89reg->ddicache, ddicache, sizeof(DDICACHE)); ++ ++ memcpy(&p89reg->usbhost11, usbhost11, sizeof(USBHOST11)); ++ memcpy(&p89reg->usbhost11cfg, usbhost11cfg, sizeof(USBHOST11CFG)); ++ //memcpy(&p89reg->usb20otg, usb20otg, sizeof(USB20OTG)); ++ //memcpy(&p89reg->usbotgconfig, usbotgconfig, sizeof(USBOTGCFG)); ++ //memcpy(&p89reg->usbphycfg, usbphycfg, sizeof(USBPHYCFG)); ++ ++ memcpy(&p89reg->rtc, rtc, sizeof(RTC)); ++ //memcpy(&p89reg->nfc, nfc, sizeof(NFC)); ++ ++ //memcpy(&p89reg->lcdc0, lcdc0, sizeof(LCDC)); ++ //memcpy(&p89reg->lcdc1, lcdc1, sizeof(LCDC)); ++ //memcpy(&p89reg->m2mscaler0, m2mscaler0, sizeof(M2MSCALER)); ++ //memcpy(&p89reg->m2mscaler1, m2mscaler1, sizeof(M2MSCALER)); ++ ++ memcpy(&p89reg->uartportmux,uartportmux,sizeof(UARTPORTMUX)); ++ ++ p89reg->uMASK = BSP_SUSPEND_MASK; ++ *pVaddr = (unsigned int)p89reg; ++ *pPaddr = DRAM_DATA_ADDRESS; ++ ++#if 0 ++ /* flush TLB and I/D cache */ ++ local_flush_tlb_all(); ++ flush_cache_all(); ++ IO_ARM_SaveREG(0x10000000, p89reg, Awake_address); ++#else ++ IO_ARM_SaveREG(SRAM_ADDR_STANDBY, (unsigned int)p89reg, Awake_address); ++#endif ++ ++ __asm__ __volatile__ ("nop\n"); ++ ++/* ++ * RESTORE REGISTER ++ */ ++ for (nCount = 100; nCount > 0; nCount --) ++ ; ++ ++ /* all peri io bus on */ ++ *(volatile unsigned long *)0xF05F5010 = 0xFFFFFFFF; ++ *(volatile unsigned long *)0xF05F5014 |= 0x7; ++ ++ ckc = (CKC *)tcc_p2v(HwCLK_BASE); ++ pic = (PIC *)tcc_p2v(HwPIC_BASE); ++ vic = (VIC *)tcc_p2v(HwVIC_BASE); ++ timer = (TIMER *)tcc_p2v(HwTMR_BASE); ++ pmu = (PMU *)tcc_p2v(HwPMU_BASE); ++ gpio = (GPIO *)tcc_p2v(HwGPIO_BASE); ++ //dram= (DRAM *)tcc_p2v(HwDRAM_BASE); ++ //drammx= (DRAMMX *)tcc_p2v(HwDRAM_BASE); ++ //dramphy= (DRAMPHY *)tcc_p2v(HwDRAMPHY_BASE); ++ //drammisc= (DRAMMISC *)tcc_p2v(HwDRAMMISC_BASE); ++ //drammembus= (DRAMMEMBUS *)tcc_p2v(HwDRAMMEMBUS_BASE); ++ misccorebus= (MISCCOREBUS *)tcc_p2v(HwCORECFG_BASE); ++ iobuscfg= (IOBUSCFG *)tcc_p2v(HwIOBUSCFG_BASE); ++ tsadc = (TSADC *)tcc_p2v(HwTSADC_BASE); ++ ++ vmtregion = (VMTREGION *)tcc_p2v(HwREGION_BASE); //twkwon ++ //usbphycfg = (USBPHYCFG *)tcc_p2v(HwUSBPHYCFG_BASE); ++ ++ //smui2cmaster0 = (SMUI2CMASTER*)tcc_p2v(HwSMU_I2CMASTER0_BASE); ++ //smui2cmaster1 = (SMUI2CMASTER*)tcc_p2v(HwSMU_I2CMASTER1_BASE); ++ //smui2ciclk = (SMUI2CICLK*)tcc_p2v(HwSMU_I2CICLK_BASE); ++ ++ ddiconfig = (DDICONFIG*)tcc_p2v(HwDDI_CONFIG_BASE); ++ ddicache = (DDICACHE*)tcc_p2v(HwDDI_CACHE_BASE); ++ ++ usbhost11 = (USBHOST11*)tcc_p2v(HwUSBHOST_BASE); ++ usbhost11cfg = (USBHOST11CFG*)tcc_p2v(HwUSBHOSTCFG_BASE); ++ ++ //usb20otg = (USB20OTG*)tcc_p2v(HwUSB20OTG_BASE); ++ //usbotgconfig = (USBOTGCFG*)tcc_p2v(HwUSBOTGCFG_BASE); ++ //usbphycfg = (USBPHYCFG*)tcc_p2v(HwUSBPHYCFG_BASE); ++ ++ rtc = (RTC *)tcc_p2v(HwRTC_BASE); ++ //nfc = (NFC *)tcc_p2v(HwNFC_BASE); ++ //lcdc0 = (LCDC *)tcc_p2v(HwLCDC0_BASE); ++ //lcdc1 = (LCDC *)tcc_p2v(HwLCDC1_BASE); ++ ++ //m2mscaler0 = (M2MSCALER *)tcc_p2v(HwM2MSCALER0_BASE); ++ //m2mscaler1 = (M2MSCALER *)tcc_p2v(HwM2MSCALER1_BASE); ++ ++ uartportmux = (UARTPORTMUX *)tcc_p2v(HwUARTPORTMUX_BASE); ++ ++ memcpy(ckc, &p89reg->ckc, sizeof(CKC)); ++ memcpy(pic, &p89reg->pic, sizeof(PIC)); ++ memcpy(vic, &p89reg->vic, sizeof(VIC)); ++ memcpy(timer, &p89reg->timer, sizeof(TIMER)); ++ memcpy(pmu, &p89reg->pmu, sizeof(PMU)); ++ memcpy(gpio, &p89reg->gpio, sizeof(GPIO)); ++ //memcpy(dram, &p89reg->dram, sizeof(DRAM)); ++ //memcpy(drammx, &p89reg->drammx, sizeof(DRAMMX)); ++ //memcpy(dramphy, &p89reg->dramphy, sizeof(DRAMPHY)); ++ //memcpy(drammisc, &p89reg->drammisc, sizeof(DRAMMISC)); ++ //memcpy(drammembus, &p89reg->drammembus, sizeof(DRAMMEMBUS)); ++ memcpy(misccorebus, &p89reg->misccorebus, sizeof(MISCCOREBUS)); ++ memcpy(iobuscfg, &p89reg->iobuscfg, sizeof(IOBUSCFG)); ++ ++ memcpy(tsadc, &p89reg->tsadc, sizeof(TSADC)); ++ ++ memcpy(vmtregion, &p89reg->vmtregion, sizeof(VMTREGION)); //twkwon ++ ++ //memcpy(smui2cmaster0, &p89reg->smui2cmaster0, sizeof(SMUI2CMASTER)); ++ //memcpy(smui2cmaster1, &p89reg->smui2cmaster1, sizeof(SMUI2CMASTER)); ++ //memcpy(smui2ciclk, &p89reg->smui2ciclk, sizeof(SMUI2CICLK)); ++ memcpy(ddiconfig, &p89reg->ddiconfig, sizeof(DDICONFIG)); ++ memcpy(ddicache, &p89reg->ddicache, sizeof(DDICACHE)); ++ ++ memcpy(usbhost11, &p89reg->usbhost11, sizeof(USBHOST11)); ++ memcpy(usbhost11cfg, &p89reg->usbhost11cfg, sizeof(USBHOST11CFG)); ++ //memcpy(usb20otg, &p89reg->usb20otg, sizeof(USB20OTG)); ++ //memcpy(usbotgconfig, &p89reg->usbotgconfig, sizeof(USBOTGCFG)); ++ //memcpy(usbphycfg, &p89reg->usbphycfg, sizeof(USBPHYCFG)); ++ ++ memcpy(rtc, &p89reg->rtc, sizeof(RTC)); ++ //memcpy(nfc, &p89reg->nfc, sizeof(NFC)); ++ ++ //memcpy(lcdc0, &p89reg->lcdc0, sizeof(LCDC)); ++ //memcpy(lcdc1, &p89reg->lcdc1, sizeof(LCDC)); ++ //memcpy(m2mscaler0, &p89reg->m2mscaler0, sizeof(M2MSCALER)); ++ //memcpy(m2mscaler1, &p89reg->m2mscaler1, sizeof(M2MSCALER)); ++ ++ memcpy(uartportmux, &p89reg->uartportmux, sizeof(UARTPORTMUX)); ++ ++ //all peri io bus restore ++ *(volatile unsigned long *)0xF05F5010 = p89reg->backup_peri_iobus0; ++ *(volatile unsigned long *)0xF05F5014 = p89reg->backup_peri_iobus1; ++ ++ iounmap(pPaddr); ++ iounmap(pVaddr); ++ iounmap(p89reg); ++} ++ ++/************************************************************************************************ ++* FUNCTION : sleep_mode_on ++* DESCRIPTION : This Function have to be executed in SRAM. ++* All Registers related to Clock are Backed up. ++************************************************************************************************/ ++static void sleep_mode_on(int type) ++{ ++ volatile unsigned int nCount = 0; ++ ++ unsigned long *lPLL0, *lPLL1, *lPLL2, *lPLL3; ++ unsigned long *lFBUS_CORE, *lFBUS_MEM, *lFBUS_DDI, *lFBUS_GRP, *lFBUS_IOB, *lFBUS_VBUS, *lFBUS_VCODEC, *lFBUS_SMU; ++ unsigned long *i, *pPCK, *BAKPCK; ++ ++ unsigned long *BACK4, *BACK5; //for pmu backup ++ ++ int lmem_div = 0; ++ int lmem_source = 0; ++ int tmpread = *(volatile unsigned long *)0xF0400008; ++ ++ tmpread &= ~0x00200000; ++ lmem_source = tmpread & 0xf; ++ tmpread &= 0xf0; ++ ++ while (tmpread) { ++ tmpread -= 16; ++ lmem_div++; ++ } ++ ++ lmem_div += 1; ++ ++ /* Let CPU Speed Lower, Low Clock Operation */ ++ /* Assign Registers to Pointers */ ++ lPLL0 = (unsigned long *)(SRAM_ADDR_VAR); ++ lPLL1 = (unsigned long *)(SRAM_ADDR_VAR + 0x04); ++ lPLL2 = (unsigned long *)(SRAM_ADDR_VAR + 0x08); ++ lPLL3 = (unsigned long *)(SRAM_ADDR_VAR + 0x0C); ++ BACK4 = (unsigned long *)(SRAM_ADDR_VAR + 0x10); ++ BACK5 = (unsigned long *)(SRAM_ADDR_VAR + 0x14); ++ lFBUS_CORE = (unsigned long *)(SRAM_ADDR_VAR + 0x18); ++ lFBUS_MEM = (unsigned long *)(SRAM_ADDR_VAR + 0x1C); ++ lFBUS_DDI = (unsigned long *)(SRAM_ADDR_VAR + 0x20); ++ lFBUS_GRP = (unsigned long *)(SRAM_ADDR_VAR + 0x24); ++ lFBUS_IOB = (unsigned long *)(SRAM_ADDR_VAR + 0x28); ++ lFBUS_VBUS = (unsigned long *)(SRAM_ADDR_VAR + 0x30); ++ lFBUS_VCODEC = (unsigned long *)(SRAM_ADDR_VAR + 0x34); ++ lFBUS_SMU = (unsigned long *)(SRAM_ADDR_VAR + 0x38); ++ i = (unsigned long *)(SRAM_ADDR_VAR + 0x3C); ++ BAKPCK = (unsigned long *)(SRAM_ADDR_VAR + 0x40); ++ ++ *lFBUS_CORE = *(volatile unsigned long *)0xF0400000; ++ *lFBUS_DDI = *(volatile unsigned long *)0xF0400004; ++ *lFBUS_MEM = *(volatile unsigned long *)0xF0400008; ++ *lFBUS_GRP = *(volatile unsigned long *)0xF040000C; ++ *lFBUS_IOB = *(volatile unsigned long *)0xF0400010; ++ *lFBUS_VBUS = *(volatile unsigned long *)0xF0400014; ++ *lFBUS_VCODEC = *(volatile unsigned long *)0xF0400018; ++ *lFBUS_SMU = *(volatile unsigned long *)0xF040001C; ++ ++ *lPLL0 = *(volatile unsigned long *)0xF0400020; ++ *lPLL1 = *(volatile unsigned long *)0xF0400024; ++ *lPLL2 = *(volatile unsigned long *)0xF0400028; ++ *lPLL3 = *(volatile unsigned long *)0xF040002c; ++ ++ /* Save All of PCK_XXX Register */ ++ pPCK = (unsigned long *)(0xF0400080); ++ ++ for (*i = 0; *i < 37; (*i)++ ) { ++ BAKPCK[*i] = *pPCK; ++ if (((BAKPCK[*i] & 0x1f000000) != 0x14000000)) { ++ *pPCK = (BAKPCK[*i] & ~0x10000000); ++ } ++ pPCK++; ++ } ++ ++ *BACK4 = *(volatile unsigned long *)0xF0404004; ++ *BACK5 = *(volatile unsigned long *)0xF0404000; ++ *BACK5 = *(volatile unsigned long *)0xF0240050; ++ ++ *BACK4 = (*(volatile unsigned long *)0xF0404018) & 0xFF; ++ ++ /* Enter Self-Refresh Mode */ ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2) //Wait PL34X_STATUS_PAUSED ++ ; ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=3) // Wait PL34X_STATUS_LOWPOWER ++ ; ++ ++ /* To prevent input leakage */ ++ *(volatile unsigned long *)0xF0304400 |= 0x00000004; ++ ++ /* DLL OFF */ ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302c &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ nCount = ((*(volatile unsigned long *)0xF030200C) & ~(0x00004000)); ++ *(volatile unsigned long *)0xF030200C = nCount| (1<<14); // Stop-MCLK Enter Self-refresh mode ++ ++ /* DRAM controller power down */ ++ *(volatile unsigned long *)0xF030302C =0x3fff; ++ *(volatile unsigned long *)0xF030302C &= ~Hw14; ++ for (nCount = 0; nCount < 10; nCount++) ++ ; ++ *(volatile unsigned long *)0xF0304400 = 0x2; ++ for (nCount = 0; nCount < 10; nCount++) ++ ; ++ *(volatile unsigned long *)0xF0304404 &= ~(Hw0|Hw1); ++ *(volatile unsigned long *)0xF0304428 &= ~(Hw0|Hw1); ++ *(volatile unsigned long *)0xF0304428 |= Hw12; ++ *(volatile unsigned long *)0xF0304428 |= Hw0; ++ ++ *(volatile unsigned long *)0xF0304400 = 0x6; ++ ++ for (nCount = 800; nCount > 0; nCount --) // Wait ++ ; ++ for (nCount = 800; nCount > 0; nCount --) // Wait ++ ; ++ ++ *(volatile unsigned long *)0xF0400000 = 0x002ffff4; // CKC-CLKCTRL0 - set cpu clk to XIN ++ *(volatile unsigned long *)0xF0400004 = 0x00200014; // CKC-CLKCTRL1 - set display clk to XIN ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // CKC-CLKCTRL2 - set memory clk to XIN ++ ++ *(volatile unsigned long *)0xF040000c = 0x00200014; // CKC-CLKCTRL3 - set graphic clk to XIN ++ *(volatile unsigned long *)0xF0400010 = 0x00200014; // CKC-CLKCTRL4 - set io clk to XIN ++ ++ *(volatile unsigned long *)0xF0400014 = 0x00200014; // CKC-CLKCTRL5 - set video bus clk to XIN ++ *(volatile unsigned long *)0xF0400018 = 0x00200014; // CKC-CLKCTRL6 - set video core clk to XIN ++ *(volatile unsigned long *)0xF040001c = 0x00200014; // CKC-CLKCTRL7 - set SMU clk to XIN ++ ++ *(volatile unsigned long *)0xF0400020 &= ~0x80000000; // CKC-PLL0CFG - PLL disable ++ *(volatile unsigned long *)0xF0400024 &= ~0x80000000; // CKC-PLL1CFG - PLL disable ++ *(volatile unsigned long *)0xF0400028 &= ~0x80000000; // CKC-PLL2CFG - PLL disable ++ *(volatile unsigned long *)0xF040002c &= ~0x80000000; // CKC-PLL3CFG - PLL disable ++ ++ for (nCount = 100; nCount > 0 ;nCount --); // Wait ++ ++ /* go power down mode...... */ ++ ++ *(volatile unsigned long *)0xF01020EC &= ~(0x00000f00); ++ *(volatile unsigned long *)0xF01020C4 &= ~(0x00040000); ++ ++ if(type == 0) ++ { ++ *(volatile unsigned long *)0xF0404008 = 0x00002800; // PMU-WKUPPOL - SRCS[15](GPIO A3) active low ++ *(volatile unsigned long *)0xF0404004 = 0x00002800; // PMU-WKUPEN - SRCS[15](GPIO A3) enable ++ }else if(type == 1) ++ { ++ *(volatile unsigned long *)0xF0404008 = 0x00000800; ++ *(volatile unsigned long *)0xF0404004 = 0x00000800; ++ ++ }else if(type == 2) ++ { ++ *(volatile unsigned long *)0xF0404008 = 0x00002000; ++ *(volatile unsigned long *)0xF0404004 = 0x00002000; ++ }else ++ { ++ *(volatile unsigned long *)0xF0404008 = 0x00002800; ++ *(volatile unsigned long *)0xF0404004 = 0x00002800; ++ } ++ ++#ifdef BUS_CONTROL ++ *(volatile unsigned long *)0xF0240050 |= Hw0; ++ *(volatile unsigned long *)0xF0404018 &= ~0x1F; ++ for (nCount = 5000; nCount > 0; nCount --) // delay ++ ; ++ *(volatile unsigned long *)0xF0404018 |= 0x1F; ++ ++ /* Video Bus, DDi Bus, Graphic Bus, IO Bus off */ ++ /* SWRESET ON */ ++// *(volatile unsigned long *)0xF0400044 |= Hw6|Hw5; // Graphic Bus ++// *(volatile unsigned long *)0xF0400044 |= Hw3; // Video Bus ++// *(volatile unsigned long *)0xF0400044 |= Hw1; // Ddi Bus ++// for (nCount = 5000; nCount > 0; nCount --) // delay ++// ; ++ ++ /* pmu disable */ ++// *(volatile unsigned long *)0xF0404018 |= Hw8; // Graphic Bus ++// *(volatile unsigned long *)0xF0404018 |= Hw6; // Video Bus ++// *(volatile unsigned long *)0xF0404018 |= Hw7; // Ddi Bus ++ ++ for (nCount = 1000; nCount > 0; nCount --) // Wait ++ ; ++#endif ++ ++ *(volatile unsigned long *)0xF0404000 |= 0x00000004; // PMU-CONTROL - Power Down(BSP default) ++ for (nCount = 10; nCount > 0; nCount --) // Wait ++ ; ++ ++ *(volatile unsigned long *)0xF0400020 = *lPLL0; ++ *(volatile unsigned long *)0xF0400024 = *lPLL1; ++ *(volatile unsigned long *)0xF0400028 = *lPLL2; ++ *(volatile unsigned long *)0xF040002c = *lPLL3; ++ ++ /* wakeup start */ ++#ifdef BUS_CONTROL ++ for (nCount = 1000; nCount > 0; nCount --) // Wait ++ ; ++ /* pmu disable */ ++// *(volatile unsigned long *)0xF0404018 &= ~Hw8; // Graphic Bus ++// *(volatile unsigned long *)0xF0404018 &= ~Hw6; // Video Bus ++// *(volatile unsigned long *)0xF0404018 &= ~Hw7; // Ddi Bus ++// for (nCount = 10000; nCount > 0; nCount --) // delay ++// ; ++ ++ /* SWRESET OFF */ ++// *(volatile unsigned long *)0xF0400044 &= ~(Hw6|Hw5); // Graphic Bus ++// *(volatile unsigned long *)0xF0400044 &= ~(Hw3); // Video Bus ++// *(volatile unsigned long *)0xF0400044 &= ~(Hw1); // Ddi Bus ++ *(volatile unsigned long *)0xF0404018 = *BACK4; ++ *(volatile unsigned long *)0xF0240050 = *BACK5; ++#endif ++ ++ for (nCount = 10; nCount > 0; nCount --) // Wait ++ ; ++ ++ *(volatile unsigned long *)0xF0400000 = *lFBUS_CORE; ++ *(volatile unsigned long *)0xF0400008 = *lFBUS_MEM; ++ ++ pPCK = (unsigned long*)(0xF0400080); ++ ++ for((*i) = 0; (*i) < 37; (*i)++) { ++ *pPCK++ = BAKPCK[*i]; ++ } ++ ++ for (nCount = 0x100; nCount > 0; nCount --) // Wait ++ ; ++ ++ *(volatile unsigned long *)0xF0400004 = *lFBUS_DDI; ++ *(volatile unsigned long *)0xF040000C = *lFBUS_GRP; ++ *(volatile unsigned long *)0xF0400010 = *lFBUS_IOB; ++ *(volatile unsigned long *)0xF0400014 = *lFBUS_VBUS; ++ *(volatile unsigned long *)0xF0400018 = *lFBUS_VCODEC; ++ *(volatile unsigned long *)0xF040001C = *lFBUS_SMU; ++ ++ /* Exit Self-Refresh Mode */ ++ *(volatile unsigned long *)0xF030200C &= ~(0x00004000); ++ *(volatile unsigned long *)0xF0304400 &= ~(0x00000004); ++ ++ //*(volatile unsigned long *)0xF0302004 = 0x00000002; // PL341_WakeUP ++ //while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ //*(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ //while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ //*(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ //while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ //*(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ //while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=3); // Wait PL34X_STATUS_LOWPOWER ++ ++ /* DLL ON */ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ *(volatile unsigned long *)0xF0303020 |= 0x00000001; // Common Register AXI_SEL ++ *(volatile unsigned long *)0xF0303020 |= 0x00000002; // Common Register IO_SEL ++ *(volatile unsigned long *)0xF0303024 &= ~(0x00000100); // PHYCTRL Seletct DDR2 ++ ++ *(volatile unsigned long *)0xF0304400 = 0x0; ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLL-On ++ ++ /* 330Mhz */ ++ if (lmem_div == 1) { ++ if ((*lPLL0/1) >= 400 && lmem_source == 0) { ++ *(volatile unsigned long *)0xF0304408 = 0x00001212; // DLLPDCFG ++ } else { ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ } ++ } else { ++ if ((*lPLL0/2) >= 400 && lmem_source == 0) { ++ *(volatile unsigned long *)0xF0304408 = 0x00001212; // DLLPDCFG ++ } else { ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ } ++ } ++ ++ ++ //*(volatile unsigned long *)0xF0304408 = 0x00001414; // DLLPDCFG ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLL-On, DLL-Start ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)) // Wait DLL Lock ++ ; ++ ++ *(volatile unsigned long *)0xF0304424 = 0x35; // DLL Force Lock Value Register ++ *(volatile unsigned long *)0xF030440C = 0x6; // Gate Control ++ ++ if (lmem_div == 1) { ++ if ((*lPLL0/1) >= 400 && lmem_source == 0) { ++ *(volatile unsigned long *)0xF0304430 = 0x1; // uRDDELAY Read Delay Register ++ } else { ++ *(volatile unsigned long *)0xF0304430 = 0x4; // uRDDELAY Read Delay Register ++ } ++ } else { ++ if ((*lPLL0/2) >= 400 && lmem_source == 0) { ++ *(volatile unsigned long *)0xF0304430 = 0x1; // uRDDELAY Read Delay Register ++ } else { ++ *(volatile unsigned long *)0xF0304430 = 0x4; // uRDDELAY Read Delay Register ++ } ++ } ++ ++ /* ++ *(volatile unsigned long *)0xF0304428 = 0 ++ | (0x1 << 0) // Calibration Start ++ | (0x0 << 1) // Update Calibration ++ | (0x0 << 2) // Override ctrl_force_impp[2:0]/impn[2:0] ++ | (0x2 << 3) // Calibration PULL-UP forced value ++ | (0x5 << 6) // Calibration PULL-DOWN forced value ++ | (0x0 << 9) // On-Die Termination Resistor Value Selection ++ | (0x1 << 12) // Termination Selection : 0 for disable ++ | (0x4 << 13) // Drive Strength ++ | (0x0 << 16) // Periodic Calibration ++ | (0x3 << 17) // Update Counter Load Value ++ ; ++ */ ++ ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ /* ZQCalWait */ ++ while (((*(volatile unsigned long *)0xF030442C & (0x00000001)) != (0x00000001))) ++ ; ++ ++ /* ZQCalUpdate */ ++ *(volatile unsigned long *)0xF0304428 |= 0x00000002; ++ *(volatile unsigned long *)0xF0304428 &= ~0x00000002; ++ /* END DLL On */ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL341_WakeUP ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3) != 2) //Wait PL34X_STATUS_PAUSED ++ ; ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3) != 0) //Wait PL34X_STATUS_CONFIG ++ ; ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3) != 1) //Wait PL34X_STATUS_READY ++ ; ++} ++ ++/************************************************************************************************ ++* FUNCTION : copy_func_to_sram ++* ++* DESCRIPTION : This Function copies sleep_mode_on Function to SRAM. ++* mode 0: sleep mode, mode 1: suspend mode ++* ++************************************************************************************************/ ++extern int noneed_respond; ++extern int sleep_type; ++extern void set_hdmi_en(int sw); ++static void copy_func_to_sram(int mode) ++{ ++ volatile unsigned int *fPtr, *p; ++ int i, hdmi_change = 0; ++ ++ PTIMER vTimerAddr = (PTIMER)((unsigned int)&HwTMR_BASE); ++ PGPIO vGpioAddr = (PGPIO)((unsigned int)&HwGPIO_BASE); ++ /* ++ * copy function sleep_mode_on to SRAM ++ */ ++ ++ if (1) { ++ fPtr = (volatile unsigned int *)sleep_mode_on; ++ lpSelfRefresh = (lpfunc)SRAM_ADDR_STANDBY; ++ p = (volatile unsigned int *)SRAM_ADDR_STANDBY; ++ ++ for (i = 0; i < SRAM_FUNC_SIZE; i++) { ++ *(p++) = *(fPtr++); ++ } ++ ++ while (--i) ++ ; ++ ++ if(gpio_get_value(GPIO_HDMI_EN)) ++ { ++ hdmi_change = 1; ++ set_hdmi_en(0); ++ } ++ ++ noneed_respond = 1;// ignore first touch when wakeup ++ ++ *(volatile unsigned long *)0xF0102024 &= ~(0xff0000);// set gpio func ++ *(volatile unsigned long *)0xF0102004 |= 0x30;// set GPIOA4 and GPIOA5 as output ++ *(volatile unsigned long *)0xF0102000 &= ~(0x30);//turn off lcd power and backlight ++ ++ // Jump to SRAM excute self-refresh mode ++ lpSelfRefresh(sleep_type); ++ ++ *(volatile unsigned long *)0xF0102000 |= 0x10;//turn on a4 ++ tca_bkl_powerup((unsigned int)vTimerAddr,(unsigned int)vGpioAddr);//turn on backlight ++ ++ if(hdmi_change) ++ set_hdmi_en(1); ++ ++ } else if (mode == BSP_SUSPEND_KEY) { ++ fPtr = (volatile unsigned int *)ddr2_self_refresh; ++ p = (volatile unsigned int *)SRAM_ADDR_STANDBY; ++ ++ for (i = 0; i < SRAM_FUNC_SIZE; i++) { ++ *(p++) = *(fPtr++); ++ } ++ ++ while (--i) ++ ; ++ ++ suspend_mode_on(); ++ } ++} ++ ++void enter_sleep_mode(void) ++{ ++ unsigned int temp; ++ PGPIO pGPIO = (PGPIO)tcc_p2v(HwGPIO_BASE); ++ ++ volatile PLCDC pLCDC_BASE0 = (volatile PLCDC)tcc_p2v(HwLCDC0_BASE); ++ volatile PLCDC pLCDC_BASE1 = (volatile PLCDC)tcc_p2v(HwLCDC1_BASE); ++ ++// tcc_store_gpio((unsigned int)pGPIO); ++ ++ temp = *(volatile unsigned long *)0xF0102024; // GPIOAFN == corebus ++ temp = *(volatile unsigned long *)0xF0102004; // ++ temp = *(volatile unsigned long *)0xF0230000; ++ temp = *(volatile unsigned long *)0xF0404018; ++ temp = *(volatile unsigned long *)0xF0400044; ++ ++ temp = *(volatile unsigned long *)0xF0400000; ++ temp = *(volatile unsigned long *)0xF0400004; ++ temp = *(volatile unsigned long *)0xF0400008; ++ temp = *(volatile unsigned long *)0xF040000c; ++ temp = *(volatile unsigned long *)0xF0400010; ++ temp = *(volatile unsigned long *)0xF0400014; ++ temp = *(volatile unsigned long *)0xF0400018; ++ temp = *(volatile unsigned long *)0xF040001c; ++ ++ temp = *(volatile unsigned long *)0xF0240050; ++ temp = *(volatile unsigned long *)0xF030302C; ++ temp = *(volatile unsigned long *)0xF0304400; ++ temp = *(volatile unsigned long *)0xF0304404; ++ temp = *(volatile unsigned long *)0xF0304428; ++ ++ pLCDC_BASE1->LCTRL &= ~Hw0; ++// pLCDC_BASE0->LCTRL &= ~Hw0; ++ ++ copy_func_to_sram(BSP_SLEEP_KEY); ++ ++ pLCDC_BASE1->LCTRL |= Hw0; ++ ++// tcc_restore_gpio((unsigned int)pGPIO); ++ ++ tcc_init_console(); ++} ++EXPORT_SYMBOL(enter_sleep_mode); ++ ++void enter_suspend_mode(void) ++{ ++ unsigned int temp; ++ ++ temp = *(volatile unsigned long *)0xF0400000; // pll0 == corebus ++ temp = *(volatile unsigned long *)0xF0102024; // GPIOAFN == corebus ++ temp = *(volatile unsigned long *)0xF0102004; // GPIOAEN == corebus ++ temp = *(volatile unsigned long *)0xF0102000; // GPIOADAT == corebus ++ ++ temp = *(volatile unsigned long *)0xF05F5010; // iobus ++ temp = *(volatile unsigned long *)0xF05F5014; // iobus ++ ++#if 1 ++// test ++ temp = *(volatile unsigned long *)0xF0302004; // PL341_PAUSE ++ temp = *(volatile unsigned long *)0xF0302000; // Wait PL34X_STATUS_PAUSED ++ temp = *(volatile unsigned long *)0xF0304400; ++ temp = *(volatile unsigned long *)0xF0304404; // DLL-0FF,DLL-Stop running ++ temp = *(volatile unsigned long *)0xF0304428; // Calibration Start,Update Calibration ++ temp = *(volatile unsigned long *)0xF030302C; //SDRAM IO Control Register Gatein Signal Power Down ++ temp = *(volatile unsigned long *)0xF030200C; ++ temp = *(volatile unsigned long *)0xF0400004; // CKC-CLKCTRL1 - set display clk to XIN ++ temp = *(volatile unsigned long *)0xF0400008; // CKC-CLKCTRL2 - set memory clk to XIN ++ temp = *(volatile unsigned long *)0xF040000c; // CKC-CLKCTRL3 - set graphic clk to XIN ++ temp = *(volatile unsigned long *)0xF0400010; // CKC-CLKCTRL4 - set io clk to XIN ++ temp = *(volatile unsigned long *)0xF0400014; // CKC-CLKCTRL5 - set video bus clk to XIN ++ temp = *(volatile unsigned long *)0xF0400018; // CKC-CLKCTRL6 - set video core clk to XIN ++ temp = *(volatile unsigned long *)0xF040001c; // CKC-CLKCTRL7 - set SMU clk to XIN ++ temp = *(volatile unsigned long *)0xF0400020; // CKC-PLL0CFG - PLL disable ++ temp = *(volatile unsigned long *)0xF0400024; // CKC-PLL1CFG - PLL disable ++ temp = *(volatile unsigned long *)0xF0400028; // CKC-PLL2CFG - PLL disable ++ temp = *(volatile unsigned long *)0xF040002c; // CKC-PLL3CFG - PLL disable ++#endif ++ ++ copy_func_to_sram(BSP_SUSPEND_KEY); ++} ++ ++#if 0 ++/************************************************************************************************ ++* FUNCTION : tcc_pm ++* ++* DESCRIPTION : It is called by Power key driver. ++* ++************************************************************************************************/ ++int tcc_pm(int mode) ++{ ++ int err = 0; ++ unsigned long save_cpsr; ++ // PTIMER vTimerAddr = (PTIMER)((unsigned int)&HwTMR_BASE); ++ // PGPIO vGpioAddr = (PGPIO)((unsigned int)&HwGPIO_BASE); ++ ++ /* ++ * all filesystem flush especially SD/MMC ++ */ ++ sys_sync(); ++ ++ /* ++ * send SUSPEND message to all platform driver ++ */ ++ err = device_suspend(PMSG_SUSPEND); ++ if (err){ ++ printk("device_suspend() fail\n"); ++ goto exit; ++ } ++ ++ /* ++ * Before enter Power Down Mode, MUST mask CPSR Irq bit ++ */ ++ local_irq_save(save_cpsr); ++ local_irq_disable(); ++ ++ if (mode == BSP_SUSPEND_KEY) { ++ enter_suspend_mode(); ++ } else if (mode == BSP_SLEEP_KEY) { ++ enter_sleep_mode(); ++ } ++ ++ /* ++ * backlight ON ++ */ ++ //tca_bkl_init((unsigned int)vTimerAddr, (unsigned int)vGpioAddr); ++ //tca_bkl_powerup((unsigned int)vTimerAddr,(unsigned int)vGpioAddr); ++ ++ /* ++ * console init ++ */ ++ tcc_init_console(); ++ ++ /* ++ * restore CPSR Irq bit ++ */ ++ local_irq_restore(save_cpsr); ++ ++ /* ++ * send RESUME message to all platform driver ++ */ ++ device_resume(PMSG_RESUME); ++ ++exit: ++ return err; ++} ++EXPORT_SYMBOL(tcc_pm); ++#endif ++ ++#if 0 /* comment by csduan */ ++#define TCC_PM_STATE_NORMAL 0x249 ++static int tcc_power_state = TCC_PM_STATE_NORMAL; ++static int tcc_pm_enter(suspend_state_t state) ++{ ++ if (tcc_power_state == BSP_SUSPEND_KEY) { ++ enter_suspend_mode(); ++ } else if (tcc_power_state == BSP_SLEEP_KEY) { ++ enter_sleep_mode(); ++ } ++ ++ tcc_init_console(); ++ return 0; ++} ++ ++static int tcc_pm_begin(suspend_state_t state) ++{ ++ return 0; ++} ++ ++static int tcc_pm_prepare(void) ++{ ++ return 0; ++} ++ ++static void tcc_pm_finish(void) ++{ ++} ++ ++static struct platform_suspend_ops tcc_pm_ops = { ++ .valid = suspend_valid_only_mem, ++ .begin = tcc_pm_begin, ++ .prepare = tcc_pm_prepare, ++ .enter = tcc_pm_enter, ++ .finish = tcc_pm_finish, ++}; ++ ++static void tcc_pm_power_off(void) ++{ ++ while (1) ++ ; ++} ++ ++static int __init tcc_pm_init(void) ++{ ++ pm_power_off = tcc_pm_power_off; ++ suspend_set_ops(&tcc_pm_ops); ++ return 0; ++} ++__initcall(tcc_pm_init); ++ ++#endif /* comment by csduan */ +diff --git a/arch/arm/mach-tcc8900/pm.h b/arch/arm/mach-tcc8900/pm.h +new file mode 100644 +index 0000000..4008b26 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/pm.h +@@ -0,0 +1,186 @@ ++/* ++ * arch/arm/mach-tcc8900/pm.h ++ * ++ * Author: ++ * Created: April 21, 2008 ++ * Description: LINUX POWER MANAGEMENT FUNCTIONS ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++#ifndef __TCC_PM_H__ ++#define __TCC_PM_H__ ++ ++#define BSP_SUSPEND_MASK 0x424E4654 /* "TFNB" */ ++ ++#define BSP_SUSPEND_KEY 0x2491 ++#define BSP_SLEEP_KEY 0x2492 ++ ++/* SRAM (on-chip 16KB) addr: physical 0x10000000 -> virtual 0xEFF00000 */ ++#define SRAM_ADDR_STANDBY 0xEFF00000 ++#define SRAM_ADDR_VAR 0xEFF01000 ++#define SRAM_FUNC_SIZE 0x300 ++ ++/* SDRAM start address for backup (kernel start - MMU(1MB) - 1MB) */ ++#define DRAM_PHYS_ADDRESS 0x40100000 ++#define DRAM_VIRT_ADDRESS 0x40100004 ++#define DRAM_DATA_ADDRESS 0x40100008 ++ ++ ++ ++typedef struct _TCC_REG_{ ++ unsigned int uMASK; // 0x00 ++ ++ unsigned int SleepState_WakeAddr; // 0x04 ++ ++ unsigned int SleepState_SYSCTL; // 0x08 ++ unsigned int SleepState_MMUTTB0; // 0x0C ++ unsigned int SleepState_MMUTTB1; // 0x10 ++ unsigned int SleepState_MMUTTBCTL; // 0x14 ++ unsigned int SleepState_MMUDOMAIN; // 0x18 ++ ++ unsigned int SleepState_SVC_SP; // 0x1C ++ unsigned int SleepState_SVC_SPSR; // 0x20 ++ unsigned int SleepState_FIQ_SPSR; // 0x24 ++ unsigned int SleepState_FIQ_R8; // 0x28 ++ unsigned int SleepState_FIQ_R9; // 0x2C ++ unsigned int SleepState_FIQ_R10; // 0x30 ++ unsigned int SleepState_FIQ_R11; // 0x34 ++ unsigned int SleepState_FIQ_R12; // 0x38 ++ unsigned int SleepState_FIQ_SP; // 0x3C ++ unsigned int SleepState_FIQ_LR; // 0x40 ++ unsigned int SleepState_ABT_SPSR; // 0x44 ++ unsigned int SleepState_ABT_SP; // 0x48 ++ unsigned int SleepState_ABT_LR; // 0x4C ++ unsigned int SleepState_IRQ_SPSR; // 0x50 ++ unsigned int SleepState_IRQ_SP; // 0x54 ++ unsigned int SleepState_IRQ_LR; // 0x58 ++ unsigned int SleepState_UND_SPSR; // 0x5C ++ unsigned int SleepState_UND_SP; // 0x60 ++ unsigned int SleepState_UND_LR; // 0x64 ++ unsigned int SleepState_SYS_SP; // 0x68 ++ unsigned int SleepState_SYS_LR; // 0x70 ++ ++ unsigned int SleepState_SVC_LR; // 0x7C ++ unsigned int temp; // 0x80 ++ ++ CKC ckc; ++ PIC pic; ++ VIC vic; ++ TIMER timer; ++ PMU pmu; ++ ++ //SMUI2CMASTER smui2cmaster0; ++ //SMUI2CMASTER smui2cmaster1; ++ //SMUI2CICLK smui2ciclk; ++ ++ GPIO gpio; ++ //DRAM dram; ++ //DRAMMX drammx; ++ //DRAMPHY dramphy; ++ //DRAMMISC drammisc; ++ //DRAMMEMBUS drammembus; ++ MISCCOREBUS misccorebus; ++ VMTREGION vmtregion; ++ //SMSHC smshc; ++ //SMSHCPORTCFG smshcportcfg; ++ //SDHOST sdhost; ++ //SDCHCTRL sdchctrl; ++ //NFC nfc; ++ //SMC smc; ++ //EDI edi; ++ //IDE ide; ++ //SATA sata; ++ //ADMA adma; ++ //ADMADAI admadai; ++ //ADMACDIF admacdif; ++ //ADMASPDIFTX admaspdiftx; ++ //RXCAP rxcap; ++ //ADMASPDIFRX admaspdifrx ++ //DAI dai; ++ //CDIF cdif; ++ //SPDIF spdif; ++ ++ USBHOST11 usbhost11; ++ USBHOST11CFG usbhost11cfg; ++ //USB20OTG usb20otg; ++ //USBOTG usbotg; ++ //USBOTGCFG usbotgconfig; ++ //USBPHYCFG usbphycfg; ++ ++ //EHI ehi; ++ //GPSB gpsb; ++ //GPSBPIDTABLE gpsbpidtable; ++ //TSIF tsif; ++ //TSIFPORTSEL tsifportsel; ++ //REMOTECON remotecon; ++ //I2CMASTER i2cmaster; ++ //I2C i2c; ++ //I2CSLAVE i2cslave; ++ //I2CSTATUS i2cstatus; ++ //UART uart0; ++ //UART uart1; ++ //UART uart2; ++ //UART uart3; ++ //UART uart4; ++ //UART uart5; ++ UARTPORTMUX uartportmux; ++ //CANCTRL canctrl; ++ //GDMACTRL gdmactrl0; ++ //GDMACTRL gdmactrl1; ++ //GDMACTRL gdmactrl2; ++ //GDMACTRL gdmactrl3; ++ RTC rtc; ++ TSADC tsadc; ++ //ECC ecc; ++ //SLCECC slcecc; ++ //MPEFEC mpefec ++ IOBUSCFG iobuscfg; ++ //EMC emc; ++ //LCDC lcdc0; ++ //LCDC lcdc1; ++ //LCDSI0 lcdsi0; ++ //LCDSI1 lcdsi1; ++ //M2MSCALER m2mscaler0; ++ //M2MSCALER m2mscaler1; ++ //NTSCPAL ntscpal; ++ //HDMICTRL hdmictrl; ++ //HDMICORE hdmicore; ++ //HDMIAES hdmiaes; ++ //HDMISPDIF hdmispdif; ++ //HDMII2S hdmii2s; ++ //HDMICEC hdmicec; ++ //CIF cif; ++ //EFFECT effect; ++ //CIFSACLER cifsacler; ++ //VIQE viqe; ++ DDICONFIG ddiconfig; ++ DDICACHE ddicache; ++ //JPEGENCODER jpegencoder; ++ //JPEGDECODER jpegdecoder; ++ //OVERLAYMIXER overlaymixer; ++ //GPUPIXELPROCESSOR gpupixelprocessor; ++ //GPUGEOMETRYPROCESSOR gpugeometryprocessor; ++ //GPUPLBCFG gpuplbcfg; ++ //GPUMMUCONFIG gpummuconfig; ++ //GPUGRPBUSCONFIG gpugrpbusconfig; ++ //GPUGRPBUSBWRAP gpugrpbusbwrap; ++ volatile unsigned int backup_peri_iobus0; ++ volatile unsigned int backup_peri_iobus1; ++} TCC_REG, *PTCC_REG; ++ ++#endif /*__TCC_PM_H__*/ +diff --git a/arch/arm/mach-tcc8900/pm_asm.S b/arch/arm/mach-tcc8900/pm_asm.S +new file mode 100644 +index 0000000..aacce2a +--- /dev/null ++++ b/arch/arm/mach-tcc8900/pm_asm.S +@@ -0,0 +1,283 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/pm_asm.S ++ * ++ * Author: ++ * Created: October, 2009 ++ * Description: LINUX POWER MANAGEMENT FUNCTIONS ++ * ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++ ++ ++#define Mode_USR 0x10 ++#define Mode_FIQ 0x11 ++#define Mode_IRQ 0x12 ++#define Mode_SVC 0x13 ++#define Mode_ABT 0x17 ++#define Mode_UND 0x1B ++#define Mode_SYS 0x1F ++#define Mode_MASK 0x1F ++#define NOINT 0xC0 ++#define I_Bit 0x80 ++#define F_Bit 0x40 ++ ++#define SYSCTL_SBZ_MASK 0xCC1A0000 ++#define SYSCTL_SBO_MASK 0x00000070 ++#define MMUTTB_SBZ_MASK 0x00001FE0 // for 8KB Boundary Size of TTB0 ++ ++ .text ++ ++/* ++ * IO_ARM_SaveREG ++ * -------------- ++ * ++ * Save ARM registers, MMU data and MODE data for suspend mode. ++ * ++ * input parameters: ++ * r0: SRAM_ADDR_STANDBY ++ * r1: TCC_REG ++ * r2: Awake_address ++ */ ++ ++ENTRY(IO_ARM_SaveREG) ++ @ address of sdram_self_refresh() (r0) ++ mov r12, r0 ++ ++ @ Save register state ++ stmdb sp!, {r4-r12} ++ stmdb sp!, {lr} ++ str r2, [r1, #0x4] // save resume function address (virtual) ++ mov r3, r1 // r1 (&p89reg) -> r3 ++ ++ ++@ ++@ Save MMU to DRAM ++@ ++ ++ @ CP15 System Control Register ++ mrc p15, 0, r2, c1, c0, 0 // load r2 with System Control Register ++ ldr r0, =SYSCTL_SBZ_MASK // Should Be Zero Mask for System Control Register ++ bic r2, r2, r0 ++ ldr r0, =SYSCTL_SBO_MASK // Should Be One Mask for System Control Register ++ orr r2, r2, r0 ++ str r2, [r3, #0x08] // [SleepState_SYSCTL] ++ ++ @ CP15 TTB Register0 ++ mrc p15, 0, r2, c2, c0, 0 // load r2 with TTB Register0 ++ ldr r0, =MMUTTB_SBZ_MASK // Should Be Zero Mask for TTB Register0 ++ bic r2, r2, r0 ++ str r2, [r3, #0x0C] // [SleepState_MMUTTB0] ++ ++ @ CP15 TTB Register1 ++ mrc p15, 0, r2, c2, c0, 1 // load r2 with TTB Register1 ++// ldr r0, =MMUTTB_SBZ_MASK // Should Be Zero Mask for TTB Register1 ++// bic r2, r2, r0 ++ str r2, [r3, #0x10] // [SleepState_MMUTTB1] ++ ++ @ CP15 TTB Control Register ++ mrc p15, 0, r2, c2, c0, 2 // load r2 with TTB Control Register ++// ldr r0, =MMUTTB_CTLSBZ_MASK // Should Be Zero Mask for TTB Register0 ++// bic r2, r2, r0 ++ str r2, [r3, #0x14] // [SleepState_MMUTTBCTL] ++ ++ @ CP15 Domain Access Control Register ++ mrc p15, 0, r2, c3, c0, 0 // load r2 with Domain Access Control Register ++ str r2, [r3, #0x18] // [SleepState_MMUDOMAIN] ++ ++ ++@ ++@ Save CPU register to DRAM ++@ ++ ++ @ Supervisor mode CPU Register ++ str sp, [r3, #0x1C] // [SleepState_SVC_SP] ++ mrs r2, spsr // Status Register ++ str r2, [r3, #0x20] // [SleepState_SVC_SPSR] ++ ++ add r3, r1, #0x24 ++ ++ @ FIQ mode CPU Registers ++ mov r1, #Mode_FIQ | NOINT // Enter FIQ mode, no interrupts ++ msr cpsr, r1 ++ mrs r2, spsr // Status Register ++ stmia r3!, {r2, r8-r12, sp, lr} // Store FIQ mode registers [SleepState_FIQ_SPSR~SleepState_FIQ_LR] ++ ++ @ Abort mode CPU Registers ++ mov r1, #Mode_ABT | NOINT // Enter ABT mode, no interrupts ++ msr cpsr, r1 ++ mrs r0, spsr // Status Register ++ stmia r3!, {r0, sp, lr} // Store ABT mode Registers [SleepState_ABT_SPSR~SleepState_ABT_LR] ++ ++ @ IRQ mode CPU Registers ++ mov r1, #Mode_IRQ | NOINT // Enter IRQ mode, no interrupts ++ msr cpsr, r1 ++ mrs r0, spsr // Status Register ++ stmia r3!, {r0, sp, lr} // Store the IRQ Mode Registers [SleepState_IRQ_SPSR~SleepState_IRQ_LR] ++ ++ @Undefined mode CPU Registers ++ mov r1, #Mode_UND | NOINT // Enter UND mode, no interrupts ++ msr cpsr, r1 ++ mrs r0, spsr // Status Register ++ stmia r3!, {r0, sp, lr} // Store the UND mode Registers [SleepState_UND_SPSR~SleepState_UND_LR] ++ ++ @ System(User) mode CPU Registers ++ mov r1, #Mode_SYS | NOINT // Enter SYS mode, no interrupts ++ msr cpsr, r1 ++ stmia r3!, {sp, lr} // Store the SYS mode Registers [SleepState_SYS_SP, SleepState_SYS_LR] ++ ++ @ Return to SVC mode ++ mov r1, #Mode_SVC | NOINT // Back to SVC mode, no interrupts ++ msr cpsr, r1 ++ ++ ldr r2, [sp] ++ str r2, [r3], #4 ++ ++ bl IO_ARM_CleanCACHE ++ ++ nop ++ nop ++ nop ++ ++#if 0 ++ ldr r0, =0x00050078 ++ mcr p15, 0, r0, c1, c0, 0 // Disable Cache/MMU Control ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++#endif ++ ++ @ jump to power-off code. ++ mov pc, r12 // jump to self-refresh code ++ENDPROC(IO_ARM_SaveREG) ++ ++ ++/* ++ * Awake_address ++ * -------------- ++ * ++ * Restore CPU Register from Sleep Data Area in DRAM ++ * r3 : p89reg ioremap virtual address, r3 is assigned by IO_ARM_RestoreREG in bootloader ++ */ ++ENTRY(Awake_address) ++ @ FIQ mode CPU Registers ++ mov r1, #Mode_FIQ | NOINT // Enter FIQ mode, no interrupts ++ msr cpsr, r1 ++ ldr r0, [r3, #0x24] ++ msr spsr, r0 ++ ldr r8, [r3, #0x28] ++ ldr r9, [r3, #0x2C] ++ ldr r10,[r3, #0x30] ++ ldr r11,[r3, #0x34] ++ ldr r12,[r3, #0x38] ++ ldr sp, [r3, #0x3C] ++ ldr lr, [r3, #0x40] ++ ++ @ Abort mode CPU Registers ++ mov r1, #Mode_ABT | I_Bit // Enter ABT mode, no IRQ - FIQ is available ++ msr cpsr, r1 ++ ldr r0, [r3, #0x44] ++ msr spsr, r0 ++ ldr sp, [r3, #0x48] ++ ldr lr, [r3, #0x4C] ++ ++ @ IRQ mode CPU Registers ++ mov r1, #Mode_IRQ | I_Bit // Enter IRQ mode, no IRQ - FIQ is available ++ msr cpsr, r1 ++ ldr r0, [r3, #0x50] ++ msr spsr, r0 ++ ldr sp, [r3, #0x54] ++ ldr lr, [r3, #0x58] ++ ++ @ Undefined mode CPU Registers ++ mov r1, #Mode_UND | I_Bit // Enter UND mode, no IRQ - FIQ is available ++ msr cpsr, r1 ++ ldr r0, [r3, #0x5C] ++ msr spsr, r0 ++ ldr sp, [r3, #0x60] ++ ldr lr, [r3, #0x64] ++ ++ @ System(User) mode CPU Registers ++ mov r1, #Mode_SYS | I_Bit // Enter SYS mode, no IRQ - FIQ is available ++ msr cpsr, r1 ++ ldr sp, [r3, #0x68] ++ ldr lr, [r3, #0x6C] ++ ++ @ Supervisor mode CPU Registers ++ mov r1, #Mode_SVC | I_Bit // Enter SVC mode, no IRQ - FIQ is available ++ msr cpsr, r1 ++ ldr r0, [r3, #0x20] ++ msr spsr, r0 ++ ldr sp, [r3, #0x1C] ++ ++ ++ @ Pop SVC Register from our Stack ++ ldr lr, [sp], #4 ++ ldmia sp!, {r4-r12} ++ ++ @ Return to PM functions ++ mov pc, lr ++ENDPROC(Awake_address) ++ ++ ++/* ++ * Clean & Flush Cache ++ * ------------------- ++ */ ++ENTRY(IO_ARM_CleanCACHE) ++ stmdb r13!, {lr} ++ ++ bl IO_ARM_CleanDCACHE ++ ++ cmp r0, #0 ++ movne r0, #0 @ Drain Write Buffer ++ mcrne p15, 0, r0, c7, c10, 4 ++ ++ ldmia r13!, {pc} ++ENDPROC(IO_ARM_CleanCACHE) ++ ++ ++ENTRY(IO_ARM_CleanDCACHE) ++ stmdb r13!, {r0-r2, lr} ++ ++ mov r1, #0 @ r1 - way (0~3) ++l01: ++ mov r1, r1, lsl #30 ++ mov r2, #0 @ r2 - set index (128 set : 0~0x1000) ++l02: ++ orr r0, r1, r2 @ set index (way & set) ++ mcr p15, 0, r0, c7, c10, 2 @ clean cache (using index) ++ add r2, r2, #0x20 @ cache block size : 32 Bytes ++ cmp r2, #0x1000 @ cache set size : 4 KBytes ++ bne l02 @ loop until done ++ ++ mov r1, r1, lsr #30 ++ add r1, r1, #1 ++ cmp r1, #4 @ cache way size : 4 ++ bne l01 ++ ++ ldmia r13!, {r0-r2, pc} ++ENDPROC(IO_ARM_CleanDCACHE) +\ No newline at end of file +diff --git a/arch/arm/mach-tcc8900/tca_ckc.c b/arch/arm/mach-tcc8900/tca_ckc.c +new file mode 100644 +index 0000000..78d2635 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tca_ckc.c +@@ -0,0 +1,1174 @@ ++/**************************************************************************** ++ * FileName : tca_ckc.c ++ * Description : ++ **************************************************************************** ++* ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++* ++ ****************************************************************************/ ++ ++ ++#if defined(_LINUX_) ++# include ++# include ++# include // for PAGE_ALIGN ++# include ++# include ++# ifndef VOLATILE ++# define VOLATILE ++# endif ++#else ++# include ++# include "oal_memory.h" ++# include "tca_ckc.h" ++# ifndef VOLATILE ++# define VOLATILE volatile ++# endif ++#endif ++ ++typedef struct { ++ unsigned uFpll; ++ unsigned char P, M, S, dummy; ++} sfPLL; ++ ++#define PLLFREQ(P, M, S) (( 120000 * (M) ) / (P) ) >> (S) // 100Hz Unit.. ++#define FPLL_t(P, M, S) PLLFREQ(P,M,S), P, M, S ++// PLL table for XIN=12MHz ++ // P, M, S ++sfPLL pIO_CKC_PLL[] = ++{ ++ {FPLL_t(3, 78, 1)} // 156MHz ++ ,{FPLL_t(3, 120, 1)} // 240 MHz ++ ,{FPLL_t(3, 135, 1)} // 270.0 MHz ++ ,{FPLL_t(2, 52, 0)} // 312 MHz ++ ,{FPLL_t(3, 95, 0)} // 380 MHz ++ ,{FPLL_t(1, 39, 0)} // 468 MHz ++ ,{FPLL_t(1, 40, 0)} // 480 MHz ++ ,{FPLL_t(1, 44, 0)} // 528 MHz ++ ,{FPLL_t(2, 104, 0)} // 624 MHz ++ ,{FPLL_t(2, 116, 0)} // 696 MHz ++ ++ ++}; ++ ++sfPLL pIO_CKC_PLL0[] = ++{ ++ {FPLL_t(2, 176, 3)} // 132 MHz ++ , {FPLL_t(2, 192, 3)} // 144 MHz ++ , {FPLL_t(3, 146, 2)} // 146 MHz ++ , {FPLL_t(1, 30, 1)} // 180 MHz ++ , {FPLL_t(3, 95, 1)} // 190 MHz ++ , {FPLL_t(1, 32, 1)} // 192 MHz ++ , {FPLL_t(3, 202, 2)} // 202 MHz ++ , {FPLL_t(2, 144, 2)} // 216 MHz ++ , {FPLL_t(2, 148, 2)} // 222 MHz ++ , {FPLL_t(3, 230, 2)} // 230 MHz ++ ,{FPLL_t(2, 216, 2)} // 324 MHz ++ ,{FPLL_t(2, 144, 1)} // 432 MHz ++ ,{FPLL_t(2, 162, 1)} // 486 MHz ++ ,{FPLL_t(2, 180, 1)} // 540 MHz ++ ,{FPLL_t(2, 200, 1)} // 600 MHz ++}; ++ ++#define NUM_PLL (sizeof(pIO_CKC_PLL)/sizeof(sfPLL)) ++#define NUM_PLL0 (sizeof(pIO_CKC_PLL0)/sizeof(sfPLL)) ++ ++#define tca_wait() { volatile int i; for (i=0; i<0x2000; i++); } ++ ++#if defined(_LINUX_) ++ #define iomap_p2v(x) (x) ++#else ++// #define iomap_p2v(x) (x & ~0x40000000) //0xF0400000 -> 0xB04 ++ #define iomap_p2v(x) (OALPAtoVA(x,FALSE)) //0xF0400000 -> 0xB04 ++#endif ++ ++/**************************************************************************************** ++* Global Variable ++* ***************************************************************************************/ ++PCKC pCKC ; ++PPMU pPMU ; ++PIOBUSCFG pIOBUSCFG; ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_init(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_init(void) ++{ ++ pCKC = (PCKC)(iomap_p2v((unsigned int)&HwCLK_BASE)); //0xF0400000 ++ pPMU = (PPMU)(iomap_p2v((unsigned int)&HwPMU_BASE)); //0xF0404000 ++ pIOBUSCFG = (PIOBUSCFG)(iomap_p2v((unsigned int)&HwIOBUSCFG_BASE)); //0xF05F5000 ++ ++} ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getpll(unsigned int ch) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE unsigned int tca_ckc_getpll(unsigned int ch) ++{ ++ volatile unsigned tPLL; ++ volatile unsigned tPLLCFG; ++ unsigned iP=0, iM=0, iS=0; ++ ++ switch(ch) ++ { ++ case DIRECTPLL0: ++ tPLLCFG = pCKC->PLL0CFG; ++ break; ++ case DIRECTPLL1: ++ tPLLCFG = pCKC->PLL1CFG; ++ break; ++ case DIRECTPLL2: ++ tPLLCFG = pCKC->PLL2CFG; ++ break; ++ case DIRECTPLL3: ++ tPLLCFG = pCKC->PLL3CFG; ++ break; ++ } ++ ++ //Fpll Clock ++ iS = (tPLLCFG & 0x7000000) >> 24; ++ iM = (tPLLCFG & 0xFFF00) >> 8; ++ iP = (tPLLCFG & 0x0003F) >> 0; ++ ++ tPLL= (((120000 * iM )/ iP) >> (iS)); ++ ++ return tPLL; ++ ++} ++ ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getcpu(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE unsigned int tca_ckc_getcpu(void) ++{ ++ unsigned int lcpu = 0; ++ unsigned int lconfig = 0; ++ unsigned int lcnt = 0; ++ unsigned int li = 0; ++ unsigned int lclksource = 0; ++ ++ lconfig = ((pCKC->CLK0CTRL & (Hw20-Hw4))>>4); ++ ++ for(li = 0; li < 16; li++) ++ { ++ if((lconfig & Hw0) == 1) ++ lcnt++; ++ lconfig = (lconfig >> 1); ++ } ++ ++ switch(pCKC->CLK0CTRL & (Hw3-Hw0)) // Check CPU Source ++ { ++ case PCDIRECTPLL0 : ++ lclksource = tca_ckc_getpll(0); ++ break; ++ case PCDIRECTPLL1 : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ case PCDIRECTPLL2 : ++ lclksource = tca_ckc_getpll(2); ++ break; ++ case PCDIRECTPLL3 : ++ lclksource = tca_ckc_getpll(3); ++ break; ++ case PCDIRECTXIN : ++ lclksource = 120000; ++ break; ++ case PCHDMI : ++ lclksource = 270000; ++ break; ++ case PCSATA : ++ lclksource = 250000; ++ break; ++ case PCUSBPHY: ++ lclksource = 480000; ++ break; ++ default : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ } ++ ++ if(pCKC->CLK0CTRL & Hw20) // Dynamic Mode ++ { ++ lcnt = pCKC->CLK0CTRL & (Hw8-Hw4); ++ lcnt = lcnt>>4; ++ lcpu = (lclksource / lcnt); ++ } ++ else ++ lcpu = (lclksource * lcnt)/16; ++ ++ return lcpu; ++} ++ ++/**************************************************************************************** ++* FUNCTION :unsigned int tca_ckc_getbus(void) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE unsigned int tca_ckc_getbus(void) ++{ ++ unsigned int lbus = 0; ++ unsigned int lconfig = 0; ++ unsigned int lclksource = 0; ++ ++ lconfig = ((pCKC->CLK2CTRL & (Hw8-Hw4))>>4); ++ ++ switch(pCKC->CLK2CTRL & (Hw3-Hw0)) // Check CPU Source ++ { ++ case PCDIRECTPLL0 : ++ lclksource = tca_ckc_getpll(0); ++ break; ++ case PCDIRECTPLL1 : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ case PCDIRECTPLL2 : ++ lclksource = tca_ckc_getpll(2); ++ break; ++ case PCDIRECTPLL3 : ++ lclksource = tca_ckc_getpll(3); ++ break; ++ case PCDIRECTXIN : ++ lclksource = 120000; ++ break; ++ case PCHDMI : ++ lclksource = 270000; ++ break; ++ case PCSATA : ++ lclksource = 250000; ++ break; ++ case PCUSBPHY: ++ lclksource = 480000; ++ break; ++ default : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ } ++ ++ lbus = lclksource /(lconfig+1); ++ ++ return lbus; ++} ++ ++/**************************************************************************************** ++* FUNCTION :static unsigned int tca_ckc_setclkctrlx(unsigned int isenable,unsigned int md,unsigned int config,unsigned int sel) ++* DESCRIPTION : not ctrl 0 and ctrl 2 (CPU, BUS CTRL) ++* ***************************************************************************************/ ++VOLATILE static unsigned int tca_ckc_gclkctrlx(unsigned int isenable,unsigned int md,unsigned int config,unsigned int sel) ++{ ++ unsigned int retVal = 0; ++ ++ retVal = ((isenable?1:0)<<21)|(md<<20)|(config<<4)|(sel<<0); ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :static unsigned int tca_ckc_clkctrly(unsigned int isenable,unsigned int md,unsigned int config,unsigned int sel) ++* DESCRIPTION : ctrl 0 and ctrl 2 (CPU and BUS CTRL) ++* config is divider (md = 0) ++* ***************************************************************************************/ ++VOLATILE static unsigned int tca_ckc_gclkctrly(unsigned int isenable,unsigned int md,unsigned int config,unsigned int sel, unsigned int ch) ++{ ++ unsigned int retVal = 0; ++// md = 0; // Normal Mode ++ ++ if(ch == CLKCTRL0) ++ { ++ switch(config) ++ { ++ case CLKDIV0: ++ config = 0xFFFF; // 1111111111111111b 16/16 ++ break; ++ case CLKDIV2: ++ config = 0xAAAA; // 1010101010101010b 8/16 ++ break; ++ case CLKDIV3: ++ config = 0x9249; // 1001001001001001b 6/16 ++ break; ++ case CLKDIV4: ++ config = 0x8888; // 1000100010001000b 4/16 ++ break; ++ case CLKDIVNONCHANGE: ++ config = 0xFFFF; // 1111111111111111b ++ break; ++ default: ++ config = 0xFFFF; // 1111111111111111b ++ break; ++ } ++ } ++ ++ if(config == CLKDIVNONCHANGE) ++ { ++ if(ch == 0) // Fcpu ++ retVal = (pCKC->CLK0CTRL & (Hw20-Hw4)); ++ else // Fmem_bus ++ retVal = (pCKC->CLK2CTRL & (Hw20-Hw4)); ++ ++ retVal |= ((isenable?1:0)<<21)|(md<<20)|(sel<<0); ++ ++ } ++ else ++ retVal = ((isenable?1:0)<<21)|(md<<20)|(config<<4)|(sel<<0); ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setfbusctrl(unsigned int clkname,unsigned int isenable,unsigned int freq, unsigned int sor) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setfbusctrl(unsigned int clkname,unsigned int isenable,unsigned int md,unsigned int freq, unsigned int sor) ++{ ++ volatile unsigned *pCLKCTRL; ++ unsigned int clkdiv = 0; ++ unsigned int clksource = 0; ++ unsigned int lconfig = 0; ++ ++ pCLKCTRL =(volatile unsigned *)((&pCKC->CLK0CTRL)+clkname); ++ ++ switch(sor) ++ { ++ case DIRECTPLL0 : ++ clksource = tca_ckc_getpll(0); ++ break; ++ case DIRECTPLL1 : ++ clksource = tca_ckc_getpll(1); ++ break; ++ case DIRECTPLL2 : ++ clksource = tca_ckc_getpll(2); ++ break; ++ case DIRECTPLL3 : ++ clksource = tca_ckc_getpll(3); ++ break; ++ case DIRECTXIN: ++ clksource = 120000; ++ break; ++ default : ++ clksource = tca_ckc_getpll(1); ++ break; ++ } ++ ++ if (freq != 0) ++ { ++ clkdiv = (clksource + (freq>>1)) / freq ; // should be even number of division factor ++ clkdiv -= 1; ++ } ++ else ++ clkdiv = 1; ++ ++ if(clkdiv == CLKDIV0) // The config value should not be "ZERO" = 1/(config+1) ++ clkdiv = 1; ++ ++ ++ if(md == DYNAMIC_MD && !(clkname == CLKCTRL0 || clkname == CLKCTRL2)) ++ { ++ /* ++ CONFIG[3:0] : Curretn Divisor(Read-only) ++ CONFIG[7:4] : Max. Divisor ++ CONFIG[11:8] : Min. Divisor ++ CONFIG[15:12] : Update Cycle Period ++ */ ++ lconfig = (clkdiv<<8); //Min. Divisor ++ clkdiv = 10; //Max. Divisor ++ lconfig |= ((clkdiv<<4)| 0xF000); // Min. Divisor = Max. Divisor/2, Update Cycle Period = F ++ ++ clkdiv = lconfig; ++ } ++ ++ if(clkname == CLKCTRL0 || clkname == CLKCTRL2) ++ { ++ *pCLKCTRL = tca_ckc_gclkctrly(isenable,md,clkdiv,sor,clkname); ++ } ++ else ++ { ++ if(isenable == 0) ++ *pCLKCTRL &= ~Hw21; ++ else ++ *pCLKCTRL = tca_ckc_gclkctrlx(isenable,md,clkdiv,sor); ++ } ++ ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_getfbusctrl(unsigned int clkname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_getfbusctrl(unsigned int clkname) ++{ ++ volatile unsigned *pCLKCTRL; ++ unsigned int lcheck = 0; ++ unsigned int lmd = 0; ++ unsigned int lconfig = 0; ++ unsigned int lsel = 0; ++ unsigned int clksource = 0; ++ ++ pCLKCTRL =(volatile unsigned *)((&pCKC->CLK0CTRL)+clkname); ++ ++ lcheck = ((*pCLKCTRL >> 21) & Hw0); ++ lmd = ((*pCLKCTRL >> 20) & Hw0); ++ lconfig = ((*pCLKCTRL >> 4) & 0xF); ++ lsel = ((*pCLKCTRL) & 0x7); ++ ++ if(!lcheck || (clkname == CLKCTRL0 || clkname == CLKCTRL2)) ++ return -1; ++ ++ if(lmd == 0) ++ { ++ switch(lsel) ++ { ++ case DIRECTPLL0 : ++ clksource = tca_ckc_getpll(0); ++ break; ++ case DIRECTPLL1 : ++ clksource = tca_ckc_getpll(1); ++ break; ++ case DIRECTPLL2 : ++ clksource = tca_ckc_getpll(2); ++ break; ++ case DIRECTPLL3 : ++ clksource = tca_ckc_getpll(3); ++ break; ++ case DIRECTXIN: ++ clksource = 120000; ++ break; ++ default : ++ clksource = tca_ckc_getpll(1); ++ break; ++ } ++ ++ } ++ else ++ return -1; ++ ++ return (clksource / (lconfig+1)); ++} ++ ++/**************************************************************************************** ++* FUNCTION :static unsigned int tca_ckc_setpllxcfg(unsigned int isEnable, int P, int M, int S) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE static unsigned int tca_ckc_gpllxcfg(unsigned int isenable, unsigned int p, unsigned int m, unsigned int s) ++{ ++ unsigned int retVal = Hw31;//Disable ++ ++ if(isenable > 0) ++ { ++ retVal = (s<<24)|(m<<8)|(p<<0); ++ retVal |= Hw31; //Enable ++ } ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :static void tca_ckc_pll(unsigned int p, unsigned int m, unsigned int s,unsigned int ch) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE static void tca_ckc_pll(unsigned int p, unsigned int m, unsigned int s,unsigned int ch) ++{ ++ volatile unsigned *pPLLCFG; ++ ++ pPLLCFG =(volatile unsigned *)((&pCKC->PLL0CFG)+ch); ++ ++ if(ch == 0) // PLL0 is System Clock Source ++ { ++ // Change System Clock Souce --> XIN (12Mhz) ++ // pCKC->CLK0CTRL = tca_ckc_gclkctrly(ENABLE,NORMAL_MD,CLKDIVNONCHANGE,DIRECTXIN,0); ++ pCKC->CLK0CTRL = tca_ckc_gclkctrly(ENABLE,NORMAL_MD,CLKDIVNONCHANGE,DIRECTPLL2,0); ++ tca_wait(); ++ } ++ ++ //Disable PLL ++ *pPLLCFG &= ~Hw31; ++ //Set PMS ++ *pPLLCFG = tca_ckc_gpllxcfg(ENABLE,p,m,s); ++ //Enable PLL ++ *pPLLCFG |= Hw31; ++ tca_wait(); ++ //Restore System Clock Source ++ if(ch == 0) ++ { ++ //pCKC->CLK2CTRL = tca_ckc_gclkctrly(ENABLE,NORMAL_MD,CLKDIVNONCHANGE,DIRECTPLL0,2); ++ pCKC->CLK0CTRL = tca_ckc_gclkctrly(ENABLE,NORMAL_MD,CLKDIVNONCHANGE,DIRECTPLL0,0); ++ } ++ ++} ++ ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_validpll(unsigned int * pvalidpll) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_validpll(unsigned int * pvalidpll) ++{ ++ unsigned int uCnt; ++ sfPLL *pPLL; ++ ++ pPLL = &pIO_CKC_PLL[0]; ++ for (uCnt = 0; uCnt < NUM_PLL; uCnt ++, pPLL ++) ++ { ++ *pvalidpll = pPLL->uFpll ; ++ pvalidpll++; ++ } ++}; ++ ++/**************************************************************************************** ++* FUNCTION :int tca_ckc_setpll(unsigned int pll, unsigned int ch) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_setpll(unsigned int pll, unsigned int ch) ++{ ++ unsigned uCnt; ++ int retVal = -1; ++ unsigned int num_pll; ++ ++ sfPLL *pPLL; ++ ++ if(pll != 0 ) ++ { ++ if(ch == 0) ++ { ++ pPLL = &pIO_CKC_PLL0[0]; ++ num_pll = NUM_PLL0; ++ } ++ else ++ { ++ pPLL = &pIO_CKC_PLL[0]; ++ num_pll = NUM_PLL; ++ } ++ ++ for (uCnt = 0; uCnt < num_pll; uCnt ++, pPLL ++) ++ if (pPLL->uFpll == pll) ++ break; ++ ++ if (uCnt < num_pll) ++ { ++ tca_ckc_pll(pPLL->P,pPLL->M ,pPLL->S,ch); ++ retVal = 0; ++ return 1; ++ } ++ } ++ ++ return -1; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setcpu(unsigned int n) ++* DESCRIPTION : n is n/16 ++* example : CPU == PLL : n=16 - CPU == PLL/2 : n=8 ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setcpu(unsigned int n) ++{ ++ unsigned int lckc0ctrl; ++ unsigned int lindex[] = {0x0,0x8000,0x8008,0x8808,0x8888,0xA888,0xA8A8,0xAAA8,0xAAAA, ++ 0xECCC,0xEECC,0xEEEC,0xEEEE,0xFEEE,0xFFEE,0xFFFE,0xFFFF}; ++ ++ ++ lckc0ctrl = pCKC->CLK0CTRL; ++ lckc0ctrl &= ~(Hw20-Hw4); ++ lckc0ctrl |= (lindex[n] << 4); ++ ++ pCKC->CLK0CTRL = lckc0ctrl; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setpmupwroff( unsigned int periname , unsigned int isenable) ++* DESCRIPTION : PMU Block : Power Off Register ++* PMU_VIDEODAC ++* PMU_HDMIPHY ++* PMU_LVDSPHY ++* PMU_USBNANOPHY ++* PMU_SATAPHY ++* PMU_MEMORYBUS ++* PMU_VIDEOBUS ++* PMU_DDIBUS ++* PMU_GRAPHICBUS ++* PMU_IOBUS ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setpmupwroff( unsigned int periname , unsigned int isenable) ++{ ++ unsigned int retVal = 0; ++ ++ switch(periname) ++ { ++ case PMU_VIDEODAC: ++ retVal = (Hw0); ++ break; ++ case PMU_HDMIPHY: ++ retVal = (Hw1); ++ break; ++ case PMU_LVDSPHY: ++ retVal = (Hw2); ++ break; ++ case PMU_USBNANOPHY: ++ retVal = (Hw3); ++ break; ++ case PMU_SATAPHY: ++ retVal = (Hw4); ++ break; ++ case PMU_MEMORYBUS: ++ retVal = (Hw5); ++ break; ++ case PMU_VIDEOBUS: ++ retVal = (Hw6); ++ break; ++ case PMU_DDIBUS: ++ retVal = (Hw7); ++ break; ++ case PMU_GRAPHICBUS: ++ retVal = (Hw8); ++ break; ++ case PMU_IOBUS: ++ retVal = (Hw9); ++ break; ++ default: ++ break; ++ } ++ ++ if(isenable) ++ pPMU->PWROFF &= ~(retVal); ++ else ++ pPMU->PWROFF |= (retVal); ++ ++} ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_getpmupwroff( unsigned int pmuoffname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_getpmupwroff( unsigned int pmuoffname) ++{ ++ unsigned int retVal = 0; ++ ++ switch(pmuoffname) ++ { ++ case PMU_VIDEODAC: ++ retVal = (pPMU->PWROFF >> 0) & Hw0; ++ break; ++ case PMU_HDMIPHY: ++ retVal = (pPMU->PWROFF >> 1) & Hw0; ++ break; ++ case PMU_LVDSPHY: ++ retVal = (pPMU->PWROFF >> 2) & Hw0; ++ break; ++ case PMU_USBNANOPHY: ++ retVal = (pPMU->PWROFF >> 3) & Hw0; ++ break; ++ case PMU_SATAPHY: ++ retVal = (pPMU->PWROFF >> 4) & Hw0; ++ break; ++ case PMU_MEMORYBUS: ++ retVal = (pPMU->PWROFF >> 5) & Hw0; ++ break; ++ case PMU_VIDEOBUS: ++ retVal = (pPMU->PWROFF >> 6) & Hw0; ++ break; ++ case PMU_DDIBUS: ++ retVal = (pPMU->PWROFF >> 7) & Hw0; ++ break; ++ case PMU_GRAPHICBUS: ++ retVal = (pPMU->PWROFF >> 8) & Hw0; ++ break; ++ case PMU_IOBUS: ++ retVal = (pPMU->PWROFF >> 9) & Hw0; ++ break; ++ default: ++ break; ++ } ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :static unsigned int tca_ckc_setpckxxx(unsigned int isenable, unsigned int sel, unsigned int div) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE static unsigned int tca_ckc_gpckxxx(unsigned int isenable, unsigned int sel, unsigned int div) ++{ ++ unsigned int retVal = Hw28; //Enable ++ ++ if(isenable > 0) ++ { ++ retVal = ((isenable?1:0)<<28)|(sel<<24)|(div<<0); ++ } ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :static unsigned int tca_ckc_setpckyyy(unsigned int isenable, unsigned int sel, unsigned int div) ++* DESCRIPTION : md (1: divider Mode, 0:DCO Mode) ++* ***************************************************************************************/ ++VOLATILE static unsigned int tca_ckc_gpckyyy(unsigned int isenable, unsigned int md, unsigned int sel, unsigned int div) ++{ ++ unsigned int retVal = Hw28;//Enable ++ ++ if(isenable > 0) ++ { ++ retVal = (md<<31)|((isenable?1:0)<<28)|(sel<<24)|(div<<0); ++ } ++ ++ return retVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setperi(unsigned int periname,unsigned int isenable, unsigned int freq, unsigned int sor) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setperi(unsigned int periname,unsigned int isenable, unsigned int freq, unsigned int sor) ++{ ++ unsigned uPll; ++ unsigned int clkdiv = 0; ++ unsigned int lclksource = 0; ++ unsigned int clkmode = 1; ++ ++ volatile unsigned *pPERI; ++ pPERI =(volatile unsigned *)((&pCKC->PCLK_TCX)+periname); ++ ++ switch(sor) ++ { ++ case PCDIRECTPLL0 : ++ lclksource = tca_ckc_getpll(0); ++ break; ++ case PCDIRECTPLL1 : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ case PCDIRECTPLL2 : ++ lclksource = tca_ckc_getpll(2); ++ break; ++ case PCDIRECTPLL3 : ++ lclksource = tca_ckc_getpll(3); ++ break; ++ case PCDIRECTXIN : ++ lclksource = 120000; ++ break; ++ case PCHDMI : ++ lclksource = 270000; ++ break; ++ case PCSATA : ++ lclksource = 250000; ++ break; ++ case PCUSBPHY: ++ lclksource = 480000; ++ break; ++ default : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ } ++ ++ if (freq != 0) ++ { ++ clkdiv = (lclksource + (freq>>1)) / freq ; // should be even number of division factor ++ clkdiv -= 1; ++ } ++ else ++ clkdiv = 0; ++ ++ if(periname == PERI_ADC || periname == PERI_SPDIF ||periname == PERI_AUD || periname == PERI_DAI) ++ { ++ if(periname == PERI_DAI) ++ { ++ clkmode = 0; // DCO Mode ++ clkdiv = (freq *32768); ++ uPll = lclksource; ++ clkdiv = clkdiv/uPll; ++ clkdiv <<= 1; ++ clkdiv = clkdiv + 1; ++ } ++ ++ *pPERI = tca_ckc_gpckyyy(isenable,clkmode,sor,clkdiv); ++ } ++ else ++ { ++ *pPERI = tca_ckc_gpckxxx(isenable,sor,clkdiv); ++ ++ } ++} ++ ++/**************************************************************************************** ++* FUNCTION : static int tca_ckc_gperi(unsigned int lclksrc, unsigned int ldiv,unsigned int lmd) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE static int tca_ckc_gperi(unsigned int lclksrc, unsigned int ldiv,unsigned int lmd) ++{ ++ if(lmd == 1) ++ { ++ if(lclksrc == PCDIRECTXIN) ++ return 120000/(ldiv+1); ++ else if(lclksrc == PCDIRECTPLL0){ ++ return (tca_ckc_getpll(0)/(ldiv+1)); ++ } ++ else if(lclksrc == PCDIRECTPLL1){ ++ return (tca_ckc_getpll(1)/(ldiv+1)); ++ } ++ else if(lclksrc == PCDIRECTPLL2){ ++ return (tca_ckc_getpll(2)/(ldiv+1)); ++ } ++ else if(lclksrc == PCDIRECTPLL3){ ++ return (tca_ckc_getpll(3)/(ldiv+1)); ++ } ++ else if(lclksrc == PCHDMI){ ++ return (270000/(ldiv+1)); ++ } ++ else if(lclksrc == PCSATA){ ++ return (250000/(ldiv+1)); ++ } ++ else if(lclksrc == PCUSBPHY){ ++ return (480000/(ldiv+1)); ++ } ++ else ++ return -1; // Not Support Others ++ ++ } ++ else ++ return -1; // TO DO ++} ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getperi(unsigned int periname) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_getperi(unsigned int periname) ++{ ++ unsigned int lreg = 0; ++ unsigned int lmd = 1; // DIVIDER mode ++ unsigned int lclksrc = 0; ++ unsigned int ldiv = 0; ++ ++ lreg =*(volatile unsigned *)((&pCKC->PCLK_TCX)+periname); ++ lclksrc = (lreg&0xF000000)>>24; ++ ++ if(periname == PERI_ADC || periname == PERI_SPDIF ||periname == PERI_AUD || periname == PERI_DAI) ++ { ++ lmd = (lreg&0x80000000); ++ ldiv = (lreg & 0xFFFF); ++ return tca_ckc_gperi(lclksrc, ldiv,lmd); ++ } ++ else ++ { ++ ldiv = (lreg & 0xFFF); ++ return tca_ckc_gperi(lclksrc, ldiv,1); ++ } ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setswresetprd(unsigned int prd) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setswresetprd(unsigned int prd) ++{ ++ pCKC->SWRESETPRD = prd<<0; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_set_iobus_swreset(unsigned int sel, unsigned int mode) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE unsigned int tca_ckc_set_iobus_swreset(unsigned int sel, unsigned int mode) ++{ ++ unsigned int lindex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7,Hw8,Hw9,Hw10,Hw11,Hw12,Hw13,Hw14,Hw15 ++ ,Hw16,Hw17,Hw18,Hw19,Hw20,Hw21,Hw22,Hw23,Hw24,Hw25,Hw26,Hw27,Hw28,Hw29,Hw30,Hw31}; ++ ++ unsigned int lrb_min; ++ unsigned int lrb_max; ++ unsigned int lrb_seperate; ++ ++ lrb_min = RB_USB11H; ++ lrb_max = RB_ALLPERIPERALS; ++ lrb_seperate = RB_ADMACONTROLLER; ++ ++ if(sel < lrb_min || sel >= lrb_max) ++ { ++ return 0; ++ } ++ ++ if(sel > lrb_seperate) ++ { ++ sel -= (lrb_seperate+1); ++ ++ if(mode) ++ pIOBUSCFG->HRSTEN1 |= lindex[sel]; ++ else ++ pIOBUSCFG->HRSTEN1 &= ~lindex[sel]; ++ } ++ else ++ { ++ if(mode) ++ pIOBUSCFG->HRSTEN0 |= lindex[sel]; ++ else ++ pIOBUSCFG->HRSTEN0 &= ~lindex[sel]; ++ } ++ ++ return 1; ++} ++ ++/**************************************************************************************** ++* FUNCTION :void tca_ckc_setswreset(unsigned int lfbusname, unsigned int mode) ++* DESCRIPTION : ++* ***************************************************************************************/ ++ ++VOLATILE void tca_ckc_setswreset(unsigned int lfbusname, unsigned int mode) ++{ ++ unsigned int hIndex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7}; ++ ++ if(mode) ++ pCKC->SWRESET |= hIndex[lfbusname]; ++ else ++ pCKC->SWRESET &= ~(hIndex[lfbusname]); ++} ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_setiobus(unsigned int sel, unsigned int mode) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_setiobus(unsigned int sel, unsigned int mode) ++{ ++ unsigned int lindex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7,Hw8,Hw9,Hw10,Hw11,Hw12,Hw13,Hw14,Hw15 ++ ,Hw16,Hw17,Hw18,Hw19,Hw20,Hw21,Hw22,Hw23,Hw24,Hw25,Hw26,Hw27,Hw28,Hw29,Hw30,Hw31}; ++ ++ unsigned int lrb_min; ++ unsigned int lrb_max; ++ unsigned int lrb_seperate; ++ ++ lrb_min = RB_USB11H; ++ lrb_max = RB_ALLPERIPERALS; ++ lrb_seperate = RB_ADMACONTROLLER; ++ ++ if(sel < lrb_min || sel >= lrb_max) ++ { ++ return -1; ++ } ++ ++ if(sel > lrb_seperate) ++ { ++ sel -= (lrb_seperate+1); ++ ++ if(mode) ++ pIOBUSCFG->HCLKEN1 |= lindex[sel]; ++ else ++ pIOBUSCFG->HCLKEN1 &= ~lindex[sel]; ++ } ++ else ++ { ++ if(mode) ++ pIOBUSCFG->HCLKEN0 |= lindex[sel]; ++ else ++ pIOBUSCFG->HCLKEN0 &= ~lindex[sel]; ++ } ++ ++ return 1; ++} ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getiobus(unsigned int sel) ++* DESCRIPTION : ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_getiobus(unsigned int sel) ++{ ++ unsigned int lindex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7,Hw8,Hw9,Hw10,Hw11,Hw12,Hw13,Hw14,Hw15 ++ ,Hw16,Hw17,Hw18,Hw19,Hw20,Hw21,Hw22,Hw23,Hw24,Hw25,Hw26,Hw27,Hw28,Hw29,Hw30,Hw31}; ++ unsigned int lrb_min; ++ unsigned int lrb_max; ++ unsigned int lrb_seperate; ++ int lretVal = 0; ++ ++ lrb_min = RB_USB11H; ++ lrb_max = RB_ALLPERIPERALS; ++ lrb_seperate = RB_ADMACONTROLLER; ++ ++ ++ if(sel < lrb_min || sel >= lrb_max) ++ { ++ return -1; ++ } ++ ++ if(sel > lrb_seperate) ++ { ++ sel -= (lrb_seperate+1); ++ ++ lretVal = (pIOBUSCFG->HCLKEN1 & lindex[sel]) ; ++ ++ } ++ else ++ { ++ lretVal = (pIOBUSCFG->HCLKEN0 & lindex[sel]) ; ++ } ++ ++ if(lretVal != 0) ++ lretVal = 1; // Enable ++ ++ return lretVal; ++} ++ ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_setsmui2c(unsigned int freq) ++* DESCRIPTION : unit : 100Hz ++* ***************************************************************************************/ ++VOLATILE void tca_ckc_setsmui2c(unsigned int freq) ++{ ++ PSMUI2CICLK lSMUICLK; ++ unsigned int lclkctrl7=0; ++ unsigned int lsel=0; ++ unsigned int lclksource=0; ++ unsigned int lclkdiv=0; ++ ++ lSMUICLK = (PSMUI2CICLK)(iomap_p2v((unsigned int)&HwSMU_I2CICLK_BASE)); //0xF0400000 ++ lclkctrl7 = (unsigned int)pCKC->CLK7CTRL; ++ ++ lsel = (lclkctrl7 & 7); ++ ++ if(((lclkctrl7 >>20) & Hw0) == 0 ) // Normal Mode ++ { ++ switch(lsel) ++ { ++ case DIRECTPLL0: ++ lclksource = tca_ckc_getpll(0); ++ break; ++ case DIRECTPLL1: ++ lclksource = tca_ckc_getpll(1); ++ break; ++ case DIRECTPLL2: ++ lclksource = tca_ckc_getpll(2); ++ break; ++ case DIRECTPLL3: ++ lclksource = tca_ckc_getpll(3); ++ break; ++ default : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ ++ } ++ } ++ ++ if (freq != 0) ++ { ++ lclkdiv = (lclksource + (freq>>1)) / freq ; // should be even number of division factor ++ lSMUICLK->ICLK = (Hw31|lclkdiv); ++ } ++ else ++ { ++ lclkdiv = 0; ++ lSMUICLK->ICLK = 0; ++ } ++ ++ ++} ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getsmui2c(void) ++* DESCRIPTION : unit : 100Hz ++* ***************************************************************************************/ ++VOLATILE int tca_ckc_getsmui2c(void) ++{ ++ PSMUI2CICLK lSMUICLK; ++ unsigned int lclkctrl7; ++ unsigned int lsel; ++ unsigned int lclksource; ++ unsigned int lclkdiv; ++ ++ lSMUICLK = (PSMUI2CICLK)(iomap_p2v((unsigned int)&HwSMU_I2CICLK_BASE)); //0xF0400000 ++ lclkctrl7 = (unsigned int)pCKC->CLK7CTRL; ++ ++ lsel = (lclkctrl7 & 7); ++ ++ if(((lclkctrl7 >>20) & Hw0) == 0 ) // Normal Mode ++ { ++ switch(lsel) ++ { ++ case DIRECTPLL0: ++ lclksource = tca_ckc_getpll(0); ++ break; ++ case DIRECTPLL1: ++ lclksource = tca_ckc_getpll(1); ++ break; ++ case DIRECTPLL2: ++ lclksource = tca_ckc_getpll(2); ++ break; ++ case DIRECTPLL3: ++ lclksource = tca_ckc_getpll(3); ++ break; ++ default : ++ lclksource = tca_ckc_getpll(1); ++ break; ++ ++ } ++ lclkdiv = (lclkctrl7 & 0xFFFF); ++ ++ if (lclkdiv != 0) ++ { ++ return (lclksource / lclkdiv) ; ++ } ++ else ++ return -1; ++ } ++ else ++ return -1; ++ ++} ++ ++/**************************************************************************************** ++* FUNCTION : void tca_ckc_setddipwdn(unsigned int lpwdn , unsigned int lmode) ++* DESCRIPTION : Power Down Register of DDI_CONFIG ++* ***************************************************************************************/ ++void tca_ckc_setddipwdn(unsigned int lpwdn , unsigned int lmode) ++{ ++ PDDICONFIG lDDIPWDN; ++ unsigned int lindex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7,Hw8}; ++ ++ lDDIPWDN = (PDDICONFIG)(iomap_p2v((unsigned int)&HwDDI_CONFIG_BASE)); //0xF0400000 ++ ++ if(lmode) // Normal ++ lDDIPWDN->PWDN &= ~lindex[lpwdn]; ++ else // Power Down ++ lDDIPWDN->PWDN |= lindex[lpwdn]; ++ ++} ++/**************************************************************************************** ++* FUNCTION : int tca_ckc_getddipwdn(unsigned int lpwdn) ++* DESCRIPTION : Power Down Register of DDI_CONFIG ++* ***************************************************************************************/ ++int tca_ckc_getddipwdn(unsigned int lpwdn) ++{ ++ PDDICONFIG lDDIPWDN; ++ unsigned int lindex[] = {Hw0,Hw1,Hw2,Hw3,Hw4,Hw5,Hw6,Hw7,Hw8}; ++ ++ lDDIPWDN = (PDDICONFIG)(iomap_p2v((unsigned int)&HwDDI_CONFIG_BASE)); //0xF0400000 ++ ++ return (lDDIPWDN->PWDN & lindex[lpwdn]); ++} ++ ++ ++/**************************************************************************************** ++* EXPORT_SYMBOL clock functions for Linux ++* ***************************************************************************************/ ++#if defined(_LINUX_) ++EXPORT_SYMBOL(tca_ckc_init); ++EXPORT_SYMBOL(tca_ckc_getpll); ++EXPORT_SYMBOL(tca_ckc_getcpu); ++EXPORT_SYMBOL(tca_ckc_getbus); ++//EXPORT_SYMBOL(tca_ckc_gclkctrlx); ++//EXPORT_SYMBOL(tca_ckc_gclkctrly); ++EXPORT_SYMBOL(tca_ckc_setfbusctrl); ++EXPORT_SYMBOL(tca_ckc_getfbusctrl); ++//EXPORT_SYMBOL(tca_ckc_gpllxcfg); ++//EXPORT_SYMBOL(tca_ckc_pll); ++EXPORT_SYMBOL(tca_ckc_validpll); ++EXPORT_SYMBOL(tca_ckc_setpll); ++EXPORT_SYMBOL(tca_ckc_setpmupwroff); ++EXPORT_SYMBOL(tca_ckc_getpmupwroff); ++//EXPORT_SYMBOL(tca_ckc_gpckxxx); ++//EXPORT_SYMBOL(tca_ckc_gpckyyy); ++EXPORT_SYMBOL(tca_ckc_setperi); ++//EXPORT_SYMBOL(tca_ckc_gperi); ++EXPORT_SYMBOL(tca_ckc_getperi); ++EXPORT_SYMBOL(tca_ckc_setswresetprd); ++EXPORT_SYMBOL(tca_ckc_set_iobus_swreset); ++EXPORT_SYMBOL(tca_ckc_setswreset); ++EXPORT_SYMBOL(tca_ckc_setiobus); ++EXPORT_SYMBOL(tca_ckc_getiobus); ++EXPORT_SYMBOL(tca_ckc_setsmui2c); ++EXPORT_SYMBOL(tca_ckc_getsmui2c); ++EXPORT_SYMBOL(tca_ckc_setddipwdn); ++EXPORT_SYMBOL(tca_ckc_getddipwdn); ++#endif ++ ++/* end of file */ +diff --git a/arch/arm/mach-tcc8900/tcc b/arch/arm/mach-tcc8900/tcc +new file mode 120000 +index 0000000..c3a8743 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc +@@ -0,0 +1 @@ ++tcc8900 +\ No newline at end of file +diff --git a/arch/arm/mach-tcc8900/tcc8900/arm_ioctlutil.S b/arch/arm/mach-tcc8900/tcc8900/arm_ioctlutil.S +new file mode 100644 +index 0000000..07d6ffc +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/arm_ioctlutil.S +@@ -0,0 +1,23 @@ ++/*************************************************************************************** ++* FileName : arm_ioctlutil.s ++**************************************************************************************** ++* ++* TCC Board Support Package ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************************/ ++ .global arm_changestack ++arm_changestack: ++ mov r0, r13 ++// ldr r13, =0xF0A03FA0 // 0x10000000 ~ 0x10003FFF SRAM(16KB) ++ ldr r13, =0xEFF03FFC // 0x10000000 ~ 0x10003FFF SRAM(16KB) ++ mov pc, lr ++ ++ .global arm_restorestack ++arm_restorestack: ++ mov r13, r0 ++ mov pc, lr ++ ++ ++/************* end of file *************************************************************/ +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.c b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.c +new file mode 100644 +index 0000000..7eb81d9 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.c +@@ -0,0 +1,2259 @@ ++#include "tcc_ckcddr2_141to190.h" ++ ++#if !defined(DRAM_MDDR) ++ ++#define DRAM_ODTOFF ++ ++ ++#define Hw13 0x00002000 ++#define DRAM_AUTOPD_ENABLE Hw13 ++#define DRAM_AUTOPD_PERIOD 7<<7 // must larger than CAS latency ++#define DRAM_SET_AUTOPD DRAM_AUTOPD_ENABLE|DRAM_AUTOPD_PERIOD ++ ++void init_clockchange125Mhz(void) ++{ ++ unsigned int lpll1 =500; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =4; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00007D03; // pms - pllout_480M ++ *(volatile unsigned long *)0xF0400024= 0x80007D03; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000|DRAM_SET_AUTOPD; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012|DRAM_SET_AUTOPD; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ // 1 Tick = 2.5ns ++ *(volatile unsigned long *)0xF0302020 = 0x0000000D; // tRAS - 45ns ++ *(volatile unsigned long *)0xF0302024 = 0x00000011; // tRC - 60ns ++ *(volatile unsigned long *)0xF0302028 = 0x00000205; // tRCD - 15ns ++ *(volatile unsigned long *)0xF030202c = 0x00001B1E; // tRFC - 105ns ++ *(volatile unsigned long *)0xF0302030 = 0x00000205; // tRP - 15ns ++ *(volatile unsigned long *)0xF0302034 = 0x00000005; // tRRD ++ *(volatile unsigned long *)0xF0302038 = 0x00000006; // tWR ++ *(volatile unsigned long *)0xF030203c = 0x00000003; // tWTR ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00003E3E; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ //*(volatile unsigned long *) 0xF0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080362; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080262; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++ #if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++ ++} ++ ++void init_clockchange130Mhz(void) ++{ ++ unsigned int lpll1 =260; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x01008203; // pms - pllout_276M ++ *(volatile unsigned long *)0xF0400024= 0x81008203; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ // 1 Tick = 2.5ns ++ *(volatile unsigned long *)0xF0302020 = 0x0000000D; // tRAS - 45ns ++ *(volatile unsigned long *)0xF0302024 = 0x00000011; // tRC - 60ns ++ *(volatile unsigned long *)0xF0302028 = 0x00000205; // tRCD - 15ns ++ *(volatile unsigned long *)0xF030202c = 0x00001B1E; // tRFC - 105ns ++ *(volatile unsigned long *)0xF0302030 = 0x00000205; // tRP - 15ns ++ *(volatile unsigned long *)0xF0302034 = 0x00000005; // tRRD ++ *(volatile unsigned long *)0xF0302038 = 0x00000006; // tWR ++ *(volatile unsigned long *)0xF030203c = 0x00000003; // tWTR ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00003E3E; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ //*(volatile unsigned long *) 0xF0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080362; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080262; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++void init_clockchange135Mhz(void) ++{ ++ unsigned int lpll1 =540; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =4; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00002D01; // pms - pllout_540M ++ *(volatile unsigned long *)0xF0400024= 0x80002D01; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ *(volatile unsigned long *)0xF0302020 = 0x0000000D; // tRAS - 45ns ++ *(volatile unsigned long *)0xF0302024 = 0x00000011; // tRC - 60ns ++ *(volatile unsigned long *)0xF0302028 = 0x00000205; // tRCD - 15ns ++ *(volatile unsigned long *)0xF030202c = 0x00001B1E; // tRFC - 105ns ++ *(volatile unsigned long *)0xF0302030 = 0x00000205; // tRP - 15ns ++ *(volatile unsigned long *)0xF0302034 = 0x00000005; // tRRD ++ *(volatile unsigned long *)0xF0302038 = 0x00000006; // tWR ++ *(volatile unsigned long *)0xF030203c = 0x00000003; // tWTR ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00003E3E; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ //*(volatile unsigned long *) 0xF0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080362; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ // *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00080262; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++ #if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++void init_clockchange141Mhz(void) ++{ ++ unsigned int lpll1 =282; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x01002F01; // pms - pllout_276M ++ *(volatile unsigned long *)0xF0400024= 0x81002F01; // pll pwr on ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000|DRAM_SET_AUTOPD; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012|DRAM_SET_AUTOPD; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0302008 = 0x00090002; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ //*(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//145Mhz ++void init_clockchange145Mhz(void) ++{ ++ unsigned int lpll1 =580; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =4; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00009103; // pms - pllout_580M ++ *(volatile unsigned long *)0xF0400024= 0x80009103; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//150Mhz ++void init_clockchange150Mhz(void) ++{ ++ unsigned int lpll1 =600; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =4; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00003201; // pms - pllout_600M ++ *(volatile unsigned long *)0xF0400024= 0x80003201; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//160Mhz ++void init_clockchange160Mhz(void) ++{ ++ unsigned int lpll1 =320; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00005003; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80005003; // pll pwr on ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//170Mhz ++void init_clockchange170Mhz(void) ++{ ++ unsigned int lpll1 =340; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00005503; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80005503; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//180Mhz ++void init_clockchange180Mhz(void) ++{ ++ unsigned int lpll1 =360; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00001E01; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80001E01; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//190Mhz ++void init_clockchange190Mhz(void) ++{ ++ unsigned int lpll1 =380; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00005F03; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80005F03; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++#endif +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.h b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.h +new file mode 100644 +index 0000000..9c9a80a +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_141to190.h +@@ -0,0 +1,23 @@ ++#if defined(_LINUX_) ++ #include ++#else ++ #include "windows.h" ++ ++ #include "bsp.h" ++ #include "tca_ckc.h" ++#endif ++ ++ ++#if !defined(DRAM_MDDR) ++extern void init_clockchange125Mhz(void); ++extern void init_clockchange130Mhz(void); ++extern void init_clockchange135Mhz(void); ++extern void init_clockchange141Mhz(void); ++extern void init_clockchange145Mhz(void); ++extern void init_clockchange150Mhz(void); ++extern void init_clockchange160Mhz(void); ++extern void init_clockchange170Mhz(void); ++extern void init_clockchange180Mhz(void); ++extern void init_clockchange190Mhz(void); ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.c b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.c +new file mode 100644 +index 0000000..9a0ff32 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.c +@@ -0,0 +1,2287 @@ ++#include "tcc_ckcddr2_200to290.h" ++ ++#if !defined(DRAM_MDDR) ++ ++//200Mhz ++void init_clockchange200Mhz(void) ++{ ++ unsigned int lpll1 =400; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00006403; // pms - pllout_400M ++ *(volatile unsigned long *)0xF0400024= 0x80006403; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//210Mhz ++void init_clockchange210Mhz(void) ++{ ++ unsigned int lpll1 =420; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00002301; // pms - pllout_420M ++ *(volatile unsigned long *)0xF0400024= 0x80002301; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//220Mhz ++void init_clockchange220Mhz(void) ++{ ++ unsigned int lpll1 =440; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00006E03; // pms - pllout_600M ++ *(volatile unsigned long *)0xF0400024= 0x80006E03; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//230Mhz ++void init_clockchange230Mhz(void) ++{ ++ unsigned int lpll1 =460; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00007303; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80007303; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//240Mhz ++void init_clockchange240Mhz(void) ++{ ++ unsigned int lpll1 =480; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00002801; // pms - pllout_480M ++ *(volatile unsigned long *)0xF0400024= 0x80002801; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//250Mhz ++void init_clockchange250Mhz(void) ++{ ++ unsigned int lpll1 =500; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00007D03; // pms - pllout_320M ++ *(volatile unsigned long *)0xF0400024= 0x80007D03; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//260Mhz ++void init_clockchange260Mhz(void) ++{ ++ unsigned int lpll1 =520; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00008203; // pms - pllout_520M ++ *(volatile unsigned long *)0xF0400024= 0x80008203; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++ ++//270Mhz ++void init_clockchange270Mhz(void) ++{ ++ unsigned int lpll1 =540; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00002D01; // pms - pllout_520M ++ *(volatile unsigned long *)0xF0400024= 0x80002D01; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++ ++//280Mhz ++void init_clockchange280Mhz(void) ++{ ++ unsigned int lpll1 =560; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00008C03; // pms - pllout_560M ++ *(volatile unsigned long *)0xF0400024= 0x80008C03; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle+1; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle+1; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = (((lcycle+1-3)<<8) | (lcycle+1)); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = (((lcycle+1-3)<<8) | (lcycle+1)); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle+1; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle+1; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle+1; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++ ++ ++//290Mhz ++void init_clockchange290Mhz(void) ++{ ++ unsigned int lpll1 =580; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00009103; // pms - pllout_580M ++ *(volatile unsigned long *)0xF0400024= 0x80009103; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = ((lcycle-3)<<8 | lcycle); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = ((lcycle-3)<<8 | lcycle); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = ((lcycle-3)<<8 | lcycle); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.h b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.h +new file mode 100644 +index 0000000..dcd04a9 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_200to290.h +@@ -0,0 +1,24 @@ ++#if defined(_LINUX_) ++ #include ++ #include ++#else ++ #include "windows.h" ++ ++ #include "bsp.h" ++ #include "tca_ckc.h" ++#endif ++ ++ ++#if !defined(DRAM_MDDR) ++ ++extern void init_clockchange200Mhz(void); ++extern void init_clockchange210Mhz(void); ++extern void init_clockchange220Mhz(void); ++extern void init_clockchange230Mhz(void); ++extern void init_clockchange240Mhz(void); ++extern void init_clockchange250Mhz(void); ++extern void init_clockchange260Mhz(void); ++extern void init_clockchange270Mhz(void); ++extern void init_clockchange280Mhz(void); ++extern void init_clockchange290Mhz(void); ++#endif +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.c b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.c +new file mode 100644 +index 0000000..a3569cd +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.c +@@ -0,0 +1,934 @@ ++#include "tcc_ckcddr2_300to330.h" ++ ++#if !defined(DRAM_MDDR) ++ ++#define DRAM_AUTOPD_ENABLE Hw13 ++#define DRAM_AUTOPD_PERIOD 7<<7 // must larger than CAS latency ++#define DRAM_SET_AUTOPD DRAM_AUTOPD_ENABLE|DRAM_AUTOPD_PERIOD ++ ++//300Mhz ++void init_clockchange300Mhz(void) ++{ ++ unsigned int lpll1 =600; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00003201; // pms - pllout_600M ++ *(volatile unsigned long *)0xF0400024= 0x80003201; // pll pwr on ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = ((lcycle-3)<<8 | lcycle); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = ((lcycle-3)<<8 | lcycle); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = ((lcycle-3)<<8 | lcycle); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//312Mhz ++void init_clockchange312Mhz(void) ++{ ++ unsigned int lpll1 =624; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00006802; // pms - pllout_624M ++ *(volatile unsigned long *)0xF0400024= 0x80006802; // pll pwr on ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = ((lcycle-3)<<8 | lcycle); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = ((lcycle-3)<<8 | lcycle); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = ((lcycle-3)<<8 | lcycle); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//320Mhz ++void init_clockchange320Mhz(void) ++{ ++ unsigned int lpll1 =640; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x0000A003; // pms - pllout_640M ++ *(volatile unsigned long *)0xF0400024= 0x8000A003; // pll pwr on ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000; ++// memory arb. end ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000445; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = ((lcycle-3)<<8 | lcycle); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = ((lcycle-3)<<8 | lcycle); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = ((lcycle-3)<<8 | lcycle); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000006; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000005; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (0 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #endif ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090004; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++} ++ ++//330Mhz ++void init_clockchange330Mhz(void) ++{ ++ unsigned int lpll1 =660; ++ unsigned int lmem_source =1; // 0 : PLL0 , 1 : PLL1 ++ unsigned int lmem_div =2; // Fmbus 130Mhz ++ ++ volatile unsigned int i = 0; ++ unsigned int ldiv = 0; ++ unsigned int lcycle = 0; ++ ++//Enter Mode ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xF0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xF0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xF030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ i = 1600; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0400030 = 0x01010101; ++ *(volatile unsigned long *)0xF0400034 = 0x01010101; ++ ++ *(volatile unsigned long *)0xF0400008 = 0x00200014; // XI - memebus ++ ++ i = 2400; ++ while(i) ++ i--; ++ ++ //PLL1 ++ *(volatile unsigned long *)0xF0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xF0400024= 0x00006E02; // pms - pllout_660M ++ *(volatile unsigned long *)0xF0400024= 0x80006E02; // pll pwr on ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++//Init DDR2 ++ *(volatile unsigned long *) 0xF0302004=0x00000003; // PL341_PAUSE ++ *(volatile unsigned long *) 0xF0302004=0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++// memory arb. ++ *(volatile unsigned long *)0xF030200C |= 0x00140000|DRAM_SET_AUTOPD; ++// memory arb. end ++// *(volatile unsigned long *) 0xF0303000 |= 0x80800000; // bit23 enable -synopt enable ++// *(volatile unsigned long *) 0xF0303010 |= 0x80800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xF030200C = 0x00150012|DRAM_SET_AUTOPD; // config0 cas 10bit, ras 13bit ++ *(volatile unsigned long *)0xF0302010 = 0x00000507; // refresh ++ ++#if defined(DRAM_BANK3) ++ *(volatile unsigned long *) 0xF030204c=0x00000571; // config2 - SOC ++#else ++ *(volatile unsigned long *) 0xF030204c=0x00000541; // config2 - SOC ++#endif ++ ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302014 = 0x0000000C; // cas_latency - 5 ++#else ++ *(volatile unsigned long *)0xF0302014 = 0x0000000A; // cas_latency - 5 ++#endif ++ ++ *(volatile unsigned long *)0xF030201c = 0x00000003; // tMRD ++ ++ ldiv = 10000/(lpll1/lmem_div); ++ ++ lcycle = 450/ldiv; ++ *(volatile unsigned long *)0xF0302020 = lcycle; // tRAS - 45ns ++ lcycle = 600/ldiv; ++ *(volatile unsigned long *)0xF0302024 = lcycle; // tRC - 60ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302028 = ((lcycle-3)<<8 | lcycle); // tRCD - 15ns ++ lcycle = 1050/ldiv; ++ *(volatile unsigned long *)0xF030202c = ((lcycle-3)<<8 | lcycle); // tRFC - 105ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302030 = ((lcycle-3)<<8 | lcycle); // tRP - 15ns ++ lcycle = 100/ldiv; ++ *(volatile unsigned long *)0xF0302034 = lcycle; // tRRD - 10ns ++ lcycle = 150/ldiv; ++ *(volatile unsigned long *)0xF0302038 = lcycle; // tWR - 15ns ++ lcycle = 75/ldiv; ++ *(volatile unsigned long *)0xF030203c = lcycle; // tWTR - 7.5ns ++ *(volatile unsigned long *)0xF0302040 = 0x00000003; // tXP - min 2tCK ++ ++ *(volatile unsigned long *)0xF0302044 = 0x00000022; // tXSR ++ *(volatile unsigned long *)0xF0302048 = 0x000000FA; // tESR ++ *(volatile unsigned long *)0xF0302054 = 0x00001619; // tFAW ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0302200 = 0x000040f0; //256MB config_chip0 ++ // *(volatile unsigned long *)0xF0302200 = 0x000040f8; //128MB config_chip0 //soc1-3 ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000001; // PL341_SLEEP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 3); // Wait until SLEEP ++ ++ *(volatile unsigned long *)0xF030302C |= 0x00004000; // SSTL SDRAM IO Control Register ++ ++ *(volatile unsigned long *)0xF0303020 = 0x00010103; // emccfg_config0 ++ *(volatile unsigned long *)0xF0303024 = 0x00000000; // SDRAM PHY Control Register ++ *(volatile unsigned long *)0xF0304400 = 0x00000000; // DDR2PHY_PHYMODE ++ *(volatile unsigned long *)0xF0304404 = 0x00000001; // DLLCTRL ++ ++ *(volatile unsigned long *)0xF0304408 = 0x00001717; // DLLPDCFG ++ ++ *(volatile unsigned long *)0xF0304404 = 0x00000003; // DLLCTRL ++ while (((*(volatile unsigned long *)0xF0304404) & (0x00000018)) != (0x00000018)); // Wait DLL Lock ++ ++ *(volatile unsigned long *)0xF0304424 = 0x00000035; // DLLFORCELOCK ++ *(volatile unsigned long *)0xF030440C = 0x00000006; // GATECTRL ++ #if defined(DRAM_CAS6) ++ *(volatile unsigned long *) 0xF0304430=0x00000004; // RDDELAY - SOC ++ #else ++ *(volatile unsigned long *) 0xF0304430=0x00000004; // RDDELAY - SOC ++ #endif ++ ++ ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = 0x0006e551; ++ #endif ++ ++ while (!((*(volatile unsigned long *)0xF030442c) & (1))); // Wait until Calibration completion without error ++ #if defined(DRAM_ODTOFF) ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xF0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ #else ++ *(volatile unsigned long *)0xF0304428 = 0x0006e553; // ZQCTRL ++ #endif ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0304428 = 0x0006e551; // ZQCTRL ++ ++ i = 3200; ++ while(i) ++ i--; ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000002; // PL34X_WAKEUP ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 2); // Wait until PAUSE ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000004; // PL341_CONFIGURE ++ while (((*(volatile unsigned long *)0xF0302000) & (0x03)) != 0); // Wait until CONFIGURE ++ ++ *(volatile unsigned long *)0xF0302008 = 0x000c0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00040000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000a0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x000b0000; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080962; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080952; // Direct COmmnad Register ++#endif ++ ++ *(volatile unsigned long *)0xF0302008 = 0x00000000; // Direct COmmnad Register ++ ++ i = 100; ++ while(i) ++ { ++ *(volatile unsigned long *) 0xF0302008=0x00040000; // dir_cmd ++ i--; ++ } ++ ++#if defined(DRAM_CAS6) ++ *(volatile unsigned long *)0xF0302008 = 0x00080862; // Direct COmmnad Register ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00080852; // Direct COmmnad Register ++#endif ++ ++#if defined(DRAM_ODTOFF) ++ ++#else ++ *(volatile unsigned long *)0xF0302008 = 0x00090380; // Direct COmmnad Register ++ *(volatile unsigned long *)0xF0302008 = 0x00090000; // Direct COmmnad Register //soc1-3 ++#endif ++ ++ ++ *(volatile unsigned long *)0xF0302004 = 0x00000000; // PL341_GO ++ ++ i = 1600; ++ while(i) ++ i--; ++} ++ ++#endif +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.h b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.h +new file mode 100644 +index 0000000..28d2e44 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcddr2_300to330.h +@@ -0,0 +1,19 @@ ++#if defined(_LINUX_) ++ #include ++ #include ++#else ++ #include "windows.h" ++ ++ #include "bsp.h" ++ #include "tca_ckc.h" ++#endif ++ ++ ++#if !defined(DRAM_MDDR) ++ ++extern void init_clockchange300Mhz(void); ++extern void init_clockchange312Mhz(void); ++extern void init_clockchange320Mhz(void); ++extern void init_clockchange330Mhz(void); ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.c b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.c +new file mode 100644 +index 0000000..849d8e2 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.c +@@ -0,0 +1,1403 @@ ++#include "tcc_ckcmddr_100to160.h" ++ ++#if defined(DRAM_MDDR) ++ ++//141Mhz ++void init_clockchange100Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00006403; // pms - pllout_400M ++ *(volatile unsigned long *)0xB0400024= 0x80006403; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange105Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00002301; // pms - pllout_420M ++ *(volatile unsigned long *)0xB0400024= 0x80002301; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++} ++ ++//145Mhz ++void init_clockchange110Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00006E03; // pms - pllout_440M ++ *(volatile unsigned long *)0xB0400024= 0x80006E03; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange115Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00007303; // pms - pllout_460M ++ *(volatile unsigned long *)0xB0400024= 0x80007303; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++//150Mhz ++void init_clockchange120Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00002801; // pms - pllout_480M ++ *(volatile unsigned long *)0xB0400024= 0x80002801; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange125Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00007D03; // pms - pllout_500M ++ *(volatile unsigned long *)0xB0400024= 0x80007D03; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++//160Mhz ++ ++void init_clockchange130Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 2 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x01008203; // pms - pllout_260M ++ *(volatile unsigned long *)0xB0400024= 0x81008203; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange135Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00002D01; // pms - pllout_540M ++ *(volatile unsigned long *)0xB0400024= 0x80002D01; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++} ++ ++ ++//170Mhz ++void init_clockchange140Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00008C03; // pms - pllout_560M ++ *(volatile unsigned long *)0xB0400024= 0x80008C03; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange145Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00009103; // pms - pllout_580M ++ *(volatile unsigned long *)0xB0400024= 0x80009103; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++//150Mhz ++void init_clockchange150Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00003201; // pms - pllout_600M ++ *(volatile unsigned long *)0xB0400024= 0x80003201; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++} ++void init_clockchange156Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 2 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00001A01; // pms - pllout_312M ++ *(volatile unsigned long *)0xB0400024= 0x80001A01; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++//#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++//#else ++// *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++//#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange160Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 2 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00005003; // pms - pllout_320M ++ *(volatile unsigned long *)0xB0400024= 0x80005003; // pms - pllout_320M ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.h b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.h +new file mode 100644 +index 0000000..ad0efe9 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_100to160.h +@@ -0,0 +1,27 @@ ++#if defined(_LINUX_) ++ #include ++ #include ++#else ++#include "windows.h" ++ ++#include "bsp.h" ++#include "tca_ckc.h" ++#endif ++ ++#if defined(DRAM_MDDR) ++ ++extern void init_clockchange100Mhz(void); ++extern void init_clockchange105Mhz(void); ++extern void init_clockchange110Mhz(void); ++extern void init_clockchange115Mhz(void); ++extern void init_clockchange120Mhz(void); ++extern void init_clockchange125Mhz(void); ++extern void init_clockchange130Mhz(void); ++extern void init_clockchange135Mhz(void); ++extern void init_clockchange140Mhz(void); ++extern void init_clockchange145Mhz(void); ++extern void init_clockchange150Mhz(void); ++extern void init_clockchange156Mhz(void); ++extern void init_clockchange160Mhz(void); ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.c b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.c +new file mode 100644 +index 0000000..a57a7fb +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.c +@@ -0,0 +1,1570 @@ ++#include "tcc_ckcmddr_20to90.h" ++ ++#if defined(DRAM_MDDR) ++void init_clockchange25Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x02006503; // pms - pllout_101M ++ *(volatile unsigned long *)0xB0400024= 0x82006503; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++//30.5Mhz ++void init_clockchange30Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x01007A03; // pms - pllout_244M ++ *(volatile unsigned long *)0xB0400024= 0x81007A03; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++//35.25Mhz ++void init_clockchange35Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x01002F01; // pms - pllout_282M ++ *(volatile unsigned long *)0xB0400024= 0x81002F01; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++void init_clockchange40Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00005003; // pms - pllout_320M ++ *(volatile unsigned long *)0xB0400024= 0x80005003; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange45Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x01001E01; // pms - pllout_180M ++ *(volatile unsigned long *)0xB0400024= 0x81001E01; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange50Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00006403; // pms - pllout_400M ++ *(volatile unsigned long *)0xB0400024= 0x80006403; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x66; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000002; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++ ++void init_clockchange55Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00006E03; // pms - pllout_440M ++ *(volatile unsigned long *)0xB0400024= 0x80006E03; // pll pwr on ++ ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 4; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x87; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x2; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x2; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x1; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x2; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 8; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange60Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00002801; // pms - pllout_480M ++ *(volatile unsigned long *)0xB0400024= 0x80002801; // pll pwr on ++ ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 4; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 5; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0xE7; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000002; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 10; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange65Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00008203; // pms - pllout_520M ++ *(volatile unsigned long *)0xB0400024= 0x80008203; // pll pwr on ++ ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 4; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 5; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0xE7; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000002; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 10; // tXSR 120ns ++ ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange70Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x01002F01; // pms - pllout_282M ++ *(volatile unsigned long *)0xB0400024= 0x81002F01; // pll pwr on ++ ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 4; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 9; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x18F; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000002; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 20; // tXSR 120ns ++ ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange75Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 8 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00003201; // pms - pllout_600M ++ *(volatile unsigned long *)0xB0400024= 0x80003201; // pll pwr on ++ ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 4; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 9; // tRC 60ns ++ ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x18F; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000002; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 20; // tXSR 120ns ++ ++ ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange80Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00005003; // pms - pllout_320M ++ *(volatile unsigned long *)0xB0400024= 0x80005003; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 3; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 5; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x14; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x66; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x14; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 10; // tXSR 120ns ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *) 0xB0304404 &= ~(0x00000003); // DLLCTRL - DLL OFF, Not Useing DLL ++ *(volatile unsigned long *)0xB0301008 = 0x00000022; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++ *(volatile unsigned long *)0xB0301008 = 0x00040022; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++} ++ ++void init_clockchange85Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++//PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00005503; // pms - pllout_340M ++ *(volatile unsigned long *)0xB0400024= 0x80005503; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++//190Mhz ++void init_clockchange90Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00001E01; // pms - pllout_360M ++ *(volatile unsigned long *)0xB0400024= 0x80001E01; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++//Change MEM Source ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++ ++void init_clockchange95Mhz(void) ++{ ++ #define lchange_source 2 ++ #define lchange_div 4 ++ ++ #define lmem_source 1 // 0 : PLL0 , 1 : PLL1 ++ #define lmem_div 4 ++ ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000003; // PL341_PAUSE ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=2); //Wait PL34X_STATUS_PAUSED ++ ++ *(volatile unsigned long *)0xB0301004 = 0x00000004; // PL341_Configure ++ while (((*(volatile unsigned long *)0xB0301000) & 0x3)!=0); //Wait PL34X_STATUS_CONFIG ++ ++// DLL OFF ++ *(volatile unsigned long *)0xB0304404 &= ~(0x00000003); // DLL-0FF,DLL-Stop running ++ *(volatile unsigned long *)0xB0304428 &= ~(0x00000003); // Calibration Start,Update Calibration ++ *(volatile unsigned long *)0xB030302C &= ~(0x00004000); //SDRAM IO Control Register Gatein Signal Power Down ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lchange_div-1) << 4)|lchange_source); // CKC-CLKCTRL2 - Mem ++ ++ //PLL1 ++ *(volatile unsigned long *)0xB0400024= 0x0000fa03; // pll pwr off ++ *(volatile unsigned long *)0xB0400024= 0x00005F03; // pms - pllout_380M ++ *(volatile unsigned long *)0xB0400024= 0x80005F03; // pll pwr on ++ ++//Init DDR2 ++ *(volatile unsigned long *)0xB030100C = 0x00210012; // config0 cas 10bit, ras 13bit , AP bit 10, Burst 4, 2chips ++ ++ *(volatile unsigned long *) 0xB0303000 |= 0x00800000; // bit23 enable -synopt enable ++ *(volatile unsigned long *) 0xB0303010 |= 0x00800000; // bit23 enable -synopt enable ++ ++ *(volatile unsigned long *)0xB030104C= 0x000002D1; ++ *(volatile unsigned long *)0xB0301010 = 0x000003E8; // refresh_prd = 1000 ++ ++#if defined(DRAM_CAS3) ++ *(volatile unsigned long *)0xB0301014 = 0x00000006; // cas_latency = 3 ++#else ++ *(volatile unsigned long *)0xB0301014 = 0x00000004; // cas_latency = 2 ++#endif ++ ++ *(volatile unsigned long *)0xB030101C = 0x00000002; // tMRD 2tck ++ *(volatile unsigned long *)0xB0301020 = 0x0000000A; // tRAS 42ns ++ *(volatile unsigned long *)0xB0301024 = 0x0000000F; // tRC 60ns ++ *(volatile unsigned long *)0xB0301028 = 0x00000014; // tRCD 18ns ++ *(volatile unsigned long *)0xB030102c = 0x00000E11; // tRFC 72ns ++ *(volatile unsigned long *)0xB0301030 = 0x00000014; // tRP 18ns ++ *(volatile unsigned long *)0xB0301034 = 0x00000001; // tRRD 12ns ++ *(volatile unsigned long *)0xB0301038 = 0x00000002; // tWR 15ns ++ *(volatile unsigned long *)0xB030103c = 0x00000001; // tWTR 1tck ++ *(volatile unsigned long *)0xB0301040 = 0x00000002; // tXP=3 ++ *(volatile unsigned long *)0xB0301044 = 0x00000016; // tXSR 120ns ++ *(volatile unsigned long *)0xB0301048 = 0x00000032; // tESR=200 ++ ++ *(volatile unsigned long *)0xB0301200 = 0x000040F0; // Chip 0 ++ ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ while (!((*(volatile unsigned long *)0xB030442c) & (1))); // Wait until Calibration completion without error ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (1 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ *(volatile unsigned long *)0xB0304428 = (3 << 17) // PRD_CAL ++ | (0 << 16) // PRD_CEN ++ | (7 << 13) // DRV_STR ++ | (1 << 12) // TERM_DIS ++ | (2 << 9) // ODT(PHY) value ++ | (5 << 6) // PULL UP ++ | (2 << 3) // PULL DOWN ++ | (0 << 2) // ZQ ++ | (0 << 1) // UPDATE ++ | (1 << 0); // CAL_START ++ ++ ++ *(volatile unsigned long *)0xB0301008 = 0x00000032; //MRS ++ *(volatile unsigned long *)0xB0301008 = 0x000a0000;//EMRS ++ *(volatile unsigned long *)0xB0301008 = 0x00080032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ *(volatile unsigned long *)0xB0301008 = 0x00040032; ++ ++//Change MEM Source ++ ++ ++ *(volatile unsigned long *)0xB0400008 = (0x00200000 | ((lmem_div-1) << 4)|lmem_source); // CKC-CLKCTRL2 - Mem ++ ++ ++ *(volatile unsigned long *) 0xB0301004=0x00000000; // PL341_GO ++ while (((*(volatile unsigned long *)0xB0301000) & (0x03)) != 1); // Wait until READY ++ ++} ++#endif +diff --git a/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.h b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.h +new file mode 100644 +index 0000000..96b719d +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc8900/tcc_ckcmddr_20to90.h +@@ -0,0 +1,29 @@ ++ ++#if defined(_LINUX_) ++ #include ++ #include ++#else ++#include "windows.h" ++ ++#include "bsp.h" ++#include "tca_ckc.h" ++#endif ++ ++#if defined(DRAM_MDDR) ++extern void init_clockchange25Mhz(void); ++extern void init_clockchange30Mhz(void); ++extern void init_clockchange35Mhz(void); ++extern void init_clockchange40Mhz(void); ++extern void init_clockchange45Mhz(void); ++extern void init_clockchange50Mhz(void); ++extern void init_clockchange55Mhz(void); ++extern void init_clockchange60Mhz(void); ++extern void init_clockchange65Mhz(void); ++extern void init_clockchange70Mhz(void); ++extern void init_clockchange75Mhz(void); ++extern void init_clockchange80Mhz(void); ++extern void init_clockchange85Mhz(void); ++extern void init_clockchange90Mhz(void); ++extern void init_clockchange95Mhz(void); ++#endif ++ +diff --git a/arch/arm/mach-tcc8900/tcc_ckc_ctrl.c b/arch/arm/mach-tcc8900/tcc_ckc_ctrl.c +new file mode 100644 +index 0000000..37eea99 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/tcc_ckc_ctrl.c +@@ -0,0 +1,803 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/tcc_ckc_ctrl.c ++ * ++ * Author: ++ * Created: 10th February, 2009 ++ * Description: Interrupt handler for Telechips TCC8900 chipset ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MACH_TCC8900) ++#include ++#include ++#include ++#include "tcc/tcc_ckcddr2_141to190.h" ++#include "tcc/tcc_ckcddr2_200to290.h" ++#include "tcc/tcc_ckcddr2_300to330.h" ++#include "tcc/tcc_ckcmddr_100to160.h" ++#include "tcc/tcc_ckcmddr_20to90.h" ++#endif ++ ++#if 0 ++//#define dbg(x...) printk(KERN_DEBUG "tcc uart: "); ++#define dbg printk ++#else /* no debug */ ++#define dbg(x...) do {} while(0) ++#endif ++ ++#define FBUS_STEP_NUM 34 ++#define FCORE_STEP_NUM 60 ++ ++typedef void (*lpfunc)(void); ++lpfunc lpSelfRefresh; ++//#define SRAM_COPY_ADDR 0xF0800000 ++#define SRAM_COPY_ADDR 0xEFF00000 ++#define SRAM_COPY_FUNC_SIZE 0x600 ++ ++unsigned int retstack = 0; ++unsigned long flags; ++ ++unsigned int FbusStepValue[FBUS_STEP_NUM] = { ++ 2640000, // PLL3 ++ 2340000, ++ 1760000, // PLL3 ++ 1560000, ++ 1320000, // PLL3 ++ 1170000, ++ 1056000, // PLL3 ++ 936000, ++ 880000, // PLL3 ++ 780000, ++ 754285, // PLL3 ++ 668571, ++ 660000, // PLL3 ++ 586666, // PLL3 ++ 585000, ++ 528000, // PLL3 ++ 520000, ++ 480000, // PLL3 ++ 468000, ++ 440000, // PLL3 ++ 425454, ++ 406153, // PLL3 ++ 390000, ++ 377142, // PLL3 ++ 360000, ++ 352000, // PLL3 ++ 334285, ++ 330000, // PLL3 ++ 312000, ++ 292500, ++ 60000, // XIN ++ 30000, // XIN ++ 10000, // XIN ++}; ++ ++unsigned int FcoreStepValue[FCORE_STEP_NUM] = { ++ 5400000, ++ 5062500,4860000,4725000,4556250,4387500,4252500,4050000,3948750,3780000,3712500, ++ 3645000,3510000,3375000,3240000,3037500,2970000,2835000,2700000,2632500,2430000, ++ 2362500,2227500,2160000,2025000,1890000,1822500,1750000,1687500,1620000,1518750, ++ 1485000,1417500,1350000 ,1215000,1125000,1080000,1012500, 960000 ,945000, 907500 , ++ 883750 ,840000 , 810000 ,787500 ,757500 ,730000 ,712500 ,660000 ,631250,607500 , ++ 577500 ,540000 , 495000 ,450000 ,405000 ,378750 ,360000 ,330000 ,270000 ++}; ++ ++unsigned int FcorePllValue[FCORE_STEP_NUM] = { ++ 5400000, ++ 5400000, 4860000, 5400000, 4860000, 5400000, 4860000, 4320000, 4860000, 4320000, 5400000, ++ 4860000, 4320000, 5400000, 3240000, 3240000, 4320000, 3240000, 5400000, 3240000, 3240000, ++ 5400000, 3240000, 2160000, 2160000, 2160000, 3240000, 2160000, 5400000, 2160000, 4860000, ++ 2160000,3240000, 2160000, 2160000, 1800000, 2160000, 3240000, 1920000, 2160000, 1320000, ++ 2020000, 1920000, 2160000, 1800000, 2020000, 1460000, 1900000, 1320000, 2020000, 3240000, ++ 1320000, 1440000, 1320000, 1440000, 2160000, 2020000, 1440000,1320000,1440000, ++}; ++ ++unsigned int FcoreDividerValue[FCORE_STEP_NUM] = { ++ 16, ++ 15, 16, 14, 15, 13, 14, 15, 13, 14, 11, ++ 12, 13, 10, 16, 15, 11, 14, 8, 13, 12, ++ 7, 11, 16, 15, 14, 9, 13, 5, 12 , 5, ++ 11, 7, 10, 9, 10, 8, 5, 8, 7, 11, ++ 7, 7, 6, 7, 6, 8, 6, 8, 5, 3, ++ 7, 6, 6, 5, 3, 3, 4, 4, 3 ++ ++}; ++ ++ ++ ++ ++void ckc_delay(unsigned int cnt) ++{ ++ volatile unsigned int count; ++ count = cnt*10000; ++ while(count--); ++} ++ ++ ++void ckc_etcblock(unsigned int lMask) ++{ ++ volatile PUSBOTGCFG pOTGCFG = (volatile PUSBOTGCFG)tcc_p2v(HwUSBOTGCFG_BASE); ++ volatile PGPUGRPBUSCONFIG pGPUGRPBUSCONFIG = (volatile PGPUGRPBUSCONFIG)tcc_p2v(HwGRPBUS_BASE); ++ ++// Disable ++ if(lMask & ETCMASK_USBPHYOFF) ++ { ++ dbg("%s: ETC_USBPHYOFF\n", __func__); ++ BITCSET(pOTGCFG->UPCR2,Hw10|Hw9,Hw9); ++ pOTGCFG->UPCR0 = 0x4840; ++ pOTGCFG->UPCR0 = 0x6940; ++ } ++ ++ if(lMask & ETCMASK_3DGPUOFF) ++ { ++ dbg("%s: ETCMASK_3DGPUOFF\n", __func__); ++ pGPUGRPBUSCONFIG->GRPBUS_PWRDOWN |= Hw0; ++ } ++ ++ if(lMask & ETCMASK_OVERLAYMIXEROFF) ++ { ++ dbg("%s: ETCMASK_OVERLAYMIXEROFF\n", __func__); ++ pGPUGRPBUSCONFIG->GRPBUS_PWRDOWN |= Hw1; ++ } ++ ++//Enable ++ if(lMask & ETCMASK_OVERLAYMIXERON) ++ { ++ dbg("%s: ETCMASK_OVERLAYMIXEROFF\n", __func__); ++ pGPUGRPBUSCONFIG->GRPBUS_PWRDOWN &= ~Hw1; ++ } ++ ++ if(lMask & ETCMASK_3DGPUON) ++ { ++ dbg("%s: ETCMASK_3DGPUON\n", __func__); ++ pGPUGRPBUSCONFIG->GRPBUS_PWRDOWN &= ~Hw0; ++ } ++ ++ if(lMask & ETCMASK_USBPHYON) ++ { ++ dbg("%s: ETC_USBPHYON\n", __func__); ++ BITCSET(pOTGCFG->UPCR2,Hw10|Hw9,0); ++ pOTGCFG->UPCR0 = 0x2842; ++ } ++} ++ ++ ++void int_alldisable(void) ++{ ++ /* ++ volatile unsigned int count; ++ count = 1; ++ while(count--); ++ */ ++ local_irq_save(flags); ++ local_irq_disable(); ++ ++} ++ ++void int_restore(void) ++{ ++ /* ++ volatile unsigned int count; ++ count = 1; ++ while(count--); ++ */ ++ ++ local_irq_restore(flags); ++} ++ ++ ++ ++static void init_copychangeclock(unsigned int lbusvalue) ++{ ++ ++ volatile unsigned int *fptr; ++ volatile unsigned int *p; ++ int i; ++ ++#if defined(CONFIG_DRAM_DDR2) ++ if(lbusvalue == 1250000) ++ fptr = (volatile unsigned int*)init_clockchange125Mhz; ++ else if(lbusvalue == 1300000) ++ fptr = (volatile unsigned int*)init_clockchange130Mhz; ++ else if(lbusvalue == 1350000) ++ fptr = (volatile unsigned int*)init_clockchange135Mhz; ++ else if(lbusvalue == 1410000) ++ fptr = (volatile unsigned int*)init_clockchange141Mhz; ++ else if(lbusvalue == 1450000) ++ fptr = (volatile unsigned int*)init_clockchange145Mhz; ++ else if(lbusvalue == 1500000) ++ fptr = (volatile unsigned int*)init_clockchange150Mhz; ++ else if(lbusvalue == 1600000) ++ fptr = (volatile unsigned int*)init_clockchange160Mhz; ++ else if(lbusvalue == 1700000) ++ fptr = (volatile unsigned int*)init_clockchange170Mhz; ++ else if(lbusvalue == 1800000) ++ fptr = (volatile unsigned int*)init_clockchange180Mhz; ++ else if(lbusvalue == 1900000) ++ fptr = (volatile unsigned int*)init_clockchange190Mhz; ++ else if(lbusvalue == 2000000) ++ fptr = (volatile unsigned int*)init_clockchange200Mhz; ++ else if(lbusvalue == 2100000) ++ fptr = (volatile unsigned int*)init_clockchange210Mhz; ++ else if(lbusvalue == 2200000) ++ fptr = (volatile unsigned int*)init_clockchange220Mhz; ++ else if(lbusvalue == 2300000) ++ fptr = (volatile unsigned int*)init_clockchange230Mhz; ++ else if(lbusvalue == 2400000) ++ fptr = (volatile unsigned int*)init_clockchange240Mhz; ++ else if(lbusvalue == 2500000) ++ fptr = (volatile unsigned int*)init_clockchange250Mhz; ++ else if(lbusvalue == 2600000) ++ fptr = (volatile unsigned int*)init_clockchange260Mhz; ++ else if(lbusvalue == 2700000) ++ fptr = (volatile unsigned int*)init_clockchange270Mhz; ++ else if(lbusvalue == 2800000) ++ fptr = (volatile unsigned int*)init_clockchange280Mhz; ++ else if(lbusvalue == 2900000) ++ fptr = (volatile unsigned int*)init_clockchange290Mhz; ++ else if(lbusvalue == 3000000) ++ fptr = (volatile unsigned int*)init_clockchange300Mhz; ++ else if(lbusvalue == 3120000) ++ fptr = (volatile unsigned int*)init_clockchange312Mhz; ++ else if(lbusvalue == 3200000) ++ fptr = (volatile unsigned int*)init_clockchange320Mhz; ++ else if(lbusvalue == 3300000) ++ fptr = (volatile unsigned int*)init_clockchange330Mhz; ++ else ++ fptr = (volatile unsigned int*)init_clockchange190Mhz; ++ ++#elif defined(CONFIG_DRAM_MDDR) ++ if(lbusvalue == 250000) // idle ++ fptr = (volatile unsigned int*)init_clockchange25Mhz; ++ else if(lbusvalue == 305000) ++ fptr = (volatile unsigned int*)init_clockchange30Mhz; ++ else if(lbusvalue == 352500) ++ fptr = (volatile unsigned int*)init_clockchange35Mhz; ++ else if(lbusvalue == 400000) ++ fptr = (volatile unsigned int*)init_clockchange40Mhz; ++ else if(lbusvalue == 450000) ++ fptr = (volatile unsigned int*)init_clockchange45Mhz; ++ else if(lbusvalue == 500000) ++ fptr = (volatile unsigned int*)init_clockchange50Mhz; ++ else if(lbusvalue == 550000) ++ fptr = (volatile unsigned int*)init_clockchange55Mhz; ++ else if(lbusvalue == 600000) ++ fptr = (volatile unsigned int*)init_clockchange60Mhz; ++ else if(lbusvalue == 650000) ++ fptr = (volatile unsigned int*)init_clockchange65Mhz; ++ else if(lbusvalue == 705000) ++ fptr = (volatile unsigned int*)init_clockchange70Mhz; ++ else if(lbusvalue == 750000) ++ fptr = (volatile unsigned int*)init_clockchange75Mhz; ++ else if(lbusvalue == 800000) ++ fptr = (volatile unsigned int*)init_clockchange80Mhz; ++ else if(lbusvalue == 850000) ++ fptr = (volatile unsigned int*)init_clockchange85Mhz; ++ else if(lbusvalue == 900000) ++ fptr = (volatile unsigned int*)init_clockchange90Mhz; ++ else if(lbusvalue == 950000) ++ fptr = (volatile unsigned int*)init_clockchange95Mhz; ++ else if(lbusvalue == 1000000) ++ fptr = (volatile unsigned int*)init_clockchange100Mhz; ++ else if(lbusvalue == 1050000) ++ fptr = (volatile unsigned int*)init_clockchange105Mhz; ++ else if(lbusvalue == 1100000) ++ fptr = (volatile unsigned int*)init_clockchange110Mhz; ++ else if(lbusvalue == 1150000) ++ fptr = (volatile unsigned int*)init_clockchange115Mhz; ++ else if(lbusvalue == 1200000) ++ fptr = (volatile unsigned int*)init_clockchange120Mhz; ++ else if(lbusvalue == 1250000) ++ fptr = (volatile unsigned int*)init_clockchange125Mhz; ++ else if(lbusvalue == 1300000) ++ fptr = (volatile unsigned int*)init_clockchange130Mhz; ++ else if(lbusvalue == 1350000) ++ fptr = (volatile unsigned int*)init_clockchange135Mhz; ++ else if(lbusvalue == 1400000) ++ fptr = (volatile unsigned int*)init_clockchange140Mhz; ++ else if(lbusvalue == 1450000) ++ fptr = (volatile unsigned int*)init_clockchange145Mhz; ++ else if(lbusvalue == 1500000) ++ fptr = (volatile unsigned int*)init_clockchange150Mhz; ++ else if(lbusvalue == 1560000) ++ fptr = (volatile unsigned int*)init_clockchange156Mhz; ++ else if(lbusvalue == 1600000) ++ fptr = (volatile unsigned int*)init_clockchange160Mhz; ++ else ++ fptr = (volatile unsigned int*)init_clockchange160Mhz; ++#endif ++ ++ ++ lpSelfRefresh = (lpfunc)(SRAM_COPY_ADDR); ++ ++ p = (volatile unsigned int*)SRAM_COPY_ADDR; ++ ++ for (i = 0;i < (SRAM_COPY_FUNC_SIZE);i++) ++ { ++ *p = *fptr; ++ p++; ++ fptr++; ++ } ++ ++ while(--i); ++ ++ // Jump to Function Start Point ++ lpSelfRefresh(); ++} ++ ++void memchange(unsigned int freq) ++{ ++ volatile PLCDC pLCDC_BASE0 = (volatile PLCDC)tcc_p2v(HwLCDC0_BASE); ++ volatile PLCDC pLCDC_BASE1 = (volatile PLCDC)tcc_p2v(HwLCDC1_BASE); ++ volatile PTIMER pTIMER = (volatile PTIMER)tcc_p2v(HwTMR_BASE); ++ ++ // Off LCD ++ pLCDC_BASE1->LCTRL &= ~Hw0; ++ pLCDC_BASE0->LCTRL &= ~Hw0; ++ ++ int_alldisable(); ++ local_flush_tlb_all(); ++ flush_cache_all(); ++ ++ pTIMER->TC32EN &= ~Hw24; ++ ++ retstack = arm_changestack(); ++ ++ init_copychangeclock(freq); ++ ++ arm_restorestack(retstack); ++ ++ pTIMER->TC32EN |= Hw24; ++ ++ int_restore(); ++ ++ // LCDC Power Up ++// pLCDC_BASE0->LCTRL |= Hw0; ++ pLCDC_BASE1->LCTRL |= Hw0; ++ *(volatile unsigned long *)0xF0200000 &= ~(0x1);//disable LCD0 ++} ++ ++int tcc_ckc_change_cpu(unsigned int cpuvalue) ++{ ++ unsigned int i, validFlag; ++ ++ int_alldisable(); ++ ++ for(i = 0; i < FCORE_STEP_NUM; i++) ++ { ++ if(cpuvalue == FcoreStepValue[i]) { ++ validFlag = 1; ++ break; ++ } ++ } ++ ++ if(validFlag == 1) ++ { ++ // Change pll ++ if(tca_ckc_getpll(0) != FcorePllValue[i]) ++ tca_ckc_setpll(FcorePllValue[i],0); ++ tca_ckc_setcpu(FcoreDividerValue[i]); ++ } ++ int_restore(); ++ ++ return validFlag == 1 ? 0 : 1; ++} ++EXPORT_SYMBOL(tcc_ckc_change_cpu); ++ ++void ckc_set_peri(struct ckc_ioctl st) ++{ ++ int_alldisable(); ++ tca_ckc_setperi(st.in_ckc.pckcname, st.in_ckc.pckcenable, ++ st.in_ckc.pckcfreq, st.in_ckc.pckcsource); ++ int_restore(); ++} ++ ++int ckc_get_peri(struct ckc_ioctl st) ++{ ++ return tca_ckc_getperi(st.in_ckc.pckcname); ++} ++ ++int ckc_set_peribus(struct ckc_ioctl st) ++{ ++ return tca_ckc_setiobus(st.in_ckc.prbname, st.in_ckc.mode); ++} ++ ++int ckc_get_peribus(struct ckc_ioctl st) ++{ ++ return tca_ckc_getiobus(st.in_ckc.prbname); ++} ++ ++void ckc_set_periswreset(struct ckc_ioctl st) ++{ ++ tca_ckc_set_iobus_swreset(st.in_ckc.prbname, OFF); ++ tca_ckc_set_iobus_swreset(st.in_ckc.prbname, ON); ++} ++ ++void ckc_set_fbusswreset(struct ckc_ioctl st) ++{ ++ tca_ckc_setswreset(st.in_ckc.fbusname, ON); ++ ckc_delay(100); ++ tca_ckc_setswreset(st.in_ckc.fbusname, OFF); ++} ++ ++void ckc_set_cpu(struct ckc_ioctl st) ++{ ++ int_alldisable(); ++ ++ tca_ckc_setcpu(st.in_ckc.cpudivider); ++ st.out_ckc.currentsysfreq = tca_ckc_getpll(0); ++ st.out_ckc.currentcpufreq = tca_ckc_getcpu(); ++ st.out_ckc.currentbusfreq = tca_ckc_getbus(); ++ ++ int_restore(); ++} ++ ++void ckc_set_smui2c(struct ckc_ioctl st) ++{ ++ tca_ckc_setsmui2c(st.in_ckc.pckcfreq); ++} ++ ++unsigned int ckc_get_cpu(struct ckc_ioctl st) ++{ ++ return tca_ckc_getcpu(); ++} ++ ++unsigned int ckc_get_bus(struct ckc_ioctl st) ++{ ++ return tca_ckc_getbus(); ++} ++ ++void ckc_get_validpllinfo(struct ckc_ioctl st) ++{ ++ tca_ckc_validpll(st.out_ckc.validpll); ++} ++ ++void ckc_set_fbus(struct ckc_ioctl st) ++{ ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname, st.in_ckc.fbusenable, ++ st.in_ckc.mode, st.in_ckc.fbusfreq, ++ st.in_ckc.fbussource); ++} ++ ++int ckc_get_fbus(struct ckc_ioctl st) ++{ ++ return tca_ckc_getfbusctrl(st.in_ckc.fbusname); ++ ++} ++ ++void ckc_set_pmupower(struct ckc_ioctl st) ++{ ++#if defined(CONFIG_TCC_R_AX) ++ if(st.in_ckc.mode == 0) ++ { ++ st.in_ckc.fbusenable = DISABLE; ++ st.in_ckc.mode = NORMAL_MD; ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname, st.in_ckc.fbusenable, st.in_ckc.mode, st.in_ckc.fbusfreq, st.in_ckc.fbussource); ++ tca_ckc_setswreset(st.in_ckc.fbusname,ON); ++ ckc_delay(100); ++ tca_ckc_setswreset(st.in_ckc.fbusname,OFF); ++ tca_ckc_setpmupwroff(st.in_ckc.pmuoffname, st.in_ckc.fbusenable); ++ } else { ++ tca_ckc_setswreset(st.in_ckc.fbusname,ON); ++ ckc_delay(100); ++ tca_ckc_setswreset(st.in_ckc.fbusname,OFF); ++ tca_ckc_setpmupwroff(st.in_ckc.pmuoffname,ENABLE); ++ ++ st.in_ckc.fbusenable = ENABLE; ++ st.in_ckc.mode = NORMAL_MD; ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,st.in_ckc.fbusenable,st.in_ckc.mode,st.in_ckc.fbusfreq,st.in_ckc.fbussource); ++ } ++#endif ++} ++ ++void ckc_get_pmupower(struct ckc_ioctl st) ++{ ++ tca_ckc_getpmupwroff(st.in_ckc.pmuoffname); ++} ++ ++void ckc_get_clockinfo(struct ckc_ioctl st) ++{ ++ st.out_ckc.currentsysfreq = tca_ckc_getpll(0); ++ st.out_ckc.currentcpufreq = tca_ckc_getcpu(); ++ st.out_ckc.currentbusfreq = tca_ckc_getbus(); ++} ++ ++void ckc_set_changefbus(struct ckc_ioctl st) ++{ ++ int i, validFlag; ++ // Except : FCORE_CPU, FMEM_BUS, FBUS_IOB ++ // Change Fbus : FBUS_DDI, FBUS_GRP, FBUS_VBUS, FBUS_VCODEC, FBUS_SMU ++ // ++ int_alldisable(); ++ local_flush_tlb_all(); ++ flush_cache_all(); ++ ++ if(st.in_ckc.fbusname != CLKCTRL0 && st.in_ckc.fbusname != CLKCTRL2 ) ++ { ++ //if(st.in_ckc.fbusfreq == 60000 || st.in_ckc.fbusfreq == 0) ++ if( st.in_ckc.fbusfreq == 0) ++ { ++#if defined(CONFIG_TCC_R_AX) ++ st.in_ckc.fbusenable = DISABLE; ++ st.in_ckc.mode = NORMAL_MD; ++ ++ if(st.in_ckc.fbusname == CLKCTRL1) ++ { ++ st.in_ckc.pmuoffname = PMU_DDIBUS; ++ validFlag = 0; ++ } ++ else if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ st.in_ckc.pmuoffname = PMU_VIDEOBUS; ++ validFlag = 1; ++ } ++ else if(st.in_ckc.fbusname == CLKCTRL3) ++ { ++ st.in_ckc.pmuoffname = PMU_GRAPHICBUS; ++ validFlag = 1; ++ } ++ else ++ validFlag = 0; ++ ++ if(validFlag == 1) ++ { ++ if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ tca_ckc_setswreset(CLKCTRL5,ON); ++ tca_ckc_setswreset(CLKCTRL6,ON); ++ ++ ckc_delay(10); ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,st.in_ckc.fbusenable,st.in_ckc.mode,st.in_ckc.fbusfreq,st.in_ckc.fbussource); ++ ++ tca_ckc_setpmupwroff(PMU_VIDEOBUS,DISABLE); ++ } ++ else ++ { ++ tca_ckc_setswreset(st.in_ckc.fbusname,ON); ++ ckc_delay(10); ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,st.in_ckc.fbusenable,st.in_ckc.mode,st.in_ckc.fbusfreq,st.in_ckc.fbussource); ++ tca_ckc_setpmupwroff(st.in_ckc.pmuoffname,DISABLE); ++ } ++ ++ if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ tca_ckc_setswreset(CLKCTRL6,OFF); ++ tca_ckc_setswreset(CLKCTRL5,OFF); ++ } ++ else ++ tca_ckc_setswreset(st.in_ckc.fbusname,OFF); ++ ++ } ++ else ++ { ++ tca_ckc_setswreset(st.in_ckc.fbusname,ON); ++ ckc_delay(10); ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,st.in_ckc.fbusenable,st.in_ckc.mode,st.in_ckc.fbusfreq,st.in_ckc.fbussource); ++ tca_ckc_setswreset(st.in_ckc.fbusname,OFF); ++ } ++ #else ++ //tca_ckc_setswreset(st.in_ckc.fbusname); ++ validFlag = 1; ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,ENABLE,NORMAL_MD,60000,DIRECTXIN); ++ #endif ++ } ++ else ++ { ++#if defined(CONFIG_TCC_R_AX) ++ if(st.in_ckc.fbusname == CLKCTRL1) ++ { ++ st.in_ckc.pmuoffname = PMU_DDIBUS; ++ validFlag = 0; ++ } ++ else if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ st.in_ckc.pmuoffname = PMU_VIDEOBUS; ++ validFlag = 1; ++ } ++ else if(st.in_ckc.fbusname == CLKCTRL3) ++ { ++ st.in_ckc.pmuoffname = PMU_GRAPHICBUS; ++ validFlag = 1; ++ } ++ else ++ validFlag = 0; ++ ++ if(validFlag == 1) ++ { ++ if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ tca_ckc_setswreset(CLKCTRL5,ON); ++ tca_ckc_setswreset(CLKCTRL6,ON); ++ tca_ckc_setpmupwroff(PMU_VIDEOBUS,ENABLE); ++ } ++ else ++ { ++ tca_ckc_setswreset(st.in_ckc.fbusname,ON); ++ tca_ckc_setpmupwroff(st.in_ckc.pmuoffname,ENABLE); ++ } ++ ++ ckc_delay(100); ++ if(st.in_ckc.fbusname == CLKCTRL5) ++ { ++ tca_ckc_setswreset(CLKCTRL6,OFF); ++ tca_ckc_setswreset(CLKCTRL5,OFF); ++ } ++ else ++ tca_ckc_setswreset(st.in_ckc.fbusname,OFF); ++ } ++ #endif ++ { ++ //validFlag = 0; ++ for(i = 0; i < FBUS_STEP_NUM; i++) ++ { ++ if(st.in_ckc.fbusfreq == FbusStepValue[i] || st.in_ckc.fbusfreq == 3300000) ++ { ++ validFlag = 1; ++ break; ++ } ++ } ++ ++ if( validFlag == 1) ++ { ++ if(i <= 12) ++ { ++ if((i%2) == 1) ++ st.in_ckc.fbussource = DIRECTPLL2; ++ else ++ st.in_ckc.fbussource = DIRECTPLL3; ++ } ++ else ++ { ++ if(i >= FBUS_STEP_NUM-3) ++ { ++ st.in_ckc.fbussource = DIRECTXIN; ++ } ++ else if(i == (FBUS_STEP_NUM-4)) ++ { ++ st.in_ckc.fbussource = DIRECTPLL2; ++ } ++ else ++ { ++ if((i%2) == 1) ++ st.in_ckc.fbussource = DIRECTPLL3; ++ else ++ st.in_ckc.fbussource = DIRECTPLL2; ++ } ++ } ++ } ++ } ++ ++ if( validFlag == 1) ++ { ++ st.in_ckc.fbusenable = ENABLE; ++ st.in_ckc.mode = NORMAL_MD; ++ tca_ckc_setfbusctrl(st.in_ckc.fbusname,st.in_ckc.fbusenable,st.in_ckc.mode,st.in_ckc.fbusfreq,st.in_ckc.fbussource); ++ } ++ } ++ int_restore(); ++ } ++} ++ ++void ckc_set_changemem(struct ckc_ioctl st) ++{ ++ volatile PLCDC pLCDC_BASE0 = (volatile PLCDC)tcc_p2v(HwLCDC0_BASE); ++ volatile PLCDC pLCDC_BASE1 = (volatile PLCDC)tcc_p2v(HwLCDC1_BASE); ++ volatile PTIMER pTIMER = (volatile PTIMER)tcc_p2v(HwTMR_BASE); ++ ++ // Off LCD ++ pLCDC_BASE1->LCTRL &= ~Hw0; ++ pLCDC_BASE0->LCTRL &= ~Hw0; ++ ++ int_alldisable(); ++ local_flush_tlb_all(); ++ flush_cache_all(); ++ ++ pTIMER->TC32EN &= ~Hw24; ++ ++ retstack = arm_changestack(); ++ ++ init_copychangeclock(st.in_ckc.busvalue); ++ ++ arm_restorestack(retstack); ++ ++ pTIMER->TC32EN |= Hw24; ++ ++ int_restore(); ++ ++ // LCDC Power Up ++ pLCDC_BASE0->LCTRL |= Hw0; ++ pLCDC_BASE1->LCTRL |= Hw0; ++} ++ ++void ckc_set_changecpu(struct ckc_ioctl st) ++{ ++ int i, validFlag; ++ ++ int_alldisable(); ++ ++ for(i = 0; i < FCORE_STEP_NUM; i++) ++ { ++ if(st.in_ckc.cpuvalue == FcoreStepValue[i]) { ++ validFlag = 1; ++ break; ++ } ++ } ++ ++ if( validFlag == 1) ++ { ++ // Change pll ++ if(tca_ckc_getpll(0) != FcorePllValue[i]) ++ tca_ckc_setpll(FcorePllValue[i],0); ++ ++ tca_ckc_setcpu(FcoreDividerValue[i]); ++ } ++ int_restore(); ++} ++ ++void ckc_set_ddipwdn(struct ckc_ioctl st) ++{ ++ tca_ckc_setddipwdn(st.in_ckc.ddipdname, st.in_ckc.mode); ++} ++ ++void ckc_get_ddipwdn(struct ckc_ioctl st) ++{ ++ st.out_ckc.retVal = tca_ckc_getddipwdn(st.in_ckc.ddipdname); ++} ++ ++void ckc_set_etcblock(struct ckc_ioctl st) ++{ ++ ckc_etcblock(st.in_ckc.etcblock); ++} ++ ++ ++EXPORT_SYMBOL(ckc_set_peri); ++EXPORT_SYMBOL(ckc_get_peri); ++EXPORT_SYMBOL(ckc_set_peribus); ++EXPORT_SYMBOL(ckc_get_peribus); ++EXPORT_SYMBOL(ckc_set_periswreset); ++EXPORT_SYMBOL(ckc_set_fbusswreset); ++EXPORT_SYMBOL(ckc_set_cpu); ++EXPORT_SYMBOL(ckc_set_smui2c); ++EXPORT_SYMBOL(ckc_get_cpu); ++EXPORT_SYMBOL(ckc_get_bus); ++EXPORT_SYMBOL(ckc_get_validpllinfo); ++EXPORT_SYMBOL(ckc_set_fbus); ++EXPORT_SYMBOL(ckc_get_fbus); ++EXPORT_SYMBOL(ckc_set_pmupower); ++EXPORT_SYMBOL(ckc_get_pmupower); ++EXPORT_SYMBOL(ckc_get_clockinfo); ++EXPORT_SYMBOL(ckc_set_changefbus); ++EXPORT_SYMBOL(ckc_set_changemem); ++EXPORT_SYMBOL(ckc_set_changecpu); ++EXPORT_SYMBOL(ckc_set_ddipwdn); ++EXPORT_SYMBOL(ckc_get_ddipwdn); ++EXPORT_SYMBOL(ckc_set_etcblock); +diff --git a/arch/arm/mach-tcc8900/time.c b/arch/arm/mach-tcc8900/time.c +new file mode 100644 +index 0000000..a561b96 +--- /dev/null ++++ b/arch/arm/mach-tcc8900/time.c +@@ -0,0 +1,135 @@ ++/* ++ * linux/arch/arm/mach-tcc8900/time.c ++ * ++ * Author: ++ * Created: 10th Feb, 2009 ++ * Description: TCC8900 Timers ++ * ++ * Copyright (C) Telechips, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++/* ++ * Returns elapsed usecs since last system timer interrupt ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include // for setup_irq() ++#include // for PAGE_ALIGN ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#define TCC_TIMER_FREQ (12 * 1000 * 1000) /* 12M */ ++#define TCC_ENABLE_BIT(X) (1 << (X)) ++ ++#if (TCC_TIMER_FREQ < (1000 * 1000)) ++# define PRESCALE_TO_MICROSEC(X) ((X) * ((1000 * 1000) / (TCC_TIMER_FREQ))) ++#else ++# define PRESCALE_TO_MICROSEC(X) ((X) / ((TCC_TIMER_FREQ) / (1000 * 1000))) ++#endif ++ ++// Global ++static volatile PTIMER pTIMER; ++static volatile PPIC pPIC; ++ ++/* ++ * Returns elapsed usecs since last system timer interrupt ++ */ ++static unsigned long tcc8900_timer_gettimeoffset(void) ++{ ++ return PRESCALE_TO_MICROSEC(pTIMER->TC32PCNT); ++} ++ ++static irqreturn_t tcc8900_timer_interrupt(int irq, void *dev_id) ++{ ++ timer_tick(); ++ ++ BITSET(pPIC->CLR0, TCC_ENABLE_BIT(irq)); ++ if(pTIMER->TC32IRQ & Hw31) ++ BITSET(pTIMER->TC32IRQ, Hw31); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction tcc8900_timer_irq = { ++ .name = "TC1_timer", ++ .flags = IRQF_DISABLED | IRQF_TIMER, ++ .handler = tcc8900_timer_interrupt, ++}; ++ ++/* ++ * Scheduler clock - returns current time in nanosec units. ++ */ ++unsigned long long sched_clock(void) ++{ ++ return ((unsigned long long)jiffies) * (1000000000llu / HZ); ++} ++ ++ ++/* ++ * Timer Initialization ++ */ ++static void __init tcc8900_timer_init(void) ++{ ++ unsigned int cpu_clk; ++ unsigned int bus_clk; ++ ++ init_pwm_list(); ++ tca_ckc_init(); ++ cpu_clk = (unsigned int)tca_ckc_getcpu(); ++ bus_clk = (unsigned int)tca_ckc_getbus(); ++ ++ pTIMER = (volatile PTIMER)tcc_p2v(HwTMR_BASE); ++ pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE); ++ ++ printk(" ### CORE CLOCK (%u Hz), BUS CLOCK (%u Hz) ###\n", cpu_clk * 100, bus_clk * 100); ++ ++ BITCLR(pTIMER->TC32EN, Hw24); ++ pTIMER->TC32EN = TCC_TIMER_FREQ / HZ; ++ pTIMER->TC32LDV = 0; ++ BITSET(pTIMER->TC32IRQ, Hw19); ++ BITSET(pTIMER->TC32EN, Hw24); ++ ++ BITSET(pPIC->SEL0, TCC_ENABLE_BIT(INT_TC1)); ++ BITSET(pPIC->IEN0, TCC_ENABLE_BIT(INT_TC1)); ++ BITSET(pPIC->INTMSK0, TCC_ENABLE_BIT(INT_TC1)); ++ BITSET(pPIC->MODEA0, TCC_ENABLE_BIT(INT_TC1)); ++ //BITCLR(pPIC->CLR0, TCC_ENABLE_BIT(INT_TC1)); ++ ++ setup_irq(INT_TC1, &tcc8900_timer_irq); ++} ++ ++struct sys_timer tcc8900_timer = { ++ .init = tcc8900_timer_init, ++ .offset = tcc8900_timer_gettimeoffset, ++}; +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index ab5f7a2..91cf6fd 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -400,7 +400,8 @@ config CPU_FEROCEON_OLD_ID + # ARMv6 + config CPU_V6 + bool "Support ARM V6 processor" +- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 ++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || MACH_TCC8900 || MACH_TCC9200 ++ default y if ARCH_TCC + default y if ARCH_MX3 + default y if ARCH_MSM + select CPU_32v6 +diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c +index 82c4b42..e93766d 100644 +--- a/arch/arm/mm/init.c ++++ b/arch/arm/mm/init.c +@@ -485,6 +485,9 @@ void __init mem_init(void) + datapages = &_end - &__data_start; + initpages = &__init_end - &__init_begin; + ++ printk("_etext:0x%p, _text:0x%p, _end:0x%p, __data_start:0x%p, __init_end:0x%p, __init_begin:0x%p\n", \ ++ &_etext, &_text, &_end, &__data_start, &__init_end, &__init_begin); ++ + #ifndef CONFIG_DISCONTIGMEM + max_mapnr = virt_to_page(high_memory) - mem_map; + #endif +diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c +index 7f36c82..af2e310 100644 +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -238,6 +238,10 @@ static struct mem_type mem_types[] = { + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, + .domain = DOMAIN_KERNEL, + }, ++ [MT_MEMORY_TCC] = { ++ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED, ++ .domain = DOMAIN_KERNEL, ++ }, + [MT_ROM] = { + .prot_sect = PMD_TYPE_SECT, + .domain = DOMAIN_KERNEL, +@@ -571,6 +575,8 @@ void __init create_mapping(struct map_desc *md) + const struct mem_type *type; + pgd_t *pgd; + ++ printk("create_mapping:0x%lx->0x%lx(0x%lx)\n", __pfn_to_phys(md->pfn), md->virtual, md->length); ++ + if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { + printk(KERN_WARNING "BUG: not creating mapping for " + "0x%08llx at 0x%08lx in user region\n", +diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile +new file mode 100644 +index 0000000..e7242fc +--- /dev/null ++++ b/arch/arm/plat-tcc/Makefile +@@ -0,0 +1,12 @@ ++ ++#obj-$(CONFIG_TCA_CKC) += tca_ckc.o ++ ++#obj-$(CONFIG_TCA_PM) += tcc_pm.o ++#ifeq ($(CONFIG_PM),y) ++#obj-$(CONFIG_TCA_PM) += tcc_asm.o ++#endif ++# ++obj-$(CONFIG_PM) += tcc_pm.o ++obj-$(CONFIG_DPM) += tcc_dpm.o ++obj-$(CONFIG_CPU_FREQ) += tcc_cpufreq.o ++ +diff --git a/arch/arm/plat-tcc/include/plat/dpm.h b/arch/arm/plat-tcc/include/plat/dpm.h +new file mode 100644 +index 0000000..f7afb18 +--- /dev/null ++++ b/arch/arm/plat-tcc/include/plat/dpm.h +@@ -0,0 +1,169 @@ ++/* ++ * include/asm-arm/arch-tcc79x/dpm.h ++ * ++ * Author: ++ * Created: June 10, 2008 ++ * Description: DPM for Telechips ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2002-2004, MontaVista Software ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * Initially based on include/asm-arm/arch-omap/omap_dpm.h ++ */ ++ ++#ifndef __ASM_ARCH_DPM_H__ ++#define __ASM_ARCH_DPM_H__ ++ ++#include ++ ++#include ++#include ++ ++/*! ++ * machine dependent operating state ++ * ++ * An operating state is a cpu execution state that has implications for power ++ * management. The DPM will select operating points based largely on the ++ * current operating state. ++ * ++ * DPM_STATES is the number of supported operating states. Valid operating ++ * states are from 0 to DPM_STATES-1 but when setting an operating state the ++ * kernel should only specify a state from the set of "base states" and should ++ * do so by name. During the context switch the new operating state is simply ++ * extracted from current->dpm_state. ++ * ++ * task states: ++ * ++ * APIs that reference task states use the range -(DPM_TASK_STATE_LIMIT + 1) ++ * through +DPM_TASK_STATE_LIMIT. This value is added to DPM_TASK_STATE to ++ * obtain the downward or upward adjusted task state value. The ++ * -(DPM_TASK_STATE_LIMIT + 1) value is interpreted specially, and equates to ++ * DPM_NO_STATE. ++ * ++ * Tasks inherit their task operating states across calls to ++ * fork(). DPM_TASK_STATE is the default operating state for all tasks, and is ++ * inherited from init. Tasks can change (or have changed) their tasks states ++ * using the DPM_SET_TASK_STATE variant of the sys_dpm() system call. ++ */ ++#define DPM_IDLE_TASK_STATE 0 ++#define DPM_IDLE_STATE 1 ++#define DPM_SLEEP_STATE 2 ++#define DPM_BASE_STATES 3 ++ ++#define DPM_TASK_STATE_LIMIT 4 ++#define DPM_TASK_STATE (DPM_BASE_STATES + DPM_TASK_STATE_LIMIT) /* 7 */ ++#define DPM_STATES (DPM_TASK_STATE + DPM_TASK_STATE_LIMIT + 1) /* 11 */ ++#define DPM_TASK_STATES (DPM_STATES - DPM_BASE_STATES) /* 5 */ ++ ++#define DPM_STATE_NAMES \ ++{ "idle-task", "idle", "sleep", \ ++ "task-4", "task-3", "task-2", "task-1",\ ++ "task", \ ++ "task+1", "task+2", "task+3", "task+4" \ ++} ++ ++ ++#define DPM_PARAM_NAMES \ ++{ "sys_cpu",\ ++ "sys_bus",\ ++ "fbus_grp",\ ++ "fbus_vbus",\ ++ "fbus_vcodec",\ ++ "fbus_smu",\ ++ "fbus_ddi",\ ++ "fbus_iobus",\ ++ "peri_lcd",\ ++ "peri_sata",\ ++ "peri_otg",\ ++ "peri_ohci",\ ++ "peri_userintr",\ ++ "peri_tvout",\ ++ "peri_hdmi",\ ++ "peri_sdhc",\ ++} ++ ++ ++/*! ++ * MD operating point parameters ++ */ ++enum { ++ DPM_MD_CORE_CPU, /* 0 */ ++ DPM_MD_CORE_BUS, /* 1 */ ++ DPM_MD_FBUS_GRP, /* 2 */ ++ DPM_MD_FBUS_VBUS, /* 3 */ ++ DPM_MD_FBUS_VCODEC, /* 4 */ ++ DPM_MD_FBUS_SMU, /* 5 */ ++ DPM_MD_FBUS_DDI, /* 6 */ ++ DPM_MD_FBUS_IOBUS, /* 7 */ ++ DPM_MD_PERI_LCD, /* 8 */ ++ DPM_MD_PERI_SATA, /* 9 */ ++ DPM_MD_PERI_OTG, /* 10 */ ++ DPM_MD_PERI_OHCI, /* 11 */ ++ DPM_MD_PERI_USERINTR, /* 12 */ ++ DPM_MD_PERI_TVOUT, /* 13 */ ++ DPM_MD_PERI_HDMI, /* 14 */ ++ DPM_MD_PERI_SDHC, /* 15 */ ++ DPM_MD_MAX, ++}; ++ ++#define DPM_PP_NBR DPM_MD_MAX ++ ++ ++#ifndef __ASSEMBLER__ ++ ++#include ++#include ++ ++#define DPM_MD_STATS ++typedef __u64 dpm_md_count_t; ++typedef __u64 dpm_md_time_t; ++ ++ ++#define dpm_time() get_cycles() ++#define dpm_time_to_usec(ticks) ({ \ ++ unsigned long long quot = (unsigned long long) ticks * 10; \ ++ do_div(quot, (unsigned long) (1000*2)); \ ++ quot; }) ++ ++ ++/*! ++ * Instances of this structure define valid Innovator operating points for DPM. ++ * Voltages are represented in mV, and frequencies are represented in KHz. ++ */ ++/* TODO */ ++/* Operating Points */ ++struct dpm_md_opt { ++ unsigned int sys_cpu; /* 0 */ ++ unsigned int sys_bus; /* 1 */ ++ unsigned int fbus_grp; /* 2 */ ++ unsigned int fbus_vbus; /* 3 */ ++ unsigned int fbus_vcodec; /* 4 */ ++ unsigned int fbus_smu; /* 5 */ ++ unsigned int fbus_ddi; /* 6 */ ++ unsigned int fbus_iobus; /* 7 */ ++ unsigned int peri_lcd; /* 8 */ ++ unsigned int peri_sata; /* 9 */ ++ unsigned int peri_otg; /* 10 */ ++ unsigned int peri_ohci; /* 11 */ ++ unsigned int peri_userintr; /* 12 */ ++ unsigned int peri_tvout; /* 13 */ ++ unsigned int peri_hdmi; /* 14 */ ++ unsigned int peri_sdhc; /* 15 */ ++}; ++ ++#endif /* __ASSEMBLER__ */ ++#endif /* __ASM_ARCH_DPM_H__ */ +diff --git a/arch/arm/plat-tcc/include/plat/pm.h b/arch/arm/plat-tcc/include/plat/pm.h +new file mode 100644 +index 0000000..2a98f50 +--- /dev/null ++++ b/arch/arm/plat-tcc/include/plat/pm.h +@@ -0,0 +1,34 @@ ++/**************************************************************** ++ * $ID: pm.h å…­, 29 8月 2009 16:53:28 +0800 root $ * ++ * * ++ * Description: * ++ * * ++ * Maintainer: ·¶Ã;Ô(Meihui Fan) * ++ * * ++ * CopyRight (c) 2009 HHTech * ++ * www.hhcn.com, www.hhcn.org * ++ * All rights reserved. * ++ * * ++ * This file is free software; * ++ * you are free to modify and/or redistribute it * ++ * under the terms of the GNU General Public Licence (GPL). * ++ * * ++ * Last modified: å…­, 29 8月 2009 16:54:15 +0800 by root # ++ ****************************************************************/ ++#ifndef PM_H ++#define PM_H ++ ++#ifdef CONFIG_PM ++ ++extern __init int tcc8902_pm_init(void); ++ ++#else ++ ++static inline int tcc8902_pm_init(void) ++{ ++ return 0; ++} ++#endif ++ ++#endif//PM_H ++/********************** End Of File: pm.h **********************/ +diff --git a/arch/arm/plat-tcc/tcc_cpufreq.c b/arch/arm/plat-tcc/tcc_cpufreq.c +new file mode 100644 +index 0000000..ca5ca78 +--- /dev/null ++++ b/arch/arm/plat-tcc/tcc_cpufreq.c +@@ -0,0 +1,125 @@ ++/**************************************************************** ++ * $ID: tcc_cpufreq.c å››, 27 8月 2009 11:39:10 +0800 root $ * ++ * * ++ * Description: CPU frequency scaling for TCC8902 * ++ * * ++ * Maintainer: (Guoqiang Wang) * ++ * * ++ * CopyRight (c) 2009 HHTech * ++ * www.hhcn.com, www.hhcn.org * ++ * All rights reserved. * ++ * * ++ * This file is free software; * ++ * you are free to modify and/or redistribute it * ++ * under the terms of the GNU General Public Licence (GPL). * ++ * * ++ * Last modified: 一, 26 10月 2009 12:08:06 +0800 by root # ++ ****************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define KHZ_T 1000 ++ ++extern unsigned int tca_ckc_getcpu(void); ++extern int tcc_ckc_change_cpu(unsigned int cpuvalue); ++static struct cpufreq_frequency_table tcc8902_freq_table[] = { ++ {0, 540000}, ++ {1, 506250}, ++ {2, 405000}, ++ {3, 324000}, ++ {4, 216000}, ++ {5, 108000}, ++ {6, 54000}, ++ {0, CPUFREQ_TABLE_END}, ++}; ++ ++int tcc8902_verify_speed(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ return cpufreq_frequency_table_verify(policy, tcc8902_freq_table); ++} ++ ++unsigned int tcc8902_getspeed(unsigned int cpu) ++{ ++ unsigned long rate; ++ ++ if (cpu) ++ return 0; ++ ++ //rate = clk_get_rate(mpu_clk) / KHZ_T; ++ printk("!!!tcc8902_getspeed\n"); ++ rate = tca_ckc_getcpu() / 10; ++ ++ return rate; ++} ++ ++static int tcc8902_target(struct cpufreq_policy *policy, ++ unsigned int target_freq, ++ unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret = 0; ++ unsigned long arm_clk; ++ unsigned int index; ++ ++ freqs.old = tca_ckc_getcpu() / 10; ++ if (cpufreq_frequency_table_target(policy, tcc8902_freq_table, target_freq, relation, &index)) ++ return -EINVAL; ++ ++ arm_clk = tcc8902_freq_table[index].frequency; ++ freqs.new = arm_clk; ++ freqs.cpu = 0; ++ ++ if(freqs.new == freqs.old) ++ return 0; ++ ++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ++ ret = tcc_ckc_change_cpu(freqs.new * 10); ++ //ret = clk_set_rate(mpu_clk, freqs.new * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ ++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); ++ return ret; ++} ++ ++static int __init tcc8902_cpu_init(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ policy->cur = tca_ckc_getcpu() / 10; ++ cpufreq_frequency_table_get_attr(tcc8902_freq_table, policy->cpu); ++ policy->cpuinfo.transition_latency = KHZ_T; //1us ++ ++ return cpufreq_frequency_table_cpuinfo(policy, tcc8902_freq_table); ++} ++ ++static struct cpufreq_driver tcc8902_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = tcc8902_verify_speed, ++ .target = tcc8902_target, ++ .get = tcc8902_getspeed, ++ .init = tcc8902_cpu_init, ++ .name = "tcc8902", ++ .owner = THIS_MODULE, ++}; ++ ++static int __init tcc8902_cpufreq_init(void) ++{ ++ return cpufreq_register_driver(&tcc8902_driver); ++} ++ ++late_initcall(tcc8902_cpufreq_init); ++ ++/****************** End Of File: tcc_cpufreq.c ******************/ +diff --git a/arch/arm/plat-tcc/tcc_dpm.c b/arch/arm/plat-tcc/tcc_dpm.c +new file mode 100644 +index 0000000..2609ced +--- /dev/null ++++ b/arch/arm/plat-tcc/tcc_dpm.c +@@ -0,0 +1,896 @@ ++/* ++ * arch/arm/plat-tcc/tcc_dpm.c DPM support for Telecips Chips ++ * ++ * Author: ++ * Created: 10th Jun, 2008 ++ * Description: tcc clock control functions. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2002, 2004 MontaVista Software . ++ * Copyright (C) 2008-2009 Telechips ++ * ++ * Based on code by Matthew Locke, Dmitry Chigirev, and Bishop Brock. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define dbg printk ++#define DEBUG ++#else /* no debug */ ++#define dbg(x...) do {} while(0) ++#endif ++ ++static int cur_lcd; ++static int cur_sata; ++static int cur_otg; ++static int cur_ohci; ++static int cur_userintr; ++static int cur_tvout; ++static int cur_hdmi; ++static int cur_sdhc; ++ ++static void ++set_cpu_clock(unsigned int sys_cpu) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int cpu = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.cpuvalue = sys_cpu ; ++ ++ ckc_set_changecpu(st); ++ ++#ifdef DEBUG ++ cpu = ckc_get_cpu(st); ++ dbg("[%s] cpu = %d\n", __func__, cpu); ++#endif ++} ++ ++static int ++get_cpu_clock(void) ++{ ++#ifdef DEBUG ++ int cpu = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++#ifdef DEBUG ++ cpu = ckc_get_cpu(st); ++ dbg("[%s] cpu = %d \n", __func__, cpu); ++ return cpu; ++#else ++ return ckc_get_cpu(st); ++#endif ++ return 0; ++} ++ ++static void ++set_bus_clock(unsigned int sys_bus) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int bus = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.busvalue = sys_bus ; ++ ++ ckc_set_changemem(st); ++#ifdef DEBUG ++ bus = ckc_get_bus(st); ++ dbg("[%s] bus = %d\n", __func__, bus); ++#endif ++} ++ ++ ++static int ++get_bus_clock(void) ++{ ++#ifdef DEBUG ++ int bus = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++#ifdef DEBUG ++ bus = ckc_get_bus(st); ++ dbg("[%s] bus = %d \n", __func__, bus); ++ return bus; ++#else ++ return ckc_get_bus(st); ++#endif ++ return 0; ++} ++ ++static void ++set_grp_clock(unsigned int fbus_grp) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int grp = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL3; ++ st.in_ckc.fbusfreq = fbus_grp; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ grp = ckc_get_fbus(st); ++ dbg("[%s] grp = %d\n", __func__, grp); ++#endif ++} ++ ++ ++static int ++get_grp_clock(void) ++{ ++#ifdef DEBUG ++ int grp = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL3; ++#ifdef DEBUG ++ grp = ckc_get_fbus(st); ++ dbg("[%s] grp = %d \n", __func__, grp); ++ return grp; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++static void ++set_vbus_clock(unsigned int fbus_vbus) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int vbus = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL5; ++ st.in_ckc.fbusfreq = fbus_vbus; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ vbus = ckc_get_fbus(st); ++ dbg("[%s] vbus = %d\n", __func__, vbus); ++#endif ++} ++ ++ ++static int ++get_vbus_clock(void) ++{ ++#ifdef DEBUG ++ int vbus = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL5; ++#ifdef DEBUG ++ vbus = ckc_get_fbus(st); ++ dbg("[%s] vbus = %d \n", __func__, vbus); ++ return vbus; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++static void ++set_vcodec_clock(unsigned int fbus_vcodec) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int vcodec = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL6; ++ st.in_ckc.fbusfreq = fbus_vcodec; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ vcodec = ckc_get_fbus(st); ++ dbg("[%s] vcodec = %d\n", __func__, vcodec); ++#endif ++} ++ ++ ++static int ++get_vcodec_clock(void) ++{ ++#ifdef DEBUG ++ int vcodec = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL6; ++#ifdef DEBUG ++ vcodec = ckc_get_fbus(st); ++ dbg("[%s] vcodec = %d \n", __func__, vcodec); ++ return vcodec; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++ ++static void ++set_smu_clock(unsigned int fbus_smu) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int smu = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL1; ++ st.in_ckc.fbusfreq = fbus_smu; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ smu = ckc_get_fbus(st); ++ dbg("[%s] smu = %d\n", __func__, smu); ++#endif ++} ++ ++ ++static int ++get_smu_clock(void) ++{ ++#ifdef DEBUG ++ int smu = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL1; ++#ifdef DEBUG ++ smu = ckc_get_fbus(st); ++ dbg("[%s] smu = %d \n", __func__, smu); ++ return smu; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++ ++static void ++set_ddi_clock(unsigned int fbus_ddi) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int ddi = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL7; ++ st.in_ckc.fbusfreq = fbus_ddi; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ ddi = ckc_get_fbus(st); ++ dbg("[%s] ddi = %d\n", __func__, ddi); ++#endif ++} ++ ++ ++static int ++get_ddi_clock(void) ++{ ++#ifdef DEBUG ++ int ddi = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL7; ++#ifdef DEBUG ++ ddi = ckc_get_fbus(st); ++ dbg("[%s] ddi = %d \n", __func__, ddi); ++ return ddi; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++ ++static void ++set_iobus_clock(unsigned int fbus_iobus) ++{ ++ struct ckc_ioctl st; ++#ifdef DEBUG ++ int iobus = 0; ++#endif ++ ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL4; ++ st.in_ckc.fbusfreq = fbus_iobus; ++ ++ ckc_set_changefbus(st); ++#ifdef DEBUG ++ iobus = ckc_get_fbus(st); ++ dbg("[%s] iobus = %d\n", __func__, iobus); ++#endif ++} ++ ++ ++static int ++get_iobus_clock(void) ++{ ++#ifdef DEBUG ++ int iobus = 0; ++#endif ++ struct ckc_ioctl st; ++ memset(&st, 0, sizeof(struct ckc_ioctl)); ++ st.in_ckc.fbusname = CLKCTRL4; ++#ifdef DEBUG ++ iobus = ckc_get_fbus(st); ++ dbg("[%s] iobus = %d \n", __func__, iobus); ++ return iobus; ++#else ++ return ckc_get_fbus(st); ++#endif ++ return 0; ++} ++ ++ ++static void ++set_lcd_clock(unsigned int peri_lcd) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_lcd == ENABLE) { ++ dbg("[%s] LCD ON\n",__func__); ++ callback_pwm_node(DEVICE_LCD , PWR_CMD_ON, &(out)); ++ } else if(peri_lcd == DISABLE){ ++ dbg("[%s] LCD OFF\n", __func__); ++ callback_pwm_node(DEVICE_LCD , PWR_CMD_OFF, &(out)); ++ } ++ cur_lcd = peri_lcd; ++} ++ ++static int ++get_lcd_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_lcd == ENABLE) ++ dbg("[%s] LCD ON\n", __func__); ++ else if(cur_lcd == DISABLE) ++ dbg("[%s] LCD OFF\n", __func__); ++#endif ++ return cur_lcd; ++} ++ ++static void ++set_sata_clock(unsigned int peri_sata) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_sata== ENABLE) { ++ dbg("[%s] SATA ON\n", __func__); ++ callback_pwm_node(DEVICE_SATA, PWR_CMD_ON, &(out)); ++ } else if(peri_sata== DISABLE){ ++ dbg("[%s] SATA OFF\n", __func__); ++ callback_pwm_node(DEVICE_SATA, PWR_CMD_OFF, &(out)); ++ } ++ cur_sata = peri_sata; ++} ++ ++static int ++get_sata_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_sata == ENABLE) ++ dbg("[%s] SATA ON\n", __func__); ++ else if(cur_sata == DISABLE) ++ dbg("[%s] SATA OFF\n", __func__); ++#endif ++ return cur_sata; ++} ++ ++ ++ ++static void ++set_otg_clock(unsigned int peri_otg) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_otg== ENABLE) { ++ dbg("[%s] OTG ON\n", __func__); ++ callback_pwm_node(DEVICE_OTG, PWR_CMD_ON, &(out)); ++ } else if(peri_otg== DISABLE){ ++ dbg("[%s] OTG OFF\n", __func__); ++ callback_pwm_node(DEVICE_OTG, PWR_CMD_OFF, &(out)); ++ } ++ cur_otg = peri_otg; ++} ++ ++static int ++get_otg_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_otg == ENABLE) ++ dbg("[%s] OTG ON\n", __func__); ++ else if(cur_otg == DISABLE) ++ dbg("[%s] OTG OFF\n", __func__); ++#endif ++ return cur_otg; ++} ++ ++ ++static void ++set_ohci_clock(unsigned int peri_ohci) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_ohci== ENABLE) { ++ dbg("[%s] OHCI ON\n", __func__); ++ callback_pwm_node(DEVICE_OHCI, PWR_CMD_ON, &(out)); ++ } else if(peri_ohci== DISABLE){ ++ dbg("[%s] OHCI OFF\n", __func__); ++ callback_pwm_node(DEVICE_OHCI, PWR_CMD_OFF, &(out)); ++ } ++ cur_ohci = peri_ohci; ++} ++ ++static int ++get_ohci_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_ohci == ENABLE) ++ dbg("[%s] OHCI ON\n", __func__); ++ else if(cur_ohci == DISABLE) ++ dbg("[%s] OHCI OFF\n", __func__); ++#endif ++ return cur_ohci; ++} ++ ++ ++static void ++set_userintr_clock(unsigned int peri_userintr) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_userintr== ENABLE) { ++ dbg("[%s] USERINTR ON\n", __func__); ++ callback_pwm_node(DEVICE_USERINTR, PWR_CMD_ON, &(out)); ++ } else if(peri_userintr== DISABLE){ ++ dbg("[%s] USERINTR OFF\n", __func__); ++ callback_pwm_node(DEVICE_USERINTR, PWR_CMD_OFF, &(out)); ++ } ++ cur_userintr = peri_userintr; ++} ++ ++static int ++get_userintr_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_userintr == ENABLE) ++ dbg("[%s] USERINTR ON\n", __func__); ++ else if(cur_userintr == DISABLE) ++ dbg("[%s] USERINTR OFF\n", __func__); ++#endif ++ return cur_userintr; ++} ++ ++ ++static void ++set_tvout_clock(unsigned int peri_tvout) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_tvout == ENABLE) { ++ dbg("[%s] TVOUT ON\n",__func__); ++ callback_pwm_node(DEVICE_TVOUT , PWR_CMD_ON, &(out)); ++ } else if(peri_tvout == DISABLE){ ++ dbg("[%s] TVOUT OFF\n", __func__); ++ callback_pwm_node(DEVICE_TVOUT , PWR_CMD_OFF, &(out)); ++ } ++ cur_tvout = peri_tvout; ++} ++ ++static int ++get_tvout_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_tvout == ENABLE) ++ dbg("[%s] TVOUT ON\n", __func__); ++ else if(cur_tvout == DISABLE) ++ dbg("[%s] TVOUT OFF\n", __func__); ++#endif ++ return cur_tvout; ++} ++ ++static void ++set_hdmi_clock(unsigned int peri_hdmi) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_hdmi == ENABLE) { ++ dbg("[%s] HDMI ON\n",__func__); ++ callback_pwm_node(DEVICE_HDMI , PWR_CMD_ON, &(out)); ++ } else if(peri_hdmi == DISABLE){ ++ dbg("[%s] HDMI OFF\n", __func__); ++ callback_pwm_node(DEVICE_HDMI , PWR_CMD_OFF, &(out)); ++ } ++ cur_hdmi = peri_hdmi; ++} ++ ++static int ++get_hdmi_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_hdmi == ENABLE) ++ dbg("[%s] HDMI ON\n", __func__); ++ else if(cur_hdmi == DISABLE) ++ dbg("[%s] HDMI OFF\n", __func__); ++#endif ++ return cur_hdmi; ++} ++ ++ ++static void ++set_sdhc_clock(unsigned int peri_sdhc) ++{ ++ stpwrinfo out; ++ ++ memset(&out, 0, sizeof(stpwrinfo)); ++ if(peri_sdhc == ENABLE) { ++ dbg("[%s] SDHC ON\n",__func__); ++ callback_pwm_node(DEVICE_SDHC , PWR_CMD_ON, &(out)); ++ } else if(peri_sdhc == DISABLE){ ++ dbg("[%s] SDHC OFF\n", __func__); ++ callback_pwm_node(DEVICE_SDHC , PWR_CMD_OFF, &(out)); ++ } ++ cur_sdhc = peri_sdhc; ++} ++ ++static int ++get_sdhc_clock(void) ++{ ++#ifdef DEBUG ++ if(cur_sdhc == ENABLE) ++ dbg("[%s] SDHC ON\n", __func__); ++ else if(cur_sdhc == DISABLE) ++ dbg("[%s] SDHC OFF\n", __func__); ++#endif ++ return cur_sdhc; ++} ++ ++ ++ ++int ++dpm_tcc_init_opt(struct dpm_opt *opt) ++{ ++ int sys_cpu = opt->pp[DPM_MD_CORE_CPU]; ++ int sys_bus = opt->pp[DPM_MD_CORE_BUS]; ++ int fbus_grp = opt->pp[DPM_MD_FBUS_GRP]; ++ int fbus_vbus = opt->pp[DPM_MD_FBUS_VBUS]; ++ int fbus_vcodec = opt->pp[DPM_MD_FBUS_VCODEC]; ++ int fbus_smu = opt->pp[DPM_MD_FBUS_SMU]; ++ int fbus_ddi = opt->pp[DPM_MD_FBUS_DDI]; ++ int fbus_iobus = opt->pp[DPM_MD_FBUS_IOBUS]; ++ int peri_lcd = opt->pp[DPM_MD_PERI_LCD]; ++ int peri_sata = opt->pp[DPM_MD_PERI_SATA]; ++ int peri_otg = opt->pp[DPM_MD_PERI_OTG]; ++ int peri_ohci = opt->pp[DPM_MD_PERI_OHCI]; ++ int peri_userintr = opt->pp[DPM_MD_PERI_USERINTR]; ++ int peri_tvout = opt->pp[DPM_MD_PERI_TVOUT]; ++ int peri_hdmi = opt->pp[DPM_MD_PERI_HDMI]; ++ int peri_sdhc = opt->pp[DPM_MD_PERI_SDHC]; ++ ++ struct dpm_md_opt *md_opt = &opt->md_opt; ++ ++ md_opt->sys_cpu = sys_cpu; ++ md_opt->sys_bus = sys_bus; ++ md_opt->fbus_grp = fbus_grp; ++ md_opt->fbus_vbus = fbus_vbus; ++ md_opt->fbus_vcodec = fbus_vcodec; ++ md_opt->fbus_smu = fbus_smu; ++ md_opt->fbus_ddi = fbus_ddi; ++ md_opt->fbus_iobus = fbus_iobus; ++ md_opt->peri_lcd = peri_lcd; ++ md_opt->peri_sata = peri_sata; ++ md_opt->peri_otg = peri_otg; ++ md_opt->peri_ohci = peri_ohci; ++ md_opt->peri_userintr = peri_userintr; ++ md_opt->peri_tvout = peri_tvout; ++ md_opt->peri_hdmi = peri_hdmi; ++ md_opt->peri_sdhc = peri_sdhc; ++ ++ return 0; ++} ++ ++int ++dpm_tcc_set_opt(struct dpm_opt *cur, struct dpm_opt *new) ++{ ++ struct dpm_md_opt *md_cur, *md_new; ++ md_cur = &cur->md_opt; ++ md_new = &new->md_opt; ++ ++ // system core cpu clock ++ dbg("[%d]: md_cur->sys_cpu = %d",__LINE__, md_cur->sys_cpu); ++ dbg("[%d]: md_new->sys_cpu = %d\n",__LINE__, md_new->sys_cpu); ++ if(md_cur->sys_cpu != md_new->sys_cpu) ++ { ++ set_cpu_clock(md_new->sys_cpu); ++ } ++ ++ // system bus clock ++ dbg("[%d]: md_cur->sys_bus = %d",__LINE__, md_cur->sys_bus); ++ dbg("[%d]: md_new->sys_bus = %d\n",__LINE__, md_new->sys_bus); ++ if(md_cur->sys_bus != md_new->sys_bus) ++ { ++ set_bus_clock(md_new->sys_bus); ++ } ++ ++ // system fbus grp clock ++ dbg("[%d]: md_cur->fbus_grp = %d",__LINE__, md_cur->fbus_grp); ++ dbg("[%d]: md_new->fbus_grp = %d\n",__LINE__, md_new->fbus_grp); ++ if(md_cur->fbus_grp != md_new->fbus_grp) ++ { ++ set_grp_clock(md_new->fbus_grp); ++ } ++ ++ // system fbus vbus clock ++ dbg("[%d]: md_cur->fbus_vbus = %d",__LINE__, md_cur->fbus_vbus); ++ dbg("[%d]: md_new->fbus_vbus = %d\n",__LINE__, md_new->fbus_vbus); ++ if(md_cur->fbus_vbus != md_new->fbus_vbus) ++ { ++ set_vbus_clock(md_new->fbus_vbus); ++ } ++ ++ // system fbus vcodec clock ++ dbg("[%d]: md_cur->fbus_vcodec = %d",__LINE__, md_cur->fbus_vcodec); ++ dbg("[%d]: md_new->fbus_vcodec = %d\n",__LINE__, md_new->fbus_vcodec); ++ if(md_cur->fbus_vcodec != md_new->fbus_vcodec) ++ { ++ set_vcodec_clock(md_new->fbus_vcodec); ++ } ++ ++ // system fbus smu clock ++ dbg("[%d]: md_cur->fbus_smu = %d",__LINE__, md_cur->fbus_smu); ++ dbg("[%d]: md_new->fbus_smu = %d\n",__LINE__, md_new->fbus_smu); ++ if(md_cur->fbus_smu != md_new->fbus_smu) ++ { ++ set_smu_clock(md_new->fbus_smu); ++ } ++ ++ ++ // system fbus ddi clock ++ dbg("[%d]: md_cur->fbus_ddi = %d",__LINE__, md_cur->fbus_ddi); ++ dbg("[%d]: md_new->fbus_ddi = %d\n",__LINE__, md_new->fbus_ddi); ++ if(md_cur->fbus_ddi != md_new->fbus_ddi) ++ { ++ set_ddi_clock(md_new->fbus_ddi); ++ } ++ ++ // system fbus iobus clock ++ dbg("[%d]: md_cur->fbus_iobus = %d",__LINE__, md_cur->fbus_iobus); ++ dbg("[%d]: md_new->fbus_iobus = %d\n",__LINE__, md_new->fbus_iobus); ++ if(md_cur->fbus_iobus != md_new->fbus_iobus) ++ { ++ set_iobus_clock(md_new->fbus_iobus); ++ } ++ ++ ++ // peri lcd clock ++ dbg("[%d]: md_cur->peri_lcd = %d",__LINE__, md_cur->peri_lcd); ++ dbg("[%d]: md_new->peri_lcd = %d\n",__LINE__, md_new->peri_lcd); ++ if(md_cur->peri_lcd != md_new->peri_lcd) ++ { ++ set_lcd_clock(md_new->peri_lcd); ++ } ++ ++ // peri sata clock ++ dbg("[%d]: md_cur->peri_sata = %d",__LINE__, md_cur->peri_sata); ++ dbg("[%d]: md_new->peri_sata = %d\n",__LINE__, md_new->peri_sata); ++ if(md_cur->peri_sata != md_new->peri_sata) ++ { ++ set_sata_clock(md_new->peri_sata); ++ } ++ ++ // peri otg clock ++ dbg("[%d]: md_cur->peri_otg = %d",__LINE__, md_cur->peri_otg); ++ dbg("[%d]: md_new->peri_otg = %d\n",__LINE__, md_new->peri_otg); ++ if(md_cur->peri_otg != md_new->peri_otg) ++ { ++ set_otg_clock(md_new->peri_otg); ++ } ++ ++ // peri ohci clock ++ dbg("[%d]: md_cur->peri_ohci = %d",__LINE__, md_cur->peri_ohci); ++ dbg("[%d]: md_new->peri_ohci = %d\n",__LINE__, md_new->peri_ohci); ++ if(md_cur->peri_ohci != md_new->peri_ohci) ++ { ++ set_ohci_clock(md_new->peri_ohci); ++ } ++ ++ // peri userintr clock ++ dbg("[%d]: md_cur->peri_userintr = %d",__LINE__, md_cur->peri_userintr); ++ dbg("[%d]: md_new->peri_userintr = %d\n",__LINE__, md_new->peri_userintr); ++ if(md_cur->peri_userintr != md_new->peri_userintr) ++ { ++ set_userintr_clock(md_new->peri_userintr); ++ } ++ ++ // peri tvout clock ++ dbg("[%d]: md_cur->peri_tvout = %d",__LINE__, md_cur->peri_tvout); ++ dbg("[%d]: md_new->peri_tvout = %d\n",__LINE__, md_new->peri_tvout); ++ if(md_cur->peri_tvout != md_new->peri_tvout) ++ { ++ set_tvout_clock(md_new->peri_tvout); ++ } ++ ++ ++ // peri hdmi clock ++ dbg("[%d]: md_cur->peri_hdmi = %d",__LINE__, md_cur->peri_hdmi); ++ dbg("[%d]: md_new->peri_hdmi = %d\n",__LINE__, md_new->peri_hdmi); ++ if(md_cur->peri_hdmi != md_new->peri_hdmi) ++ { ++ set_hdmi_clock(md_new->peri_hdmi); ++ } ++ ++ ++ // peri sdhc clock ++ dbg("[%d]: md_cur->peri_sdhc = %d",__LINE__, md_cur->peri_sdhc); ++ dbg("[%d]: md_new->peri_sdhc = %d\n",__LINE__, md_new->peri_sdhc); ++ if(md_cur->peri_sdhc != md_new->peri_sdhc) ++ { ++ set_sdhc_clock(md_new->peri_sdhc); ++ } ++ ++ ++ return 0; ++} ++ ++/* Fully determine the current machine-dependent operating point, and fill in a ++ structure presented by the caller. This should only be called when the ++ dpm_sem is held. This call can return an error if the system is currently at ++ an operating point that could not be constructed by dpm_md_init_opt(). */ ++ ++int ++dpm_tcc_get_opt(struct dpm_opt *opt) ++{ ++ struct dpm_md_opt *md_opt = &opt->md_opt; ++ ++ md_opt->sys_cpu = get_cpu_clock(); ++ md_opt->sys_bus = get_bus_clock(); ++ md_opt->fbus_grp = get_grp_clock(); ++ md_opt->fbus_vbus = get_vbus_clock(); ++ md_opt->fbus_vcodec = get_vcodec_clock(); ++ md_opt->fbus_smu = get_smu_clock(); ++ md_opt->fbus_ddi = get_ddi_clock(); ++ md_opt->fbus_iobus = get_iobus_clock(); ++ md_opt->peri_lcd = get_lcd_clock(); ++ md_opt->peri_sata= get_sata_clock(); ++ md_opt->peri_otg= get_otg_clock(); ++ md_opt->peri_ohci= get_ohci_clock(); ++ md_opt->peri_userintr= get_userintr_clock(); ++ md_opt->peri_tvout = get_tvout_clock(); ++ md_opt->peri_hdmi = get_hdmi_clock(); ++ md_opt->peri_sdhc = get_sdhc_clock(); ++ ++ return 0; ++} ++ ++ ++/**************************************************************************** ++ * DPM Idle Handler ++ ****************************************************************************/ ++ ++static void (*orig_idle)(void); ++ ++void dpm_tcc_idle(void) ++{ ++ extern void default_idle(void); ++ ++ if (orig_idle) ++ orig_idle(); ++ else { ++ local_irq_disable(); ++ if (!need_resched()) { ++ timer_dyn_reprogram(); ++ arch_idle(); ++ } ++ local_irq_enable(); ++ } ++} ++ ++/**************************************************************************** ++ * Initialization/Exit ++ ****************************************************************************/ ++ ++extern void (*pm_idle)(void); ++ ++static void ++dpm_tcc_startup(void) ++{ ++ dbg("(%s)%s:%d\n", __FILE__, __func__, __LINE__); ++ /* ++ if (pm_idle != dpm_idle) { ++ orig_idle = pm_idle; ++ pm_idle = dpm_idle; ++ } ++ */ ++ dbg("(%s)%s:%d\n", __FILE__, __func__, __LINE__); ++} ++ ++static void ++dpm_tcc_cleanup(void) ++{ ++ dbg("%s:%d\n", __func__, __LINE__); ++ pm_idle = orig_idle; ++} ++ ++int __init ++dpm_tcc_init(void) ++{ ++ printk("Telechips Dynamic Power Management.\n"); ++ dpm_md.init_opt = dpm_tcc_init_opt; ++ dpm_md.set_opt = dpm_tcc_set_opt; ++ dpm_md.get_opt = dpm_tcc_get_opt; ++ dpm_md.check_constraint = dpm_default_check_constraint; ++ dpm_md.idle = dpm_tcc_idle; ++ dpm_md.startup = dpm_tcc_startup; ++ dpm_md.cleanup = dpm_tcc_cleanup; ++ ++ return 0; ++} ++ ++__initcall(dpm_tcc_init); ++ +diff --git a/arch/arm/plat-tcc/tcc_pm.c b/arch/arm/plat-tcc/tcc_pm.c +new file mode 100644 +index 0000000..2a242f3 +--- /dev/null ++++ b/arch/arm/plat-tcc/tcc_pm.c +@@ -0,0 +1,96 @@ ++/**************************************************************** ++ * $ID: tcc_pm.c å…­, 29 8月 2009 16:38:08 +0800 root $ * ++ * * ++ * Description: TCC8902 Power Manager (Suspend-To-RAM) support * ++ * * ++ * Maintainer: Guoqiang Wang * ++ * * ++ * CopyRight (c) 2009 HHTech * ++ * www.hhcn.com, www.hhcn.org * ++ * All rights reserved. * ++ * * ++ * This file is free software; * ++ * you are free to modify and/or redistribute it * ++ * under the terms of the GNU General Public Licence (GPL). * ++ * * ++ * Last modified: 一, 07 12月 2009 16:05:41 +0800 by duanius # ++ ****************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern void selfrefresh_test(void); ++ ++/* tcc8902_pm_enter ++ * ++ * central control for sleep/resume process ++*/ ++extern void enter_sleep_mode(void); ++static int tcc8902_pm_enter(suspend_state_t state) ++{ ++ unsigned long regs_save[16]; ++ unsigned int tmp; ++ ++ /* ensure the debug is initialised (if enabled) */ ++ if (state != PM_SUSPEND_MEM) { ++ printk(KERN_ERR "error: only PM_SUSPEND_MEM supported\n"); ++ return -EINVAL; ++ } ++ ++ printk("selfrefresh_test\n"); ++ enter_sleep_mode(); ++ ++ return 0; ++} ++ ++/* ++ * Called after processes are frozen, but before we shut down devices. ++ */ ++static int tcc8902_pm_prepare(suspend_state_t state) ++{ ++ return 0; ++} ++ ++/* ++ * Called after devices are re-setup, but before processes are thawed. ++ */ ++static int tcc8902_pm_finish(suspend_state_t state) ++{ ++ return 0; ++} ++ ++static struct platform_suspend_ops tcc8902_pm_ops = { ++ .prepare = tcc8902_pm_prepare, ++ .enter = tcc8902_pm_enter, ++ .finish = tcc8902_pm_finish, ++ .valid = suspend_valid_only_mem, ++}; ++ ++/* tcc8902_pm_init ++ * ++ * Attach the power management functions. This should be called ++ * from the board specific initialisation if the board supports ++ * it. ++*/ ++ ++int __init tcc8902_pm_init(void) ++{ ++ printk("TCC8902 Power Management, (c) 2009 HHCN \n"); ++ ++ suspend_set_ops(&tcc8902_pm_ops); ++ return 0; ++} ++/******************** End Of File: tcc_pm.c ********************/ +diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types +index 43aa202..df01e83 100644 +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1899,3 +1899,7 @@ rut100 MACH_RUT100 RUT100 1908 + asusp535 MACH_ASUSP535 ASUSP535 1909 + htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 + sygdg1 MACH_SYGDG1 SYGDG1 1911 ++ ++tcc8900 MACH_TCC8900 TCC8900 4000 ++tcc9100 MACH_TCC9100 TCC9100 4001 ++tcc9200 MACH_TCC9200 TCC9200 4002 +diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h +index c85860b..8de86e4 100644 +--- a/arch/arm/vfp/vfp.h ++++ b/arch/arm/vfp/vfp.h +@@ -377,6 +377,6 @@ struct op { + u32 flags; + }; + +-#ifdef CONFIG_SMP ++#if defined(CONFIG_SMP) || defined(CONFIG_PM) + extern void vfp_save_state(void *location, u32 fpexc); + #endif +diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S +index a62dcf7..c92a08b 100644 +--- a/arch/arm/vfp/vfphw.S ++++ b/arch/arm/vfp/vfphw.S +@@ -101,9 +101,12 @@ ENTRY(vfp_support_entry) + VFPFSTMIA r4, r5 @ save the working registers + VFPFMRX r5, FPSCR @ current status + tst r1, #FPEXC_EX @ is there additional state to save? +- VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set) +- tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? +- VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present) ++ beq 1f ++ VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) ++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? ++ beq 1f ++ VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) ++1: + stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 + @ and point r4 at the word at the + @ start of the register dump +@@ -117,9 +120,12 @@ no_old_VFP_process: + @ FPEXC is in a safe state + ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 + tst r1, #FPEXC_EX @ is there additional state to restore? +- VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set) +- tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write? +- VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present) ++ beq 1f ++ VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) ++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? ++ beq 1f ++ VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) ++1: + VFPFMXR FPSCR, r5 @ restore status + + check_for_exception: +@@ -166,7 +172,7 @@ process_exception: + @ retry the faulted instruction + ENDPROC(vfp_support_entry) + +-#ifdef CONFIG_SMP ++#if defined(CONFIG_SMP) || defined(CONFIG_PM) + ENTRY(vfp_save_state) + @ Save the current VFP state + @ r0 - save location +@@ -175,9 +181,12 @@ ENTRY(vfp_save_state) + VFPFSTMIA r0, r2 @ save the working registers + VFPFMRX r2, FPSCR @ current status + tst r1, #FPEXC_EX @ is there additional state to save? +- VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set) +- tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? +- VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) ++ beq 1f ++ VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) ++ tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? ++ beq 1f ++ VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) ++1: + stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 + mov pc, lr + ENDPROC(vfp_save_state) +diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c +index c0d2c9b..7a818a0 100644 +--- a/arch/arm/vfp/vfpmodule.c ++++ b/arch/arm/vfp/vfpmodule.c +@@ -322,6 +322,61 @@ static void vfp_enable(void *unused) + set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); + } + ++#ifdef CONFIG_PM ++#include ++ ++int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) ++{ ++ struct thread_info *ti = current_thread_info(); ++ u32 fpexc = fmrx(FPEXC); ++ ++ /* if vfp is on, then save state for resumption */ ++ if (fpexc & FPEXC_EN) { ++ printk(KERN_DEBUG "%s: saving vfp state\n", __func__); ++ vfp_save_state(&ti->vfpstate, fpexc); ++ ++ /* disable, just in case */ ++ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); ++ } ++ ++ /* clear any information we had about last context state */ ++ memset(last_VFP_context, 0, sizeof(last_VFP_context)); ++ ++ return 0; ++} ++ ++int vfp_pm_resume(struct sys_device *dev) ++{ ++ /* ensure we have access to the vfp */ ++ vfp_enable(NULL); ++ ++ /* and disable it to ensure the next usage restores the state */ ++ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); ++ ++ return 0; ++} ++ ++static struct sysdev_class vfp_pm_sysclass = { ++ .name = "vfp", ++ .suspend = vfp_pm_suspend, ++ .resume = vfp_pm_resume, ++}; ++ ++static struct sys_device vfp_pm_sysdev = { ++ .cls = &vfp_pm_sysclass, ++}; ++ ++static void vfp_pm_init(void) ++{ ++ sysdev_class_register(&vfp_pm_sysclass); ++ sysdev_register(&vfp_pm_sysdev); ++} ++ ++ ++#else ++static inline void vfp_pm_init(void) { } ++#endif /* CONFIG_PM */ ++ + #include + + /* +@@ -365,6 +420,7 @@ static int __init vfp_init(void) + vfp_vector = vfp_support_entry; + + thread_register_notifier(&vfp_notifier_block); ++ vfp_pm_init(); + + /* + * We detected VFP, and the support code is +diff --git a/drivers/Kconfig b/drivers/Kconfig +index 2f557f5..b1eae9d 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -107,4 +107,6 @@ source "drivers/uio/Kconfig" + source "drivers/xen/Kconfig" + + source "drivers/staging/Kconfig" ++ ++source "drivers/dpm/Kconfig" + endmenu +diff --git a/drivers/Makefile b/drivers/Makefile +index fceb71a..c560b88 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -6,6 +6,8 @@ + # + + obj-y += gpio/ ++obj-y += i2c/ ++obj-$(CONFIG_SPI) += spi/ + obj-$(CONFIG_PCI) += pci/ + obj-$(CONFIG_PARISC) += parisc/ + obj-$(CONFIG_RAPIDIO) += rapidio/ +@@ -34,6 +36,7 @@ obj-$(CONFIG_FB_INTEL) += video/intelfb/ + obj-y += serial/ + obj-$(CONFIG_PARPORT) += parport/ + obj-y += base/ block/ misc/ mfd/ net/ media/ ++obj-$(CONFIG_DPM) += dpm/ + obj-$(CONFIG_NUBUS) += nubus/ + obj-$(CONFIG_ATM) += atm/ + obj-y += macintosh/ +@@ -47,7 +50,6 @@ obj-$(CONFIG_UIO) += uio/ + obj-y += cdrom/ + obj-y += auxdisplay/ + obj-$(CONFIG_MTD) += mtd/ +-obj-$(CONFIG_SPI) += spi/ + obj-$(CONFIG_PCCARD) += pcmcia/ + obj-$(CONFIG_DIO) += dio/ + obj-$(CONFIG_SBUS) += sbus/ +@@ -66,7 +68,6 @@ obj-$(CONFIG_GAMEPORT) += input/gameport/ + obj-$(CONFIG_INPUT) += input/ + obj-$(CONFIG_I2O) += message/ + obj-$(CONFIG_RTC_LIB) += rtc/ +-obj-y += i2c/ + obj-$(CONFIG_W1) += w1/ + obj-$(CONFIG_POWER_SUPPLY) += power/ + obj-$(CONFIG_HWMON) += hwmon/ +diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig +index 421b7c7..790cab2 100644 +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -724,5 +724,13 @@ config PATA_BF54X + + If unsure, say N. + ++config SATA_TCC ++ bool "Telechips SATA support (TCC8900 only)" ++ default y ++ help ++ Telechips Serial ATA. ++ ++ If unsure, say N. ++ + endif # ATA_SFF + endif # ATA +diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile +index 674965f..6486672 100644 +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o + obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o + obj-$(CONFIG_PDC_ADMA) += pdc_adma.o + obj-$(CONFIG_SATA_FSL) += sata_fsl.o ++obj-$(CONFIG_SATA_TCC) += sata_snps.o + + obj-$(CONFIG_PATA_ALI) += pata_ali.o + obj-$(CONFIG_PATA_AMD) += pata_amd.o +diff --git a/drivers/ata/sata_snps.c b/drivers/ata/sata_snps.c +new file mode 100644 +index 0000000..0ad9d38 +--- /dev/null ++++ b/drivers/ata/sata_snps.c +@@ -0,0 +1,1294 @@ ++/* ++ * linux/drivers/ata/sata_snps.c ++ * ++ * Author: ++ * Created: 1st April, 2009 ++ * Description: Driver for SATA Host Controller ++ * ++ * Copyright (c) 2009 Telechips, Inc. ++ * Copyright (c) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sata_snps.h" ++ ++#define DRV_NAME "tcc_sata" ++#define DRV_VERSION "0.1" ++ ++//#define jprintk(f, a...) printk("---J--- [%s:%d] " f, __func__, __LINE__, ##a) ++#define jprintk(f, a...) ++ ++//#define sata_printk(f, a...) printk("---sata--- [%s:%d] " f, __func__, __LINE__, ##a) ++#define sata_printk(f, a...) ++ ++#if defined(CONFIG_TCC_R_AX) ++#define __RX_TEST_DBTSR__ 8 ++#define __TX_TEST_DBTSR__ 8 ++//#define HSATA_DMA_DBTSR_VAL (((__RX_TEST_DBTSR__) << 16) | ((__TX_TEST_DBTSR__) << 0)) ++#define HSATA_DMA_DBTSR_VAL (((__RX_TEST_DBTSR__) << 16) | ((254 - 8) << 0)) ++#elif defined(CONFIG_TCC_R_XX) ++#define __RX_TEST_DBTSR__ 1 ++#define __TX_TEST_DBTSR__ 1 ++#define HSATA_DMA_DBTSR_VAL (((__RX_TEST_DBTSR__) << 16) | ((__TX_TEST_DBTSR__) << 0)) ++#else ++#error "Undefined TCC8900 revision type !!!" ++#endif ++ ++#define WAIT_TIME_FOR_DMA_DONE (1000 * 10) ++ ++static void tcc_exec_command_by_tag(struct ata_port *ap, const struct ata_taskfile *tf, u8 tag); ++static void tcc_sata_setup_port(struct ata_ioports *port, void __iomem *base); ++ ++ ++static struct task_struct *start_sata_thread(int (*threadfn)(void *data), ++ struct tcc_sata_dev *tcc_dev, ++ const char namefmt[]) ++{ ++ struct task_struct *ret_task = NULL; ++ if (tcc_dev) { ++ tcc_dev->is_continue = 1; ++ ret_task = kthread_run(threadfn, tcc_dev, namefmt); ++ if (IS_ERR(ret_task)) { ++ tcc_dev->is_continue = 0; ++ ret_task = NULL; ++ printk("[%s:%d] cannot run kernel_thread !!!! \n", __func__, __LINE__); ++ } ++ } ++ return ret_task; ++} ++ ++static void stop_sata_thread(struct tcc_sata_dev *tcc_dev) ++{ ++ if (tcc_dev) { ++ tcc_dev->is_continue = 0; ++ if (tcc_dev->fetch_task) { ++ wake_up(&(tcc_dev->job_wait_q)); ++ kthread_stop(tcc_dev->fetch_task); ++ tcc_dev->fetch_task = NULL; ++ } ++ } ++} ++ ++static void tcc_start_dma(GDMANCTRL *reg) ++{ ++ BITSET(reg->CHCTRL, Hw0 | Hw2); ++} ++ ++static void tcc_stop_dma(GDMANCTRL *reg) ++{ ++ BITCLR(reg->CHCTRL, Hw0 | Hw2); ++} ++ ++static int init_tx_dma(GDMANCTRL *reg, unsigned long fifo) ++{ ++ if (reg) { ++ BITCLR(reg->CHCTRL, Hw0); ++ ++ reg->ST_DADR = fifo; ++ ++ (reg->DPARAM)[0] = 0xFFFFE000 | 4; // fifo mask ++ //(reg->DPARAM)[0] = 0; // fifo mask ++ (reg->SPARAM)[0] = 0x0 | 4; ++ ++ reg->CHCTRL &= 0x00000001; ++ ++#if (__TX_TEST_DBTSR__ == 8) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw6 | Hw7 | Hw8 | Hw9 | Hw12)); ++#elif (__TX_TEST_DBTSR__ == 4) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw7 | Hw8 | Hw9 | Hw12)); ++#elif (__TX_TEST_DBTSR__ == 2) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw6 | Hw8 | Hw9 | Hw12)); ++#else ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw8 | Hw9 | Hw12)); ++#endif ++ /* clear DRI at RPTCTRL */ ++ BITCLR(reg->RPTCTRL, Hw31); ++ ++ BITSET(reg->EXTREQ, Hw14); ++ ++ return 0; ++ } ++ return -1; ++} ++ ++static int init_rx_dma(GDMANCTRL *reg, unsigned long fifo) ++{ ++ if (reg) { ++ BITCLR(reg->CHCTRL, Hw0); ++ ++ reg->ST_SADR = fifo; ++ ++ (reg->SPARAM)[0] = 0xFFFFE000 | 4; // fifo mask ++ //(reg->SPARAM)[0] = 0; // fifo mask ++ (reg->DPARAM)[0] = 0x0 | 4; ++ ++ reg->CHCTRL &= 0x00000001; ++ ++#if (__RX_TEST_DBTSR__ == 8) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw6 | Hw7 | Hw8 | Hw9)); ++#elif (__RX_TEST_DBTSR__ == 4) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw7 | Hw8 | Hw9)); ++#elif (__RX_TEST_DBTSR__ == 2) ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw6 | Hw8 | Hw9)); ++#else ++ BITSET(reg->CHCTRL, (Hw3 | Hw5 | Hw8 | Hw9)); ++#endif ++ /* clear DRI at RPTCTRL */ ++ BITCLR(reg->RPTCTRL, Hw31); ++ ++ BITSET(reg->EXTREQ, Hw13); ++ return 0; ++ } ++ return -1; ++} ++ ++#if 0 ++static void set_tx_dma(GDMANCTRL *reg, unsigned long dma_addr, unsigned int length) ++{ ++ reg->ST_SADR = dma_addr; ++ reg->HCOUNT = length / (4 * __TX_TEST_DBTSR__); ++} ++#else ++static void set_tx_dma(struct tcc_sata_dev *tcc_dev, struct tcc_sg_list * p_list) ++{ ++ tcc_dev->is_tx_complete = 0; ++ tcc_dev->is_last_tx = (p_list->flags & _TCC_DMA_END_) ? 1 : 0; ++ ++ tcc_dev->dma_tx_reg->ST_SADR = p_list->dma_addr; ++ tcc_dev->dma_tx_reg->HCOUNT = p_list->length / (4 * __TX_TEST_DBTSR__); ++} ++#endif ++ ++#if 0 ++static void set_rx_dma(GDMANCTRL *reg, unsigned long dma_addr, unsigned int length) ++{ ++ reg->ST_DADR = dma_addr; ++ reg->HCOUNT = length / (4 * __RX_TEST_DBTSR__); ++} ++#else ++static void set_rx_dma(struct tcc_sata_dev *tcc_dev, struct tcc_sg_list * p_list) ++{ ++ tcc_dev->is_rx_complete = 0; ++ tcc_dev->is_last_rx = (p_list->flags & _TCC_DMA_END_) ? 1 : 0; ++ ++ tcc_dev->dma_rx_reg->ST_DADR = p_list->dma_addr; ++ tcc_dev->dma_rx_reg->HCOUNT = p_list->length / (4 * __RX_TEST_DBTSR__); ++} ++#endif ++ ++/* ++ * success: return value => (ret == 0) ++ * fail : return value => (ret != 0) ++ */ ++static int confirm_dma_job(struct tcc_dma_Q *h) ++{ ++ if (h) { ++ if (h->top != h->pre) { ++ h->top = h->pre; ++ return 1; ++ } ++ return 0; ++ } ++ return -1; ++} ++ ++/* ++ * success: return value => (ret == 0) ++ * fail : return value => (ret != 0) ++ */ ++static int flush_dma_job(struct tcc_dma_Q *h) ++{ ++ if (h) { ++ h->pre = h->bottom = h->top = 0; ++ return 0; ++ } ++ return -1; ++} ++ ++/* ++ * success: return value => (ret == 0) ++ * fail : return value => (ret != 0) ++ */ ++static int push_dma_job(struct tcc_dma_Q *h, unsigned int dma_addr, unsigned int len, int flags) ++{ ++ if (h) { ++ h->sg_list[h->pre].dma_addr = dma_addr; ++ h->sg_list[h->pre].length = len; ++ h->sg_list[h->pre].flags = flags; ++ ++ if (h->pre + 1 >= TCC_SG_LIST_MAX) { ++ h->pre = 0; ++ } else { ++ h->pre++; ++ } ++ ++ if (h->pre == h->bottom) { ++ printk("!!!!!!!!!!!! overflow !!!!!!!!!!!!!!!!!\n"); ++ } ++ return 0; ++ } ++ return -1; ++} ++ ++/* ++ * success: return value => (ret > 0) ++ * empty : return value => (ret == 0) ++ * fail : return value => (ret < 0) ++ */ ++static int pop_dma_job(struct tcc_dma_Q *h, struct tcc_sg_list *p) ++{ ++ if (h && p) { ++ if (h->top != h->bottom) { ++ memcpy(p, &(h->sg_list[h->bottom]), sizeof(struct tcc_sg_list)); ++ if (h->bottom + 1 >= TCC_SG_LIST_MAX) { ++ h->bottom = 0; ++ } else { ++ h->bottom++; ++ } ++ return 1; ++ } ++ return 0; ++ } ++ return -1; ++} ++ ++static void wait_for_bits(volatile PSATA pSata, int ret_on_rst, int timeout_val, int exp_val, int mask, int *matched) ++{ ++ int timeout_cnt = 0, error = 0; ++ int failed; ++ int rdata = 0, i = 0; ++ int phy_sig_det_w = 1; ++ ++ *matched = 0; ++ ++ // wait for busy, and Drq to be cleared. ++ // or timeout or reset, if checking reset ++ while ((timeout_cnt < timeout_val) ++ && !*matched && (error == 0) ++ && !(!phy_sig_det_w && ret_on_rst)) { ++ rdata = pSata->CDR7; ++ failed = 0; ++ ++ for (i = 0; i <= 31; i = i + 1) { ++ if ((((mask >> i) & 1) == 1) && (((rdata >> i) & 1) != ((exp_val >> i) & 1))) { ++ failed = 1; ++ } ++ } ++ ++ if (failed == 0) { ++ *matched = 1; ++ } ++ ++ // After bits matched, check for error ++ if (*matched) { ++ if (((rdata & 0xff) != 0x7f) // we're not in Power on reset ++ && (((rdata >> CDR7_ERR) & 1) == 1)) // we do have error bit set ++ { ++ error = 1; ++ } ++ } else { ++ timeout_cnt = timeout_cnt + 1; ++ } ++ ++ } ++ ++ if ((ret_on_rst == 1) && !phy_sig_det_w) { ++ printk("wait_for_bits: detected a Non recov err, while waiting for bits on reg 0x%x\n", ++ 0x1C); ++ } else if (timeout_cnt >= timeout_val) { ++ printk("wait_for_bits: Timeout waiting reg at address '0x%x' to equal '0x%x'\n", ++ 0x1C, exp_val ); ++ } else { ++ printk("wait_for_bits: Got register at address '0x%x' reg expected_value='0x%x', actual='0x%x'\n", ++ 0x1C, exp_val, rdata); ++ } ++} ++ ++static void wait_for_bsydrq(volatile PSATA pSata, int ret_on_rst, int timeout_val, int *matched) ++{ ++ int exp_val = 0; ++ int mask = 0x88; ++ ++ wait_for_bits(pSata, ret_on_rst, timeout_val, exp_val, mask, matched); ++} ++ ++static int prog_host_speed(volatile PSATA pSata, int speed, int *spd_ok) ++{ ++ int spd_select; ++ int reset; ++ int reg_data; ++ //int i; ++ int ret_on_rst; ++ int timeout_val; ++ int matched; ++ ++ // Initialize ++ ret_on_rst = 0; ++ //timeout_val = 1000000; // Must Be Huge For Speed Negotiation ++ timeout_val = 1000000; // Must Be Huge For Speed Negotiation ++ ++ // Set speed ++ spd_select = (speed == 2) ? 0x2 : 0x1; ++ ++ // Reset Device with correct speed ++ reset = 1; ++ reg_data = (spd_select << 4) | reset; ++ ++ // Write SCR2 with speed and reset ++ pSata->SCR2 = reg_data; ++ ++ // Need to wait a few clocks of slowest ++ //mdelay(1); ++ mdelay(10); ++ ++ // Set normal operation & correct speed ++ reset = 0; ++ reg_data = spd_select << 4 | reset; ++ //HwSATA->nSCR2 = reg_data; ++ pSata->SCR2 = reg_data; ++ ++ // Wait for BSY & DRQ to be cleared ++ wait_for_bsydrq(pSata, ret_on_rst, timeout_val, &matched); ++ ++ if (matched) { ++ printk("prog_host_speed: Host Speed selected [speed:%d] SCR0[0x%X]\n", ++ speed, pSata->SCR0); ++ *spd_ok = 1; ++ return 0; ++ } else { ++ printk("prog_host_speed: TIMEOUT - Host Speed timed out waiting for speed change! [speed:%d], SCR0[0x%X]\n", ++ speed, pSata->SCR0); ++ *spd_ok = 0; ++ } ++ return -1; ++} ++ ++static int tcc_sata_hw_init(unsigned long sata_base) ++{ ++ int spd_ok = 0; ++ volatile PSATA pSata = (volatile PSATA)sata_base; ++ ++ if (prog_host_speed(pSata, 2, &spd_ok) == 0) { ++ return 0; ++ } else if (prog_host_speed(pSata, 1, &spd_ok) == 0) { ++ return 0; ++ } ++ return -1; ++} ++ ++static int tcc_sata_check_atapi_dma(struct ata_queued_cmd *qc) ++{ ++ u8 cmnd = qc->scsicmd->cmnd[0]; ++ ++ switch (cmnd) { ++ case READ_10: ++ case READ_12: ++ case READ_16: ++ case WRITE_10: ++ case WRITE_12: ++ case WRITE_16: ++ //printk("ATAPI DMA OK ~~~[0x%X]\n", cmnd); ++ return 0; ++ ++ default: ++ //printk("ATAPI DMA FAIL [0x%X] ~~~\n", cmnd); ++ return -1; ++ } ++} ++ ++static irqreturn_t tcc_dma_isr(int irq, void *dev_id) ++{ ++ struct ata_host *host = (struct ata_host *)dev_id; ++ struct tcc_sata_dev *tcc_dev = host->private_data; ++ ++ struct tcc_sg_list list; ++ if (irq == tcc_dev->dma_rx_irq) { ++ tcc_dev->dma_rx_reg->CHCTRL |= Hw3; ++ tcc_stop_dma(tcc_dev->dma_rx_reg); ++ ++ if (tcc_dev->is_last_rx) { ++ tcc_dev->is_rx_complete = 1; ++ wake_up(&(tcc_dev->rx_dma_wait_q)); ++ } else { ++ if (pop_dma_job(&(tcc_dev->dma_q), &list) > 0) { ++ if (list.flags & _TCC_DMA_RX_) { ++ set_rx_dma(tcc_dev, &list); ++ tcc_start_dma(tcc_dev->dma_rx_reg); ++ } ++ } else { ++ printk("something wrong !!!!!!!!!!!!!!!!!!!! [%s:%d]\n", __func__, __LINE__); ++ tcc_dev->is_rx_complete = 1; ++ wake_up(&(tcc_dev->rx_dma_wait_q)); ++ } ++ } ++ } else if (irq == tcc_dev->dma_tx_irq) { ++ tcc_dev->dma_tx_reg->CHCTRL |= Hw3; ++ tcc_stop_dma(tcc_dev->dma_tx_reg); ++ if (tcc_dev->is_last_tx) { ++ writel(HSATA_DMACR_TXRX_CLEAR, tcc_dev->membase + HSATA_DMACR_REG); /* rx/tx disable */ ++ tcc_dev->is_tx_complete = 1; ++ wake_up(&(tcc_dev->tx_dma_wait_q)); ++ } else { ++ if (pop_dma_job(&(tcc_dev->dma_q), &list) > 0) { ++ if (list.flags & _TCC_DMA_TX_) { ++ set_tx_dma(tcc_dev, &list); ++ tcc_start_dma(tcc_dev->dma_tx_reg); ++ } ++ } else { ++ printk("something wrong !!!!!!!!!!!!!!!!!!!! [%s:%d]\n", __func__, __LINE__); ++ tcc_dev->is_tx_complete = 1; ++ wake_up(&(tcc_dev->tx_dma_wait_q)); ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static void tcc_port_stop(struct ata_port *ap) ++{ ++ struct tcc_sata_dev *tcc_dev = ap->host->private_data; ++ ++ if (tcc_dev) { ++ stop_sata_thread(tcc_dev); ++ free_irq(tcc_dev->dma_tx_irq, ap->host); ++ free_irq(tcc_dev->dma_rx_irq, ap->host); ++ ++ if (tcc_dev->membase) { ++ iounmap(tcc_dev->membase); ++ kfree(tcc_dev); ++ } ++ } ++ ap->host->private_data = NULL; ++} ++ ++static int fetch_dma_thread(void *arg) ++{ ++ struct tcc_sata_dev *tcc_dev = (struct tcc_sata_dev *)arg; ++ int ret = 0; ++ ++ sata_printk("### start kernel thread ###\n"); ++ if (tcc_dev) { ++ struct tcc_sg_list list; ++ do { ++ ret = wait_event_interruptible_timeout(tcc_dev->job_wait_q, ++ (tcc_dev->dma_q.top != tcc_dev->dma_q.bottom) || !(tcc_dev->is_continue), ++ msecs_to_jiffies(1000)); ++ while (tcc_dev->is_continue) { ++ if (pop_dma_job(&(tcc_dev->dma_q), &list) > 0) { ++ sata_printk("--- DMA [%s] dma_addr[0x%X], len[%d], flags[0x%X]\n", ++ list.flags & _TCC_DMA_RX_ ? "RX" : "TX", list.dma_addr, list.length, list.flags); ++ ++ //ret = readl(tcc_dev->membase + HSATA_DBTSR_REG); ++ //printk("before Rx/Tx DBTSR_REG[0x%X], dma HCOUNT[0x%X]\n", ret, tcc_dev->dma_rx_reg->HCOUNT); ++ ++ if (list.flags & _TCC_DMA_START_) { ++ //printk("--- start DMA [%s] dma_addr[0x%X], len[%d], flags[0x%X]\n", ++ // list.flags & _TCC_DMA_RX_ ? "RX" : "TX", list.dma_addr, list.length, list.flags); ++ ++ writel(HSATA_DMACR_TXRX_CLEAR, tcc_dev->membase + HSATA_DMACR_REG); /* rx/tx disable */ ++ writel(HSATA_DMA_DBTSR_VAL, tcc_dev->membase + HSATA_DBTSR_REG); ++ ++ writel((list.flags & _TCC_DMA_RX_) ? HSATA_DMACR_RX_EN : HSATA_DMACR_TX_EN, ++ tcc_dev->membase + HSATA_DMACR_REG); ++ if (list.flags & _TCC_DMA_RX_) { ++ set_rx_dma(tcc_dev, &list); ++ tcc_start_dma(tcc_dev->dma_rx_reg); ++ if (wait_event_interruptible_timeout((tcc_dev->rx_dma_wait_q), ++ tcc_dev->is_rx_complete, ++ msecs_to_jiffies(WAIT_TIME_FOR_DMA_DONE)) == 0) { ++ tcc_stop_dma(tcc_dev->dma_rx_reg); ++ flush_dma_job(&(tcc_dev->dma_q)); ++ ret = readl(tcc_dev->membase + HSATA_DBTSR_REG); ++ printk("[%s:%d] RX wait_event timeout (%dms) !!!\n", ++ __func__, __LINE__, WAIT_TIME_FOR_DMA_DONE); ++ printk("rx DBTSR_REG[0x%X], dma HCOUNT[0x%X]\n", ret, tcc_dev->dma_rx_reg->HCOUNT); ++ } ++ } else { ++ set_tx_dma(tcc_dev, &list); ++ tcc_start_dma(tcc_dev->dma_tx_reg); ++ if (wait_event_interruptible_timeout((tcc_dev->tx_dma_wait_q), ++ tcc_dev->is_tx_complete, ++ msecs_to_jiffies(WAIT_TIME_FOR_DMA_DONE)) == 0) { ++ tcc_stop_dma(tcc_dev->dma_tx_reg); ++ flush_dma_job(&(tcc_dev->dma_q)); ++ ret = readl(tcc_dev->membase + HSATA_DBTSR_REG); ++ printk("[%s:%d] TX wait_event timeout (%dms) !!!\n", ++ __func__, __LINE__, WAIT_TIME_FOR_DMA_DONE); ++ printk("tx DBTSR_REG[0x%X], dma HCOUNT[0x%X]\n", ret, tcc_dev->dma_tx_reg->HCOUNT); ++ } ++ } ++ } else { ++ flush_dma_job(&(tcc_dev->dma_q)); ++ printk("[%s:%d] mismatch q-list !!!\n", __func__, __LINE__); ++ } ++ } else { ++ break; ++ } ++ } ++ } while (!kthread_should_stop()); ++ } ++ sata_printk("### end kernel thread ###\n"); ++ return 0; ++} ++ ++static int tcc_port_start(struct ata_port *ap) ++{ ++ volatile u32 val32; ++ struct tcc_sata_dev *tcc_dev = NULL; ++ volatile PPIC pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE); ++ int ret = 0; ++ unsigned long sata_base = 0; ++ unsigned long tx_base = (unsigned long)tcc_p2v(HwGDMA2_BASE); ++ unsigned long rx_base = (unsigned long)tcc_p2v(HwGDMA3_BASE); ++ unsigned long mmio_base_addr = (unsigned long)(ap->private_data); ++ ++ tcc_dev = kmalloc(sizeof(struct tcc_sata_dev), GFP_KERNEL); ++ if (tcc_dev) { ++ memset(tcc_dev, 0, sizeof(struct tcc_sata_dev)); ++ tcc_dev->membase = ioremap_nocache(mmio_base_addr, 0x800); ++ tcc_sata_setup_port(&ap->ioaddr, tcc_dev->membase); ++ ap->host->private_data = tcc_dev; ++ } else { ++ printk("[%s:%d] cannot allocate 'tcc_dev struct' \n", __func__, __LINE__); ++ return -1; ++ } ++ HSATA_ENABLE_INTERRUPTS(tcc_dev); ++ ++ tcc_dev->dma_tx_reg = (GDMANCTRL *)(tx_base + 0x60); ++ tcc_dev->dma_rx_reg = (GDMANCTRL *)(rx_base + 0x60); ++ ++ tcc_dev->dma_tx_irq = INT_DMA2_CH2; ++ tcc_dev->dma_rx_irq = INT_DMA3_CH2; ++ ++ BITSET(pPIC->MODE0, Hw29); // level-trigger ++ BITCLR(pPIC->POL0, Hw29); // active-high ++ ++ init_waitqueue_head(&(tcc_dev->job_wait_q)); ++ init_waitqueue_head(&(tcc_dev->tx_dma_wait_q)); ++ init_waitqueue_head(&(tcc_dev->rx_dma_wait_q)); ++ ++ init_rx_dma(tcc_dev->dma_rx_reg, TCC_DMADR_REG_ADDR); ++ init_tx_dma(tcc_dev->dma_tx_reg, TCC_DMADR_REG_ADDR); ++ writel(HSATA_DMACR_TXMODE_BIT, tcc_dev->membase + HSATA_DMACR_REG); /* disable */ ++ ++ tcc_dev->fetch_task = start_sata_thread(fetch_dma_thread, tcc_dev, "tcc_sata_task"); ++ if (tcc_dev->fetch_task == NULL) { ++ return -1; ++ } ++ ++ ret = request_irq(tcc_dev->dma_rx_irq, ++ tcc_dma_isr, ++ IRQF_SHARED, /* flags */ ++ "HSATA-DMA-RX", /* in /proc/interrupts */ ++ ap->host); /* user data passed to ISR */ ++ if (!ret) { ++ ret = request_irq(tcc_dev->dma_tx_irq, ++ tcc_dma_isr, ++ IRQF_SHARED, /* flags */ ++ "HSATA-DMA-TX", /* in /proc/interrupts */ ++ ap->host); /* user data passed to ISR */ ++ if (!ret) { ++ sata_base = (unsigned long)tcc_p2v(HwSATA_BASE); ++ tcc_sata_hw_init(sata_base); ++ ++ writel(HSATA_DMA_DBTSR_VAL, tcc_dev->membase + HSATA_DBTSR_REG); ++ ++ val32 = readl(tcc_dev->membase + HSATA_SCR0_REG); ++ switch (HSATA_SCR0_SPD_GET(val32)) { ++ case 0x0: ++ printk("Rx_DBTSR[%d] Tx_DBTSR[%d] **** NO NEGOTIATED SPEED!!! ****\n", __RX_TEST_DBTSR__, __TX_TEST_DBTSR__); ++ break; ++ case 0x1: ++ printk("Rx_DBTSR[%d] Tx_DBTSR[%d] **** GEN I RATE NEGOTIATED ****\n", __RX_TEST_DBTSR__, __TX_TEST_DBTSR__); ++ break; ++ case 0x2: ++ printk("Rx_DBTSR[%d] Tx_DBTSR[%d] **** GEN II RATE NEGOTIATED ****\n", __RX_TEST_DBTSR__, __TX_TEST_DBTSR__); ++ break; ++ } ++ return 0; ++ } else { ++ printk("ERROR rx request_irq ret[%d]\n", ret); ++ free_irq(tcc_dev->dma_rx_irq, ap->host); ++ } ++ } else { ++ printk("ERROR tx request_irq ret[%d]\n", ret); ++ } ++ return -1; ++} ++ ++ ++static int tcc_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) ++{ ++ if (sc_reg > SCR_CONTROL) { ++ return -EINVAL; ++ } ++ *val = readl((void *)link->ap->ioaddr.scr_addr + (sc_reg * 4)); ++ return 0; ++} ++ ++static int tcc_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) ++{ ++ if (sc_reg > SCR_CONTROL) { ++ return -EINVAL; ++ } ++ writel(val, (void *)link->ap->ioaddr.scr_addr + (sc_reg * 4)); ++ return 0; ++} ++ ++static void tcc_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) ++{ ++ unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; ++ ++ sata_printk("TFLAGS: %s %s %s %s\n", ++ (tf->flags & ATA_TFLAG_LBA48) ? "LBA48" : "NOT-LBA48", ++ (tf->flags & ATA_TFLAG_ISADDR) ? "ISADDR" : "", ++ (tf->flags & ATA_TFLAG_DEVICE) ? "DEVICE" : "", ++ (tf->flags & ATA_TFLAG_WRITE) ? "WRITE" : "READ"); ++ sata_printk("CTL: %s %s %s\n", ++ (tf->ctl & ATA_HOB) ? "HOB" : "NOT-HOB", ++ (tf->ctl & ATA_SRST) ? "SRST" : "NOT-SRST", ++ (tf->ctl & ATA_NIEN) ? "NIEN" : "INTERRUPTS-ENABLED"); ++ ++ if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { ++ sata_printk("hob: feat=0x%X nsect=0x%X, lba:0x%X 0x%X 0x%X\n", ++ tf->hob_feature, ++ tf->hob_nsect, ++ tf->hob_lbal, ++ tf->hob_lbam, ++ tf->hob_lbah); ++ } ++ ++ if (is_addr) { ++ sata_printk("feat=0x%X nsect=0x%X, lba:0x%X 0x%X 0x%X\n", ++ tf->feature, ++ tf->nsect, ++ tf->lbal, ++ tf->lbam, ++ tf->lbah); ++ } ++ ++ if (tf->flags & ATA_TFLAG_DEVICE) { ++ sata_printk("ATA_TFLAG_DEVICE device=0x%X (%s)\n", tf->device, ++ (tf->device & ATA_LBA) ? "LBA" : "CHS"); ++ } ++ ++ if (!is_addr) { ++ sata_printk("is_addr=%d\n", is_addr); ++ } ++ ++ ata_sff_tf_load(ap, tf); ++} ++ ++static void tcc_tf_read(struct ata_port *ap, struct ata_taskfile *tf) ++{ ++ jprintk(" nsect=0x%X, lba:0x%X 0x%X 0x%X device=0x%x\n", ++ tf->nsect, tf->lbal, tf->lbam, tf->lbah, tf->device); ++ ++ if (tf->flags & ATA_TFLAG_LBA48) { ++ jprintk("hob: feat=0x%X nsect=0x%X, lba:0x%X 0x%X 0x%X\n", ++ tf->hob_feature, tf->hob_nsect, tf->hob_lbal, ++ tf->hob_lbam, tf->hob_lbah); ++ } ++ ++ ata_sff_tf_read(ap, tf); ++} ++ ++static struct scsi_host_template tcc_sata_sht = { ++ ATA_BMDMA_SHT(DRV_NAME), ++}; ++ ++static u8 tcc_stat_check_status(struct ata_port *ap) ++{ ++ return ioread8(ap->ioaddr.status_addr); ++} ++ ++static void tcc_dma_setup_noexec_by_tag(struct ata_queued_cmd *qc, u8 tag) ++{ ++ //struct tcc_sata_dev *tcc_dev = qc->ap->host->private_data; ++ jprintk("DMA SETUP tag=%d id=%d [%s]\n", tag, qc->ap->print_id, (qc->dma_dir == DMA_TO_DEVICE) ? "WRITE" : "READ"); ++} ++ ++static void tcc_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) ++{ ++ tcc_exec_command_by_tag(ap, tf, 0); ++} ++ ++static void tcc_dma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag) ++{ ++ tcc_dma_setup_noexec_by_tag(qc, tag); ++ tcc_exec_command(qc->ap, &qc->tf); ++} ++ ++ ++void tcc_dma_setup(struct ata_queued_cmd *qc) ++{ ++ //struct tcc_sata_dev *tcc_dev = qc->ap->host->private_data; ++ tcc_dma_setup_by_tag(qc, 0); ++ ++} ++ ++void tcc_dma_start_by_tag(struct ata_queued_cmd *qc, u8 tag) ++{ ++ struct tcc_sata_dev *tcc_dev = qc->ap->host->private_data; ++ ++ confirm_dma_job(&(tcc_dev->dma_q)); ++ wake_up(&(tcc_dev->job_wait_q)); ++} ++ ++ ++static void tcc_dma_start(struct ata_queued_cmd *qc) ++{ ++ tcc_exec_command(qc->ap, &qc->tf); ++ tcc_dma_start_by_tag(qc, 0); ++} ++ ++void tcc_dma_stop(struct ata_queued_cmd *qc) ++{ ++ struct tcc_sata_dev *tcc_dev = qc->ap->host->private_data; ++ if (qc->dma_dir != DMA_TO_DEVICE) { ++ writel(HSATA_DMACR_TXRX_CLEAR, tcc_dev->membase + HSATA_DMACR_REG); /* rx/tx disable */ ++ } else { ++ //writel(HSATA_DMACR_TXRX_CLEAR, tcc_dev->membase + HSATA_DMACR_REG); /* rx/tx disable */ ++ } ++} ++ ++ ++u8 tcc_dma_status(struct ata_port *ap) ++{ ++ //struct tcc_sata_dev *tcc_dev = qc->ap->host->private_data; ++ return ATA_DMA_INTR; ++} ++ ++void tcc_irq_clear(struct ata_port *ap) ++{ ++ /* read status reg to clear interrupt in controller */ ++ ata_sff_check_status(ap); ++} ++ ++static void tcc_exec_command_by_tag(struct ata_port *ap, const struct ata_taskfile *tf, u8 tag) ++{ ++ struct ata_host *host = ap->host; ++ struct tcc_sata_dev *tcc_dev = host->private_data; ++ volatile u32 val32; ++ ++ switch (tf->command) { ++ case ATA_CMD_CHK_POWER: ++ jprintk("ATA_CMD_CHK_POWER - tag=%d\n", tag); break; ++ case ATA_CMD_EDD: ++ jprintk("ATA_CMD_EDD - tag=%d\n", tag); break; ++ case ATA_CMD_FLUSH: ++ jprintk("ATA_CMD_FLUSH - tag=%d\n", tag); break; ++ case ATA_CMD_FLUSH_EXT: ++ jprintk("ATA_CMD_FLUSH_EXT - tag=%d\n", tag); break; ++ case ATA_CMD_ID_ATA: ++ jprintk("ATA_CMD_ID_ATA - tag=%d\n", tag); break; ++ case ATA_CMD_ID_ATAPI: ++ jprintk("ATA_CMD_ID_ATAPI - tag=%d\n", tag); break; ++ case ATA_CMD_READ: ++ jprintk("ATA_CMD_READ - tag=%d\n", tag); break; ++ case ATA_CMD_READ_EXT: ++ jprintk("ATA_CMD_READ_EXT - tag=%d\n", tag); break; ++ case ATA_CMD_WRITE: ++ jprintk("ATA_CMD_WRITE - tag=%d\n", tag); break; ++ case ATA_CMD_WRITE_EXT: ++ jprintk("ATA_CMD_WRITE_EXT - tag=%d\n", tag); break; ++ case ATA_CMD_PIO_READ: ++ jprintk("ATA_CMD_PIO_READ - tag=%d\n", tag); break; ++ case ATA_CMD_PIO_READ_EXT: ++ jprintk("ATA_CMD_PIO_READ_EXT - tag=%d\n", tag); break; ++ case ATA_CMD_PIO_WRITE: ++ jprintk("ATA_CMD_PIO_WRITE - tag=%d\n", tag); break; ++ case ATA_CMD_PIO_WRITE_EXT: ++ jprintk("ATA_CMD_PIO_WRITE_EXT - tag=%d\n", tag); break; ++ case ATA_CMD_SET_FEATURES: ++ jprintk("ATA_CMD_SET_FEATURES - tag=%d\n", tag); break; ++ case ATA_CMD_PACKET: ++ jprintk("ATA_CMD_PACKET - tag=%d\n", tag); break; ++ case HSATA_CMD_QWRITE: ++ jprintk("HSATA_CMD_QWRITE - tag=%d\n", tag); break; ++ case HSATA_CMD_QREAD: ++ jprintk("HSATA_CMD_QREAD - tag=%d\n", tag); break; ++ default: ++ jprintk("ATA_CMD_??? (0x%X)\n", tf->command); break; ++ } ++ ++ val32 = readl(tcc_dev->membase + HSATA_SERROR_REG); ++ jprintk("SERROR=0x%X\n", val32 ); ++ writel(val32, tcc_dev->membase + HSATA_SERROR_REG); ++ val32 = readl(tcc_dev->membase + HSATA_INTPR_REG); ++ jprintk("INTPR=0x%x\n", val32); ++ ++ ata_sff_exec_command(ap, tf); ++} ++ ++void tcc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag) ++{ ++ struct scatterlist *sg = qc->sg; /* include/asm-arm/scatterlist.h */ ++ struct ata_port *ap = qc->ap; ++ struct tcc_sata_dev *tcc_dev = ap->host->private_data; ++ unsigned int nelem; ++ int dir, flags = _TCC_DMA_START_; ++ unsigned int fis_len = 0, dma_addr = 0, sg_len = 0, offset = 0, len = 0; ++ ++ if (!(qc->flags & ATA_QCFLAG_DMAMAP)) { ++ jprintk("NO DMA - exiting\n"); ++ return; ++ } ++ ++#if 0 ++ assert(sg != NULL); ++ assert(qc->n_elem > 0); ++#endif ++ ++ dir = qc->dma_dir; ++ ++ jprintk("QC PREP id=%d dma dir=%s n_elem=%d\n", ++ qc->ap->print_id, (dir == DMA_FROM_DEVICE) ? "FROM_DEVICE" : "TO_DEVICE", qc->n_elem); ++ ++ for (nelem = qc->n_elem; nelem; nelem--) { ++ dma_addr = (unsigned int)sg_dma_address(sg); ++ sg_len = sg_dma_len(sg); ++ while (sg_len) { ++ ++ flags |= ((dir == DMA_TO_DEVICE) ? _TCC_DMA_TX_ : _TCC_DMA_RX_); ++ ++ offset = dma_addr & 0xFFFF; ++ len = sg_len; ++ ++ if ((offset + sg_len) > 0x10000) { ++ printk("overflow !!!!!!!!!! offset[%u], sg_len[%u]\n", offset, sg_len); ++ len = 0x10000 - offset; ++ } ++ ++ if ((fis_len + len) > 8192) { ++ sata_printk("SPLITTING: fis_len=%d/0x%x len=%d/0x%x\n", fis_len, fis_len, len, len); ++ len = (8192 - fis_len); ++ fis_len = 0; ++ } else { ++ fis_len += len; ++ } ++ ++ if (fis_len == 8192) { ++ fis_len = 0; ++ } ++ ++ sata_printk("+++ DMA sg nelem=%d dma_addr=0x%X sg_len=%d [%s]\n", ++ qc->n_elem, dma_addr, sg_len, (dir == DMA_TO_DEVICE) ? "TX" : "RX"); ++ ++ sg_len -= len; ++ if ((sg_len == 0) && (nelem == 1)) { ++ flags |= _TCC_DMA_END_; ++ sata_printk("********* LAST DMA LIST *********\n"); ++ } ++ ++ push_dma_job(&(tcc_dev->dma_q), dma_addr, len, flags); ++ dma_addr += len; ++ flags = 0; ++ } ++ sg++; ++ } ++} ++ ++static void tcc_qc_prep(struct ata_queued_cmd *qc) ++{ ++ if (!(qc->flags & ATA_QCFLAG_DMAMAP)) { ++ return; ++ } ++ tcc_qc_prep_by_tag(qc, 0); ++} ++ ++ ++static unsigned int tcc_qc_issue_prot(struct ata_queued_cmd *qc) ++{ ++ jprintk("id=%d\n", qc->ap->print_id); ++ ++ /* see promise driver also */ ++ switch (qc->tf.protocol) { ++ case ATA_PROT_DMA: ++ jprintk("ATA_PROT_DMA\n"); ++ break; ++ case ATA_PROT_PIO: ++ jprintk("ATA_PROT_PIO\n"); ++ break; ++ } ++ return ata_sff_qc_issue(qc); ++} ++ ++static struct ata_port_operations tcc_sata_ops = { ++ //.inherits = &ata_bmdma_port_ops, ++ //.inherits = &sata_pmp_port_ops, ++ ++ .inherits = &ata_sff_port_ops, ++ .mode_filter = ata_bmdma_mode_filter, ++ .bmdma_setup = tcc_dma_setup, ++ .bmdma_start = tcc_dma_start, ++ .bmdma_stop = tcc_dma_stop, ++ .bmdma_status = tcc_dma_status, ++ ++ .sff_exec_command = tcc_exec_command, ++ ++ .sff_tf_load = tcc_tf_load, ++ .sff_tf_read = tcc_tf_read, ++ .sff_check_status = tcc_stat_check_status, ++ .check_atapi_dma = tcc_sata_check_atapi_dma, ++ ++ .scr_read = tcc_scr_read, ++ .scr_write = tcc_scr_write, ++ ++ .port_start = tcc_port_start, ++ .port_stop = tcc_port_stop, ++ .sff_irq_clear = tcc_irq_clear, ++ ++ .qc_prep = tcc_qc_prep, ++ .qc_issue = tcc_qc_issue_prot, ++ ++}; ++ ++static void tcc_sata_setup_port(struct ata_ioports *port, void __iomem *base) ++{ ++ port->cmd_addr = base + 0x00; ++ port->data_addr = base + 0x00; ++ ++ ++ port->error_addr = base + 0x04; ++ port->feature_addr = base + 0x04; ++ ++ port->nsect_addr = base + 0x08; ++ ++ port->lbal_addr = base + 0x0c; ++ port->lbam_addr = base + 0x10; ++ port->lbah_addr = base + 0x14; ++ ++ port->device_addr = base + 0x18; ++ ++ port->command_addr = base + 0x1c; ++ port->status_addr = base + 0x1c; ++ ++ port->altstatus_addr = base + 0x20; ++ port->ctl_addr = base + 0x20; ++ ++ { ++ unsigned long sata_base = (unsigned long)tcc_p2v(HwGDMA2_BASE); ++ sata_base += 0x60; ++ port->bmdma_addr = (void __iomem *)(sata_base); /* we better never use this */ ++ } ++ port->scr_addr = base + 0x24; ++ ++} ++ ++static const struct ata_port_info sata_tcc_port_info[] = { ++ { ++ .flags = (ATA_FLAG_SATA /* loik ??? flags */ ++ | ATA_FLAG_NO_LEGACY /* no legacy mode check */ ++ //| ATA_FLAG_SRST /* use ATA SRST, not E.D.D. */ ++ | ATA_FLAG_MMIO), /* use MMIO, not PortIO */ ++ ++ .pio_mask = 0x1f, /* pio0-4 - IDENTIFY DEVICE word 63 */ ++ .udma_mask = 0x7f, /* udma0-6 - IDENTIFY DEVICE word 88 */ ++ //.mwdma_mask = 0x07, /* mwdma0-2 - IDENTIFY DEVICE word 64 */ ++ .port_ops = &tcc_sata_ops, ++ }, ++}; ++ ++static irqreturn_t tcc_sata_isr(int irq, void *dev_id) ++{ ++ struct ata_host *host = (struct ata_host *)dev_id; ++ struct tcc_sata_dev *tcc_dev = host->private_data; ++ struct ata_port *ap; ++ volatile u32 intpr; ++ volatile u32 val32; ++ unsigned int handled = 0; ++ unsigned int i; ++ u32 err_interrupt; ++ u8 tag; ++ volatile u32 sactive, tmp; ++ struct ata_queued_cmd *qc; ++ //unsigned long flags; ++ ++ //spin_lock_irqsave(&host->lock, flags); ++ ++ ap = host->ports[0]; ++ ++ intpr = readl(tcc_dev->membase + HSATA_INTPR_REG); ++ jprintk("INTPR=0x%x\n", intpr); ++ ++ if (intpr & HSATA_INTMR_ERRM_BIT) { ++ val32 = readl(tcc_dev->membase + HSATA_SERROR_REG); ++ sata_printk("============> SERROR=0x%08x INTPR=0x%x\n", val32, intpr); ++ writel(val32, tcc_dev->membase + HSATA_SERROR_REG); /* to clear */ ++ writel(HSATA_INTMR_ERRM_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ err_interrupt = 1; ++ handled = 1; ++ goto DONE; ++ } else { ++ err_interrupt = 0; ++ } ++ ++ tmp = readl(tcc_dev->membase + HSATA_SACTIVE_REG); ++ jprintk("SACTIVE=0x%x\n", tmp); ++ ++ if (intpr & HSATA_INTMR_NEWFP_BIT) { ++ writel(HSATA_INTMR_NEWFP_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ tag = ((u8)readl(tcc_dev->membase + HSATA_FPTAGR_REG)) & 0x1f; ++ sata_printk("============> NEWFP tag=%d\n", tag); ++ handled = 1; ++ goto DONE; ++ } ++ ++ if (intpr & HSATA_INTMR_DMAT_BIT) { ++ writel(HSATA_INTMR_DMAT_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ sata_printk("============> HSATA_INTMR_DMAT_BIT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ if (intpr & HSATA_INTMR_PMABORT) { ++ writel(HSATA_INTMR_PMABORT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ sata_printk("============> HSATA_INTMR_PMABORT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ if (intpr & HSATA_INTMR_NEWBIST_BIT) { ++ writel(HSATA_INTMR_NEWBIST_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ sata_printk("============> HSATA_INTMR_NEWBIST_BIT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ if (intpr & HSATA_INTMR_PRIMERR_BIT) { ++ writel(HSATA_INTMR_PRIMERR_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ sata_printk("============> HSATA_INTMR_PRIMERR_BIT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ if (intpr & HSATA_INTMR_CMDABORT_BIT) { ++ writel(HSATA_INTMR_CMDABORT_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ sata_printk("============> HSATA_INTMR_CMDABORT_BIT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ if (intpr & HSATA_INTMR_CMDGOOD_BIT) { ++ writel(HSATA_INTMR_CMDGOOD_BIT, tcc_dev->membase + HSATA_INTPR_REG); /* to clear */ ++ jprintk("============> HSATA_INTMR_CMDGOOD_BIT\n"); ++ handled = 1; ++ goto DONE; ++ } ++ ++ sactive = readl(tcc_dev->membase + HSATA_SACTIVE_REG); /* remaining pending */ ++ if (sactive) { ++ sata_printk("UNEXPECTED SACTIVE??? sactive=0x%x\n", sactive ); ++ } ++ ++ for (i = 0; i < host->n_ports; i++) { ++ struct ata_port *ap; ++ ++ ap = host->ports[i]; ++ if (ap && ++ !(ap->flags & ATA_FLAG_DISABLED)) { ++ ++ qc = ata_qc_from_tag(ap, ap->link.active_tag); ++ if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && ++ (qc->flags & ATA_QCFLAG_ACTIVE)) { ++ handled |= ata_sff_host_intr(ap, qc); ++ } ++ } ++ } ++ ++ sata_printk("====================> INTR DONE\n"); ++ if (handled == 0) { ++ sata_printk("handled error !!!!!!!!! \n"); ++ if ((qc = ata_qc_from_tag(ap, ap->link.active_tag))) { ++ ata_qc_complete(qc); ++ } ++ ata_sff_check_status(ap); ++ handled = 1; ++ } ++ ++ //spin_unlock_irqrestore(&host->lock, flags); ++DONE: ++ return IRQ_RETVAL(handled); ++} ++ ++static int tcc_sata_remove(struct platform_device *pdev) ++{ ++ struct ata_host *host = platform_get_drvdata(pdev); ++ //struct tcc_sata_dev *tcc_dev = NULL; ++ ++ if (host) { ++ ata_host_detach(host); ++ } ++ return 0; ++} ++ ++static int __init tcc_sata_probe(struct platform_device *pdev) ++{ ++ const struct ata_port_info *ppi[] = { &(sata_tcc_port_info[0]), NULL }; ++ struct ata_host *host; ++ int n_ports; ++ struct resource *res; ++ struct ata_port *ap = NULL; ++ int irq = -1; ++ PPMU p_pmu = (PPMU)tcc_p2v(HwPMU_BASE); ++ volatile PPIC pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE); ++ ++ printk("TCC SATA version " DRV_VERSION "\n"); ++ ++ BITCLR(p_pmu->PWROFF, Hw4); // SATA popwer on ++ tca_ckc_setiobus(RB_SATAHCONTROLLER, 1); ++ ++ BITSET(pPIC->SEL1, 1 << (INT_SATA - 32)); ++ BITSET(pPIC->MODE1, 1 << (INT_SATA - 32)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ return -EINVAL; ++ } ++ irq = platform_get_irq(pdev, 0); ++ ++ /* allocate host */ ++ n_ports = 1; ++ host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); ++ if (!host) { ++ return -ENOMEM; ++ } ++ ++ ap = host->ports[0]; ++ ap->private_data = (void *)(res->start); ++ platform_set_drvdata(pdev, host); ++ ++ return ata_host_activate(host, irq, tcc_sata_isr, IRQF_SHARED, &tcc_sata_sht); ++ //return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED, &tcc_sata_sht); ++} ++ ++static struct platform_driver tcc_sata_driver = { ++ .probe = tcc_sata_probe, ++ .remove = tcc_sata_remove, ++ .driver = { ++ .name = "tcc-sata", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++#ifdef CONFIG_SATA_TCC ++static stpwrinfo sata_pwrinfo = { PWR_STATUS_ON }; ++/********************************************************************** ++ * [The condition of SATA power control ] ++ * 1 The Main-Board must be greater than version 1.0 or equal. ++ * 2 And you need to fix the Main-Board. (refer to the schematic) ++ * ********************************************************************/ ++static int sata_pwr_ctl(void *h_private, int cmd, void *p_out) ++{ ++ int ret = -EINVAL; ++ PPMU p_pmu = (PPMU)tcc_p2v(HwPMU_BASE); ++ ++ switch (cmd) { ++ case PWR_CMD_OFF: ++ sata_printk("PWR_CMD_OFF command ==> [%d]\n", cmd); ++ if (sata_pwrinfo.status == PWR_STATUS_ON) { ++ platform_driver_unregister(&tcc_sata_driver); ++ tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, SATA_ON, OUTPUT, LOW, SET_DIRECTION | SET_VALUE); ++ BITSET(p_pmu->PWROFF, Hw4); // SATA popwer off ++ tca_ckc_setiobus(RB_SATAHCONTROLLER, 0); ++ sata_pwrinfo.status = PWR_STATUS_OFF; ++ ret = 0; ++ } else { ++ //printk("already SATA power is ON !!!\n"); ++ ret = 0; ++ } ++ break; ++ case PWR_CMD_ON: ++ sata_printk("PWR_CMD_ON command ==> [%d]\n", cmd); ++ if (sata_pwrinfo.status == PWR_STATUS_OFF) { ++ tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, SATA_ON, OUTPUT, HIGH, SET_DIRECTION | SET_VALUE); ++ if (platform_driver_register(&tcc_sata_driver) == 0) { ++ sata_pwrinfo.status = PWR_STATUS_ON; ++ ret = 0; ++ } else { ++ ret = -EIO; ++ tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, SATA_ON, OUTPUT, LOW, SET_DIRECTION | SET_VALUE); ++ BITSET(p_pmu->PWROFF, Hw4); // SATA popwer off ++ tca_ckc_setiobus(RB_SATAHCONTROLLER, 0); ++ printk("cannot register a SATA driver !!!\n"); ++ } ++ } else { ++ //printk("already SATA power is OFF !!!\n"); ++ ret = 0; ++ } ++ break; ++ case PWR_CMD_GETSTATUS: ++ sata_printk("PWR_CMD_GETSTATUS command ==> [%d]\n", cmd); ++ memcpy(p_out, &sata_pwrinfo, sizeof(stpwrinfo)); ++ ret = 0; ++ break; ++ /* ++ case PWR_CMD_MAX: ++ printk("PWR_CMD_MAX command ==> [%d]\n", cmd); ++ break; ++ */ ++ default: ++ printk("unknown pwr command !!! ==> [%d]\n", cmd); ++ break; ++ } ++ return ret; ++} ++#endif ++ ++static int __init tcc_sata_init(void) ++{ ++ tcc_pca953x_setup(PCA9539_U3_SLAVE_ADDR, PWR_GP4, OUTPUT, HIGH, SET_DIRECTION | SET_VALUE); ++ tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, SATA_ON, OUTPUT, HIGH, SET_DIRECTION | SET_VALUE); ++#ifdef CONFIG_SATA_TCC ++ sata_pwrinfo.status = PWR_STATUS_ON; ++ insert_pwm_node(DEVICE_SATA, sata_pwr_ctl, NULL); ++#endif ++ //return platform_driver_probe(&tcc_sata_driver, tcc_sata_probe); ++ return platform_driver_register(&tcc_sata_driver); ++} ++ ++static void __exit tcc_sata_exit(void) ++{ ++ PPMU p_pmu = (PPMU)tcc_p2v(HwPMU_BASE); ++#ifdef CONFIG_SATA_TCC ++ remove_pwm_node(DEVICE_SATA); ++#endif ++ platform_driver_unregister(&tcc_sata_driver); ++ ++ BITSET(p_pmu->PWROFF, Hw4); // SATA popwer off ++ tca_ckc_setiobus(RB_SATAHCONTROLLER, 0); ++ tcc_pca953x_setup(PCA9539_U2_SLAVE_ADDR, SATA_ON, OUTPUT, LOW, SET_DIRECTION | SET_VALUE); ++} ++ ++MODULE_AUTHOR("Telechips"); ++MODULE_DESCRIPTION("TCC SATA controller"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ ++module_init(tcc_sata_init); ++module_exit(tcc_sata_exit); ++ +diff --git a/drivers/ata/sata_snps.h b/drivers/ata/sata_snps.h +new file mode 100644 +index 0000000..ee35d1b +--- /dev/null ++++ b/drivers/ata/sata_snps.h +@@ -0,0 +1,157 @@ ++ ++#ifndef __SATA_SNPS_H__ ++#define __SATA_SNPS_H__ ++ ++/* ++ * HSATA Registers ++ */ ++#define TCC_SATA_BASE_ADDR 0xF0560000 ++#define HSATA_MEM_BASE TCC_SATA_BASE_ADDR ++ ++ ++#define HSATA_SCR0_REG 0x0024 ++#define HSATA_SCR0_SPD_GET(v) (((v) & 0x000000f0) >> 4) ++#define HSATA_SCR1_REG 0x0028 ++#define HSATA_SCR2_REG 0x002C ++#define HSATA_SCR3_REG 0x0030 ++#define HSATA_SCR4_REG 0x0034 ++ ++#define HSATA_SSTATUS_REG HSATA_SCR0_REG ++#define HSATA_SERROR_REG HSATA_SCR1_REG ++#define HSATA_SERROR_ERR_BITS 0x0000ffff ++#define HSATA_SCONTROL_REG HSATA_SCR2_REG ++#define HSATA_SACTIVE_REG HSATA_SCR3_REG ++#define HSATA_SNOTIFICATION_REG HSATA_SCR4_REG ++ ++#define HSATA_FPTAGR_REG 0x0064 ++#define HSATA_FPBOR_REG 0x0068 ++#define HSATA_FPTCR_REG 0x006C ++#define HSATA_DMACR_REG 0x0070 ++ ++#if 1 ++#define HSATA_DMACR_TXMODE_BIT 0x04 ++#define HSATA_DMACR_TX_EN 0x01 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_RX_EN 0x02 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_TXRX_EN 0x03 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_TXRX_CLEAR HSATA_DMACR_TXMODE_BIT ++#else ++#define HSATA_DMACR_TXMODE_BIT 0x00 ++#define HSATA_DMACR_TX_EN 0x01 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_RX_EN 0x02 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_TXRX_EN 0x03 | HSATA_DMACR_TXMODE_BIT ++#define HSATA_DMACR_TXRX_CLEAR HSATA_DMACR_TXMODE_BIT ++#endif ++ ++ ++ ++#define HSATA_DBTSR_REG 0x0074 ++#define HSATA_INTPR_REG 0x0078 ++//#define HSATA_INTPR_ERR_BIT 0x00000008 ++//#define HSATA_INTPR_FP_BIT 0x00000002 /* new DMA setup FIS arrived */ ++#define HSATA_INTMR_REG 0x007C ++ ++ ++ ++#define HSATA_INTMR_DMAT_BIT Hw0 ++#define HSATA_INTMR_NEWFP_BIT Hw1 ++#define HSATA_INTMR_PMABORT Hw2 ++#define HSATA_INTMR_ERRM_BIT Hw3 ++#define HSATA_INTMR_NEWBIST_BIT Hw4 ++#define HSATA_INTMR_PRIMERR_BIT Hw5 ++#define HSATA_INTMR_CMDABORT_BIT Hw6 ++#define HSATA_INTMR_CMDGOOD_BIT Hw7 ++ ++#define TCC_INTR_CHECK_BIT (HSATA_INTMR_DMAT_BIT \ ++ | HSATA_INTMR_NEWFP_BIT \ ++ | HSATA_INTMR_PMABORT \ ++ | HSATA_INTMR_ERRM_BIT \ ++ | HSATA_INTMR_NEWBIST_BIT \ ++ | HSATA_INTMR_PRIMERR_BIT \ ++ | HSATA_INTMR_CMDABORT_BIT \ ++ | HSATA_INTMR_CMDGOOD_BIT) ++ ++ ++ ++#define HSATA_ERRMR_REG 0x0080 ++#define HSATA_LLCR_REG 0x0084 ++#define HSATA_PHYCR_REG 0x0088 ++#define HSATA_PHYSR_REG 0x008C ++#define HSATA_RXBISTPD_REG 0x0090 ++#define HSATA_RXBISTD1_REG 0x0094 ++#define HSATA_RXBISTD2_REG 0x0098 ++#define HSATA_TXBISTPD_REG 0x009C ++#define HSATA_TXBISTD1_REG 0x00A0 ++#define HSATA_TXBISTD2_REG 0x00A4 ++#define HSATA_BISTCR_REG 0x00A8 ++#define HSATA_BISTFCTR_REG 0x00AC ++#define HSATA_BISTSR_REG 0x00B0 ++#define HSATA_BISTDECR_REG 0x00B4 ++ ++#define HSATA_TESTR_REG 0x00F4 ++#define HSATA_VERSONR_REG 0x00F8 ++#define HSATA_IDR_REG 0x00FC ++ ++#define HSATA_CMD_QWRITE 0x61 /* these don't seem to be defined in ata.h/libata.h */ ++#define HSATA_CMD_QREAD 0x60 ++ ++ ++#define TCC_DMADR_REG 0x0400 ++#define TCC_DMADR_REG_ADDR (HSATA_MEM_BASE + TCC_DMADR_REG) ++ ++ ++#define HSATA_ENABLE_INTERRUPTS(tcc_dev) \ ++ { \ ++ volatile u32 val32; \ ++ /* enable all err interrupts */ \ ++ /* COMRESET clears reg INTMR so .. see where this func is called */ \ ++ writel( 0xffffffff, tcc_dev->membase + HSATA_ERRMR_REG ); \ ++ val32 = readl( tcc_dev->membase + HSATA_INTMR_REG ); \ ++ writel( val32 | TCC_INTR_CHECK_BIT, \ ++ tcc_dev->membase + HSATA_INTMR_REG ); \ ++ val32 = readl( tcc_dev->membase + HSATA_INTMR_REG ); \ ++ jprintk("INTMR=0x%x", val32);\ ++ } ++ ++ ++#define TCC_QCMD_MAX 128 ++#define TCC_SG_LIST_MAX (TCC_QCMD_MAX * 8) ++ ++#define _TCC_DMA_TX_ 0x01 ++#define _TCC_DMA_RX_ 0x02 ++#define _TCC_DMA_END_ 0x04 ++#define _TCC_DMA_START_ 0x08 ++ ++ ++#define CDR7_ERR 0 ++ ++struct tcc_sg_list { ++ unsigned int dma_addr; ++ unsigned int length; ++ int flags; ++}; ++ ++struct tcc_dma_Q { ++ struct tcc_sg_list sg_list[TCC_SG_LIST_MAX]; ++ int top, bottom, pre; ++}; ++ ++struct tcc_sata_dev { ++ void __iomem *membase; ++ GDMANCTRL *dma_tx_reg, *dma_rx_reg; ++ int dma_tx_irq, dma_rx_irq; ++ ++ struct tcc_dma_Q dma_q; ++ int is_rx_complete, is_tx_complete; ++ int is_last_rx, is_last_tx; ++ wait_queue_head_t job_wait_q; ++ wait_queue_head_t tx_dma_wait_q; ++ wait_queue_head_t rx_dma_wait_q; ++ int is_continue; ++ struct task_struct *fetch_task; ++}; ++ ++ ++ ++ ++#endif /*__SATA_SNPS_H__*/ ++ +diff --git a/drivers/base/power/Makefile b/drivers/base/power/Makefile +index 911208b..205a2dd 100644 +--- a/drivers/base/power/Makefile ++++ b/drivers/base/power/Makefile +@@ -1,6 +1,7 @@ + obj-$(CONFIG_PM) += sysfs.o + obj-$(CONFIG_PM_SLEEP) += main.o + obj-$(CONFIG_PM_TRACE_RTC) += trace.o ++obj-$(CONFIG_DPM) += power-dpm.o + + ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG + ccflags-$(CONFIG_PM_VERBOSE) += -DDEBUG +diff --git a/drivers/base/power/power-dpm.c b/drivers/base/power/power-dpm.c +new file mode 100644 +index 0000000..b184b85 +--- /dev/null ++++ b/drivers/base/power/power-dpm.c +@@ -0,0 +1,464 @@ ++/* ++ * power-dpm.c -- Dynamic Power Management LDM power hooks ++ * ++ * (c) 2003 MontaVista Software, Inc. This file is licensed under the ++ * terms of the GNU General Public License version 2. This program is ++ * licensed "as is" without any warranty of any kind, whether express or ++ * implied. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "power.h" ++#include ++#include ++ ++/* ++ * power hotplug events ++ */ ++#if 0 ++#define dbg printk ++#else /* no debug */ ++#define dbg(x...) do {} while(0) ++#endif ++ ++#define BUFFER_SIZE 1024 /* should be enough memory for the env */ ++#define NUM_ENVP 32 /* number of env pointers */ ++static unsigned long sequence_num; ++static spinlock_t sequence_lock = SPIN_LOCK_UNLOCKED; ++ ++void power_event(char *eventstr) ++{ ++ char *argv [3]; ++ char **envp = NULL; ++ char *buffer = NULL; ++ char *scratch; ++ int i = 0; ++ int retval; ++ unsigned long seq; ++ ++ if (!uevent_helper[0]) ++ return; ++ ++ envp = kmalloc(NUM_ENVP * sizeof (char *), GFP_KERNEL); ++ if (!envp) ++ return; ++ memset (envp, 0x00, NUM_ENVP * sizeof (char *)); ++ ++ buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL); ++ if (!buffer) ++ goto exit; ++ ++ argv [0] = uevent_helper; ++ argv [1] = "power"; ++ argv [2] = 0; ++ ++ /* minimal command environment */ ++ envp [i++] = "HOME=/"; ++ envp [i++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin"; ++ ++ scratch = buffer; ++ ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "ACTION=event") + 1; ++ ++ spin_lock(&sequence_lock); ++ seq = sequence_num++; ++ spin_unlock(&sequence_lock); ++ ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "SEQNUM=%ld", seq) + 1; ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "EVENT=%s", eventstr) + 1; ++ ++ pr_debug ("%s: %s %s %s %s %s %s %s\n", __FUNCTION__, argv[0], argv[1], ++ envp[0], envp[1], envp[2], envp[3], envp[4]); ++ retval = call_usermodehelper (argv[0], argv, envp, 0); ++ if (retval) ++ pr_debug ("%s - call_usermodehelper returned %d\n", ++ __FUNCTION__, retval); ++ ++exit: ++ kfree(buffer); ++ kfree(envp); ++ return; ++} ++ ++void device_power_event(struct device * dev, char *eventstr) ++{ ++ char *argv [3]; ++ char **envp = NULL; ++ char *buffer = NULL; ++ char *scratch; ++ int i = 0; ++ int retval; ++ unsigned long seq; ++ ++ if (!uevent_helper[0]) ++ return; ++ ++ envp = kmalloc(NUM_ENVP * sizeof (char *), GFP_KERNEL); ++ if (!envp) ++ return; ++ memset (envp, 0x00, NUM_ENVP * sizeof (char *)); ++ ++ buffer = kmalloc(BUFFER_SIZE, GFP_KERNEL); ++ if (!buffer) ++ goto exit; ++ ++ argv [0] = uevent_helper; ++ argv [1] = "power"; ++ argv [2] = 0; ++ ++ /* minimal command environment */ ++ envp [i++] = "HOME=/"; ++ envp [i++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin"; ++ ++ scratch = buffer; ++ ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "ACTION=device-event") + 1; ++ ++ spin_lock(&sequence_lock); ++ seq = sequence_num++; ++ spin_unlock(&sequence_lock); ++ ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "SEQNUM=%ld", seq) + 1; ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "DEVICE=%s", dev->bus_id) + 1; ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "EVENT=%s", eventstr) + 1; ++ envp [i++] = scratch; ++ scratch += sprintf(scratch, "SUBSYSTEM=power") + 1; ++ ++ pr_debug ("%s: %s %s %s %s %s %s %s %s %s\n", __FUNCTION__, argv[0], argv[1], ++ envp[0], envp[1], envp[2], envp[3], envp[4], envp[5], ++ envp[6]); ++ retval = call_usermodehelper (argv[0], argv, envp, 0); ++ if (retval) ++ pr_debug ("%s - call_usermodehelper returned %d\n", ++ __FUNCTION__, retval); ++ ++exit: ++ kfree(buffer); ++ kfree(envp); ++ return; ++} ++ ++/* ++ * Device constraints ++ */ ++ ++#ifdef CONFIG_DPM ++LIST_HEAD(dpm_constraints); ++DECLARE_MUTEX(dpm_constraints_sem); ++ ++void assert_constraints(struct constraints *constraints) ++{ ++ if (! constraints || constraints->asserted) ++ return; ++ ++ down(&dpm_constraints_sem); ++ constraints->asserted = 1; ++ list_add_tail(&constraints->entry, &dpm_constraints); ++ up(&dpm_constraints_sem); ++ ++ /* DPM-PM-TODO: Check against DPM state. */ ++ ++} ++ ++ ++void deassert_constraints(struct constraints *constraints) ++{ ++ if (! constraints || ! constraints->asserted) ++ return; ++ ++ down(&dpm_constraints_sem); ++ constraints->asserted = 0; ++ list_del_init(&constraints->entry); ++ up(&dpm_constraints_sem); ++} ++ ++ ++EXPORT_SYMBOL(assert_constraints); ++EXPORT_SYMBOL(deassert_constraints); ++ ++static ssize_t ++constraints_show(struct device * dev, struct device_attribute *attr, ++ char * buf) ++{ ++ int i, cnt = 0; ++ ++ if (dev->constraints) { ++ for (i = 0; i < dev->constraints->count; i++) { ++ cnt += sprintf(buf + cnt,"%s: min=%d max=%d\n", ++ dpm_param_names[dev->constraints->param[i].id], ++ dev->constraints->param[i].min, ++ dev->constraints->param[i].max); ++ } ++ ++ cnt += sprintf(buf + cnt,"asserted=%s violations=%d\n", ++ dev->constraints->asserted ? ++ "yes" : "no", dev->constraints->violations); ++ } else { ++ cnt += sprintf(buf + cnt,"none\n"); ++ } ++ ++ return cnt; ++} ++ ++static ssize_t ++constraints_store(struct device * dev, struct device_attribute *attr, ++ const char * buf, size_t count) ++{ ++ int num_args, paramid, min, max; ++ int cidx; ++ const char *cp, *paramname; ++ int paramnamelen; ++ int provisional = 0; ++ int ret = 0; ++ ++ if (!dev->constraints) { ++ if (! (dev->constraints = kmalloc(sizeof(struct constraints), ++ GFP_KERNEL))) ++ return -EINVAL; ++ ++ memset(dev->constraints, 0, ++ sizeof(struct constraints)); ++ provisional = 1; ++ } ++ ++ cp = buf; ++ while((cp - buf < count) && *cp && (*cp == ' ')) ++ cp++; ++ ++ paramname = cp; ++ ++ while((cp - buf < count) && *cp && (*cp != ' ')) ++ cp++; ++ ++ paramnamelen = cp - paramname; ++ num_args = sscanf(cp, "%d %d", &min, &max); ++ ++ if (num_args != 2) { ++ printk("DPM: Need 2 integer parameters for constraint min/max.\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ for (paramid = 0; paramid < DPM_PP_NBR; paramid++) { ++ if (strncmp(paramname, dpm_param_names[paramid], paramnamelen) == 0) ++ break; ++ } ++ ++ if (paramid >= DPM_PP_NBR) { ++ printk("DPM: Unknown power parameter name in device constraints\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ for (cidx = 0; cidx < dev->constraints->count; cidx++) ++ /* ++ * If the new range overlaps an existing range, ++ * modify the existing one. ++ */ ++ ++ if ((dev->constraints->param[cidx].id == paramid) && ++ ((max == -1) || ++ (max >= dev->constraints->param[cidx].min)) && ++ ((min == -1) || ++ (min <= dev->constraints->param[cidx].max))) ++ break; ++ ++ if (cidx >= DPM_CONSTRAINT_PARAMS_MAX) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ /* Error if max is less than min */ ++ if (max < min) { ++ printk("DPM: Max value of the constraint should not be less than min\n"); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ dev->constraints->param[cidx].id = paramid; ++ dev->constraints->param[cidx].max = max; ++ dev->constraints->param[cidx].min = min; ++ ++ if (cidx == dev->constraints->count) ++ dev->constraints->count++; ++ ++ /* New constraints should start off with same state as power ++ state */ ++ if (provisional && (dev->power.power_state.event == PM_EVENT_ON)) ++ assert_constraints(dev->constraints); ++ ++out: ++ ++ if (provisional && (ret < 0)) { ++ kfree(dev->constraints); ++ dev->constraints = NULL; ++ } ++ ++ return ret < 0 ? ret : count; ++} ++ ++DEVICE_ATTR(constraints,S_IWUSR | S_IRUGO, ++ constraints_show,constraints_store); ++ ++#else /* CONFIG_DPM */ ++void assert_constraints(struct constraints *constraints) ++{ ++} ++ ++void deassert_constraints(struct constraints *constraints) ++{ ++} ++#endif /* CONFIG_DPM */ ++ ++#ifdef CONFIG_DPM ++ ++#if 0 ++/* ++ * Driver scale callbacks ++ */ ++ ++static struct notifier_block *dpm_scale_notifier_list[SCALE_MAX]; ++static DECLARE_MUTEX(dpm_scale_sem); ++ ++/* This function may be called by the platform frequency scaler before ++ or after a frequency change, in order to let drivers adjust any ++ clocks or calculations for the new frequency. */ ++ ++void dpm_driver_scale(int level, struct dpm_opt *newop) ++{ ++ atomic_notifier_call_chain(&dpm_scale_notifier_list[level], level, newop); ++ up(&dpm_scale_sem); ++} ++ ++void dpm_register_scale(struct notifier_block *nb, int level) ++{ ++ down(&dpm_scale_sem); ++ atomic_notifier_chain_register(&dpm_scale_notifier_list[level], nb); ++ up(&dpm_scale_sem); ++} ++ ++void dpm_unregister_scale(struct notifier_block *nb, int level) ++{ ++ down(&dpm_scale_sem); ++ atomic_notifier_chain_unregister(&dpm_scale_notifier_list[level], nb); ++ up(&dpm_scale_sem); ++} ++#endif ++ ++ ++int dpm_constraint_rejects = 0; ++ ++//EXPORT_SYMBOL(dpm_default_check_constraint); ++int ++dpm_default_check_constraint(struct constraint_param *param, ++ struct dpm_opt *opt) ++{ ++ return (opt->pp[param->id] == -1) || ++ ((param->min == -1 || opt->pp[param->id] >= param->min) && ++ (param->max == -1 || opt->pp[param->id] <= param->max)); ++} ++ ++static int ++dpm_check_a_constraint(struct constraints *constraints, struct dpm_opt *opt) ++{ ++ int i; ++ int failid = -1; ++ int ppconstraint[DPM_PP_NBR]; ++ ++ ++ if (! constraints || !constraints->asserted) ++ return 1; ++ ++ /* ++ * ppconstraint[ppid] == 0 means power param has not been checked ++ * for a constraint ++ * == -1 means power param has matched a constraint ++ * > 0 means constraint #n-1 mismatched ++ * ++ * failid == pp id of (a) failed constraint ++ */ ++ ++ memset(ppconstraint, 0, sizeof(ppconstraint)); ++ ++ for (i = 0; i < constraints->count; i++) { ++ struct constraint_param *param = &constraints->param[i]; ++ ++ if (! dpm_md_check_constraint(param, opt)) { ++ if (ppconstraint[param->id] == 0) { ++ failid = param->id; ++ ppconstraint[failid] = i+1; ++ } ++ } else ++ ppconstraint[param->id] = -1; ++ } ++ ++ if ((failid >= 0) && (ppconstraint[failid] > 0)) { ++#ifdef CONFIG_DPM_TRACE ++ struct constraint_param *param = ++ &constraints->param[ppconstraint[failid]-1]; ++ ++ dpm_trace(DPM_TRACE_CONSTRAINT_ASSERTED, ++ param->id, param->min, param->max, ++ opt); ++#endif ++ return 0; ++ } ++ ++ return 1; ++} ++ ++int dpm_check_constraints(struct dpm_opt *opt) ++{ ++ struct list_head * entry; ++ int valid = 1; ++ ++ list_for_each(entry,&dpm_constraints) { ++ struct constraints *constraints = ++ list_entry(entry, struct constraints, entry); ++ if (!dpm_check_a_constraint(constraints, opt)) { ++ constraints->violations++; ++ dpm_constraint_rejects++; ++ valid = 0; ++ } ++ } ++ ++ return valid; ++} ++ ++int dpm_show_opconstraints(struct dpm_opt *opt, char * buf) ++{ ++#ifdef CONFIG_PM ++ struct list_head * entry; ++ int len = 0; ++ ++ list_for_each_prev(entry,&dpm_list) { ++ struct device * dev = to_device(entry); ++ ++ if (!dpm_check_a_constraint(dev->constraints, opt)) { ++ len += sprintf(buf + len, "%s/%s\n", dev->bus->name, ++ dev->bus_id); ++ } ++ } ++ ++ return len; ++#else /* CONFIG_PM */ ++ return 0; ++#endif /* CONFIG_PM */ ++} ++ ++#endif /* CONFIG_DPM */ +diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig +index 0344a8a..6aa4cd5 100644 +--- a/drivers/block/Kconfig ++++ b/drivers/block/Kconfig +@@ -446,4 +446,6 @@ config BLK_DEV_HD + + If unsure, say N. + ++source "drivers/block/tcc/Kconfig" ++ + endif # BLK_DEV +diff --git a/drivers/block/Makefile b/drivers/block/Makefile +index 204332b..98b42f4 100644 +--- a/drivers/block/Makefile ++++ b/drivers/block/Makefile +@@ -32,3 +32,6 @@ obj-$(CONFIG_BLK_DEV_UB) += ub.o + obj-$(CONFIG_BLK_DEV_HD) += hd.o + + obj-$(CONFIG_XEN_BLKDEV_FRONTEND) += xen-blkfront.o ++ ++obj-$(CONFIG_TCC_NAND_V6) += tcc/ ++obj-$(CONFIG_TCC_NAND_V7) += tcc/ +diff --git a/drivers/block/tcc/Kconfig b/drivers/block/tcc/Kconfig +new file mode 100644 +index 0000000..6c3b059 +--- /dev/null ++++ b/drivers/block/tcc/Kconfig +@@ -0,0 +1,13 @@ ++choice ++ prompt "TCC nand flash support" ++ depends on ARCH_TCC ++ default TCC_NAND_V7 ++ ---help--- ++ ++config TCC_NAND_V6 ++ tristate "TCC nand flash driver V6" ++ ++config TCC_NAND_V7 ++ tristate "TCC nand flash driver V7" ++ ++endchoice +diff --git a/drivers/block/tcc/Makefile b/drivers/block/tcc/Makefile +new file mode 100644 +index 0000000..b3c0814 +--- /dev/null ++++ b/drivers/block/tcc/Makefile +@@ -0,0 +1,33 @@ ++DEF_NAND := -D_LINUX_ ++DEF_NAND += -DUSE_V_ADDRESS ++DEF_NAND += -DNAND_INCLUDE ++DEF_NAND += -DNAND_BOOT_INCLUDE ++DEF_NAND += -D_NAND_DEVICE_CONFIG_ ++DEF_NAND += -DINTERNAL_HIDDEN_STORAGE_INCLUDE ++DEF_NAND += -DECC_TEST ++ ++ifeq ($(CONFIG_ARCH_TCC8900), y) ++DEF_NAND += -DTCC89XX -DTCC89X -DTCC8900 ++TCC_ARCH = TCC8900 ++endif ++ ++ifneq ($(CONFIG_TCC_NAND_V6),) ++NAND_VER := V6005 ++obj-$(CONFIG_TCC_NAND_V6) := $(TCC_ARCH)_nand.o ++$(TCC_ARCH)_nand-objs := nand_drv.o nand_io_v6.o ++endif ++ ++ifneq ($(CONFIG_TCC_NAND_V7),) ++NAND_VER := V7014 ++DEF_NAND += -DNAND_BOOT_REV ++obj-$(CONFIG_TCC_NAND_V7) := $(TCC_ARCH)_nand.o ++$(TCC_ARCH)_nand-objs := nand_drv_v7.o nand_io_v7.o ++endif ++ ++NAND_INC = drivers/block/tcc/inc ++EXTRA_CFLAGS += $(DEF_NAND) -I$(NAND_INC) -I$(NAND_INC)/fwdn -I$(NAND_INC)/tnftl ++ ++LIBS = libtnftl/libtnftl_$(NAND_VER)_$(TCC_ARCH).o ++ ++$(TCC_ARCH)_nand-objs += kernel_nand_drv.o nand_crc.o nand_buffer.o fwupgrade.o init_ddr2.o init_mddr.o $(LIBS) ++ +diff --git a/drivers/block/tcc/fwupgrade.c b/drivers/block/tcc/fwupgrade.c +new file mode 100644 +index 0000000..e2f6c64 +--- /dev/null ++++ b/drivers/block/tcc/fwupgrade.c +@@ -0,0 +1,598 @@ ++/**************************************************************************** ++ * FileName : Fwupgrade.c ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++#if defined(_LINUX_) || defined(_WINCE_) ++#include ++#include "IO_TCCXXX.h" ++#include "TC_File.h" ++#include "browse.h" ++//#include "fwdn_protocol.h" ++#include "fwupgrade.h" ++//#include "usb.h" ++#include "FSAPP.h" ++#include "nand_drv.h" ++#endif ++ ++#if defined (NKUSE) ++#include "windows.h" ++#include "stdlib.h" ++#elif defined (__KERNEL__) ++#include ++#endif ++ ++//unsigned int gMAX_ROMSIZE; //twkwon: Initialize???? ++ ++#if 0 ++const unsigned int CRC32_TABLE[256] = { ++ 0x00000000, 0x90910101, 0x91210201, 0x01B00300, ++ 0x92410401, 0x02D00500, 0x03600600, 0x93F10701, ++ 0x94810801, 0x04100900, 0x05A00A00, 0x95310B01, ++ 0x06C00C00, 0x96510D01, 0x97E10E01, 0x07700F00, ++ 0x99011001, 0x09901100, 0x08201200, 0x98B11301, ++ 0x0B401400, 0x9BD11501, 0x9A611601, 0x0AF01700, ++ 0x0D801800, 0x9D111901, 0x9CA11A01, 0x0C301B00, ++ 0x9FC11C01, 0x0F501D00, 0x0EE01E00, 0x9E711F01, ++ 0x82012001, 0x12902100, 0x13202200, 0x83B12301, ++ 0x10402400, 0x80D12501, 0x81612601, 0x11F02700, ++ 0x16802800, 0x86112901, 0x87A12A01, 0x17302B00, ++ 0x84C12C01, 0x14502D00, 0x15E02E00, 0x85712F01, ++ 0x1B003000, 0x8B913101, 0x8A213201, 0x1AB03300, ++ 0x89413401, 0x19D03500, 0x18603600, 0x88F13701, ++ 0x8F813801, 0x1F103900, 0x1EA03A00, 0x8E313B01, ++ 0x1DC03C00, 0x8D513D01, 0x8CE13E01, 0x1C703F00, ++ 0xB4014001, 0x24904100, 0x25204200, 0xB5B14301, ++ 0x26404400, 0xB6D14501, 0xB7614601, 0x27F04700, ++ 0x20804800, 0xB0114901, 0xB1A14A01, 0x21304B00, ++ 0xB2C14C01, 0x22504D00, 0x23E04E00, 0xB3714F01, ++ 0x2D005000, 0xBD915101, 0xBC215201, 0x2CB05300, ++ 0xBF415401, 0x2FD05500, 0x2E605600, 0xBEF15701, ++ 0xB9815801, 0x29105900, 0x28A05A00, 0xB8315B01, ++ 0x2BC05C00, 0xBB515D01, 0xBAE15E01, 0x2A705F00, ++ 0x36006000, 0xA6916101, 0xA7216201, 0x37B06300, ++ 0xA4416401, 0x34D06500, 0x35606600, 0xA5F16701, ++ 0xA2816801, 0x32106900, 0x33A06A00, 0xA3316B01, ++ 0x30C06C00, 0xA0516D01, 0xA1E16E01, 0x31706F00, ++ 0xAF017001, 0x3F907100, 0x3E207200, 0xAEB17301, ++ 0x3D407400, 0xADD17501, 0xAC617601, 0x3CF07700, ++ 0x3B807800, 0xAB117901, 0xAAA17A01, 0x3A307B00, ++ 0xA9C17C01, 0x39507D00, 0x38E07E00, 0xA8717F01, ++ 0xD8018001, 0x48908100, 0x49208200, 0xD9B18301, ++ 0x4A408400, 0xDAD18501, 0xDB618601, 0x4BF08700, ++ 0x4C808800, 0xDC118901, 0xDDA18A01, 0x4D308B00, ++ 0xDEC18C01, 0x4E508D00, 0x4FE08E00, 0xDF718F01, ++ 0x41009000, 0xD1919101, 0xD0219201, 0x40B09300, ++ 0xD3419401, 0x43D09500, 0x42609600, 0xD2F19701, ++ 0xD5819801, 0x45109900, 0x44A09A00, 0xD4319B01, ++ 0x47C09C00, 0xD7519D01, 0xD6E19E01, 0x46709F00, ++ 0x5A00A000, 0xCA91A101, 0xCB21A201, 0x5BB0A300, ++ 0xC841A401, 0x58D0A500, 0x5960A600, 0xC9F1A701, ++ 0xCE81A801, 0x5E10A900, 0x5FA0AA00, 0xCF31AB01, ++ 0x5CC0AC00, 0xCC51AD01, 0xCDE1AE01, 0x5D70AF00, ++ 0xC301B001, 0x5390B100, 0x5220B200, 0xC2B1B301, ++ 0x5140B400, 0xC1D1B501, 0xC061B601, 0x50F0B700, ++ 0x5780B800, 0xC711B901, 0xC6A1BA01, 0x5630BB00, ++ 0xC5C1BC01, 0x5550BD00, 0x54E0BE00, 0xC471BF01, ++ 0x6C00C000, 0xFC91C101, 0xFD21C201, 0x6DB0C300, ++ 0xFE41C401, 0x6ED0C500, 0x6F60C600, 0xFFF1C701, ++ 0xF881C801, 0x6810C900, 0x69A0CA00, 0xF931CB01, ++ 0x6AC0CC00, 0xFA51CD01, 0xFBE1CE01, 0x6B70CF00, ++ 0xF501D001, 0x6590D100, 0x6420D200, 0xF4B1D301, ++ 0x6740D400, 0xF7D1D501, 0xF661D601, 0x66F0D700, ++ 0x6180D800, 0xF111D901, 0xF0A1DA01, 0x6030DB00, ++ 0xF3C1DC01, 0x6350DD00, 0x62E0DE00, 0xF271DF01, ++ 0xEE01E001, 0x7E90E100, 0x7F20E200, 0xEFB1E301, ++ 0x7C40E400, 0xECD1E501, 0xED61E601, 0x7DF0E700, ++ 0x7A80E800, 0xEA11E901, 0xEBA1EA01, 0x7B30EB00, ++ 0xE8C1EC01, 0x7850ED00, 0x79E0EE00, 0xE971EF01, ++ 0x7700F000, 0xE791F101, 0xE621F201, 0x76B0F300, ++ 0xE541F401, 0x75D0F500, 0x7460F600, 0xE4F1F701, ++ 0xE381F801, 0x7310F900, 0x72A0FA00, 0xE231FB01, ++ 0x71C0FC00, 0xE151FD01, 0xE0E1FE01, 0x7070FF00 ++}; ++#else ++extern const unsigned CRC32_TABLE[]; ++#endif ++ ++typedef void ROM_Upgrade(unsigned char *, unsigned int, unsigned int, unsigned char *); ++ROM_Upgrade *pROMUpgradeFunc; ++ ++extern int TCDB_SaveDBHeader(unsigned char ucAssociation, int iPartID); ++extern void ResetSystem(void); ++ ++ ++#define MAXBUFFSIZE 16*1024 // ++ ++extern int gSDUpgrading; ++ ++unsigned char gBuffer[MAXBUFFSIZE]; ++ ++#if defined(_WINCE_) || defined(_LINUX_) ++/////////////////////////////////////////////////////////////////////////////////// ++// ++// Function : FWUG_GetTempBuffer() ++// ++// Description : Get temporary buffer to store data ++// ++/////////////////////////////////////////////////////////////////////////////////// ++char *FWUG_GetTempBuffer(unsigned int *uiBufSize) ++{ ++#if defined (NKUSE) || defined(__KERNEL__) ++ *uiBufSize = MAXBUFFSIZE; ++ return gBuffer; ++#else ++ if (gSDUpgrading == 1) ++ { ++ *uiBufSize = MAXBUFFSIZE; ++ return gBuffer; ++ } ++ else ++ { ++ *uiBufSize = FSAPP_GetMaxCopySize(); ++ return FSAPP_GetFileBuffer(); ++ } ++#endif ++} ++ ++/////////////////////////////////////////////////////////////////////////////////// ++// ++// Function : FWUG_CheckBattery ++// ++// Description : Check Battery ++// ++/////////////////////////////////////////////////////////////////////////////////// ++int FWUG_CheckBattery(void) ++{ ++#ifdef BATTERY_INCLUDE ++ unsigned int batteryValue = 0; ++ unsigned int Emergencycount = 0; ++ int i; ++ ++ for(i=0; i<20; i++) ++ { ++ batteryValue = BATTERY_GetBatteryVoltage(); ++ if(batteryValue < 110) ++ Emergencycount++; ++ ++ if(Emergencycount > 10) ++ { ++ SerialWriteString("BAT too low!!"); ++ CAPP_ReturnSetClock(); // 20041207 ++ return 0; ++ } ++ ++ TC_TimeDly(10); ++ } ++#endif ++ return 1; ++} ++ ++#if !defined(__KERNEL__) ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int FWUG_CheckROMFileCRC ++* ++* DESCRIPTION : ++* INPUT: ++* ++* OUTPUT: ++* ++* REMARK : ++**************************************************************************/ ++unsigned int FWUG_CheckROMFileCRC(int iFilehandle, unsigned char *buf, unsigned int uiBufSize) ++{ ++ unsigned int i; ++ unsigned int uiROMFileSize; ++ unsigned int uiVerifyCRC; ++ unsigned int uiTempCRC; ++ unsigned int uiCRCSize; ++ unsigned int uiCnt; ++ unsigned int uiMode; ++ ++ uiROMFileSize = 0x00; ++ uiVerifyCRC = 0x00; ++ uiTempCRC = 0x00; ++ ++ memset( buf, 0x00, uiBufSize ); ++ TC_Read( iFilehandle, buf, 32 ); //header size ++ ++ uiTempCRC |= ( buf[27] & 0x000000FF) << 24; ++ uiTempCRC |= ( buf[26] & 0x000000FF) << 16; ++ uiTempCRC |= ( buf[25] & 0x000000FF) << 8; ++ uiTempCRC |= ( buf[24] & 0x000000FF) ; ++ ++ uiROMFileSize |= ( buf[31] & 0x000000FF) << 24; ++ uiROMFileSize |= ( buf[30] & 0x000000FF) << 16; ++ uiROMFileSize |= ( buf[29] & 0x000000FF) << 8; ++ uiROMFileSize |= ( buf[28] & 0x000000FF) ; ++ ++ TC_Seek( iFilehandle, 0, TC_SEEK_SET ); ++ ++ if (uiBufSize < uiROMFileSize ) ++ { ++ uiCnt = ( uiROMFileSize + ( uiBufSize - 1)) / uiBufSize; ++ for ( i = 0; i < uiCnt ; i++ ) ++ { ++ if ( i == (uiCnt -1 )) ++ uiCRCSize = ( uiROMFileSize - uiBufSize * (uiCnt - 1)); ++ else ++ uiCRCSize = uiBufSize; ++ ++ TC_Read( iFilehandle, buf, uiCRCSize ); ++ ++ if ( i == 0 ) ++ uiMode = 1; ++ else ++ uiMode = 2; ++ ++ uiVerifyCRC = CalCRC_ROMFile(buf, uiCRCSize, uiVerifyCRC, uiMode); ++ ++ } ++ } ++ else ++ { ++ TC_Read( iFilehandle, buf, uiROMFileSize ); ++ ++ uiMode = 1; ++ uiVerifyCRC = CalCRC_ROMFile( buf, uiROMFileSize, uiVerifyCRC, uiMode); ++ } ++ ++ TC_Seek( iFilehandle, 0, TC_SEEK_SET ); ++ ++ if ( uiTempCRC != uiVerifyCRC ) ++ return 1; ++ else ++ return SUCCESS; ++} ++#endif ++ ++/////////////////////////////////////////////////////////////////////////////////// ++// ++// Function : FWUG_MainFunc ++// ++// Description : Main function to upgrade Firmware ++// ++/////////////////////////////////////////////////////////////////////////////////// ++#if !defined(__KERNEL__) ++int FWUG_MainFunc(int hFile, int iFileSize) ++#else ++/* if Linux Kernel */ ++int FWUG_MainFunc(char *rom_buf, unsigned int uiROMFileSize) ++#endif ++{ ++ unsigned int iRev; ++ unsigned int uiBufSize; ++ unsigned char *buf; ++ ++ unsigned int i; ++ unsigned int uRemainSize, uReadSize; ++ unsigned int dwBlockOffSet, dwPageOffSet; ++ unsigned int nStBlockOffSet, nStPageOffSet; ++ unsigned char GMC_Num; ++ unsigned char FlagofNewSizeBigger; ++ unsigned int nSecureMode = DISABLE; ++ ++#if !defined(__KERNEL__) ++ unsigned int uiROMFileSize; ++ unsigned int iFilehandle; ++ #if defined(NKUSE) ++ iFilehandle = TC_Open((char*)hFile, NULL, NULL, NULL); ++#else ++ iFilehandle = hFile; ++ #endif ++#else ++ unsigned int rom_offset; ++#endif ++ ++ //=============================================================== ++ // Check condition for FW Upgrade ++ //=============================================================== ++ if((buf = FWUG_GetTempBuffer(&uiBufSize))==0) ++ { ++ return ERR_FWUG_NOT_EXISTMEMORY; ++ } ++ ++#if !defined(__KERNEL__) ++/* if Linux Kernel, already crc checked in tccbox */ ++ iRev = FWUG_CheckROMFileCRC( iFilehandle, buf, uiBufSize ); ++ if ( iRev != SUCCESS ) ++ { ++ return -1; ++ } ++#endif ++ ++ if(!FWUG_CheckBattery()) ++ { ++ return ERR_FWUG_FAIL_BATCHECK; ++ } ++ ++ //=============================================================== ++ // UPGRADE - NANDFLASH ++ //=============================================================== ++ ++ /* Setting Intial Parameters */ ++#if !defined(__KERNEL__) ++ uiROMFileSize = TC_Length(iFilehandle); ++#endif ++ ++ #ifdef TNFTL_V7_INCLUDE ++ FWUG_NAND_SetEnableNandBootOnlyMode( ENABLE ); ++ FWUG_NAND_SetNBAreaEndPBAdd(TNFTL_MAX_BLOCK_NUM_OF_NBAREA); // Physical Block Num ++ #endif ++ ++ #if defined(FWUG_V2_INCLUDE) ++ nSecureMode = FWUG_NAND_GetFlagOfUseSecureMode(); ++ #endif ++ ++ /* PreProcess before write code */ ++ if (( iRev = FWUG_NAND_PreProcess( uiROMFileSize, &FlagofNewSizeBigger )) != SUCCESS ) ++ { ++ goto FWUG_FAIL; ++ } ++ ++ ++ /* Write CODE Data */ ++ for ( i = 0 ; i < 2; ++i ) ++ { ++ uRemainSize = uiROMFileSize; ++#if !defined(__KERNEL__) ++ TC_Seek( iFilehandle, 0, TC_SEEK_SET ); ++#else ++ rom_offset = 0; ++#endif ++ ++ if ( FlagofNewSizeBigger == TRUE ) ++ GMC_Num = ( i == 0 ) ? FIRST : SECOND; ++ else ++ GMC_Num = ( i == 0 ) ? SECOND : FIRST; ++ ++ #if defined(FWUG_V1_INCLUDE) ++ if (( iRev = FWUG_NAND_WriteCodePreProcess( GMC_Num, uiROMFileSize, &nStBlockOffSet, &nStPageOffSet )) != SUCCESS ) ++ #elif defined(FWUG_V2_INCLUDE) ++ if (( iRev = FWUG_NAND_WriteCodePreProcess( GMC_Num, uiROMFileSize, &nStBlockOffSet, &nStPageOffSet, nSecureMode )) != SUCCESS ) ++ #endif ++ { ++ goto FWUG_FAIL; ++ } ++ ++ while ((int)uRemainSize > 0) ++ { ++ uReadSize = ( uRemainSize >= uiBufSize ) ? uiBufSize : uRemainSize; ++#if !defined(__KERNEL__) ++ uReadSize = TC_Read( iFilehandle, buf, uReadSize ); ++#else ++ memcpy(buf, rom_buf + rom_offset, uReadSize); ++ rom_offset += uReadSize; ++#endif ++ ++#ifdef TNFTL_V7_INCLUDE ++ if (( iRev = FWUG_NAND_WriteCodeNAND( GMC_Num, nStBlockOffSet, nStPageOffSet, buf, uReadSize, &dwBlockOffSet, &dwPageOffSet, nSecureMode )) != SUCCESS ) ++#else ++ if (( iRev = FWUG_NAND_WriteCodeNAND( nStBlockOffSet, nStPageOffSet, buf, uReadSize, &dwBlockOffSet, &dwPageOffSet, nSecureMode )) != SUCCESS ) ++#endif ++ { ++ goto FWUG_FAIL; ++ } ++ nStBlockOffSet = dwBlockOffSet; ++ nStPageOffSet = dwPageOffSet; ++ uRemainSize -= uReadSize; ++ } ++ ++ if (( iRev = FWUG_NAND_WriteCodePostProcess( GMC_Num, nStBlockOffSet, nStPageOffSet )) != SUCCESS ) ++ { ++ goto FWUG_FAIL; ++ } ++ } ++ ++ /* PostProcess after write code */ ++ if (( iRev = FWUG_NAND_PostProcess((void*)0, TRUE, nSecureMode )) != SUCCESS ) ++ { ++ goto FWUG_FAIL; ++ } ++ ++ //=============================================================== ++ // CLOSE ++ //=============================================================== ++#if !defined(__KERNEL__) ++#if defined(NKUSE) ++ TC_Close(iFilehandle); ++#endif ++#endif ++ ++ if (TC_ISERR(iRev)) ++ { ++ return -1; ++ } ++ ++ return SUCCESS; ++ ++FWUG_FAIL: ++ return iRev; ++} ++ ++#endif ++ ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int FWUG_CalcCrc(unsigned int *base, unsigned int length, unsigned int *crctable); ++* ++* DESCRIPTION : ++* INPUT: ++* base = ++* crctable = ++* length = ++* ++* OUTPUT: int - Return Type ++* = ++* REMARK : ++**************************************************************************/ ++unsigned int FWUG_CalcCrc(unsigned int *base, unsigned int length, const unsigned int *crctable) ++{ ++ unsigned int crcout = 0; ++ unsigned int cnt, i, code, tmp; ++ ++ for(cnt=0; cnt>8)^crctable[tmp&0xFF]; ++ code = code >> 8; ++ } ++ } ++ return crcout; ++} ++ ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int FWUG_CalcCrc8(unsigned char *base, unsigned int length, unsigned int *crctable); ++* ++* DESCRIPTION : ++* INPUT: ++* base = ++* crctable = ++* length = ++* ++* OUTPUT: int - Return Type ++* = ++* REMARK : ++**************************************************************************/ ++unsigned int FWUG_CalcCrc8(unsigned char *base, unsigned int length, const unsigned int *crctable) ++{ ++ unsigned int crcout = 0; ++ unsigned int cnt; ++ unsigned char code, tmp; ++ ++ for(cnt=0; cnt>8)^crctable[tmp&0xFF]; ++ } ++ return crcout; ++} ++ ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int FWUG_CalcCrcI(unsigned uCRCIN, unsigned *base, unsigned int length, unsigned int *crctable); ++* ++* DESCRIPTION : ++* INPUT: ++* base = ++* crctable = ++* length = ++* ++* OUTPUT: int - Return Type ++* = ++* REMARK : ++**************************************************************************/ ++unsigned int FWUG_CalcCrcI(unsigned uCRCIN, unsigned *base, unsigned int length, const unsigned int *crctable) ++{ ++ unsigned int crcout = uCRCIN; ++ unsigned int cnt, i, code, tmp; ++ ++ for(cnt=0; cnt>8)^crctable[tmp&0xFF]; ++ code = code >> 8; ++ } ++ } ++ return crcout; ++} ++ ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int FWUG_CalcCrc8I(unsigned uCRCIN, unsigned char *base, unsigned int length, unsigned int *crctable); ++* ++* DESCRIPTION : ++* INPUT: ++* base = ++* crctable = ++* length = ++* ++* OUTPUT: int - Return Type ++* = ++* REMARK : ++**************************************************************************/ ++unsigned int FWUG_CalcCrc8I(unsigned uCRCIN, unsigned char *base, unsigned int length, const unsigned int *crctable) ++{ ++ unsigned int crcout = uCRCIN; ++ unsigned int cnt; ++ unsigned char code, tmp; ++ ++ for(cnt=0; cnt>8)^crctable[tmp&0xFF]; ++ } ++ return crcout; ++} ++ ++/************************************************************************** ++* FUNCTION NAME : ++* unsigned int CalCRC_ROMFile(unsigned int *pBuffer,unsigned int size,unsigned int crcout, unsigned int mode); ++* ++* DESCRIPTION : ++* INPUT: ++* crcout = ++* mode = ++* pBuffer = ++* size = ++* ++* OUTPUT: int - Return Type ++* = ++* REMARK : ++**************************************************************************/ ++unsigned int CalCRC_ROMFile(unsigned int *pBuffer,unsigned int size,unsigned int crcout, unsigned int mode) ++{ ++ ++ unsigned int cnt, i, code, tmp; ++ unsigned int CrcRegion; ++ ++ ++ CrcRegion = (size>>2); ++ ++ for(cnt=0; cnt>8)^CRC32_TABLE[tmp&0xFF]; ++ code = code >> 8; ++ } ++ } ++ ++ return crcout; ++} ++ ++/************* end of file *************************************************************/ +diff --git a/drivers/block/tcc/inc/common.h b/drivers/block/tcc/inc/common.h +new file mode 100644 +index 0000000..d15bfd8 +--- /dev/null ++++ b/drivers/block/tcc/inc/common.h +@@ -0,0 +1,23 @@ ++#ifndef __COMMON_H__ ++#define __COMMON_H__ ++ ++#include ++ ++#if defined(TCC8900) ++#include ++#include ++#else ++#error "Not defined Chips..." ++#endif ++ ++#include ++ ++/* ++ * Macro ++ */ ++#define read_reg(a) (*(volatile unsigned long *)a) ++#define write_reg(v, a) (*(volatile unsigned long *)a = v) ++ ++ ++#endif /* __COMMON_H__ */ ++ +diff --git a/drivers/block/tcc/inc/config.h b/drivers/block/tcc/inc/config.h +new file mode 100644 +index 0000000..fd48ceb +--- /dev/null ++++ b/drivers/block/tcc/inc/config.h +@@ -0,0 +1,56 @@ ++/*************************************************************************************** ++* FileName : config.h ++* Description : NAND Configuration File ++**************************************************************************************** ++* ++* TCC Board Support Package ++* Copyright (c) Telechips, Inc. ++* ALL RIGHTS RESERVED ++* ++****************************************************************************************/ ++ ++ ++#ifndef __CONFIG_H__ ++#define __CONFIG_H__ ++ ++#include ++#include ++ ++/*************************************************************************************** ++* TCC8900 specific config ++****************************************************************************************/ ++#if defined(TCC8900) ++ ++#define TCC_ARCH "TCC8900" ++ ++#if defined(_BOARD_VERSION_TCC8900_WINCE_LINUX_DEMO_V01_) ++#define TCC_BOARD "TCC8900_WINCE_LINUX_DEMO_V0.1" ++#endif ++ ++/*************************************************************************************** ++* ERROR: Undefined target ++****************************************************************************************/ ++#else ++ #error "Undefined Target" ++#endif ++ ++ ++/*************************************************************************************** ++* ETC. ++****************************************************************************************/ ++/*--------------------------------- ++ * DRIVER TYPE ++ *--------------------------------- ++ */ ++#define KERNEL_DRIVER /* kernel module driver */ ++ ++ ++/*--------------------------------- ++ * Default ++ *--------------------------------- ++ */ ++#define PRINTF printk ++ ++ ++#endif /* __CONFIG_H__ */ ++/************* end of file *************************************************************/ +diff --git a/drivers/block/tcc/inc/def_tcc.h b/drivers/block/tcc/inc/def_tcc.h +new file mode 100644 +index 0000000..b22123f +--- /dev/null ++++ b/drivers/block/tcc/inc/def_tcc.h +@@ -0,0 +1,6 @@ ++#ifdef NAND_BOOT_REV ++#define NAND_VER "V7014" ++#else ++#define NAND_VER "V6005" ++#endif ++ +diff --git a/drivers/block/tcc/inc/fwdn/Disk.h b/drivers/block/tcc/inc/fwdn/Disk.h +new file mode 100644 +index 0000000..5bdff47 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/Disk.h +@@ -0,0 +1,314 @@ ++/**************************************************************************** ++ * FileName : Disk.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++#ifndef __DISK_H__ ++#define __DISK_H__ ++ ++/******************************************************************************* ++ * DISK Interface Error Code Macro ++ ******************************************************************************/ ++#define _ERR(x) (0x80000000 | (x)) ++#define ENOTSUPPORT _ERR(0x10) // Function does not support ++#define EINITFAIL _ERR(0x11) // Device Initialization Failed ++ ++/***************************************************************************** ++ * disk device type enumeration value ++ *****************************************************************************/ ++typedef enum ++{ ++ DISK_DEVICE_HDD=0, ++ DISK_DEVICE_NAND, ++ DISK_DEVICE_NAND_HD, ++ DISK_DEVICE_UHP, ++ DISK_DEVICE_TRIFLASH, ++ DISK_DEVICE_MMC, ++ DISK_DEVICE_MS, ++ DISK_DEVICE_TRIFLASH_HD, ++ #ifdef EXTERNAL_HIDDEN_STORAGE_INCLUDE ++ DISK_DEVICE_MMC_HD, ++ #endif ++ MAX_DEVICE_NUM ++}DISK_DEVICE; ++ ++#define DISK_DEVICE_INTERNAL 1 ++ ++/***************************************************************************** ++ * disk device property and sub-property enumeration value ++ *****************************************************************************/ ++typedef enum ++{ ++ DISK_DEVICE_UNLOCK=0, ++ DISK_DEVICE_LOCK ++}DISK_LOCK_FLAG; ++ ++typedef enum ++{ ++ DISK_STATE_NOTMOUNTED, ++ DISK_STATE_MOUNTSUCCEED, ++ DISK_STATE_MOUNTERR ++}DISK_MOUNT_STATE; ++ ++typedef enum ++{ ++ DISK_STATE_FREE, ++ DISK_STATE_BUSY ++}DISK_BUSY_STATE; ++ ++typedef enum ++{ ++ DISK_STATE_INIT, ++ DISK_STATE_POWERON, ++ DISK_STATE_POWEROFF, ++ DISK_STATE_STANDBY, ++ DISK_STATE_IDLE, ++ DISK_STATE_SLEEP, ++ DISK_STATE_RESET ++}DISK_POWER_STATE; ++ ++typedef enum ++{ ++ DISK_MSC_DRV_NOT_SUPPORT, ++ DISK_MSC_DRV_SUPPORT ++}DISK_MSC_DRV_STATE; ++ ++typedef enum ++{ ++ DISK_MOUNT_TYPE_INTERNAL, ++ DISK_MOUNT_TYPE_EXTERNAL, ++ DISK_MOUNT_TYPE_MAXIUM ++}DISK_MOUNT_TYPE_STATE; ++ ++typedef struct ++{ ++ const char *Name; ++ DISK_LOCK_FLAG LockFlag; ++ DISK_DEVICE DiskType; ++ DISK_MOUNT_STATE MountState; ++ DISK_BUSY_STATE BusyState; ++ DISK_MSC_DRV_STATE MSCDrvSupport; ++ DISK_MOUNT_TYPE_STATE DrvMountType; ++ int PartitionIndex; ++}DISK_PROPERTY; ++ ++/******************************************************************************* ++ * DISK Interface Function Type Definitions ++ ******************************************************************************/ ++typedef int (*tDeviceRwFunctions)(int, unsigned long, unsigned short, void *); ++ ++typedef int (*tDeviceWriteMultiStartFunctions)(unsigned long, unsigned long); ++typedef int (*tDeviceWriteMultiFunctions)(int, unsigned long, unsigned short, void *); ++typedef int (*tDeviceWriteMultiStopFunctions)(void); ++ ++typedef int (*tDeviceReadMultiStartFunctions)(unsigned long, unsigned long); ++typedef int (*tDeviceReadMultiFunctions)(int, unsigned long, unsigned short, void *); ++typedef int (*tDeviceReadMultiStopFunctions)(void); ++ ++typedef unsigned long (*tDeviceHiddenRWFunctions)(unsigned long , unsigned short, unsigned char *); ++typedef int (*tDeviceHiddenClearPageFunctions)(unsigned long , unsigned long); ++ ++typedef int (*tDeviceIoctlFunctions)(int, void *); ++ ++/******************************************************************************* ++ * DISK Interface Function Definitions ++ ******************************************************************************/ ++typedef struct DeviceDriverStruct ++{ ++ DISK_PROPERTY Property; ++ tDeviceRwFunctions ReadSector; ++ tDeviceRwFunctions WriteSector; ++ tDeviceReadMultiStartFunctions ReadMultiStart; ++ tDeviceReadMultiFunctions ReadMultiSector; ++ tDeviceReadMultiStopFunctions ReadMultiStop; ++ tDeviceWriteMultiStartFunctions WriteMultiStart; ++ tDeviceWriteMultiFunctions WriteMultiSector; ++ tDeviceWriteMultiStopFunctions WriteMultiStop; ++ tDeviceHiddenRWFunctions HDReadSector; ++ tDeviceHiddenRWFunctions HDWriteSector; ++ tDeviceHiddenClearPageFunctions HDClearSector; ++ tDeviceIoctlFunctions Ioctl; ++}tDeviceDriver; ++ ++/******************************************************************************* ++ * DISK Ioctl Function List ( Enumeration Value ) ++ * ++ * DEV_INITIALIZE ++ * Initialize Variable , Register and Hardware ++ * ++ * DEV_GET_DISKINFO ++ * Get the environmant variables like head, cylinder, sector ... ++ * ++ * DEV_FORMAT_DISK ++ * low level format command ( if it necessary ) ++ * ++ * DEV_ERASE_INIT ++ * prepare erasing command ++ * ++ * DEV_ERASE_BLOCK ++ * erase sector command ++ * ++ * DEV_ERASE_CLOSE ++ * finish erasing command ++ * ++ * DEV_WRITEBACK_ON_IDLE ++ * flush data cache command while system is in idle state ++ ******************************************************************************/ ++ ++#define YES 1 ++#define NO 0 ++ ++#define TC_LOWLEVEL_YES 1 ++#define TC_LOWLEVEL_NO 0 ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_GET_DISKINFO Function Parameter structure ++ ******************************************************************************/ ++typedef struct ioctl_diskinfo_t ++{ ++ unsigned short head; ++ unsigned short cylinder; ++ unsigned short sector; ++ unsigned short sector_size; ++ unsigned int Total_sectors; ++}ioctl_diskinfo_t; ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_ERASE_INIT Function Parameter structure ++ ******************************************************************************/ ++typedef struct ioctl_diskeraseinit_t ++{ ++ unsigned short sector_per_cluster; ++ unsigned long data_start_sector; ++}ioctl_diskeraseinit_t; ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_ERASE_BLOCK Function Parameter structure ++ ******************************************************************************/ ++typedef struct ioctl_diskerase_t ++{ ++ unsigned long current_cluster; ++ unsigned long content_fat; ++}ioctl_diskerase_t; ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_HIDDEN_CLEAR_PAGE Function Parameter structure ++ ******************************************************************************/ ++// typedef struct ioctl_diskhdclear_t { ++// unsigned long start_page; ++// unsigned long end_page; ++// }ioctl_diskhdclear_t; ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_HIDDEN_READ/WRITE_PAGE Function Parameter structure ++ ******************************************************************************/ ++typedef struct ioctl_diskhdread4_t ++{ ++ unsigned long start_page; ++ unsigned long page_offset; ++ unsigned long read_size; ++ unsigned char *buff; ++}ioctl_diskhdread4_t; ++ ++/******************************************************************************* ++ * DISK Ioctl DEV_BOOTCODE_READ/WRITE_PAGE Function Parameter structure ++ ******************************************************************************/ ++typedef struct ioctl_diskrwpage_t ++{ ++ unsigned long start_page; ++ unsigned long rw_size; ++ unsigned char *buff; ++}ioctl_diskrwpage_t; ++ ++ ++ ++ ++/******************************************************************************* ++ * DISK Interface Function Definitions ++ ******************************************************************************/ ++ ++int DISK_FindDisk(int drv_type); ++int DISK_ReadSector(int drv_type, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++int DISK_WriteSector(int drv_type, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++ ++int DISK_ReadMultiStart(int drv_type, int lba_addr, int size); ++int DISK_ReadMultiSector(int drv_type, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++int DISK_ReadMultiStop(int drv_type); ++ ++int DISK_WriteMultiStart(int drv_type, int lba_addr, int size); ++int DISK_WriteMultiSector(int drv_type, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++int DISK_WriteMultiStop(int drv_type); ++ ++int DISK_HDReadSector(unsigned int drv_type, unsigned long page_addr, unsigned short count, unsigned char *buff); ++int DISK_HDWriteSector(unsigned int drv_type, unsigned long page_addr, unsigned short count, unsigned char *buff); ++int DISK_HDClearSector(unsigned int drv_type, unsigned long start_page_addr, unsigned long end_page_addr); ++ ++int DISK_Ioctl(unsigned int drv_type, int function, void *param); ++int DISK_GetTotalDiskCount(void); ++int DISK_GetDiskType(int index); ++int DISK_GetDiskTypeByPartID(int PartID ); ++int DISK_GetSupportMSCDrive(int index ); ++int DISK_GetDiskMountType(int index ); ++int DISK_SetState(DISK_DEVICE disk, DISK_MOUNT_STATE state); ++int DISK_GetState(DISK_DEVICE disk); ++int DISK_SetDiskPartitionIndex(DISK_DEVICE disk, int index); ++int DISK_GetDiskPartitionIndex(DISK_DEVICE disk); ++int DISK_SetBusyState(DISK_DEVICE disk, DISK_BUSY_STATE busyFlag); ++int DISK_GetBusyState(DISK_DEVICE disk); ++ ++extern unsigned char *DISK_GetDeviceName(DISK_DEVICE disk); ++extern unsigned int DISK_GetDeviceStatus(int iDeviceNum,int iUSBMode,int iExtDevice); ++ ++ ++/******************************************************************************* ++ * DISK List Array pre-definition ( in disk.c) ++ ******************************************************************************/ ++extern tDeviceDriver DiskList[]; ++extern const unsigned int DISK_DefaultDriveType; ++ ++typedef enum ++{ ++ /* Do Not Change below functions*/ ++ DEV_INITIALIZE = 0, ++ DEV_MOUNT, ++ DEV_GET_DISKINFO, ++ DEV_FORMAT_DISK, ++ DEV_ERASE_INIT, ++ DEV_ERASE_BLOCK, ++ DEV_ERASE_CLOSE, ++ DEV_WRITEBACK_ON_IDLE, ++ /* You can add new function from here */ ++ DEV_HIDDEN_READ_PAGE_4, ++ DEV_GET_MAXMULTISECTOR, ++ DEV_SET_POWER, ++ DEV_GET_POWER, ++ DEV_BOOTCODE_READ_PAGE, ++ DEV_BOOTCODE_WRITE_PAGE, ++ DEV_SERIAL_PROCESS, ++ DEV_GET_MAX_SECTOR_PER_BLOCK, ++ DEV_GET_INSERTED, ++ DEV_GET_INITED, ++ DEV_GET_WRITE_PROTECT, ++ DEV_SET_REMOVED, ++ DEV_GET_PREV_STATUS, ++ DEV_GET_PLAYABLE_STATUS, ++ DEV_STOP_TRANSFER, ++ DEV_TELL_DATASTARTSECTOR, ++ DEV_CHECK_CRC_NANDBOOT_IMAGE_ROM, ++ DEV_GET_HIDDEN_SIZE, ++ DEV_GET_SUPPORT_FAT_FORMAT, /* [1429] */ ++ DEV_FORCE_FLUSH_CACHE_DATA, ++ DEV_SET_ALIGEN_CACHE, ++ DEV_SET_MULTISECTOR, // twkwon: Han DR ++ DEV_SET_HIDDEN_SIZE, ++ DEV_END_OF_FUNCTION ++}IOCTL_FUNCTIONS; ++ ++#endif // __DISK_H__ ++/* end of file */ ++ +diff --git a/drivers/block/tcc/inc/fwdn/FSAPP.h b/drivers/block/tcc/inc/fwdn/FSAPP.h +new file mode 100644 +index 0000000..285c387 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/FSAPP.h +@@ -0,0 +1,130 @@ ++/*****************************************************************************/ ++// File System refer for K-FileSystem ++// FSAPP.C ++// Copyright 2003 Telechips, Inc. ++// ++// 2004. 06. 4 ++/*****************************************************************************/ ++#ifndef __FSAPP_H__ ++#define __FSAPP_H__ ++ ++#if defined(_LINUX_) ++#include ++#include ++#elif defined(_WINCE_) ++#include "file.h" ++#include "Disk.h" ++#endif ++ ++#ifndef CLEAR ++#define CLEAR 0 ++#endif ++#ifndef DIRTY ++#define DIRTY 1 ++#endif ++ ++//============================================================================= ++//* ++//* ++//* [ EXTERNAL DEFINATION ] ++//* ++//* ++//============================================================================= ++#define _NOTMUSICFILE -1 ++// DEFINITION FOR MAXIMUM HANDLE OF FILES OR DIRECTORIES ++#define MAX_HANDLE 5 ++#define MAX_FD MAX_HANDLE ++#define MAX_DIR 2 ++// DEFAULT FILE FORMAT ++#define DEFAULT_ROOT_ENTRY_COUNT 512 // normal number of the root entry count ++#define HIDDEN_SIZE 31 // NAND, UFD etc... But NOT HDD ++ ++#define ENTRY_SIZE 32 // 1 entry size [byte] ++#define ENTRY_CHUNK 11 ++#define ENTRY_BUFFER_SIZE (ENTRY_CHUNK * ENTRY_SIZE) ++ ++#define FSAPP_MAX_PART_NUMBER 10 //driveInfo[FSAPP_MAX_PART_NUMBER] / physicalDrvType[FSAPP_MAX_PART_NUMBER] ++ ++//============================================================================= ++//* ++//* ++//* [ EXTERNAL VARIABLE DEFINE ] ++//* ++//* ++//============================================================================= ++ ++extern int totalHdlr; ++extern int gDiskIdleTime; ++ ++extern FDstruc fd[MAX_FD]; ++extern HANDLERstruc fhandler[MAX_HANDLE]; ++extern FDIRENTstruc fdir[MAX_DIR]; ++extern unsigned char physicalDrvType[FSAPP_MAX_PART_NUMBER]; ++ ++//============================================================================= ++//* ++//* ++//* [ FUCTIONS DEFINE ] ++//* ++//* ++//============================================================================= ++extern void FAT_InitDriveInfo( void ); ++extern int FAT_InitFS( void ); ++extern void FAT_InitVariable( void ); ++extern int FAT_MountDrive(int drvTypeID, unsigned int lun); ++extern int FAT_UnmountDrive(int drvTypeID); ++extern void FAT_InitializeForFlexibility(unsigned char valueOfHandle, unsigned char *entryBufferPointer, HANDLERstruc *fhandlerStruc, ++ unsigned char valueOfFd, FDstruc *fdStruc, unsigned char valueOfDir, FDIRENTstruc *fdirStruc); ++ ++extern int FSAPP_InitDiskDevice( int DeviceID ); ++extern int FSAPP_GetMaxCopySize( void ); ++extern unsigned char *FSAPP_GetFileBuffer( void ); ++extern void FSAPP_InitializeFS( void ); ++extern unsigned long FSAPP_GetDiskSector( unsigned char drvType, DISKINFOstruc *disk ); ++ ++extern int FSAPP_Get_part_id(unsigned char drvType, unsigned char mount); ++ ++extern int FSAPP_disk_RWsector(int drvTypeID, unsigned char drv_num,unsigned long LBA_addr, unsigned short nSector, void *buff, unsigned char RWflag); ++extern int FSAPP_diskIoctl_DEV_GET_MAXMULTISECTOR(int drvTypeID, unsigned short *nSector); ++extern int FSAPP_diskIoctl_DEV_ERASE_INIT(int drvTypeID, unsigned char secPerClus, unsigned long dataStartSec); ++extern int FSAPP_diskIoctl_DEV_ERASE_BLOCK(int drvTypeID, unsigned long currCluster, unsigned long contentFAT); ++extern int FSAPP_diskIoctl_DEV_ERASE_CLOSE(int drvTypeID); ++extern int FSAPP_diskIoctl_DEV_SET_MULTISECTOR(int drvTypeID, unsigned short *max_multi_sector); ++extern int FSAPP_diskIoctl_DEV_TELL_DATASTARTSECTOR(int drvTypeID, unsigned long int data_start_sector); ++extern int FSAPP_diskIoctl_DEV_GET_MAX_SECTOR_PER_BLOCK(int drvTypeID, unsigned short int *SpB); ++extern int FSAPP_diskIoctl_DEV_STOP_TRANSFER(int drvTypeID); ++ ++extern int FSAPP_DISK_WriteMultiStart(int drvTypeID, int lba_addr, int size); ++extern int FSAPP_DISK_WriteMultiSector(int drvTypeID, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++extern int FSAPP_DISK_ReadMultiStart(int drvTypeID, int lba_addr, int size); ++extern int FSAPP_DISK_ReadMultiSector(int drvTypeID, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++extern int FSAPP_DISK_ReadMultiStop(int drvTypeID); ++extern int FSAPP_DISK_WriteMultiStop(int drvTypeID); ++ ++extern int FSAPP_physicalStorage_HDD(int drvTypeID); ++ ++extern int FSAPP_ReadSector_Common(int drvTypeID, int lun, unsigned long lba_addr, unsigned short nSector, void *buff); ++extern int FSAPP_WriteSector_Common(int drvTypeID, int lun, unsigned long lba_addr, unsigned short nSector, void *buff, unsigned char FormatFlag); ++ ++extern int FSAPP_getUsedClus_PS(int drvTypeID, int partID, unsigned FAT1_PhySector, unsigned short nSector); ++extern int FSAPP_cleanFATcache_PS(int drvTypeID, int partID, unsigned long FAT2_PhySector, unsigned long FAT_Sector, unsigned char *sbuffer); ++extern int FSAPP_changeFATcache_PS(int drvTypeID, int partID, unsigned long FAT1_PhySector, unsigned int Offset_Sector, unsigned char *fatBuff); ++extern int FSAPP_fatWriteClus_PS(int drvTypeID, unsigned short nCount, unsigned long sector_addr, unsigned short nSector, unsigned short multi_sector, int multi_byte, unsigned char *temp_buff); ++extern unsigned int FSAPP_FormatClear_PS(int drvTypeID, unsigned long sectorPerFAT, unsigned int nSector, unsigned char *pBuff, void *SecBuff); ++ ++extern unsigned int FSAPP_FormatDrive( DISK_DEVICE diskDevice, unsigned int *multiPartition_SectorSize, unsigned int *validFAT); ++ ++extern int FSAPP_FormatRootEntry_PS(int drvTypeID, int halfEntryNum, unsigned nSector, unsigned char writeVolume, void *pBuff, unsigned char *BS_VolLab); ++ ++extern unsigned int FSAPP_decide_MakeMBR(int drvTypeID, unsigned char SecPerClus, unsigned int *numOfSecPR, unsigned int *validFAT, void *pBuff, struct _DISK_INFO *disk); ++extern unsigned char FSAPP_decide_DrvNum(int drvTypeID); ++extern int Initialize_FileSystem(DISK_DEVICE mDeviceNum, int partID); ++ ++ ++ ++extern unsigned char *FSAPP_SetVolumeLabel(unsigned int partID, void* VolLab); ++extern unsigned char *FSAPP_GetVolumeLabel(unsigned int partID); ++ ++extern unsigned int FSAPP_PartitionWrite(DISK_DEVICE diskDevice, unsigned int partitionID, unsigned int lba, void *pBuff, unsigned short nSector); ++extern unsigned int FSAPP_PartitionRead(DISK_DEVICE diskDevice, unsigned int partitionID, unsigned int lba, void *pBuff, unsigned short nSector); ++#endif +diff --git a/drivers/block/tcc/inc/fwdn/KFSutils.h b/drivers/block/tcc/inc/fwdn/KFSutils.h +new file mode 100644 +index 0000000..9dd3f77 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/KFSutils.h +@@ -0,0 +1,23 @@ ++ ++/**************************************************************************** ++ * FileName : KFSutils.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++ ++extern char upperChar(char ch); ++extern char lowerChar(char ch); ++extern int printNum(char *sNum, int value); ++extern int str_cmp(void *sA, void *sB); ++extern int str_cmp16(void *sA, void *sB); ++extern int str_len(void *pStr); ++extern int mem_cmp(void *sA, void *sB, int len); ++extern void* mem_cpy(void *pDes, void *pSrc, long size); ++extern void* mem_cpyw(void *pDes, void *pSrc, long size); ++extern void* mem_set(void *pDes, unsigned char value, long size); +diff --git a/drivers/block/tcc/inc/fwdn/TC_File.h b/drivers/block/tcc/inc/fwdn/TC_File.h +new file mode 100644 +index 0000000..9c4d7b2 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/TC_File.h +@@ -0,0 +1,164 @@ ++/**************************************************************************** ++ * FileName : TC_File.h ++ * Description : File System Abstraction Layer ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++#ifndef __TC_File_H__ ++#define __TC_File_H__ ++ ++#if defined(_LINUX_) ++ #include ++ #include ++#elif defined(_WINCE_) ++ #include "file.h" ++ #include "Disk.h" ++#endif ++ ++#ifndef _UINT8_ ++ #define _UINT8_ ++ typedef unsigned char UINT8; ++#endif ++ ++typedef int TC_STAT; ++typedef unsigned long long TC_U64; ++typedef unsigned int TC_U32; ++typedef unsigned short TC_U16; ++typedef unsigned char TC_U8; ++ ++typedef signed long long TC_S64; ++typedef signed int TC_S32; ++typedef signed short TC_S16; ++typedef signed char TC_S8; ++ ++typedef char * TC_STR8; ++#ifndef _CHAR_ ++ #define _CHAR_ ++ typedef char CHAR; ++#endif ++ ++typedef struct { ++ unsigned char second; ++ unsigned char minute; ++ unsigned char hour; ++ unsigned char day; ++ unsigned char date; ++ unsigned char month; ++ unsigned short year; ++} TC_DATETIME; ++ ++ ++typedef unsigned long _dev_t; ++typedef unsigned short _ino_t; ++typedef long _off_t; ++typedef unsigned long _mode_t; ++typedef unsigned long _time_t; ++ ++typedef struct// _stat ++{ ++ _dev_t st_dev; /* device */ ++ _ino_t st_ino; /* inode */ ++ _mode_t st_mode; /* protection */ ++ short st_nlink; /* number of hard links */ ++ short st_uid; /* user ID of owner */ ++ short st_gid; /* group ID of owner */ ++ _dev_t st_rdev; /* device type (if inode device) */ ++ _off_t st_size; /* total size, in bytes */ ++ _time_t st_atime; /* time of last access */ ++ _time_t st_mtime; /* time of last modification */ ++ _time_t st_ctime; /* time of last change */ ++} stat; ++ ++ #define TC_O_RDONLY 0x0000 ++ #define TC_O_WRONLY 0x0001 ++ #define TC_O_RDWR 0x0002 ++ #define TC_O_APPEND 0x0008 ++ #define TC_O_CREAT 0x0100 ++ #define TC_O_TRUNC 0x0200 ++ ++/* File creation permissions for open */ ++/* Note: OCTAL */ ++ #define TC_A_READ 0000400 /* Write permitted */ ++ #define TC_A_WRITE 0000200 /* Read permitted. (Always true anyway)*/ ++ #define TC_SUCCESS 0 ++ typedef TC_S32 TC_DRIVE; ++ typedef int TC_DIR; ++ typedef int TC_PDIR; ++ typedef FDIRENTstruc TC_DS; ++ typedef DIRENTstruc TC_DENTRY; ++ ++ #define TC_ISDIRSP(X) (0) ++ ++ #define TC_StartDrive 1/* DISK_DEVICE_INTERNAL */ ++ #define TC_DriveNum uNDRIVES ++ ++ #define TC_INTERNAL_DRIVE(X) (0) ++ ++ #define TC_UFD_DEVICE DISK_DEVICE_UHP ++ #define TC_HDD_DEVICE DISK_DEVICE_HDD ++ #define TC_NAND_DEVICE DISK_DEVICE_NAND ++ #define TC_TRIFLASH_DEVICE DISK_DEVICE_TRIFLASH ++ #define TC_SDMMC_DEVICE DISK_DEVICE_MMC ++ #define TC_ISINTDRIVE(X) ((X) == TC_StartDrive) ++ ++ #define TC_Set_Drive(X, Y) ((X) = (Y)) ++ #define TC_Inc_Drive(X, Y) ((X) += (Y)) ++ #define TC_Get_DriveNo(X) ((X)) ++ ++ #define TC_Get_Attribute(X) ((X)->type) ++ #define TC_Get_Cluster(X, Y) ((X)->startCluster) ++ #define TC_Get_Size(X, Y) ((X)->fileSize) ++ #define TC_Get_LFN(X) ((X)->lFileName) ++ #define TC_Get_SFName(X) ((X)->sFileName) ++ #define TC_Get_SFext(X) ((X)->sFileName+9) ++ ++ #define TC_A_RDONLY FILE_READ_ONLY ++ #define TC_A_HIDDEN FILE_HIDDEN ++ #define TC_A_SYSTEM FILE_SYSTEM ++ #define TC_A_VOLUME FILE_VOLUME_ID ++ #define TC_A_DIRENT FILE_DIRECTORY ++ #define TC_A_ARCHIVE FILE_ARCHIVE ++ #define TC_A_NORMAL FILE_NORMAL ++ ++ #define TC_MAX_PATH 255 ++ #define TC_MAX_DIR MAX_DIR ++ ++#define TC_ISERR(X) ((signed)(X) < 0) ++#define TC_ISOK(X) ((signed)(X) >= 0) ++ ++#define TC_ISHERR(X) ((signed)(X) < 0) ++#define TC_ISHOK(X) ((signed)(X) >= 0) ++ ++#define TC_ISRWERR(X) ((signed)(X) <= 0) ++ ++#define TC_SEEK_SET 0 ++#define TC_SEEK_CUR 1 ++#define TC_SEEK_END 2 ++ ++#define TC_LOWLEVEL_YES 1 ++#define TC_LOWLEVEL_NO 0 ++ ++#define UNDEFINED_HANDLE (-1) ++ ++TC_STAT TC_Open(char *name, TC_U32 uFlag, TC_U32 uMode, TC_U32 uDirNum); ++TC_S32 TC_Read(TC_S32 iHandle, void *pBuff, TC_S32 iCount); ++TC_S32 TC_Write(TC_S32 iHandle, void *pBuff, TC_S32 iCount); ++TC_S32 TC_Seek(TC_S32 iHandle, TC_S32 iOffset, TC_S32 iOrigin); ++TC_STAT TC_Close(TC_S32 iHandle); ++TC_S32 TC_Length(TC_S32 iHandle); ++TC_STAT TC_DeleteIndex(TC_U32 uIndex, TC_U32 uDirNum); ++TC_STAT TC_Make_Dir(TC_STR8 pName, TC_U32 uDirNum); ++TC_STAT TC_SyncDrives(TC_S32 uDriveNo, TC_U32 uNum); ++TC_U32 TC_Get_FileIndex(TC_S32 iHandle, TC_U32 uDirNum); ++TC_STAT TC_Set_Current_Dir(TC_S32 iPartID, TC_STR8 pPath, TC_U32 uDirNum); ++TC_STAT TC_CloseNGetFileProperty(TC_S32 iHandle, unsigned int *iFileProperty); ++ ++//ENHANCED_DELETION_SPEED ++ ++ #endif ++/* end of file */ +diff --git a/drivers/block/tcc/inc/fwdn/browse.h b/drivers/block/tcc/inc/fwdn/browse.h +new file mode 100644 +index 0000000..f87724f +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/browse.h +@@ -0,0 +1,455 @@ ++/******************************************************************************* ++*** ++*** TELECHIPS. ++*** ++*** ++*** ++*******************************************************************************/ ++#ifndef _BROWSE_H_ ++#define _BROWSE_H_ ++ ++#if defined(_LINUX_) ++#include ++#endif ++ ++//#ifndef _MAIN_H_ ++// #include "main.h" ++//#endif ++ ++#define ROOTDIR 0 ++#define _MUSICFILE 1 ++#define _NOTMUSICFILE -1 ++ ++#define WITHNULL 0 ++ ++#define _DIR 0 ++#define _FILE 1 ++//#define _DONOTUSE 2 ++ ++#ifndef KILO ++#define KILO 1024 ++#endif ++ ++// Error Message ++enum { ++ BRWS_NO_ERROR = 0, ++ BRWS_ERROR_NODIR, ++ BRWS_ERROR_NOFILE, ++ BRWS_ERROR_CANTGO, ++ BRWS_ERROR_UNDEF_ATTR, ++ BRWS_ERROR_INVALID_INDEX, ++ BRWS_ERROR_FAILE_DELETE, ++ BRWS_ERROR_UHP_BUSY, ++ BRWS_UNDEF_ERROR ++}; ++ ++enum{ ++BRWS_EXT_MP3, ++#ifdef MTX_INCLUDE ++BRWS_EXT_MTX, ++#endif ++#ifdef WMA_INCLUDE ++BRWS_EXT_WMA, ++#ifdef TRUSTED_FLASH_INCLUDE ++BRWS_EXT_SMA, ++#endif ++#endif ++#ifdef MP2_INCLUDE ++BRWS_EXT_MP2, ++#endif ++#ifdef OGG_INCLUDE ++BRWS_EXT_OGG, ++#endif ++#ifdef EAACPlus_INCLUDE ++BRWS_EXT_EAACPlus_AAC, ++BRWS_EXT_EAACPlus_M4A, ++BRWS_EXT_EAACPlus_MP4, ++BRWS_EXT_EAACPlus_ADIF, ++BRWS_EXT_EAACPlus_ADTS, ++BRWS_EXT_EAACPlus_3GP, ++#endif ++#ifdef WAV_INCLUDE ++BRWS_EXT_WAV, ++#endif ++#ifdef MP4_INCLUDE ++BRWS_EXT_MP4, ++#endif ++#ifdef WMV_INCLUDE ++BRWS_EXT_WMV, ++#ifdef TRUSTED_FLASH_INCLUDE ++BRWS_EXT_SMV, ++#endif ++#endif ++#if defined(JPG_INCLUDE) || defined (MULTI_CODEC_INCLUDE) ++BRWS_EXT_JPG, ++#endif ++#if defined(PNG_INCLUDE) ++BRWS_EXT_PNG, ++#endif ++#if defined(BMP_INCLUDE) ++BRWS_EXT_BMP, ++#endif ++#if defined(GIF_INCLUDE) ++BRWS_EXT_GIF, ++#endif ++#ifdef AUDIBLE_INCLUDE ++BRWS_EXT_AA, ++#endif ++#if defined (MULTI_CODEC_INCLUDE) ++BRWS_EXT_TXT, ++#endif ++#ifdef M3U_INCLUDE ++BRWS_EXT_M3U, ++#endif ++#if defined(MTP_CUSTOM_IMAGE_INCLUDE) ++BRWS_EXT_FIL, ++#endif ++#ifdef RHAPSODY_INCLUDE ++BRWS_EXT_XML, ++#endif ++BRWS_EXT_MAX ++}; ++ ++/* Start - skott 's code */ ++#define MAX_PLAYLIST_NUM 1*KILO ++ ++// 2M Buffer config ++#ifdef BRWS_STR_NAND_INCLUDE ++#define BRWS_NAME_BUFFER_SIZE (4096) ++#elif defined(MTP_INCLUDE) ++#define BRWS_NAME_BUFFER_SIZE (256) ++#else ++#define BRWS_NAME_BUFFER_SIZE (KILO*KILO*2) ++#endif ++#define MAX_INDEX_LIST_NUM 1*KILO ++ ++#ifdef MTP_INCLUDE ++#define MAX_FOLDER_NUM MTPDB_DEVICE_FOLDER_MAX ++#define MAX_MUSICFILE_NUM MTPDB_DEVICE_FILE_MAX ++#else ++#define MAX_FOLDER_NUM 2*KILO ++#define MAX_MUSICFILE_NUM 1*KILO ++#endif ++ ++ ++typedef enum ++{ ++ DB_NOT_USED =0, ++ DB_USED ++#ifdef MTP_INCLUDE ++ ,DB_BE_DELETED ++#endif ++}DB_USAGE_TYPE; ++ ++ ++ ++/* Status Define ++================================================================== ++|B7 | B6 | B5 | B4 | B3 / B2 | B1 | B0 | ++================================================================== ++|reserved | Reference | Reference | AlbumJacket | Protection | Protection Status | ++| | Flag | member flag| Exist Flag | Status | | ++================================================================== ++*/ ++typedef struct{ ++ unsigned int ucMotherIndex; ++ unsigned int ucFileIndex; ++ unsigned char ucAttr; ++ unsigned char ucPartition_ID; ++ unsigned char ucStatus; ++ unsigned char ucCodec; ++#ifndef MTP_INCLUDE ++ unsigned int ucShortFileName; ++ unsigned int ucLongFileName; ++ unsigned char fLfn; ++ unsigned char dummy[3]; ++#else ++ unsigned long ulCluster; //start cluster in FAT ++ unsigned short usCRC16FileName; //verify filename ++//MTPDB2DB--> ++ unsigned short usPacketOffset; ++//<--MTPDB2DB ++#ifdef VIDEOART_INCLUDE ++ unsigned int AlbumArtIndex; ++#else ++ unsigned short AlbumArtIndex; ++#endif ++ unsigned short ObjectFormat; ++ ++#ifdef MEDIA_RESUME_INCLUDE ++ unsigned short usLastTimeSec; ++#endif ++ ++#endif ++}_FILE_LIST_TYPE,*pFILE_LIST_TYPE; ++ ++typedef struct{ ++ unsigned short ucFileCount; // Total File Number ++ unsigned short ucFolderCount; // Total Folder Number ++ unsigned int ucMotherIndex; // Mother Index Number ++ unsigned int ucFolderIndex; // The order of folder in entry field like 1st, 2nd .. ++ unsigned long ulCluster; // Start Cluster in FAT ++ unsigned char ucPartition_ID; // Partition ID ++ unsigned char fUsed; // Used or Not used ++#ifndef MTP_INCLUDE ++ unsigned int ucShortFolderName; ++ unsigned int ucLongFolderName; ++ unsigned char fLfn; ++ unsigned char dummy[3]; ++#else ++ unsigned short usCRC16FileName; //verify filename ++//MTPDB2DB--> ++ unsigned short usPacketOffset; ++//<--MTPDB2DB ++ unsigned char ucStatus; ++ unsigned char ReferenceCount; ++#endif ++}_FOLDER_LIST_TYPE,*pFOLDER_LIST_TYPE; ++ ++ ++typedef struct{ ++ unsigned char ucName[9]; // Disk name ++ unsigned char ucUsed; // Used or not ++ unsigned char ucDeviceType; // Device type from enum DISK_DEVICE ++ unsigned char ucPartID; // Partition ID ++ unsigned int uiFolderNum; // Total folder number in disk ++ unsigned int uiFileNum; // Total file number in disk ++ unsigned int uiRootIndex; // Root index at stTotalFolderList[] ++// unsigned char dummy; ++}_DEVICE_TYPE_INFO; ++ ++#define BRWS_MAKE_LIST_OF_FOLDER 0x01 ++#define BRWS_MAKE_LIST_OF_FILE 0x02 ++#define BRWS_MAKE_LIST_OF_ALL BRWS_MAKE_LIST_OF_FOLDER | BRWS_MAKE_LIST_OF_FILE ++ ++#define BRWS_MAKE_PLAY_LIST_ALL 0x80 ++#define BRWS_MAKE_PLAY_LIST_SIMAGE 0x40 ++#define BRWS_MAKE_PLAY_LIST_TEXT 0x20 ++#define BRWS_MAKE_PLAY_LIST_MPG4 0x10 ++#define BRWS_MAKE_PLAY_LIST_AUDIO 0x08 ++#define BRWS_MAKE_PLAY_LIST_M3U 0x04 ++ ++#define BRWS_SEARCH_ALL_FOLDER -1 ++ ++#define BRWS_NAME_AREA_SIZE 4096 ++ ++enum ++{ ++ FOLDER_RECORD = 10, ++#ifdef _RECORD_SUB_FOLDER_INCLUDE_ ++ #ifdef _RECORD_SUB_FOLDER_LINEIN_INCLUDE_ ++ FOLDER_RECORD_LINEIN, ++ #endif ++ #ifdef _RECORD_SUB_FOLDER_FM_INCLUDE_ ++ FOLDER_RECORD_FM, ++ #endif ++ #ifdef _RECORD_SUB_FOLDER_VOICE_INCLUDE_ ++ FOLDER_RECORD_VOICE, ++ #endif ++ #ifdef _RECORD_SUB_FOLDER_CAM_INCLUDE_ ++ FOLDER_RECORD_CAM, ++ #endif ++ #ifdef _RECORD_SUB_FOLDER_TV_INCLUDE_ ++ FOLDER_RECORD_TV, ++ #endif ++#endif ++ FOLDER_PHOTO, ++ FOLDER_AUDIBLE, ++ FOLDER_CONFIG, ++ FOLDER_ROOT, ++ FOLDER_DEFAULT, ++ FOLDER_UNKNOWN ++}; ++ ++#ifdef _RECORD_SUB_FOLDER_INCLUDE_ ++typedef enum ++{ ++#ifdef _RECORD_SUB_FOLDER_LINEIN_INCLUDE_ ++ RECORD_FOLDER_LINEIN, ++#endif ++#ifdef _RECORD_SUB_FOLDER_FM_INCLUDE_ ++ RECORD_FOLDER_FM, ++#endif ++#ifdef _RECORD_SUB_FOLDER_VOICE_INCLUDE_ ++ RECORD_FOLDER_VOICE, ++#endif ++#ifdef _RECORD_SUB_FOLDER_CAM_INCLUDE_ ++ RECORD_FOLDER_CAM, ++#endif ++#ifdef _RECORD_SUB_FOLDER_TV_INCLUDE_ ++ RECORD_FOLDER_TV, ++#endif ++ RECORD_SUB_FOLDER_UNKNOWN, ++ RECORD_SUB_FOLDER_MAX = RECORD_SUB_FOLDER_UNKNOWN ++}RECORD_SUB_FOLDER_TYPE; ++#endif ++ ++ ++/*-------------------------------------------------------------- ++ Folder Index Function ++----------------------------------------------------------------*/ ++extern unsigned int BRWS_GetRecordFileIndex(void); ++extern unsigned int BRWS_GetRecordFolderIndex(void); ++extern unsigned int BRWS_GetRecordFolderCluster(void); ++#ifdef _RECORD_SUB_FOLDER_INCLUDE_ ++extern unsigned int BRWS_GetRecordSubFolderIndex(unsigned int rec_sub_type); ++extern unsigned int BRWS_GetRecordSubFolderCluster(unsigned int rec_sub_type); ++#endif ++extern unsigned int BRWS_GetCurrFolderIndex(void); ++extern void BRWS_SaveFolderIndex(unsigned int iIndex); ++ ++ ++/*-------------------------------------------------------------- ++ Functions for making File List ++ ++ name : BRWS_MakePlayList ++----------------------------------------------------------------*/ ++extern unsigned int BRWS_MakePlayList(int uiTotalIndex, unsigned short *ptrList, unsigned char ucMode ); ++ ++extern unsigned int BRWS_FindFileNumInPlayList(int uiTotalIndex, unsigned int uiDBIndex, unsigned char ucMode ); ++ ++ ++/*-------------------------------------------------------------- ++Get Count Value Function ++----------------------------------------------------------------*/ ++extern unsigned int BRWS_GetTotalFolderNum( void ); ++extern unsigned int BRWS_GetTotalFileCount( void ); ++ ++/*-------------------------------------------------------------- ++utility Function ++----------------------------------------------------------------*/ ++extern int BRWS_FindMusicFile(const char *filename, int mode); ++extern int BRWS_CorrectDirName(char *path); ++extern void BRWS_CharCopy(const char *input, char *output, int num); ++extern int BRWS_CharNICmp(const char *src1, const char *src2, int cmplen); ++extern int BRWS_IsReadOnly(int attr); ++ ++/*-------------------------------------------------------------- ++Check the main device if config folder is existed. if not existing config folder, create it. ++----------------------------------------------------------------*/ ++extern int BRWS_CheckConfigFolderIs(int iPartID, int dir_num); ++ ++/*-------------------------------------------------------------- ++Audible function ++----------------------------------------------------------------*/ ++#ifdef AUDIBLE_INCLUDE ++extern int BRWS_CheckAudibleFolderIs(int); ++#endif ++/*-------------------------------------------------------------- ++Recoding function ++----------------------------------------------------------------*/ ++extern int BRWS_CheckRecodingFolderIs(int); ++extern int BRWS_ChangeRecodingFolder(void); ++extern int BRWS_UpdateRecodingDB(void); ++ ++/*-------------------------------------------------------------- ++Check File Attrive Function ++----------------------------------------------------------------*/ ++extern int BRWS_CheckFileAttrive(unsigned int uiFileIdx); ++ ++ ++/*-------------------------------------------------------------- ++Format Drive Function ++ ++----------------------------------------------------------------*/ ++extern int BRWS_FormatDrive(unsigned short mode, int iPartID); ++ ++ ++/*-------------------------------------------------------------- ++Delete File Function ++----------------------------------------------------------------*/ ++extern int BRWS_DeleteFile(unsigned int uiCurrFileNum, unsigned int uiFolderIdx); ++ ++/*--------------------------------------------------------------------- ++ BRWS_ReProfilingMTPUIDB ++-----------------------------------------------------------------------*/ ++extern int BRWS_ReProfilingMTPUIDB(void); ++ ++/*-------------------------------------------------------------- ++Copy File Function ++----------------------------------------------------------------*/ ++extern int BRWS_CopyFile(unsigned int uiSrcFileIndex, unsigned int uiDstFolderIndex); ++ ++/*-------------------------------------------------------------- ++Check Disk WP Status ++----------------------------------------------------------------*/ ++extern int BRWS_CheckWPStatus(int part_ID); ++ ++/*-------------------------------------------------------------- ++Check CRC of Image on NAND Disk ++----------------------------------------------------------------*/ ++#ifdef NAND_BOOT_INCLUDE ++extern int BRWS_CheckCRCOfNANDBOOT( void ); ++#endif ++ ++/*-------------------------------------------------------------- ++ Change Folder usign cluster ++----------------------------------------------------------------*/ ++extern int BRWS_CheckIsFolderRoot( unsigned int uiIndex ); ++ ++extern int BRWS_ChangeBackgroundFolder( unsigned int uiTotalIndex ); ++ ++extern int BRWS_ChangeFolder( unsigned int uiTotalIndex ); ++ ++extern int BRWS_InitializeCurrFolderList(unsigned int uiTotalIndex, unsigned short *ptrList, unsigned char ucMode ); ++ ++extern int BRWS_InitializeDeviceList(unsigned short *ptrList); ++ ++/*-------------------------------------------------------------- ++Folder Name Function ++----------------------------------------------------------------*/ ++extern unsigned char *BRWS_GetFolderName( unsigned int uiIndex, unsigned char *fLfn); ++extern unsigned char *BRWS_GetFileName( unsigned int uiFileIndex, unsigned char *fLfn); ++ ++/*-------------------------------------------------------------- ++ Search all file and folder in Selected Folder ++----------------------------------------------------------------*/ ++ ++extern int BRWS_SearchFolder(int iPartID, unsigned int uiTotalIndex); ++ ++/*-------------------------------------------------------------- ++ Make Folder and File List DataBase ++ : using BRWS_SearchFolder(); ++ ++----------------------------------------------------------------*/ ++extern void BRWS_InitializeFolderDB( void ); ++ ++extern int BRWS_AddDevice( unsigned char *ucName, unsigned char ucType ); ++extern int BRWS_RefreshMainDevice( void ); ++ ++extern int BRWS_SaveBRWSDB(void); ++extern int BRWS_LoadBRWSDB(void); ++extern int BRWS_DelBRWSDB(void); ++ ++#ifdef BRWS_STR_NAND_INCLUDE ++extern unsigned char *BRWS_GetNameString(unsigned int Offset); ++extern void BRWS_InitNameStringArea(unsigned int uiStartAddr,unsigned int uiSectorSize); ++extern void BRWS_CleanNameString(unsigned char *ucSrcString,unsigned int uiOffset); ++#endif ++extern void BRWS_PutNameString(unsigned char *ucSrcString,unsigned int uiOffset,unsigned char ucNameChar); ++extern unsigned char BRWS_GetDeviceStatus(unsigned int uiIndex); ++extern unsigned int BRWS_GetDefaultDevice(void); ++extern void BRWS_SetDefaultDevice(unsigned int uiDefaultDevice); ++extern unsigned int BRWS_GetDeviceCount(void); ++extern unsigned int BRWS_GetTotalDeviceCount(void); ++extern void BRWS_RemoveDevice(unsigned char ucDeviceType); ++extern unsigned char BRWS_GetFilePartID(unsigned int uiFileIndex); ++/* End - skott 's code */ ++ ++ extern int BRWS_CHeckFFREWSeekStatus(void); ++ ++extern int BRWS_IsTAGJPGCodec(int iCurrentCodec); ++extern int BRWS_IsMP3MP2Codec(int iCurrentCodec); ++extern int BRWS_IsAudibleCodec(int iCurrentCodec); ++extern int BRWS_IsImageCodec(int iCurrentCodec); ++extern int BRWS_IsBackgroundImageCodec(unsigned int uiBackgroundCodec); ++extern int BRWS_IsEAACPlusCodec(int iCurrentCodec); ++extern int BRWS_IsVideoCodec(int iCurrentCodec); ++extern int BRWS_IsWMVVideoCodec(int iCurrentCodec); ++extern int BRWS_IsDrmCodec(int iCurrentCodec); ++extern void BRWS_FILE_OpenDir(int iCurrentCodec, unsigned int uiTotalIndex) ; ++extern void BRWS_DisplayProgressFile(int iStartIndex, unsigned int Count,unsigned int MaxFileNum); ++extern unsigned long BRWS_GetFileCluster(int index); ++ ++#endif ++ +diff --git a/drivers/block/tcc/inc/fwdn/fat.h b/drivers/block/tcc/inc/fwdn/fat.h +new file mode 100644 +index 0000000..075ebc1 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fat.h +@@ -0,0 +1,740 @@ ++/*****************************************************************************/ ++// ++// Definition for FAT Application using Telechips Software. ++// ++// Copyright 2008 Telechips, Inc. ++// ++/*****************************************************************************/ ++ ++#include "FSAPP.h" ++ ++#ifndef __FAT_H__ ++#define __FAT_H__ ++ ++//============================================================================= ++//* ++//* ++//* [ ERROR CODE ENUMERATION ] ++//* ++//* ++//============================================================================= ++enum ++{ ++ FS_SUCCESS = 0, ++ FS_FAIL, ++ ++ ERR_FS_NOT_VALID_MBR, ++ ERR_FS_NOT_READ_MBR, ++ ERR_FS_NOT_FORMATTED, ++ ERR_FS_NOT_DELETE_FILE, ++ ERR_FS_NOT_DELETE_DIR, ++ ERR_FS_NOT_FIND_PARTITION_INFO, ++ ERR_FS_NOT_VALID_FAT_TYPE, ++ ERR_FS_NOT_VALID_READ_BOOTSECTOR, ++ ERR_FS_INVALID_SECTOR_SIZE, ++ ERR_FS_NOT_VALID_CLUSTER_PARAMETER, ++ ERR_FS_NOT_READ_SECTOR, ++ ERR_FS_NOT_WRITE_SECTOR, ++ ERR_FS_NOT_GET_LOGDRV_INFO, ++ ERR_FS_NOT_GET_PREVIOUS_DIR, ++ ERR_FS_NOT_GET_NEXT_CLUSTER, ++ ERR_FS_NOT_GET_PREV_CLUSTER, ++ ERR_FS_NOT_GET_EMPTY_CLUSTER, ++ ERR_FS_NOT_GET_INFO_FILEORDIR, ++ ERR_FS_NOT_GET_TOTAL_FILEORDIR, ++ ERR_FS_NOT_GET_PARENT_DIR_CLUSTER, ++ ERR_FS_NOT_FIND_DIR_CLUSTER_WITHDIRNAME, ++ ERR_FS_NOT_CREATE_DIRECTORY, ++ ERR_FS_NOT_DIRECTORY_CLUSTER, ++ ERR_FS_NOT_UPDATE_ENTRY, ++ ERR_FS_NOT_GET_FILEINFO_WITHFILENAME, ++ ERR_FS_NOT_OPEN_FAT_CHCHE, ++ ERR_FS_NOT_FLUSH_FAT_CACHE, ++ ERR_FS_NOT_SAME_FAT1_FAT2, ++ ERR_FS_NOT_READY_VIRTUAL_FAT1_FORSMC, ++ ERR_FS_NOT_READ_FROM_VIRTUAL_FAT1_FORSMC, ++ ERR_FS_NOT_WRITE_FAT_CONTENT_TO_VIRTUAL_FAT1_FORSMC, ++ ERR_FS_FAILED_READ_SECTOR, ++ ERR_FS_FAILED_FORMAT, ++ ERR_FS_PARAMETER_GET_DRV_PARTITON, ++ ERR_FS_NOT_VALID_PARAMETER ++}; ++ ++ ++//============================================================================= ++//* ++//* ++//* [ EXTERNAL DEFINATION ] ++//* ++//* ++//============================================================================= ++#define FAT_BOOTSIG 0xAA55 ++ ++// Some useful cluster numbers ++#define FAT_MSDOSFSROOT 0 /* cluster 0 means the root dir */ ++#define FAT_CLUST_FREE 0 /* cluster 0 also means a free cluster */ ++#define FAT_CLUST_RSRVD 0xfffffff6 /* reserved cluster range */ ++#define FAT_CLUST_BAD 0xfffffff7 /* a cluster with a defect */ ++#define FAT_CLUST_EOFS 0xfffffff8 /* start of eof cluster range */ ++#define FAT_CLUST_EOFE 0xffffffff /* end of eof cluster range */ ++ ++#define FAT12_MASK 0x00000fff /* mask for 12 bit cluster numbers */ ++#define FAT16_MASK 0x0000ffff /* mask for 16 bit cluster numbers */ ++#define FAT32_MASK 0x0fffffff /* mask for FAT32 cluster numbers */ ++ ++#define FAT12_EOFS 0x0FF8 ++#define FAT16_EOFS 0xFFF8 ++#define FAT32_EOFS 0x0FFFFFF8 ++// Partition Type used in the partition record ++#define PART_TYPE_UNKNOWN 0x00 ++#define PART_TYPE_FAT12 0x01 ++#define PART_TYPE_DOSFAT16 0x04 ++#define PART_TYPE_EXTDOS 0x05 ++#define PART_TYPE_FAT16 0x06 ++#define PART_TYPE_FAT32 0x0B ++#define PART_TYPE_FAT32LBA 0x0C ++#define PART_TYPE_FAT16LBA 0x0E ++#define PART_TYPE_EXTDOSLBA 0x0F ++ ++#define FS_MAX_SHIFT_FACTOR 17 ++ ++#define DRIVE0 0 ++#define MAX_MULTI_SECTOR 32 // 32 SECTORS ++#define MAX_MULTI_BYTE 16384 // 16 [Kbyte] = 512[byte] * 32 ++#define MAX_SECTOR_SIZE 4096 // [byte] = maximum bytes per sector ++#define MAX_CLUSTER_SIZE 65536 // 512(byte) * 128(sec) ++ ++#define FAT_BOOTSIG 0xAA55 ++#define EXTENDED_BOOTSIG 0x29 ++ ++#define FAT12 2 ++#define FAT16 1 ++#define FAT32 0 ++ ++#define FAT_DIR_EMPTY 0x00 // directory entry is free. never been used. ++#define FAT_DIR_E5 0x05 // value for 0xE5. because 0xE5 is a real char in KANJI ++#define FAT_DIR_DELETED 0xE5 // this directory entry is free. ++ ++#define ATTR_NORMAL 0x00 // normal file ++#define ATTR_READ_ONLY 0x01 // file is read only ++#define ATTR_HIDDEN 0x02 // file is hidden ++#define ATTR_SYSTEM 0x04 // file is a system file ++#define ATTR_VOLUME_ID 0x08 // entry is a volume label ++#define ATTR_DIRECTORY 0x10 // entry is a directory name ++#define ATTR_ARCHIVE 0x20 // file is new or modified ++#define ATTR_LONG_NAME 0x0F // this is a long file name entry ++ ++#define LCASE_BASE 0x08 // filename base in lower case ++#define LCASE_EXT 0x10 // filename extension in lower case ++ ++#define DIR_ENTRY_PER_SECTOR 0x10 // 16 = 512/32 ++ ++#define LAST_LONG_ENTRY 0x40 // mask for the last dir entry ++#define LDIR_ORD_MAX 0x3F // Max. count of LDIR_Ord ++ ++#define LDIR_CHAR_PER_ENTRY 13 // Number of character of a long dir entry. ++#define LDIR_MAX_CHAR 255 // max. number of character of the long file name ++#define MAX_ROOT_ENTRY_COUNT 1024 // max. number of the root entry count ++ ++#define FAT_CACHE_SECTOR 3 // 3 sectors = 512 * 3 [byte] ++ ++// LOCK FLAG OF THE FILE SYSTEM TEMPORARY BUFFER ++#define LOCK_BUFF 0x0001 ++#define UNLOCK_BUFF 0x0000 ++#define DIRTY_BIT 0x0100 ++ ++// MAXIMUM NUMBER OF PARTITIONS ++#define FS_MAX_PART_NUMBER FSAPP_MAX_PART_NUMBER ++ ++#define START_YEAR 1980 // Year 1980 ++ ++#define FILE_OP_WRITE 0x00010000 // write file ++#define FILE_OP_OPEN 0x00000001 // opened file ++#define FILE_OP_CH_SIZE 0x00020000 // changed file size ++#define FILE_OP_UP_ENT 0x00100000 // update short entry. else create new entry ++ ++#define ADDITION 1 ++#define SUBTRACTION 2 ++// special option ++#define _NEW_WRITE_ENTRY ++ ++ ++//============================================================================= ++//* ++//* ++//* [ STRUCT DEFINE ] ++//* ++//* ++//============================================================================= ++ ++/////////////////////////////////////////////////////////////////////////////// ++///////////////////////// MBR /////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// FOR EACH PARTITION ENTRY INFORMATION(16 BYTES) STRUCTURE ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _PARTITION_INFO // length 16 bytes partion entry information ++#elif defined(_LINUX_) ++typedef struct _PARTITION_INFO // length 16 bytes partion entry information ++#endif ++{ ++ ++ unsigned char boot_id; // Bootable? 0=no , 128(0x80) = yes ++ unsigned char begin_head; // beginning head number ++ unsigned char begin_sector; // beginning sector number ++ unsigned short begin_cylinder; // 10bit number [high 2bit], with high 2bits put in begin sector ++ unsigned char system_id; // Operating System type indicator code ++ unsigned char end_head; // ending head number ++ unsigned char end_sector; // ending sector numer ++ unsigned short end_cylinder; // 10bit number [high 2bit] , with high 2bits put in end sector ++ unsigned long relative_first_sector; // first sector relative to start of disk ++ unsigned long number_sector_partition; // number of sectors in partion ++ ++ ++#if defined(_WINCE_) ++}PARTINFOstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) PARTINFOstruc; ++#endif ++ ++ ++ ++// FOR EACH PARTITION AREA ALL DATA STRUCTURE ++#if defined(_WINCE_) ++#pragma pack(1) ++struct _MBR_INFO ++#elif defined(_LINUX_) ++struct _MBR_INFO ++#endif ++{ ++ ++ PARTINFOstruc parts[4]; ++ unsigned short signature; // two signature bytes (2 bytes) ++ ++ ++#if defined(_WINCE_) ++}; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)); ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++///////////////////////// PBR /////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// COMMON BPB SPEC. FOR FAT16/32. (36 BYTES) ++#if defined(_WINCE_) ++#pragma pack(1) ++struct _BPB ++#elif defined(_LINUX_) ++struct _BPB ++#endif ++{ ++ ++ unsigned char BS_jmpBoot[3]; // jump instruction to boot code. 0xE9xxx or 0xEBxx90 ++ char BS_OEMName[8]; // OEM name and version ++ unsigned short BPB_BytsPerSec; // Count of bytes per sector. default 512 ++ unsigned char BPB_SecPerClus; // Number of sectors per cluster ++ unsigned short BPB_RsvdSecCnt; // Number of reserved sectors ++ unsigned char BPB_NumFATs; // Count of FAT data on the volume. default 2 ++ unsigned short BPB_RootEntCnt; // Number of the Root directory entries. FAT32 = 0 ++ unsigned short BPB_TotSec16; // 16 bit total count of sector < 65536. FAT32 = 0 ++ unsigned char BPB_Media; // media discriptor. 0xF8 --> "Fixed Disk" ++ unsigned short BPB_FATSz16; // Number of sectors per FAT ++ unsigned short BPB_SecPerTrk; // sector per track ++ unsigned short BPB_NumHeads; // Number of heads ++ unsigned long BPB_HiddSec; // count of hidden sectors ++ unsigned long BPB_TotSec32; // total count of sectors on the volume. ++ ++ ++#if defined(_WINCE_) ++}; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)); ++#endif ++ ++ ++ ++// EXTENDED BS(BOOT SECTOR) SPEC. FOR FAT16/32. (26 BYTES) ++#if defined(_WINCE_) ++#pragma pack(1) ++struct _EXTENDED_BS ++#elif defined(_LINUX_) ++struct _EXTENDED_BS ++#endif ++{ ++ ++ unsigned char BS_DrvNum; // drive number : HDD(0x80), FDD(0x00) ++ unsigned char BS_Reserved1; // reserved(used by Windows NT) ++ unsigned char BS_BootSig; // Extended boot signature (0x29) ++ unsigned char BS_VolID[4]; // Volume serial number ++ char BS_VolLab[11]; // Volume label ++ char BS_FilSysType[8]; // FS type string "FAT12","FAT16","FAT" ++ ++ ++#if defined(_WINCE_) ++}; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)); ++#endif ++ ++ ++ ++// BPB SPEC. FOR FAT32 ONLY. (54 BYTES) ++#if defined(_WINCE_) ++#pragma pack(1) ++struct _BPB_FAT32 ++#elif defined(_LINUX_) ++struct _BPB_FAT32 ++#endif ++{ ++ ++ unsigned long BPB_FATSz32; // Number of sectors per FAT for FAT32 ++ unsigned short BPB_ExtFlags; // extended flags ++ unsigned short BPB_FSVer; // FAT file system version. ++ unsigned long BPB_RootClus; // starting cluster number of the root directory. ++ unsigned short BPB_FSInfo; // sector number of FSINFO structure. Usually 1. ++ unsigned short BPB_BkBootSec; // backup boot sector. Usually 6. ++ unsigned char BPB_Reserved[12]; // reserved for future expansion. Must be all zero. ++ unsigned char BS_DrvNum; ++ unsigned char BS_Reserved1; ++ unsigned char BS_BootSig; ++ unsigned char BS_VolID[4]; ++ char BS_VolLab[11]; // Volume label ++ char BS_FilSysType[8]; // Reserved 12 bytes for future expansion. all zeros. ++ ++ ++#if defined(_WINCE_) ++}; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)); ++#endif ++ ++ ++ ++// BS(BOOT SECTOR) AND BPB(BIOS PARAMETER BLOCK) STRUCTURE FOR FAT32 ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _BSBPB_INFO ++#elif defined(_LINUX_) ++typedef struct _BSBPB_INFO ++#endif ++{ ++ ++ struct _BPB BPB_data; // Common BPB data (25 bytes) ++ struct _BPB_FAT32 BPB_FAT32; // Extended BPB Info. for FAT32 only. (28 bytes) ++ struct _EXTENDED_BS BS_extended; // Extended BS for FAT12/16 (26 bytes) ++ ++ ++#if defined(_WINCE_) ++}BSBPBstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) BSBPBstruc; ++#endif ++ ++ ++ ++// BS(BOOT SECTOR) AND BPB(BIOS PARAMETER BLOCK) STRUCTURE FOR FAT12/16 ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _BSBPB1216_INFO ++#elif defined(_LINUX_) ++typedef struct _BSBPB1216_INFO ++#endif ++{ ++ ++ struct _BPB BPB_data; // Common BPB data (25 bytes) ++ struct _EXTENDED_BS BS_extended; // Extended BS for FAT12/16 (26 bytes) ++ ++ ++#if defined(_WINCE_) ++}BSBPB1216struc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) BSBPB1216struc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++///////////////////// Reserved Area(FSInfo) ///////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// FAT32 FSINFO SECTOR STRUCTURE & BACKUP BOOT SECTOR. ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _FSINFO_SECTOR // for FAT32 FSInfo ++#elif defined(_LINUX_) ++typedef struct _FSINFO_SECTOR // for FAT32 FSInfo ++#endif ++{ ++ ++ ++ unsigned long FSI_LeadSig; // lead signature for FSInfo. Usually 0x41615252 ++ unsigned char FSI_Reserved1[480]; // reserved field. initial value is all zeros. ++ unsigned long FSI_StrucSig; // usually 0x61417272 in spec. ++ unsigned long FSI_Free_Count; // (free cluster count on the volume) <= (volume cluster count) ++ unsigned long FSI_Nxt_Free; // next available cluster number. typically last cluster no. ++ unsigned char FSI_Reserved2[12]; // reserved for future expansion. all zeros. ++ unsigned long FSI_TrailSig; // trail signature = 0xAA550000 for FSInfo Sector. ++ ++ ++#if defined(_WINCE_) ++}FSINFOstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) FSINFOstruc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++///////////////////// Logical Drv Structure ///////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _DRIVE_INFO ++#elif defined(_LINUX_) ++typedef struct _DRIVE_INFO ++#endif ++{ ++ ++ struct _PARTITION_INFO part; // partition info : 18 Bytes ++ struct _BSBPB_INFO BS; ++ ++ unsigned char Drv_Type; // 0: HDD, 1: MMC/SD, 2: USB_DRV, 3: NAND_DRV ++ unsigned char FAT_Type; // 0: FAT32 1: FAT16 2:FAT32 ++ unsigned short LUN; // logical unit number ++ unsigned short part_index; // logical partition or drive index(number). ++ unsigned long nCluster; // Temporary Variable for Disk Size ++ unsigned long FAT1StartSector; // FAT1 Start Sector ++ unsigned long FAT2StartSector; // FAT2 Start Sector ++ unsigned long FATSize; // FAT Size ++ unsigned long FirstDataSector; // Cluster Start Sector 2TH CLUSTER ++ unsigned long DirStartSector; // Root Start Sector ++ unsigned long DataSec; // Total Data Sector ++ unsigned long CountofClusters; // Total Count of clusters ++ unsigned long ClusterSize; // Cluster Byte Size ++ unsigned short ClusterShift; // Cluster Shift Factor Size ++ unsigned short BytsPerSecShift; // Sector Bytes Shift Factor Size ++ unsigned short SecPerClusShift; // Sectors Per Cluster Shift Factor Size ++ unsigned long UsedClusters; // Used total data capacity [byte] ++ ++ ++#if defined(_WINCE_) ++}DRIVE_INFOstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) DRIVE_INFOstruc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////// File Entry Structure ///////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// FAT DIRECTORY ENTRY STRUCTURE(32 BYTES DATA). ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _FAT_DIR_ENTRY // FAT 32 bytes for directory entry ++#elif defined(_LINUX_) ++typedef struct _FAT_DIR_ENTRY // FAT 32 bytes for directory entry ++#endif ++{ ++ ++ unsigned char Name[8]; // file name field ++ unsigned char Extension[3]; // file extension field ++ unsigned char Attr; // File attributes ++ unsigned char NTRes; // reserved for Windows NT VFAT lower case flags. ++ unsigned char CrtTimeTenth; // Millisecond stamp at file creation time. 0-199/(2 sec) ++ unsigned short CrtTime; // Time file was created. ++ unsigned short CrtDate; // Date file was created. ++ unsigned short LstAccDate; // Last access date. ++ unsigned short FstClusHI; // High word of this entry's first cluster number. zero for FAT12/16. ++ unsigned short WrtTime; // Time of last write. ++ unsigned short WrtDate; // Date of last write. ++ unsigned short FstClusLO; // Low word of this entry's first cluster number. ++ unsigned long FileSize; // this file's size in bytes. ++ ++ ++#if defined(_WINCE_) ++}ENTRY_INFO; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) ENTRY_INFO; ++#endif ++ ++ ++ ++// FAT LONG DIRECTORY ENTRY STRUCTURE. ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _FAT_LONG_DIR_ENTRY // FAT 32 bytes for long directory entry ++#elif defined(_LINUX_) ++typedef struct _FAT_LONG_DIR_ENTRY // FAT 32 bytes for long directory entry ++#endif ++{ ++ ++ unsigned char LDIR_Ord; // order of this entry in the sequence of long dir entries. ++ char LDIR_Name1[10]; // char 1-5 of the long-name sub-component ++ unsigned char LDIR_Attr; // Attributes - must be ATTR_LONG_NAME(0x0F) ++ unsigned char LDIR_Type; // If zero, this entry is a sub-component of a long name. ++ unsigned char LDIR_Chksum; // checksum of name in the short dir entry ++ char LDIR_Name2[12]; // char 6-11 of the long-name sub-component ++ unsigned short LDIR_FstClusLO; // must be zero. ++ char LDIR_Name3[4]; // char 12-13 of the long-name sub-component ++ ++ ++#if defined(_WINCE_) ++}FAT_LDIR; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) FAT_LDIR; ++#endif ++ ++ ++ ++// FAT32 DIRECTORY ENTRY. ++typedef struct _FAT32DIRENT ++{ ++ union ++ { ++ ENTRY_INFO s; ++ FAT_LDIR l; ++ }entry; ++}FAT32DIRENTstruc; ++ ++ ++ ++// FILE OR DIRECTORY ENTRY POSITION STRUCTURE ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _FAT_ENTRY_POS ++#elif defined(_LINUX_) ++typedef struct _FAT_ENTRY_POS ++#endif ++{ ++ ++ int entryOffset; ++ int entrySectorOffset; ++ unsigned long dirCluster; ++ short entryCount; ++ ++ ++#if defined(_WINCE_) ++}ENTPOSstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) ENTPOSstruc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////// FAT Cache Structure ////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// FAT CACHE CONTROL ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _FAT_CACHE ++#elif defined(_LINUX_) ++typedef struct _FAT_CACHE ++#endif ++{ ++ ++ unsigned int InCache; ++ int drvTypeID; ++ int partID; ++ unsigned short status; ++ ++ ++#if defined(_WINCE_) ++}FATCACHEstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) FATCACHEstruc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++//////// Lock/Unlock struc. of Entry Sector bufferEntry /////////////// ++/////////////////////////////////////////////////////////////////////////////// ++// ENTRY SECTOR BUFFER CONTROL ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _SECTOR_BUFF ++#elif defined(_LINUX_) ++typedef struct _SECTOR_BUFF ++#endif ++{ ++ ++ unsigned int InSector; // sector buffer address ++ int part_id; // partition index ++ unsigned short status; // lock or dirty bit ++ ++ ++#if defined(_WINCE_) ++}SECBUFFstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) SECBUFFstruc; ++#endif ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////// ++ ++ ++ ++struct _FDIRENT; ++struct _FD; ++struct _DISK_INFO; ++ ++//============================================================================= ++//* ++//* ++//* [ EXTERNAL VARIABLE DEFINE ] ++//* ++//* ++//============================================================================= ++//FAT File System Global Variables. ++extern int fat_total_partition; // total partition counter ++extern unsigned short fat_valid_partition; // primary & logical partition counter. ++ ++extern unsigned char max_handle; ++extern unsigned char max_fd; ++extern unsigned char max_dir; ++extern HANDLERstruc *fHandler; ++extern FDstruc *fD; ++extern FDIRENTstruc *fDir; ++ ++extern unsigned int fat_sbuffer[]; ++extern unsigned short fat_cache[(512 * FAT_CACHE_SECTOR) >> 1]; // fat cache buffer = 512 bytes * 3 ++ ++extern DRIVE_INFOstruc driveInfo[FS_MAX_PART_NUMBER]; // current drive information ++extern FATCACHEstruc fatCache; ++extern SECBUFFstruc secBuffer; ++ ++extern unsigned char *entry_buffer; // entry chunk buffer ++ ++// FILE DATE & TIME DEFINITION ++extern volatile unsigned short file_year; // initial value = 1980 ++extern volatile unsigned char file_month; // initial value = 1 ++extern volatile unsigned char file_day; // initial value = 1 ++extern volatile unsigned char file_hours; // initial value = 0 ++extern volatile unsigned char file_min; // initial value = 0 ++extern volatile unsigned char file_sec; // initial value = 0 ++ ++ ++//============================================================================= ++//* ++//* ++//* [ FUCTIONS DEFINE ] ++//* ++//* ++//============================================================================= ++extern int FAT_GetNextCluster(int drvTypeID, int partID, unsigned long curr_cluster, unsigned long *next_cluster, void *fat_buff); ++extern int FAT_SetNextCluster(int drvTypeID, int partID, unsigned long curr_cluster, unsigned long next_cluster, void *fat_buff); ++extern unsigned long FAT_ReadEntrySector(int drvTypeID, int partID, unsigned long dir_cluster, unsigned long SectorIndex, void *buff); ++extern unsigned long FAT_ReadDirSector(int drvTypeID, int partID, unsigned long dir_cluster, unsigned long SectorIndex, void *buff, int *preSkip); ++extern int FAT_FindFileEntryWithID(int drvTypeID, unsigned long dirCluster, int file_id, struct _FDIRENT *pFDir); ++extern int FAT_FindFileEntryWithEntryOffset(int drvTypeID, int partID, unsigned long dirCluster, int file_id, struct _FDIRENT *pFDir); ++extern int FAT_FindDirEntryWithID(int drvTypeID, unsigned long dirCluster, int dir_id, struct _FDIRENT *pFDir); ++extern int FAT_FindDirEntryWithEntryOffset(int drvTypeID, int partID, unsigned long dirCluster, int dir_id, struct _FDIRENT *pDir); ++extern int FAT_GetDirContents(int drvTypeID, int partID, unsigned long start_cluster, int *file_count, int *subdir_count); // 0923 ++extern int FAT_GetParentDirEntry(int drvTypeID, int partID, struct _FDIRENT *pDir, unsigned long dir_cluster); ++extern int FAT_FindDirEntryWithCluster(int drvTypeID, int partID, unsigned long start_cluster, unsigned long dir_cluster, struct _FDIRENT *pDir); ++extern int FAT_ReadCluster(int drvTypeID, int partID, unsigned short nSector, unsigned long currCluster, unsigned long offset, unsigned char *pBuff, int nRead, int clusterSize); ++extern int FAT_WriteCluster(int drvTypeID, int partID, unsigned short nSector, unsigned long currCluster, unsigned long offset, unsigned char *pBuff, int nWrite, int clusterSize); ++extern int FAT_GetEmptyCluster(int drvTypeID, int partID, unsigned long curr_cluster, unsigned long *Empty_Clus, void *fat_buff); ++extern int FAT_MakeSubDir(int drvTypeID, int partID, char *pName, unsigned long dirCluster, int option); ++extern int FAT_GetFreeEntryCount(int drvTypeID, int partID, unsigned long dirCluster, int *entryOffset, ++ int *entrySectorOffset, unsigned long *entryCluster, int entryNeeds ); ++extern unsigned long FAT_GetFileStartCluster(int drvTypeID, int partID, unsigned long curr_cluster); ++extern int FAT_WriteEntrySector(int drvTypeID, int partID, unsigned long dir_cluster, int entrySectorOffset, void *buff); ++extern unsigned long FAT_WriteSector(int drvTypeID, int partID, unsigned long dir_cluster, int SectorIndex, void *buff); ++extern int FAT_ClearFileCluster(int drvTypeID, int partID, unsigned long curr_cluster, void *buff); ++extern int FAT_DeleteFileEntry(int drvTypeID, int partID, unsigned long dir_cluster, int sector_offset, int entry_offset, void *pBuff); ++extern int FAT_UpdateFATCache(void *buff); ++extern int FAT_MakeEmptyEntry(int drvTypeID, int partID, unsigned long uwStrCluster, int *npEntryOffset, int *npEntrySecOffset, unsigned long *lpEntryCluster, int entryNeeds ); ++extern int FAT_MakeNewFD(int drvTypeID, struct _FDIRENT *pDir, char *pName, struct _FD *pFD); ++extern int FAT_MountDrive(int drvTypeID, unsigned int lun); ++extern int FAT_UnmountDrive(int drvTypeID); ++ ++extern int FAT_MakeShortEntryFile(int drvTypeID, int partID, struct _FD *pFD, unsigned char *dir_ent); ++extern int FAT_FindShortFile(int drvTypeID, int partID, unsigned long dir_cluster, char *pName, struct _FDIRENT *pFDir); ++extern int FAT_readdir(int drvTypeID, int partID, unsigned long dir_cluster, struct _FDIRENT *pFDir, int mode, void *entry_buff); ++extern int FAT_GetEntryData(int drvTypeID, int partID, ENTPOSstruc *pEntPos, void *pBuff); ++extern unsigned char FAT_ChkSum(unsigned char *pFcbName); ++extern int FAT_FormatFAT(int drvTypeID, unsigned int partID, unsigned char SecPerClus, ++ void *SecBuff, struct _DISK_INFO *disk, unsigned char writeVolume); ++extern int FAT_FormatFAT32(int drvTypeID, unsigned int partID, unsigned char SecPerClus, ++ void *SecBuff, struct _DISK_INFO *disk, unsigned char writeVolume); ++extern void FAT_InitVariable(void); ++extern void FAT_InitDriveInfo(void); ++extern unsigned long FAT_ArithmeticOperationForCluster(int partID, int nCluster, char arithOperator); ++extern int FAT_UpdateEntryCountToCache(int drvTypeID, unsigned long dir_cluster, int nCount); ++extern void FAT_SetReservedSector(unsigned long sector_addr); ++extern unsigned long FAT_ReadTotalSectorFromHidden(unsigned long *); ++extern int FAT_GetUsedClusters(int drvTypeID, int partID); ++extern int FAT_MakeDotEntry(int drvTypeID, int partID, unsigned long start_cluster, unsigned long parent_cluster); ++extern int FAT_ClearCluster(int drvTypeID, int partID, unsigned long curr_cluster); ++extern unsigned long FAT_ReadSector(int drvTypeID, int partID, unsigned long dir_cluster, unsigned long SectorIndex, void *buff); ++ ++extern int _FAT_MakeNewFD(struct _FDIRENT *pDir, char *pName, struct _FD *pFD); ++ ++ ++extern int drv_WriteSector(int drvTypeID, unsigned long LBA_addr, unsigned short nSector, void *buff); ++extern int drv_ReadSector(int drvTypeID, unsigned long LBA_addr, unsigned short nSector, void *buff); ++extern void lockSecBuff(void); ++extern void unlockSecBuff(void); ++extern void lockFATBuff(void); ++extern void unlockFATBuff(void); ++extern unsigned short makeWrtDate(unsigned short year, unsigned char month, unsigned char day); ++extern unsigned short makeWrtTime(unsigned char hours, unsigned char min, unsigned char sec); ++ ++extern int check_free_entry(int drvTypeID, int partID, unsigned long dir_cluster, int *entryOffset, int *entrySectorOffset, unsigned long *entryCluster, int nEntry); ++extern int str_cmpu(void *sA, void *sB); ++extern int str_len16(void *pString); ++extern int find_DirEntry(int drvTypeID, int partID, unsigned long startCluster, unsigned char *pFileName); ++extern int makeShortName(void *pN, void *sN, int num_tail, unsigned short type); ++extern int makeDirEntry(void *sName, unsigned char attr, unsigned long entry_cluster, unsigned char *dir_ent); ++ ++extern int FAT_getUsedClus_Common(int drvTypeID, int partID, unsigned short nSector, unsigned long FAT1_PhySector); ++extern int FAT_fatCache_Common(int drvTypeID, int partID, unsigned long FAT2_PhySector, unsigned long FAT_Sector, unsigned short nSector, unsigned char *sbuffer, unsigned char RWflag); ++extern unsigned int FAT_Format_ClearCommon(int drvTypeID, int sectorPerFAT, unsigned long nSector, unsigned char *pBuff, void *SecBuff, unsigned char multiFlag); ++extern int FAT_FormatRE_Common(int drvTypeID, int halfEntryNum, unsigned nSector, unsigned char writeVolume, void *pBuff, unsigned char *BS_VolLab); ++ ++extern unsigned int FAT_makeMBR(int drvTypeID, unsigned int *numOfSecPR, unsigned int *validFAT, unsigned char SecPerClus, void *pBuff, struct _DISK_INFO *disk); ++ ++extern int FAT_CheckDirContentsExist(int drvTypeID, int partID, unsigned long start_cluster, int *file_count, int *subdir_count); ++extern short getLongEntryName(int drvTypeID, int partID, struct _FDIRENT *pFDir, unsigned long sector_offset, int entry_offset, struct _FAT_LONG_DIR_ENTRY *entry, void *buff); ++extern unsigned long cluster2sector(int partID, unsigned long cluster); ++ ++extern int FDISK_PartitionWrite(int drvTypeID, unsigned int partitionID, unsigned int relativeLBA, void *pBuff, unsigned short nSector); ++extern int FDISK_PartitionRead(int drvTypeID, unsigned int partitionID, unsigned int relativeLBA, void *pBuff, unsigned short nSector); ++ ++#endif // __FAT_H__ +diff --git a/drivers/block/tcc/inc/fwdn/file.h b/drivers/block/tcc/inc/fwdn/file.h +new file mode 100644 +index 0000000..c7e395d +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/file.h +@@ -0,0 +1,284 @@ ++/*****************************************************************************/ ++// File Defition for Telechips Software. ++// ++// Copyright 2008 Telechips, Inc. ++// ++/*****************************************************************************/ ++ ++#ifndef __FILE_H__ ++#define __FILE_H__ ++ ++//============================================================================= ++//* ++//* ++//* [ EXTERNAL DEFINATION ] ++//* ++//* ++//============================================================================= ++#define ROOT_DIR_ID 0xFFFF0000 ++ ++// FILE ACCESS MODE ++#define FILE_ACCESSMASK 0x07 ++#define FILE_READ 0x00 /* File Read Only */ ++#define FILE_WRITE 0x01 /* File Write Only */ ++#define FILE_REWRITE 0x02 /* File Read/Write */ ++#define FILE_COPY 0x10 ++ ++#define FILE_OEXIST 0x00010000 /* Open Existing File */ ++#define FILE_OTRUNC 0x00020000 /* Truncate Existing File */ ++#define FILE_OAPPEND 0x00040000 /* Open Exisging File at EOF */ ++#define FILE_OCREAT 0x00100000 /* Create Unexisting File */ ++ ++// FILE ATTRIBUTE ++#define FILE_NORMAL 0x00 ++#define FILE_READ_ONLY 0x01 ++#define FILE_HIDDEN 0x02 ++#define FILE_SYSTEM 0x04 ++#define FILE_VOLUME_ID 0x08 ++#define FILE_DIRECTORY 0x10 ++#define FILE_ARCHIVE 0x20 ++ ++// FILE CREATE OPTION ++#define FILE_NO_TILDE 0x0100 /* do not make file with numeric-tail */ ++#define FILE_NO_CMP 0x0200 ++ ++// REFERENCE POINT OF FILE POINTER. ++#define FSEEK_SET 0 // file beginning ++#define FSEEK_CUR 1 // current FP position ++#define FSEEK_END 2 // file ending ++ ++#define FILE_FIND_FIRST 0x00 ++#define FILE_FIND_NEXT 0x01 ++#define FILE_SKIP_LFN 0x02 ++#define FILE_SAVE_S_ENTRY 0x04 ++ ++//============================================================================= ++//* ++//* ++//* [ ERROR CODE ENUMERATION ] ++//* ++//* ++//============================================================================= ++typedef enum ++{ ++ ERR_FS_FAIL = -1, ++ ERR_FS_FULL_ROOT_ENTRY = -2 ++} FS_ERROR; ++ ++//============================================================================= ++//* ++//* ++//* [ STRUCT DEFINE ] ++//* ++//* ++//============================================================================= ++typedef struct _HANDLER // FILE HANDLER STRUCTURE. ++{ ++ int lock; // used handle ++ unsigned long usage; // Usage of this handle. Read, Write, Copy etc... ++ unsigned char *pEntry; // entry chunk pointer ++ short nEntry; // number of entry in entry chunk data. 32 [byte] ++}HANDLERstruc; ++ ++typedef struct _FD // FILE DESCRIPTOR STRUCTURE. ++{ ++ int part_id; // current partition index ++ int file_id; // file id in a parent directory. NOT used anymore. ++ unsigned long dirCluster; // number of the start cluster of a parent directory ++ ++ char lFileName[258]; // long file or dir name ++ char sFileName[13]; // short file or dir name ++ long fileSize; // file size [byte]. ++ unsigned long startCluster; // number of the start cluster of a file or directory ++ ++ int pre_clusterCnt; ++ unsigned long cntCluster; ++ ++ int entryOffset; // short entry offset(slot) in current sector ++ int entrySectorOffset; // current sector number in current directory ++ unsigned long entryCluster; // just debugging ++ ++ unsigned long clusterSize; // cluster size of the current partition [byte] ++ unsigned short type; // file type or attribute. (READ ONLY, HIDDEN, SYSTEM, DIRECTORY, ARCHIVE) ++ unsigned long mode; // Access Mode of file. (READ, WRITE, REWRITE) ++ unsigned long offset; // file pointer [byte] ++ int refCnt; // referenct flag. lower 16 bit : referenct count, upper 16 bit : dirty bit ++}FDstruc; ++ ++typedef struct _FDIRENT // FILE OR DIRECTORY ENTRY STRUCTURE. ++{ ++ char lFileName[258]; // long file name ++ char sFileName[13]; // short file name ++ unsigned char ref; ++ long fileSize; // file size [byte] ++ unsigned short type; // file attribute. ++ ++ unsigned long startCluster; // cluster of the current file or directory ++ unsigned long parentCluster; // cluster of the parent directory ++ ++ int entryOffset; // short entry offset(slot) in current sector ++ int entrySectorOffset; // current sector number in current directory ++ unsigned long entryCluster; // just debugging ++ ++ int file_cnt; // file count. only valid when FILE_Refresh() was excuted. ++ int subdir_cnt; // sub-directory(folder) count. only valid when FILE_Refresh() was excuted. ++ int part_id; // current partition index ++ short entryCount; // total entry count ++}FDIRENTstruc; ++ ++// SHORT DIRECTORY ENTRY STRUCTURE(32 BYTES DATA). ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _SFN_DIR_ENTRY // FAT 32 bytes for directory entry ++#elif defined(_LINUX_) ++typedef struct _SFN_DIR_ENTRY // FAT 32 bytes for directory entry ++#endif ++{ ++ unsigned char Name[8]; ++ unsigned char Extension[3]; ++ unsigned char Attr; ++ unsigned char NTRes; ++ unsigned char CrtTimeTenth; ++ unsigned short CrtTime; ++ unsigned short CrtDate; ++ unsigned short LstAccDate; ++ unsigned short FstClusHI; ++ unsigned short WrtTime; ++ unsigned short WrtDate; ++ unsigned short FstClusLO; ++ unsigned long FileSize; ++#if defined(_WINCE_) ++}SFN_INFO; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) SFN_INFO; ++#endif ++ ++ ++#if defined(_WINCE_) ++#pragma pack() ++typedef struct _DIRENT // FILE OR DIRECTORY ENTRY STRUCTURE. - for FILE_ReadDir() ++#elif defined(_LINUX_) ++typedef struct _DIRENT // FILE OR DIRECTORY ENTRY STRUCTURE. - for FILE_ReadDir() ++#endif ++{ ++ SFN_INFO sEntry; // short entry slot ++ char *lFileName; // pointer of the long file name ++ char *sFileName; // pointer of the short file name ++ unsigned char LFNflag; // 0: no LFN, 1: has LFN ++ unsigned short type; // file attribute. file or directory ++ unsigned long startCluster; // cluster of the directory or file ++ unsigned int offset; ++ int part_id; // current partition index ++#if defined(_WINCE_) ++}DIRENTstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++}DIRENTstruc; ++#endif ++ ++#ifndef _DISKINFOstruc_ ++#define _DISKINFOstruc_ ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _DISK_INFO // DISK INFORMATION STRUCTURE. - for File_Format() ++#elif defined(_LINUX_) ++typedef struct _DISK_INFO // DISK INFORMATION STRUCTURE. - for File_Format() ++#endif ++{ ++ unsigned short head; ++ unsigned short cylinder; ++ unsigned short sector; ++ unsigned short sector_size; ++#if defined(_WINCE_) ++}DISKINFOstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) DISKINFOstruc; ++#endif ++#endif //#ifndef _DISKINFOstruc_ ++ ++ ++#if defined(_WINCE_) ++#pragma pack(1) ++typedef struct _DRV_INFO // PARTITION (OR DRIVE) SIMPLE INFORMATION ++#elif defined(_LINUX_) ++typedef struct _DRV_INFO // PARTITION (OR DRIVE) SIMPLE INFORMATION ++#endif ++{ ++ unsigned char Drv_Type; // HDD_DRV, MMC_DRV, USB_DRV, NAND_DRV ++ unsigned char FAT_Type; // FAT32, FAT16, FAT32 ++ unsigned short part_id; // logical partition or drive index(number). ++ unsigned short BytsPerSec; // Count of bytes per sector. normally 512 ++ unsigned long ClusterSize; // Cluster Byte Size ++ unsigned long CountofClusters; // total number of clusters ++ unsigned long UsedClusters; // Used total data capacity [byte] ++#if defined(_WINCE_) ++}DRVINFOstruc; ++#pragma pack() ++#elif defined(_LINUX_) ++} __attribute__((packed)) DRVINFOstruc; ++#endif ++ ++//============================================================================= ++//* ++//* ++//* [ FUCTIONS DEFINE ] ++//* ++//* ++//============================================================================= ++extern FDstruc *FILE_pGetFD(int nFD); ++extern FDIRENTstruc *FILE_pGetDIR(int dir_num); ++extern FDIRENTstruc *FILE_pGetFDir(int nFDir); ++extern int FILE_InitSystem(void); ++extern int FILE_Write(int nHandle, void *pBuff, int size); // write a file ++extern int FILE_OpenDirByEntryId(int drvTypeID, int partID, int dir_id, int dir_num); // open directory. ++extern int FILE_MakeDir(char *pName, int dir_num); // make sub-directory ++extern int FILE_MakeDirWithHDAttr(char *pName, int dir_num); // make sub-directory with HIDDEN attribute ++extern int FILE_MakeHideDir(char *pName, int dir_num); ++extern int FILE_Create(char *pName, unsigned short type, int dir_num); // create a file. ++extern int FILE_CreateLFN(void *pName, unsigned short type, int dir_num); // create a file that name has unicode ++extern int FILE_RemoveByEntryId(int dir_num, int file_id); // remove a file ++extern int FILE_Change2ParentDir(int dir_num); //change directory to parent directory ++extern int FILE_Refresh(int dir_num); // reload current directory information ++extern unsigned long FILE_TotalDiskCluster(int drvTypeID); ++extern unsigned long FILE_AvailableDiskCluster(int drvTypeID); // get free size of the current drive ++extern unsigned long FILE_GetClusterSize(int drvTypeID); ++extern int FILE_OpenName(char *pName, char *mode, int dir_num); ++extern int FILE_OpenDirName(char *pName, char *mode, int dir_num); ++extern int FILE_ReadDir(int mode, int dir_num, FDIRENTstruc *pFDir, DIRENTstruc *pEnt); ++extern void FILE_InitFDIRstruc(FDIRENTstruc *pFDir); ++extern int FILE_OpenDirWithCluster(int partID, unsigned long dir_cluster, int dir_num); ++extern int FILE_Copy(int dir_num, int sHandle, long *copy_status); ++extern int FILE_Format(int drvTypeID, int partID, unsigned char writeVolume, ++ unsigned char SecPerClus, unsigned int CntOfClus, struct _DISK_INFO *disk); ++ ++extern int FILE_FormatMBR(int drvTypeID, unsigned char writeVolume, unsigned char SecPerClus, unsigned int *numOfSecPR, unsigned int *validFAT, struct _DISK_INFO *disk); ++ ++ ++extern int FILE_DiskInfo(int partID, DRVINFOstruc *pDrive); ++extern int FILE_GetValidPartNum(void); ++extern int FILE_RemoveDirByEntryId(int dir_num, int dir_id); ++extern int FILE_RemoveWithHandle(int dir_num, int nHandle); ++extern void FILE_UpdateDate(unsigned short year, unsigned char month, unsigned char day); ++extern void FILE_UpdateTime(unsigned char hours, unsigned char min, unsigned char sec); ++extern int FILE_CheckRootDir(int dir_num); ++extern int FILE_GetUsedClusters(int drvTypeID); ++extern int FILE_RenameLFN(int nHandle, void *pName, int dir_num); ++extern int FILE_OpenDirOnlySearch(int partID, unsigned long dir_cluster, int dir_num); ++ ++ ++#ifdef NED_INCLUDE ++#include "NED/NED_FS.H" ++#else ++extern int FILE_OpenByEntryId(int file_id, unsigned long mode, int dir_num); // open a file. get handle ++extern int FILE_Close(int nHandle); // close a file. return handle ++extern int FILE_Read(int nHandle, void *pBuff, int size); // read a file ++extern int FILE_Seek(int nHandle, long offset, int whence); // move file pointer. ++extern int FILE_Read_bs(int nHandle, void *pBuff, int size); // special function ++extern long FILE_Tell(int nHandle); // get a current file pointer ++extern int FILE_Length(int nHandle); // get a current file size ++#endif ++ ++#endif ++ +diff --git a/drivers/block/tcc/inc/fwdn/fwdn_drv_v3.h b/drivers/block/tcc/inc/fwdn/fwdn_drv_v3.h +new file mode 100644 +index 0000000..8471c96 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwdn_drv_v3.h +@@ -0,0 +1,172 @@ ++/**************************************************************************** ++ * FileName : Fwdn_drv_v3.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++#ifndef _FWDN_DRV_V3_H_ ++#define _FWDN_DRV_V3_H_ ++ ++#if defined(_LINUX_) ++#include ++#elif defined(_WINCE_) ++#include "nand_drv.h" ++#endif ++ ++enum ++{ ++ ERR_FWDN_DRV_WRONG_PARAMETER = 0x10000000, ++ ERR_FWDN_DRV_DISK_IOCTRL_DEV_INITIALIZE, ++ ERR_FWDN_DRV_DISK_COMPARE, ++ ERR_FWDN_DRV_DISK_WRITE, ++ ERR_FWDN_DRV_DISK_READ, ++}; ++ ++enum ++{ ++ FWDN_DRV_TARGET_NAND = 1, ++ FWDN_DRV_TARGET_NOR, ++ FWDN_DRV_TARGET_TRIFLASH, ++ FWDN_DRV_TARGET_EEPROM, ++ FWDN_DRV_TARGET_SFLASH, ++ FWDN_DRV_TARGET_HDD ++}; ++ ++enum ++{ ++ FWDN_DISK_NONE, ++ FWDN_DISK_HDD, ++ FWDN_DISK_MMC, ++ FWDN_DISK_UHP, ++ FWDN_DISK_NAND, ++ FWDN_DISK_TRIFLASH, ++ FWDN_DISK_NOR, ++ FWDN_DISK_SFLASH, ++ FWDN_DISK_MAX ++}; ++ ++enum ++{ ++ SN_NOT_EXIST = 0, ++ SN_VALID_16, ++ SN_INVALID_16, ++ SN_VALID_32, ++ SN_INVALID_32 ++}; ++ ++ ++typedef int (*fpFWDN_DRV_FirmwareWrite_ReadFromHost)(unsigned char *buff, unsigned int size, unsigned int srcAddr, unsigned int percent); ++typedef int (*FXN_FWDN_DRV_RquestData)(unsigned char *buff, unsigned int size); ++typedef unsigned int (*FXN_FWDN_DRV_ReadFromHost)(void *buff, unsigned int size); ++typedef unsigned int (*FXN_FWDN_DRV_SendToHost)(void *buff, unsigned int size); ++ ++typedef struct _tag_DeviceInfoType { ++ unsigned int DefaultDiskType; // Default Disk Type. nand, tri-flash, hdd ... ++ unsigned int DevSerialNumberType; // Device Serial Number type SN_NOT_EXIST.. ++ unsigned char DevSerialNumber[32]; ++} FWDN_DEVICE_INFORMATION, *pFWDN_DEVICE_INFORMATION; ++ ++typedef struct _tag_NAND_HiddenSizeInfo { ++ unsigned int HiddenPageSize; // Default Hidden Area Pages ++ unsigned int MultiHiddenAreaNum; // Multi Hidden Num ++ unsigned int MultiHiddenSize[8]; // Multi Hidden Configuration ++ unsigned int ROAreaSize; ++} NAND_HIDDEN_INFO, *pNAND_HIDDEN_INFO; ++ ++typedef struct _tag_NAND_DISK_INFO_T { ++ unsigned int bootSize_MB; ++ unsigned int totalSize_MB; ++ unsigned int multiHiddenSystemSize_MB; ++} NAND_DISK_INFO_T; ++ ++typedef struct __NAND_DeviceInfo { ++ unsigned short int DevID[8]; ++ unsigned int MediaNums; // Media Number of NANDFLASH ++ unsigned int MAX_ROMSize; ++ unsigned int ExtendedPartitionNum; ++ unsigned int ExtPartitionSize[12]; ++ unsigned int ExtPartitionWCacheNum[12]; ++ unsigned int ROAreaSize; ++ unsigned short int PBpV; // Physical all Block Number ++ unsigned short int PpB; // Page Number Per Block ++ unsigned short int PageSize; // Page Size ++ unsigned short int SpareSize; ++} NAND_DEVICE_INFO, *pNAND_DEVICE_INFO; ++ ++#ifdef TRIFLASH_INCLUDE ++#define MMC_DISK_MAX_HIDDEN_NUMBER 4 ++ ++typedef struct _tag_MMC_DISK_INFO_T { ++ unsigned int nTotalSector; ++ unsigned int nBootSector; ++ unsigned int nHiddenNum; ++ unsigned int nHiddenSector[MMC_DISK_MAX_HIDDEN_NUMBER]; ++ unsigned int nBytePerSector; ++} MMC_DISK_INFO_T; ++#endif ++//============================================================== ++// ++// Global Variables ++// ++//============================================================== ++extern FWDN_DEVICE_INFORMATION FWDN_DeviceInformation; ++extern unsigned int gFWDN_DRV_ErrorCode; ++ ++#define FWDN_DRV_GetErrorCode() gFWDN_DRV_ErrorCode ++#define FWDN_DRV_ClearErrorCode() gFWDN_DRV_ErrorCode = 0 ++#define FWDN_DRV_SetErrorCode(a) gFWDN_DRV_ErrorCode = a ++ ++//============================================================== ++// ++// Function Prototypes ++// ++//============================================================== ++void initSourcePosition(void); ++int setSourcePosition(int offset); ++ ++void FWDN_InitCACHE(void); ++void FWDN_SetRWSize(unsigned long uSize); ++ ++void FWDN_DRV_SaveSdCfg(unsigned int sdCfg); ++unsigned int FWDN_DRV_GetSdCfg(void); ++pFWDN_DEVICE_INFORMATION FWDN_DRV_GetDeviceInfo(void); ++int FWDN_DRV_SerialNumberWrite(unsigned char *serial, unsigned int overwrite); ++int FWDN_DRV_FirmwareWrite(unsigned int fwSize, unsigned int TargetMemType, fpFWDN_DRV_FirmwareWrite_ReadFromHost fFWDN_DRV_FirmwareWrite_ReadFromHost); ++int FWDN_DRV_FirmwareWrite_Read(unsigned char *buff, unsigned int size, unsigned int percent); ++ ++void FWDN_DRV_DISK_Select(unsigned char fwdnDiskType); ++int FWDN_DRV_DISK_Init(TNFTL_CALLBACK_HANDLER pCallBackHandler, unsigned int stage, void *pInfo, unsigned short infoSize); ++void FWDN_DRV_DISK_InfoRead(void *pDiskInfo, unsigned char *pSize); ++ ++int FWDN_DRV_DISK_Read(unsigned int lba, unsigned int size, FXN_FWDN_DRV_SendToHost fxnFwdnDrvSendToHost); ++int FWDN_DRV_DISK_Write(unsigned int lba, unsigned int size, FXN_FWDN_DRV_ReadFromHost fxnFwdnDrvReadFromHost); ++ ++void FWDN_DRV_DISK_Hidden_InfoRead(void *pInfo, unsigned char *pSize); ++int FWDN_DRV_DISK_Hidden_Clean(void); ++int FWDN_DRV_DISK_Hidden_Write(unsigned int index, unsigned int startpage, unsigned int sizebyte, FXN_FWDN_DRV_RquestData fxnFwdnDrvRequestData); ++int FWDN_DRV_DISK_MTD_Write(unsigned int startpage, unsigned int sizebyte, FXN_FWDN_DRV_ReadFromHost fxnFwdnDrvReadFromHost); ++ ++int FWDN_DRV_DISK_DATA_Partition(void *pMultiPartitionSizeArray, unsigned int length); ++int FWDN_DRV_DISK_DATA_Image_Write(unsigned int nPartitionID, unsigned int offset, unsigned int size, FXN_FWDN_DRV_RquestData fxnFwdnDrvRequestData); ++int FWDN_DRV_DISK_FS_Mount(unsigned int partID); ++int FWDN_DRV_DISK_FS_Format(unsigned int partID, char *volumeParam); ++int FWDN_DRV_DISK_FS_MkDir(unsigned char *name); ++int FWDN_DRV_DISK_FS_ChDir(unsigned char *name); ++int FWDN_DRV_DISK_FS_FileWrite(unsigned char *name, unsigned int size, FXN_FWDN_DRV_RquestData fxnFwdnDrvRequestData); ++ ++unsigned char FWDN_DRV_DISK_DUMP_InfoRead(unsigned char *pBuf); ++int FWDN_DRV_DISK_DUMP_BlockRead(unsigned int Param0, unsigned int Param1, unsigned int Param2, FXN_FWDN_DRV_SendToHost fxnFwdnDrvSendToHost); ++ ++unsigned int FWDN_FNT_SetSN(unsigned char* ucTempData, unsigned int uiSNOffset); ++void FWDN_FNT_VerifySN(unsigned char* ucTempData, unsigned int uiSNOffset); ++void FWDN_FNT_InsertSN(unsigned char *pSerialNumber); ++unsigned char FWDN_DRV_FirmwareMemoryType(void); ++#endif // _FWDN_DRV_H_ ++ ++/* end of file */ ++ +diff --git a/drivers/block/tcc/inc/fwdn/fwdn_drv_v7.h b/drivers/block/tcc/inc/fwdn/fwdn_drv_v7.h +new file mode 100644 +index 0000000..ffd38bf +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwdn_drv_v7.h +@@ -0,0 +1,158 @@ ++/**************************************************************************** ++ * FileName : Fwdn_drv_v7.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++#ifndef _FWDN_DRV_V7_H_ ++#define _FWDN_DRV_V7_H_ ++ ++#define FWDN_DEVICE_INIT_BITMAP_LOW_FORMAT (1<<0) ++#define FWDN_DEVICE_INIT_BITMAP_DUMP (1<<1) ++#define FWDN_DEVICE_INIT_BITMAP_UPDATE (1<<2) ++#define FWDN_DEVICE_INIT_BITMAP_LOW_FORMAT_LEVEL2 (1<<3) ++ ++enum ++{ ++ ERR_FWDN_DRV_WRONG_PARAMETER = 0x10000000, ++ ERR_FWDN_DRV_IOCTRL_DEV_INITIALIZE, ++ ERR_FWDN_DRV_AREA_WRITE_COMPARE, ++ ERR_FWDN_DRV_RESET_NOT_SUPPORT, ++ ERR_FWDN_DRV_INSUFFICIENT_MEMORY, ++ ERR_FWDN_DRV_AREA_WRITE, ++ ERR_FWDN_DRV_AREA_READ, ++}; ++ ++enum ++{ ++ FWDN_DISK_NONE, ++ FWDN_DISK_HDD, ++ FWDN_DISK_MMC, ++ FWDN_DISK_UHP, ++ FWDN_DISK_NAND, ++ FWDN_DISK_TRIFLASH, ++ FWDN_DISK_NOR, ++ FWDN_DISK_SFLASH, ++ FWDN_DISK_MAX ++}; ++ ++enum ++{ ++ SN_NOT_EXIST = 0, ++ SN_VALID_16, ++ SN_INVALID_16, ++ SN_VALID_32, ++ SN_INVALID_32 ++}; ++ ++ ++typedef int (*FXN_FWDN_DRV_FirmwareWrite_ReadFromHost)(unsigned char *buff, unsigned int size, unsigned int srcAddr, unsigned int percent); ++typedef unsigned int (*FXN_FWDN_DRV_ReadFromHost)(void *buff, unsigned int size); ++typedef unsigned int (*FXN_FWDN_DRV_SendToHost)(void *buff, unsigned int size); ++typedef void (*FXN_FWDN_DRV_Response_RequestData)(unsigned int dataSize); ++typedef int (*FXN_FWDN_DRV_RquestData)(unsigned char *buff, unsigned int size); ++typedef void (*FXN_FWDN_DRV_SendStatus)(unsigned int param0, unsigned int param1, unsigned int param2); ++typedef void (*FXN_FWDN_DRV_Progress)( unsigned int percent ); ++ ++typedef struct _tag_FWDN_AREA_T { ++ unsigned int nSector; ++ char name[16]; ++} FWDN_AREA_T; ++ ++#define FWDN_AREA_LIST_MAX 20 ++typedef struct _tag_DeviceInfoType { ++ unsigned int DevSerialNumberType; // Device Serial Number type SN_NOT_EXIST.. ++ unsigned char DevSerialNumber[32]; ++ FWDN_AREA_T area[FWDN_AREA_LIST_MAX]; // Default Area = area[0] ++} FWDN_DEVICE_INFORMATION, *pFWDN_DEVICE_INFORMATION; ++ ++typedef struct _tag_NAND_HiddenSizeInfo { ++ unsigned int HiddenNum; // Total Hidden Area Num ++ unsigned int HiddenPageSize[12]; // Each Hidden Area's Size ++ unsigned int RO_PageSize; ++} NAND_PARTITION_INFO, *pNAND_HIDDEN_INFO; ++ ++ typedef struct __NAND_DeviceInfo { ++ unsigned short int DevID[8]; ++ unsigned int MediaNums; // Media Number of NANDFLASH ++ unsigned int MAX_ROMSize; ++ unsigned int ExtendedPartitionNum; ++ unsigned int ExtPartitionSize[12]; ++ unsigned int ExtPartitionWCacheNum[12]; ++ unsigned int ROAreaSize; ++ unsigned short int PBpV; // Physical all Block Number ++ unsigned short int PpB; // Page Number Per Block ++ unsigned short int PageSize; // Page Size ++ unsigned short int SpareSize; ++} NAND_DEVICE_INFO, *pNAND_DEVICE_INFO; ++ ++typedef struct _tag_NAND_DISK_INFO_T { ++ unsigned int bootSize_MB; ++ unsigned int diskSize_MB; ++} NAND_DISK_INFO_T; ++ ++//============================================================== ++// ++// Global Variables ++// ++//============================================================== ++extern FWDN_DEVICE_INFORMATION FWDN_DeviceInformation; ++extern unsigned int gFWDN_DRV_ErrorCode; ++ ++#define FWDN_DRV_GetErrorCode() gFWDN_DRV_ErrorCode ++#define FWDN_DRV_ClearErrorCode() gFWDN_DRV_ErrorCode = 0 ++#define FWDN_DRV_SetErrorCode(a) gFWDN_DRV_ErrorCode = a ++ ++//============================================================== ++// ++// Function Prototypes ++// ++//============================================================== ++void initSourcePosition(void); ++ ++//void FWDN_CheckOption(void); ++ ++// for Device ++void FWDN_DRV_Reset(void); ++int FWDN_DRV_SessionStart(void); ++int FWDN_DRV_SessionEnd(unsigned int bSuccess); ++int FWDN_DRV_Init(unsigned int bmFlag, const FXN_FWDN_DRV_Progress fxnFwdnDrvProgress, char *message, unsigned int messageSize); ++pFWDN_DEVICE_INFORMATION FWDN_DRV_GetDeviceInfo(void); ++int FWDN_DRV_SerialNumberWrite(unsigned char *serial, unsigned int overwrite); ++int FWDN_DRV_FirmwareWrite(unsigned int fwSize, FXN_FWDN_DRV_FirmwareWrite_ReadFromHost fxnFWDN_DRV_FirmwareWrite_ReadFromHost); ++int FWDN_DRV_FirmwareWrite_Read(unsigned char *buff, unsigned int size, unsigned int percent); ++ ++#if 0//TNFTL_V7_INCLUDE ++int FWDN_DRV_NAND_GANG_Format(void); ++int FWDN_DRV_NAND_GANG_Write( NAND_PART_INFO *sNandPartInfo, FXN_FWDN_DRV_RquestData fxnFwdnDrvRequestData ); ++#endif ++ ++// for Disk ++int FWDN_DRV_AREA_Write(char *name, unsigned int lba, unsigned int nSector, FXN_FWDN_DRV_RquestData fxnFwdnDrvRequestData); ++int FWDN_DRV_AREA_CalcCRC( char *name ++ ,unsigned int lba ++ ,unsigned int nSector ++ ,unsigned int *pCrc ++ ,FXN_FWDN_DRV_SendStatus fxnFwdnDrvSendStatus ); ++ ++unsigned char FWDN_DRV_DUMP_InfoRead(void *pBuf); ++int FWDN_DRV_DUMP_BlockRead(unsigned int Param0, unsigned int Param1, unsigned int Param2, ++ FXN_FWDN_DRV_Response_RequestData fxnFwdnDrvResponseRequestData, ++ FXN_FWDN_DRV_SendToHost fxnFwdnDrvSendToHost); ++int FWDN_DRV_DUMP_BlockWrite(unsigned int Param0, unsigned int Param1, unsigned int Param2, ++ FXN_FWDN_DRV_Response_RequestData fxnFwdnDrvResponseRequestData, ++ FXN_FWDN_DRV_ReadFromHost fxnFwdnDrvReadFromHost); ++ ++unsigned int FWDN_FNT_SetSN(unsigned char* ucTempData, unsigned int uiSNOffset); ++void FWDN_FNT_VerifySN(unsigned char* ucTempData, unsigned int uiSNOffset); ++void FWDN_FNT_InsertSN(unsigned char *pSerialNumber); ++unsigned char FWDN_DRV_FirmwareStorageID(void); ++#endif // _FWDN_DRV_V7_H_ ++ ++/* end of file */ ++ +diff --git a/drivers/block/tcc/inc/fwdn/fwdn_protocol_v3.h b/drivers/block/tcc/inc/fwdn/fwdn_protocol_v3.h +new file mode 100644 +index 0000000..f330e29 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwdn_protocol_v3.h +@@ -0,0 +1,117 @@ ++#ifndef __FWDN_PROTOCOL_V2__ ++#define __FWDN_PROTOCOL_V2__ ++ ++//////////////////////////////////////////////////////////////////////////// ++// ++// FWDN Protocol V3 ++// ++//////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Command ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_CMD_NONE 0x0000 ++#define FWDN_CMD_UBS_PING 0x0001 ++#define FWDN_CMD_UBS_INITCODE_LOAD 0x0002 ++#define FWDN_CMD_UBS_ROM_LOAD 0x0003 ++ ++#define FWDN_CMD_PING 0x0100 ++#define FWDN_CMD_DEVICE_RESET 0x0101 ++#define FWDN_CMD_DEVICE_SETTING 0x0102 ++#define FWDN_CMD_DEVICE_INFO_READ 0x0103 ++#define FWDN_CMD_SERIAL_NUMBER_WRITE 0x0104 ++#define FWDN_CMD_FIRMWARE_WRITE 0x0105 ++#define FWDN_CMD_SESSION_START 0x0106 ++#define FWDN_CMD_SESSION_END 0x0107 ++ ++#define FWDN_CMD_DISK_SELECT 0x0200 ++#define FWDN_CMD_DISK_INIT 0x0201 ++#define FWDN_CMD_DISK_INFO_READ 0x0202 ++ ++#define FWDN_CMD_DISK_HIDDEN_INFO_READ 0x0210 ++#define FWDN_CMD_DISK_HIDDEN_CLEAN 0x0211 ++#define FWDN_CMD_DISK_HIDDEN_WRITE 0x0212 ++#define FWDN_CMD_DISK_HIDDEN_READ 0x0213 ++#define FWDN_CMD_DISK_MTD_WRITE 0x0214 ++ ++#define FWDN_CMD_DISK_DATA_PARTITION 0x0220 ++#define FWDN_CMD_DISK_DATA_READ 0x0221 ++#define FWDN_CMD_DISK_DATA_WRITE 0x0222 ++#define FWDN_CMD_DISK_DATA_IMAGE_WRITE 0x0223 ++ ++#define FWDN_CMD_DISK_DATA_FS_MOUNT 0x0230 ++#define FWDN_CMD_DISK_DATA_FS_FORMAT 0x0231 ++#define FWDN_CMD_DISK_DATA_FS_MKDIR 0x0232 ++#define FWDN_CMD_DISK_DATA_FS_CHDIR 0x0233 ++#define FWDN_CMD_DISK_DATA_FS_FILE_WRITE 0x0234 ++ ++#define FWDN_CMD_DISK_DUMP_INFO_READ 0x0240 ++#define FWDN_CMD_DISK_DUMP_BLOCK_READ 0x0241 ++ ++#define FWDN_CMD_TEST_SEND 0x0300 ++#define FWDN_CMD_TEST_RECEIVE 0x0301 ++ ++#define FWDN_CMD_TNFTL_V5_DEBUG 0x0F00 ++ ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Response Ack Type ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_RSP_NACK 0x00 ++#define FWDN_RSP_ACK 0x01 ++#define FWDN_RSP_NYET 0x02 ++ ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Command / Response Signatures ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_COMMAND_SIGNATURE 0x43445746L //"FWDC" ; FWDn Command ++#define FWDN_RESPONSE_SIGNATURE 0x52445746L //"FWDR" ; FWDn Response ++ ++ ++#define FWDN_EXTRA_RSP_MAX_SIZE 0xFF ++ ++#if defined(_WINCE_) ++#pragma pack(push, 1) ++#endif ++ ++typedef struct _tag_FWDN_COMMAND_T ++{ ++ unsigned long Signature; ++ unsigned short CmdType; ++ unsigned short ExtraCmdSize; ++ unsigned long DataSize; ++ unsigned long Param0; ++ unsigned long Param1; ++ unsigned long Param2; ++ ++#if defined(_LINUX_) ++} __attribute__((packed)) FWDN_COMMAND_T; ++#else ++} FWDN_COMMAND_T; ++#endif ++ ++typedef struct _tag_FWDN_RESPONSE_T ++{ ++ unsigned long Signature; ++ unsigned short CmdType; ++ unsigned char AckType; ++ unsigned char ExtraRspSize; ++ unsigned long DataSize; ++ unsigned long Param0; ++ unsigned long Param1; ++ unsigned long Param2; ++ ++#if defined(_LINUX_) ++} __attribute__((packed)) FWDN_RESPONSE_T; ++#else ++} FWDN_RESPONSE_T; ++#endif ++ ++#if defined(_WINCE_) ++#pragma pack(pop) ++#endif ++ ++void FWDN_PROT_CheckCommand(void); ++ ++#endif //__FWDN_PROTOCOL_V2__ +diff --git a/drivers/block/tcc/inc/fwdn/fwdn_protocol_v7.h b/drivers/block/tcc/inc/fwdn/fwdn_protocol_v7.h +new file mode 100644 +index 0000000..a09e0dc +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwdn_protocol_v7.h +@@ -0,0 +1,121 @@ ++#ifndef __FWDN_PROTOCOL_V7__ ++#define __FWDN_PROTOCOL_V7__ ++ ++//////////////////////////////////////////////////////////////////////////// ++// ++// FWDN Protocol V7 ++// ++//////////////////////////////////////////////////////////////////////////// ++#define FEATURE_FWDN_COMM_VTC ++ ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Command ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_CMD_NONE 0x0000 ++ ++#define FWDN_CMD_UBS_PING 0x0001 ++#define FWDN_CMD_UBS_INITCODE_LOAD 0x0002 ++#define FWDN_CMD_UBS_ROM_LOAD 0x0003 ++ ++#define FWDN_CMD_DEVICE_RESET 0x0100 ++#define FWDN_CMD_DEVICE_PING 0x0101 ++#define FWDN_CMD_DEVICE_INIT 0x0102 ++#define FWDN_CMD_DEVICE_INFO_READ 0x0103 ++#define FWDN_CMD_DEVICE_SESSION_START 0x0104 ++#define FWDN_CMD_DEVICE_SESSION_END 0x0105 ++#define FWDN_CMD_DEVICE_SERIAL_NUMBER_WRITE 0x0106 ++#define FWDN_CMD_DEVICE_FIRMWARE_WRITE 0x0107 ++ ++#define FWDN_CMD_AREA_INFO_READ 0x0200 ++#define FWDN_CMD_AREA_WRITE 0x0201 ++#define FWDN_CMD_AREA_READ 0x0202 ++#define FWDN_CMD_AREA_CALC_CRC 0x0203 ++ ++#define FWDN_CMD_DUMP_INFO_READ 0x0300 ++#define FWDN_CMD_DUMP_BLOCK_READ 0x0301 ++#define FWDN_CMD_DUMP_BLOCK_WRITE 0x0302 ++ ++#define FWDN_CMD_TNFTL_V5_DEBUG 0x0F00 ++ ++#define FWDN_CMD_NAND_GANG_CLEAR 0x1000 ++#define FWDN_CMD_NAND_GANG_WRITE 0x1001 ++ ++#define FWDN_CMD_TEST_SEND 0xEF00 ++#define FWDN_CMD_TEST_RECEIVE 0xEF01 ++ ++///////////////////////////////////////////////////////// ++// 0xF000 ~ 0xFFFF is reserved for vendor ++///////////////////////////////////////////////////////// ++ ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Response Ack Type ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_RSP_NACK 0x00 ++#define FWDN_RSP_ACK 0x01 ++#define FWDN_RSP_NYET 0x02 ++ ++ ++//////////////////////////////////////////////////////////////////////////// ++// FWDN Command / Response Signatures ++//////////////////////////////////////////////////////////////////////////// ++#define FWDN_COMMAND_SIGNATURE 0x43445746L //"FWDC" ; FWDn Command ++#define FWDN_RESPONSE_SIGNATURE 0x52445746L //"FWDR" ; FWDn Response ++ ++ ++#define FWDN_EXTRA_RSP_MAX_SIZE 0xFF ++ ++ ++#if defined(_WINCE_) ++#pragma pack(push, 1) ++#endif ++ ++typedef struct _tag_FWDN_COMMAND_T ++{ ++ unsigned long Signature; ++ unsigned short CmdType; ++ unsigned short SubCmdType; ++ unsigned long ExtraCmdSize; ++ unsigned long Param0; ++ unsigned long Param1; ++ unsigned long Param2; ++ unsigned long Param3; ++ unsigned long Param4; ++ ++#if defined(_LINUX_) ++} __attribute__((packed)) FWDN_COMMAND_T; ++#else ++} FWDN_COMMAND_T; ++#endif ++ ++typedef struct _tag_FWDN_RESPONSE_T ++{ ++ unsigned long Signature; ++ unsigned short CmdType; ++ unsigned char AckType; ++ unsigned char reserved; ++ unsigned long DataSize; ++ unsigned long Param0; ++ unsigned long Param1; ++ unsigned long Param2; ++ ++#if defined(_LINUX_) ++} __attribute__((packed)) FWDN_RESPONSE_T; ++#else ++} FWDN_RESPONSE_T; ++#endif ++ ++#if defined(_WINCE_) ++#pragma pack(pop) ++#endif ++ ++typedef enum { ++ FWDN_COMM_VTC, ++ FWDN_COMM_CDC ++} FWDN_COMM_T; ++ ++void FWDN_PROT_SetComm(FWDN_COMM_T commType); ++void FWDN_PROT_CheckCommand(void); ++ ++#endif //__FWDN_PROTOCOL_V4__ +diff --git a/drivers/block/tcc/inc/fwdn/fwupgrade.h b/drivers/block/tcc/inc/fwdn/fwupgrade.h +new file mode 100644 +index 0000000..3ee0915 +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwupgrade.h +@@ -0,0 +1,178 @@ ++/**************************************************************************** ++ * FileName : fwupgrade.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++#ifndef _FWUPGRADE_H_ ++#define _FWUPGRADE_H_ ++ ++#if defined(_LINUX_) ++#include ++//#include ++#elif defined(_WINCE_) ++//#include "main.h" ++#endif ++ ++//********************************************************************** ++//* Define FWUG Library version for ChipSet ++//********************************************************************** ++#if 0 ++#if defined(NU_FILE_INCLUDE) ++ #if defined(TCC78X) ++ #define FWUG_V1_INCLUDE ++ #else ++ #define FWUG_V2_INCLUDE ++ #endif ++#else /* K-FILESYSTEM */ ++#define FWUG_V1_INCLUDE ++#endif ++#else ++ #define FWUG_V2_INCLUDE //twkwon ++#endif ++ ++//***************************************************************************** ++//* ++//* ++//* [ General DEFINE & TYPEDEF ] ++//* ++//* ++//***************************************************************************** ++#ifndef ON ++#define ON 0x01 ++#endif ++#ifndef OFF ++#define OFF 0x00 ++#endif ++#ifndef DISABLE ++#define DISABLE 0 ++#endif ++#ifndef ENABLE ++#define ENABLE 1 ++#endif ++#ifndef FALSE ++#define FALSE 0 ++#endif ++#ifndef TRUE ++#define TRUE (!FALSE) ++#endif ++#ifndef NULL ++#define NULL (0) ++#endif ++ ++#if 0 ++#ifndef U8 ++typedef unsigned char U8; ++#endif ++#ifndef U16 ++typedef unsigned short int U16; ++#endif ++#ifndef U32 ++typedef unsigned int U32; ++#endif ++#endif ++ ++enum ++{ ++ FIRST = 0, ++ SECOND, ++ REPETITIONNUM ++}; ++ ++//***************************************************************************** ++//* ++//* ++//* [ ERROR CODE ENUMERATION ] ++//* ++//* ++//***************************************************************************** ++#ifndef SUCCESS ++#define SUCCESS 0 ++#endif ++ ++typedef enum ++{ ++ ERR_FWUG_NOT_EXISTMEMORY = 0x1000, ++ ERR_FWUG_FAIL_OPENROMFILE, ++ ERR_FWUG_FAIL_CLOSEROMFILE, ++ ERR_FWUG_FAIL_READROMFILE, ++ ERR_FWUG_CANCEL_FWUPGRADE, ++ ERR_FWUG_FAIL_BATCHECK, ++ ERR_FWUG_FAIL_ROMFILESIZEBIG, ++ ERR_FWUG_FAIL_GETGOODBLOCKLIST, ++ ERR_FWUG_NOT_EXISTSERIALNUM, ++ ERR_FWUG_FAIL_GMCDATAWRITE, ++ ERR_FWUG_FAIL_GMCSPAREWRITE, ++ ERR_FWUG_FAIL_CODEDATAWRITE, ++ ERR_FWUG_FAIL_CODESPAREWRITE, ++ ERR_FWUG_FAIL_MCDATAWRITE, ++ ERR_FWUG_FAIL_MCSPAREWRITE, ++ ERR_FWUG_FAIL_FWUPGRADE, ++ ERR_FWUG_FAIL_CHECK_TFLASH, ++ ERR_FWUG_FAIL_SCAN_TFLASH, ++ ERR_FWUG_FAIL_CODEWRITETFLASH, ++ ERR_FWUG_FAIL_CODEREADTFLASH, ++ ERR_FWUG_FAIL_HEADERWRITETFLASH, ++ ERR_FWUG_FAIL_HEADERREADTFLASH, ++ ERR_FWUG_FAIL ++} FWUG_ERROR; ++ ++typedef int (*fFWUG_ReadDATA)(unsigned int uDest, unsigned int uSize, unsigned int percent); ++ ++extern const unsigned int CRC32_TABLE[]; ++ ++//***************************************************************************** ++//* ++//* ++//* [ EXTERNAL FUCTIONS DEFINE ] ++//* ++//* ++//***************************************************************************** ++extern unsigned char gFW_FirmwareDevice, gFW_SerialNumberDevice; ++ ++extern char *FWUG_GetTempBuffer(unsigned int *uiBufSize); ++extern int FWUG_ReadDATA(unsigned int uDest, void *uHandler, unsigned int uSize, unsigned int percent); ++extern unsigned int CalCRC_ROMFile(unsigned int *pBuffer,unsigned int size,unsigned int crcout, unsigned int mode); ++extern int FWUG_VerifySerialNumber(unsigned char* ucBuf, unsigned int uiOffset); ++ ++extern unsigned int FWUG_CalcCrc(unsigned int *base, unsigned int length, const unsigned int *crctable); ++extern unsigned int FWUG_CalcCrc8(unsigned char *base, unsigned int length, const unsigned int *crctable); ++extern unsigned int FWUG_CalcCrcI(unsigned uCRCIN, unsigned *base, unsigned int length, const unsigned int *crctable); ++extern unsigned int FWUG_CalcCrc8I(unsigned uCRCIN, unsigned char *base, unsigned int length, const unsigned int *crctable); ++ ++/* TFLASH */ ++extern unsigned int FwdnReadTriflashFirmware(unsigned int master); ++extern int FwdnWriteTriflashFirmware(unsigned uFWSize); ++extern int FwdnGetTriflashSerial(void); ++extern int FwdnSetTriflashSerial(unsigned char *ucData, unsigned int overwrite); ++extern int FwdnClearTriflashHiddenArea(void); ++/* HDD */ ++extern int FwdnClearHddHiddenArea(void); ++/* NOR */ ++extern unsigned int FwdnReadNorFlashFirmware(unsigned int master); ++extern int FwdnWriteNorFlashFirmware(unsigned uFWSize); ++extern int FwdnGetNorSerial(void); ++extern int FwdnSetNorSerial(unsigned char *ucData, unsigned int overwrite); ++/* NAND */ ++extern unsigned int FwdnReadNandFirmware(unsigned int master); ++extern int FwdnWriteNandFirmware(unsigned uFWSize); ++extern int FwdnGetNandSerial(void); ++extern int FwdnSetNandSerial(unsigned char *ucData, unsigned int overwrite); ++extern int FwdnClearNandHiddenArea(unsigned int start, unsigned int pagesize); ++extern void FWDN_FNT_VerifySN(unsigned char* ucTempData, unsigned int uiSNOffset); ++/* SFLASH */ ++extern unsigned int FwdnReadSFlashFirmware(unsigned int master); ++extern int FwdnWriteSFlashFirmware(unsigned uSFBase, unsigned uFWBase, unsigned int uiROMFileSize); ++extern int FwdnGetSFlashSerial(void); ++extern int FwdnSetSFlashSerial(unsigned char *ucData, unsigned int overwrite); ++/* EEPROM */ ++extern int FwdnWriteEEPROMFirmware(unsigned uFWSize); ++ ++#endif // _FWUPGRADE_H_ ++ ++/* end of file */ ++ +diff --git a/drivers/block/tcc/inc/fwdn/fwupgrade_NAND_v6.h b/drivers/block/tcc/inc/fwdn/fwupgrade_NAND_v6.h +new file mode 100644 +index 0000000..6f6a31c +--- /dev/null ++++ b/drivers/block/tcc/inc/fwdn/fwupgrade_NAND_v6.h +@@ -0,0 +1,162 @@ ++/**************************************************************************** ++ * FileName : fwupgrade_NAND.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++#ifndef _FWUPGRADE_NAND_H_ ++#define _FWUPGRADE_NAND_H_ ++ ++#if defined(NAND_BOOT_REV) ++ #if defined(_LINUX_) ++ #include ++ #elif defined(_WINCE_) ++ #include "tnftl_v7.h" ++ #else ++ #include "tnftl_v7.h" ++ #endif ++#else ++ #if defined(_LINUX_) ++ #include ++ #elif defined(_WINCE_) ++ #include "tnftl_v6.h" ++ #else ++ #include "tnftl_v6.h" ++ #endif ++#endif ++ ++//***************************************************************************** ++//* ++//* ++//* [ General DEFINE & TYPEDEF ] ++//* ++//* ++//***************************************************************************** ++#ifndef ON ++#define ON 0x01 ++#endif ++#ifndef OFF ++#define OFF 0x00 ++#endif ++#ifndef DISABLE ++#define DISABLE 0 ++#endif ++#ifndef ENABLE ++#define ENABLE 1 ++#endif ++#ifndef FALSE ++#define FALSE 0 ++#endif ++#ifndef TRUE ++#define TRUE 1 ++#endif ++#ifndef NAND_TYPE_PURE_NAND ++#define NAND_TYPE_PURE_NAND 0 ++#endif ++#ifndef NAND_TYPE_LBA_NAND ++#define NAND_TYPE_LBA_NAND 1 ++#endif ++ ++//***************************************************************************** ++//* ++//* ++//* [ EXTERNAL GLOBAL VARIABLE DEFINE ] ++//* ++//* ++//***************************************************************************** ++#define BIG 0x04 ++#define SMALL 0x00 ++#define PARALLEL 0x08 ++#define SERIAL 0x00 ++ ++#define EXTENDED_PAGE 0x80 ++#define NORMAL_PAGE 0x00 ++#define WIDE_SPARE 0x08 ++#define NORMAL_SPARE 0x00 ++ ++#define MAX_GOOD_BLOCK_LIST_LEN (759*2) ++ ++#if defined(TNFTL_V5_INCLUDE) || defined(TNFTL_V6_INCLUDE) ++#define FWUG_NAND_IO_READPAGE NAND_IO_ReadNBPage ++#define FWUG_NAND_IO_WRITEPAGE NAND_IO_WriteNBPage ++#else ++#define FWUG_NAND_IO_READPAGE NAND_IO_ReadPage ++#define FWUG_NAND_IO_WRITEPAGE NAND_IO_WritePage ++#endif ++ ++//***************************************************************************** ++//* ++//* ++//* [ ERROR CODE ENUMERATION ] ++//* ++//* ++//***************************************************************************** ++#ifndef SUCCESS ++#define SUCCESS 0 ++#endif ++ ++typedef enum ++{ ++ ERR_FWUG_NAND_WRONG_PARAMETER = 0x0C000000, ++ ERR_FWUG_NAND_FAILED_GET_INFO_GMC, ++ ERR_FWUG_NAND_FAILED_GET_SDCFG_FROM_MC, ++ ERR_FWUG_NAND_FAILED_READY_NB_AREA, ++ ERR_FWUG_NAND_FAILED_COPY_IMAGE, ++ ERR_FWUG_NAND_FAILED_SET_START_ADDRESS_IN_GMC, ++ ERR_FWUG_NAND_FAILED_WRITE_MASTER_CLUSTER, ++ ERR_FWUG_NAND_FAILED_ROMFILESIZE_OVER, ++ ERR_FWUG_NAND_FAILED_CHECK_CRC_ROMCODE, ++ ERR_FWUG_NAND_FAILED_WRITE_CODE_DATA, ++ ERR_FWUG_NAND_FAILED_WRITE_MC_DATA, ++ ERR_FWUG_NAND_FAILED_WRITE_GMC_DATA, ++ ERR_FWUG_NAND_FAILED_NO_BMP, ++ ERR_FWUG_NAND_FAILED_NOT_EXIST_NANDBOOT_AREA, ++ ERR_FWUG_NAND_FAILED_CHECK_CRC_MC, ++ ERR_FWUG_NAND_FAILED_NOT_EXIST_NANDBOOT_SIG, ++ ERR_FWUG_NAND_FAILED_NOT_EXIST_MC_DATA, ++ ERR_FWUG_NAND_FAILED_MEM_INITCODESIZE_OVER ++} FWUG_NAND_ERROR; ++ ++//***************************************************************************** ++//* ++//* ++//* [ EXTERNAL FUCTIONS DEFINE ] ++//* ++//* ++//***************************************************************************** ++extern void FWUG_NAND_SetEnableNandBootOnlyMode( U32 value ); ++extern void FWUG_NAND_SetParameterForMC( U32 uiSDRAMConfig, U32 uiStExeAddr ); ++extern void FWUG_NAND_SetFlagOfUseSecureMode( U32 nValue ); ++extern U32 FWUG_NAND_GetFlagOfUseSecureMode( void ); ++extern U8 FWUG_NAND_GetCurrentNANDType( void ); ++extern FWUG_NAND_ERROR FWUG_NAND_SetNBAreaEndPBAdd( U32 nPhyBlockAddr ); ++extern FWUG_NAND_ERROR FWUG_NAND_ClearHDArea( void ); ++extern FWUG_NAND_ERROR FWUG_NAND_PreProcess( U32 uiROMFileSize, U8* pFlagNewBig ); ++extern FWUG_NAND_ERROR FWUG_NAND_PostProcess( U8* nSNBuf, U32 nSNMode, U32 nSecureMode ); ++extern FWUG_NAND_ERROR FWUG_NAND_WriteCodePreProcess( U8 ucNum, U32 uiROMFileSize, U32 *rStBlockOffSet, U32 *rStPageOffSet, U32 nSecureMode ); ++#ifdef TNFTL_V7_INCLUDE ++extern FWUG_NAND_ERROR FWUG_NAND_WriteCodeNAND( U16 nRomNum, U32 nStBlockOffSet, U32 nStPageOffSet, U8 *WriteBufAddr, U32 iBufSize, U32 *rBlockOffSet, U32 *rPageOffSet, U32 nSecureMode ); ++#else ++extern FWUG_NAND_ERROR FWUG_NAND_WriteCodeNAND( U32 nStBlockOffSet, U32 nStPageOffSet, U8* WriteBufAddr, U32 iBufSize, U32 *rBlockOffSet, U32 *rPageOffSet, U32 nSecureMode ); ++#endif ++extern FWUG_NAND_ERROR FWUG_NAND_WriteCodePostProcess( U8 ucNum, U32 nStBlockOffSet, U32 nStPageOffSet ); ++extern FWUG_NAND_ERROR FWUG_NAND_GetSerialNumberNAND( U8* nSID ); ++extern unsigned int FWUG_NAND_CRCUpdate(unsigned char * pBuffer, unsigned int nBufferSize, unsigned int StCRCout, unsigned int nMode, unsigned int nRemainSize); ++ ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_GetSerialNumberNAND( U8* nSID ); ++extern void FWUG_NAND_LBA_InitVariable(U32 nCrc128k, U32 nCrc256k); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_WriteCodePreProcess(U8 ucNum, U32 uiROMFileSize, U32 * rStBlockOffSet, U32 * rStPageOffSet, U32 nSecureMode); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_WriteCodeNAND(U32 nStBlockOffSet, U32 nStPageOffSet, U8 * WriteBufAddr, U32 iBufSize, U32 * rBlockOffSet, U32 * rPageOffSet, U32 nSecureMode); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_WriteMC(unsigned char ucNum); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_WriteGMC(U8 * nSNBuf, U32 nSNMode, U32 nSecureMode); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_WriteCodetoVFP(U32 nSectorAddr, U8 * WriteBufAddr, U32 iBufSize, U32 * rSectorAddr, U32 nSecureMode); ++extern FWUG_NAND_ERROR FWUG_NAND_LBA_PostProcess(U8 nMode); ++ ++#endif // _FWUPGRADE_NAND_H_ ++ ++/* end of file */ ++ +diff --git a/drivers/block/tcc/inc/tnftl/IO_TCCXXX.h b/drivers/block/tcc/inc/tnftl/IO_TCCXXX.h +new file mode 100644 +index 0000000..cb049bd +--- /dev/null ++++ b/drivers/block/tcc/inc/tnftl/IO_TCCXXX.h +@@ -0,0 +1,3872 @@ ++/************************************************************************ ++* TELECHIPS Digital Audio Player ++* ------------------------------------------------ ++* ++* FUNCTION : ++* MODEL : TCCXXX ++* CPU NAME : TCCXXX ++* SOURCE : IO_TCCXXX.h ++* ++* START DATE : FEB. 16. 2009 ++* MODIFY DATE : FEB. 16. 2009 ++* DEVISION : DEPT. SYSTEM 3 GROUP ++* : TELECHIPS, INC. ++************************************************************************/ ++ ++ ++/**************************************************************************** ++ Revision History ++ **************************************************************************** ++ ++ 2009/02/16 : . ++ ++ ****************************************************************************/ ++ ++ ++#ifndef __IO_TCCXXX_H ++#define __IO_TCCXXX_H ++ ++#if defined(_LINUX_) ++#include ++#endif ++ ++//#define USE_IO_DEBUG ++ ++#if (defined(SDRAM_SIZE) && (SDRAM_SIZE > 0x200000)) ++#define DBG_MAXSTR_TX 0x100000 ++#else ++#define DBG_MAXSTR_TX 0x10 ++#endif ++#define DBG_BUFMASK_TX (DBG_MAXSTR_TX - 1) ++#define DBG_MAXSTR_RX 0x10 ++ ++//#define USE_DOMEASURE ++//#define CHECK_SPEED ++#define LOW_FREQ_PLL_INCLUDE ++ ++// Select EHI Slave System among the followings. ++ //#define EHIS_TCC77X ++ #define EHIS_TCC75X ++ ++//#include "main.h" ++ ++#ifdef TCC92XX ++#include "TCC92xx_Physical.h" ++#include "TCC92xx_Structures.h" ++#elif defined(TCC89XX) ++#if defined(_LINUX_) ++#include ++#include ++#elif defined(_WINCE_) ++#include "TCC89x_Physical.h" ++#include "TCC89x_Structures.h" ++#endif ++#elif defined(TCC79XX) ++#include "TCC79xx.h" ++#else ++#error "-- Not defined chip models --" ++#endif ++ ++ ++#ifdef TCC79XX ++ #define HwSDR_FIX 0x07282000 ++ #define HwSDR_RFR 0 ++ #define HwSDCFG_P0 HwSDCFG ++ #define HwSDCFG_P1 HwSDCFG ++#elif defined(TCC92XX) || defined(TCC89XX) ++ #define HwSDR_FIX 0x07282000 ++ #define HwSDR_RFR 0 ++ #define HwSDCFG_P0 HwSDCFG ++ #define HwSDCFG_P1 HwSDCFG ++#endif ++ ++#define HwSDR_RBC HwSDCFG_AM_RBC ++ ++#define HwSDR_CL3 HwSDCFG_CL ++ ++// SDRAM BusWidth ++#define HwSDR_X16 Hw30 ++#define HwSDR_X32 HwZERO ++ ++// SDRAM Size (Col, Row Address bus width) ++#define HwSDR_2MB (HwSDCFG_CW8 + HwSDCFG_RW11) ++#define HwSDR_4MB (HwSDCFG_CW8 + HwSDCFG_RW11) ++#define HwSDR_8MB (HwSDCFG_CW8 + HwSDCFG_RW12) ++#define HwSDR_16MB (HwSDCFG_CW9 + HwSDCFG_RW12) ++#define HwSDR_32MB (HwSDCFG_CW9 + HwSDCFG_RW13) ++#define HwSDR_64MB (HwSDCFG_CW10 + HwSDCFG_RW13) ++ ++ ++#if (defined(TELECHIPS_SV) && !defined(USE_IO_DEBUG)) ++ //#define USE_IO_DEBUG ++#endif ++ ++#ifndef SET ++ #define SET 1 ++#endif ++#ifndef CLR ++ #define CLR 0 ++#endif ++ ++#if defined(_LINUX_) ++#ifndef _U32_ ++#define _U32_ ++ typedef unsigned int U32; ++#endif ++#ifndef _U16_ ++#define _U16_ ++ typedef unsigned short U16; ++#endif ++#ifndef _U8_ ++#define _U8_ ++ typedef unsigned char U8; ++#endif ++#ifndef WINVER ++ #ifndef _BOOL_ ++ #define _BOOL_ ++ typedef unsigned int BOOL; ++ #endif ++#endif ++#else ++#ifndef U32 ++ typedef unsigned int U32; ++#endif ++#ifndef U16 ++ typedef unsigned short U16; ++#endif ++#ifndef U8 ++ typedef unsigned char U8; ++#endif ++ ++#ifndef WINVER ++ #ifndef BOOL ++ typedef unsigned int BOOL; ++ #endif ++#endif ++#endif ++ ++#ifndef S32 ++ typedef signed int S32; ++#endif ++#ifndef S16 ++ typedef signed short S16; ++#endif ++#ifndef S8 ++ typedef signed char S8; ++#endif ++ ++typedef int (*ICallBack)(int num); ++ ++/* ============================= ++ General Bit Operator ++ ============================= */ ++// Bit manipulation macro that is modifying its argument. (task type) ++#ifndef BITSET ++#define BITSET(X, MASK) ( (X) |= (U32)(MASK) ) ++#endif ++#ifndef BITSCLR ++#define BITSCLR(X, SMASK, CMASK) ( (X) = ((((U32)(X)) | ((U32)(SMASK))) & ~((U32)(CMASK))) ) ++#endif ++#ifndef BITCSET ++#define BITCSET(X, CMASK, SMASK) ( (X) = ((((U32)(X)) & ~((U32)(CMASK))) | ((U32)(SMASK))) ) ++#endif ++#ifndef BITCLR ++#define BITCLR(X, MASK) ( (X) &= ~((U32)(MASK)) ) ++#endif ++#ifndef BITXOR ++#define BITXOR(X, MASK) ( (X) ^= (U32)(MASK) ) ++#endif ++ ++// Bit manipulation macro that is not modifying its argument. (function type) ++#ifndef fBITSET ++#define fBITSET(X, MASK) ( (X) | (U32)(MASK) ) ++#endif ++#ifndef fBITSCLR ++#define fBITSCLR(X, SMASK, CMASK) ( ((((U32)(X)) | ((U32)(SMASK))) & ~((U32)(CMASK))) ) ++#endif ++#ifndef fBITCSET ++#define fBITCSET(X, CMASK, SMASK) ( ((((U32)(X)) & ~((U32)(CMASK))) | ((U32)(SMASK))) ) ++#endif ++#ifndef fBITCLR ++#define fBITCLR(X, MASK) ( (X) & ~((U32)(MASK)) ) ++#endif ++#ifndef fBITXOR ++#define fBITXOR(X, MASK) ( (X) ^ (U32)(MASK) ) ++#endif ++ ++#ifndef ISSET ++#define ISSET(X, MASK) ( (U32)(X) & ((U32)(MASK)) ) ++#endif ++#ifndef IS ++#define IS(X, MASK) ( (U32)(X) & ((U32)(MASK)) ) ++#endif ++#ifndef ISONE ++#define ISONE(X, MASK) ( (U32)(X) & ((U32)(MASK)) ) ++#endif ++ ++#ifndef ISALLONE ++#define ISALLONE(X, MASK) ( ((U32)(X) & ((U32)(MASK))) == ((U32)(MASK)) ) ++#endif ++ ++#ifndef ISCLR ++#define ISCLR(X, MASK) ( !(((U32)(X)) & ((U32)(MASK))) ) ++#endif ++#ifndef ISZERO ++#define ISZERO(X, MASK) ( !(((U32)(X)) & ((U32)(MASK))) ) ++#endif ++#ifndef ISNOT ++#define ISNOT(X, MASK) ( !(((U32)(X)) & ((U32)(MASK))) ) ++#endif ++ ++#ifndef BYTE_OF ++#define BYTE_OF(X) ( *(volatile unsigned char *)(&(X)) ) ++#endif ++#ifndef SHORT_OF ++#define SHORT_OF(X) ( *(volatile short *)(&(X)) ) ++#endif ++#ifndef HWORD_OF ++#define HWORD_OF(X) ( *(volatile unsigned short *)(&(X)) ) ++#endif ++#ifndef WORD_OF ++#define WORD_OF(X) ( *(volatile unsigned int *)(&(X)) ) ++#endif ++ ++#ifndef byte_of ++#define byte_of(X) ( *(volatile unsigned char *)((X)) ) ++#endif ++#ifndef short_of ++#define short_of(X) ( *(volatile short *)((X)) ) ++#endif ++#ifndef hword_of ++#define hword_of(X) ( *(volatile unsigned short *)((X)) ) ++#endif ++#ifndef word_of ++#define word_of(X) ( *(volatile unsigned int *)((X)) ) ++#endif ++ ++#define CkWaitPLLLOCK() { while (ISCLR(HwPLLMODE, Hw20)); } ++ ++#define SBase(X) Load$$ ## X ## $$Base ++#define DBase(X) Image$$ ## X ## $$Base ++#define SSize(X) Image$$ ## X ## $$Length ++#define ZIBase(X) Image$$ ## X ## $$ZI$$Base ++#define ZISize(X) Image$$ ## X ## $$ZI$$Length ++#define Region(X) &SBase(X), &DBase(X), &SSize(X), &ZIBase(X), &ZISize(X) ++#define ExternRegion(X) SBase(X), DBase(X), SSize(X), ZIBase(X), ZISize(X) ++ ++ ++/************************************************************************ ++* Clock Controller ++************************************************************************/ ++typedef struct { ++ unsigned uFpll; ++ unsigned char P, M, S, dummy; ++} sPLL; ++ ++ ++enum { ++ XIN_FREQ_120000, ++ XIN_FREQ_480000 ++}; ++ ++enum { ++ IO_CKC_Ftimerx = 0, ++ IO_CKC_Ftimert, ++ IO_CKC_Ftimerz, ++ IO_CKC_Flcd0, ++ IO_CKC_Flcd1, ++ IO_CKC_Flcdsi, // 5 ++ IO_CKC_Fcifmc, ++ IO_CKC_Fcifsc, ++ IO_CKC_Fout0, ++ IO_CKC_Fout1, ++ IO_CKC_Fhdmi, // 10 ++ IO_CKC_Fdummy, ++ IO_CKC_Fsdmmc0, ++ IO_CKC_Fmstick, ++ IO_CKC_Fi2c, ++ IO_CKC_Fuart0, // 15 ++ IO_CKC_Fuart1, ++ IO_CKC_Fuart2, ++ IO_CKC_Fuart3, ++ IO_CKC_Fuart4, ++ IO_CKC_Fuart5, // 20 ++ IO_CKC_Fgpsb0, ++ IO_CKC_Fgpsb1, ++ IO_CKC_Fgpsb2, ++ IO_CKC_Fgpsb3, ++ IO_CKC_Fgpsb4, // 25 ++ IO_CKC_Fgpsb5, ++ IO_CKC_Fadc, ++ IO_CKC_Fspdif, ++ IO_CKC_Fehi0, ++ IO_CKC_Fehi1, // 30 ++ IO_CKC_Faud, ++ IO_CKC_Fdummy1, ++ IO_CKC_Fdummy2, ++ IO_CKC_Fsdmmc1, ++ IO_CKC_Fdummy3, // 35 ++ IO_CKC_Fdai, ++ ++ IO_CKC_Flast ++}; ++ ++ ++/********************************************************** ++* void IO_CKC_WaitPLL(void); ++* Input : ++* Return : ++* Description : Loop waiting PLL locked. ++**********************************************************/ ++#define IO_CKC_WaitPLL() { int i; for (i=0; i<0x1000; i++); } ++ ++ ++/********************************************************** ++* void IO_CKC_EnableBUS(unsigned X); ++* Input : X = Bitmap dedicated to each peripheral ++* Return : ++* Description : Enable(1) the bus clock fed to each peripheral. ++* The other bus clocks are not influenced. ++**********************************************************/ ++#define IO_CKC_EnableBUS(X) (BITSET(HwIOBUSCFG->HCLKEN0, (X))) ++#define IO_CKC_EnableBUS1(X) (BITSET(HwIOBUSCFG->HCLKEN1, (X))) ++ ++/********************************************************** ++* Derivatives of IO_CKC_EnableBUS() function. ++* Input : ++* Return : ++* Description : Enable the bus clock fed to each peripheral. ++**********************************************************/ ++#define IO_CKC_EnableBUS_USB() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_USB)) ++#define IO_CKC_EnableBUS_IDE() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_IDE)) ++#define IO_CKC_EnableBUS_DMA() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_DMA)) ++#define IO_CKC_EnableBUS_SDC() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_SD)) ++#define IO_CKC_EnableBUS_MS() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_MS)) ++#define IO_CKC_EnableBUS_I2C() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_I2C)) ++#define IO_CKC_EnableBUS_NFC() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_NFC)) ++#define IO_CKC_EnableBUS_EHI0() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_EHI0)) ++#define IO_CKC_EnableBUS_EHI1() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_EHI1)) ++#define IO_CKC_EnableBUS_UART0() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART0)) ++#define IO_CKC_EnableBUS_UART1() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART1)) ++#define IO_CKC_EnableBUS_UART2() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART2)) ++#define IO_CKC_EnableBUS_UART3() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART3)) ++#define IO_CKC_EnableBUS_UART4() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART4)) ++#define IO_CKC_EnableBUS_UART5() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART5)) ++#define IO_CKC_EnableBUS_GPSB0() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB0)) ++#define IO_CKC_EnableBUS_GPSB1() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB1)) ++#define IO_CKC_EnableBUS_GPSB2() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB2)) ++#define IO_CKC_EnableBUS_GPSB3() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB3)) ++#define IO_CKC_EnableBUS_GPSB4() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB4)) ++#define IO_CKC_EnableBUS_GPSB5() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB5)) ++#define IO_CKC_EnableBUS_DAI() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_DAI)) ++#define IO_CKC_EnableBUS_ECC() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_ECC)) ++#define IO_CKC_EnableBUS_SPDIF() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_SPDIF)) ++#define IO_CKC_EnableBUS_RTC() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_RTC)) ++#define IO_CKC_EnableBUS_TSADC() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_TSADC)) ++#define IO_CKC_EnableBUS_GPS() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPS)) ++#define IO_CKC_EnableBUS_ADMA() (BITSET(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_ADMA)) ++#define IO_CKC_EnableBUS_MPE() (BITSET(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_MPE)) ++#define IO_CKC_EnableBUS_TSIF() (BITSET(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_TSIF)) ++#define IO_CKC_EnableBUS_SRAM() (BITSET(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_SRAM)) ++ ++ ++/********************************************************** ++* void IO_CKC_DisableBUS(unsigned X); ++* Input : X = Bitmap dedicated to each peripheral ++* Return : ++* Description : Disable(1) the bus clock fed to each peripheral. ++* The other bus clocks are not influenced. ++**********************************************************/ ++#define IO_CKC_DisableBUS(X) (BITCLR(HwIOBUSCFG->HCLKEN0, X)) ++#define IO_CKC_DisableBUS1(X) (BITCLR(HwIOBUSCFG->HCLKEN1, (X))) ++ ++/********************************************************** ++* Derivatives of IO_CKC_DisableBUS() function. ++* Input : ++* Return : ++* Description : Disable the bus clock fed to each peripheral. ++**********************************************************/ ++#define IO_CKC_DisableBUS_USB() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_USB)) ++#define IO_CKC_DisableBUS_IDE() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_IDE)) ++#define IO_CKC_DisableBUS_DMA() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_DMA)) ++#define IO_CKC_DisableBUS_SDC() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_SD)) ++#define IO_CKC_DisableBUS_MS() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_MS)) ++#define IO_CKC_DisableBUS_I2C() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_I2C)) ++#define IO_CKC_DisableBUS_NFC() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_NFC)) ++#define IO_CKC_DisableBUS_EHI0() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_EHI0)) ++#define IO_CKC_DisableBUS_EHI1() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_EHI1)) ++#define IO_CKC_DisableBUS_UART0() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART0)) ++#define IO_CKC_DisableBUS_UART1() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART1)) ++#define IO_CKC_DisableBUS_UART2() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART2)) ++#define IO_CKC_DisableBUS_UART3() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART3)) ++#define IO_CKC_DisableBUS_UART4() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART4)) ++#define IO_CKC_DisableBUS_UART5() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_UART5)) ++#define IO_CKC_DisableBUS_GPSB0() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB0)) ++#define IO_CKC_DisableBUS_GPSB1() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB1)) ++#define IO_CKC_DisableBUS_GPSB2() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB2)) ++#define IO_CKC_DisableBUS_GPSB3() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB3)) ++#define IO_CKC_DisableBUS_GPSB4() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB4)) ++#define IO_CKC_DisableBUS_GPSB5() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPSB5)) ++#define IO_CKC_DisableBUS_DAI() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_DAI)) ++#define IO_CKC_DisableBUS_ECC() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_ECC)) ++#define IO_CKC_DisableBUS_SPDIF() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_SPDIF)) ++#define IO_CKC_DisableBUS_RTC() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_RTC)) ++#define IO_CKC_DisableBUS_TSADC() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_TSADC)) ++#define IO_CKC_DisableBUS_GPS() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_GPS)) ++#define IO_CKC_DisableBUS_ADMA() (BITCLR(HwIOBUSCFG->HCLKEN0, HwIOBUSCFG_ADMA)) ++#define IO_CKC_DisableBUS_MPE() (BITCLR(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_MPE)) ++#define IO_CKC_DisableBUS_TSIF() (BITCLR(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_TSIF)) ++#define IO_CKC_DisableBUS_SRAM() (BITCLR(HwIOBUSCFG->HCLKEN1, HwIOBUSCFG_SRAM)) ++ ++// IOBUS AHB 0 ++#define IO_CKC_BUS_USB HwIOBUSCFG_USB ++#define IO_CKC_BUS_IDE HwIOBUSCFG_IDE ++#define IO_CKC_BUS_DMA HwIOBUSCFG_DMA ++#define IO_CKC_BUS_SD HwIOBUSCFG_SD ++#define IO_CKC_BUS_MS HwIOBUSCFG_MS ++#define IO_CKC_BUS_I2C HwIOBUSCFG_I2C ++#define IO_CKC_BUS_NFC HwIOBUSCFG_NFC ++#define IO_CKC_BUS_EHI0 HwIOBUSCFG_EHI0 ++#define IO_CKC_BUS_EHI1 HwIOBUSCFG_EHI1 ++#define IO_CKC_BUS_UART0 HwIOBUSCFG_UART0 ++#define IO_CKC_BUS_UART1 HwIOBUSCFG_UART1 ++#define IO_CKC_BUS_UART2 HwIOBUSCFG_UART2 ++#define IO_CKC_BUS_UART3 HwIOBUSCFG_UART3 ++#define IO_CKC_BUS_UART4 HwIOBUSCFG_UART4 ++#define IO_CKC_BUS_UART5 HwIOBUSCFG_UART5 ++#define IO_CKC_BUS_GPSB0 HwIOBUSCFG_GPSB0 ++#define IO_CKC_BUS_GPSB1 HwIOBUSCFG_GPSB1 ++#define IO_CKC_BUS_GPSB2 HwIOBUSCFG_GPSB2 ++#define IO_CKC_BUS_GPSB3 HwIOBUSCFG_GPSB3 ++#define IO_CKC_BUS_GPSB4 HwIOBUSCFG_GPSB4 ++#define IO_CKC_BUS_GPSB5 HwIOBUSCFG_GPSB5 ++#define IO_CKC_BUS_DAI HwIOBUSCFG_DAI ++#define IO_CKC_BUS_ECC HwIOBUSCFG_ECC ++#define IO_CKC_BUS_SPDIF HwIOBUSCFG_SPDIF ++#define IO_CKC_BUS_RTC HwIOBUSCFG_RTC ++#define IO_CKC_BUS_TSADC HwIOBUSCFG_TSADC ++#define IO_CKC_BUS_GPS HwIOBUSCFG_GPS ++#define IO_CKC_BUS_ADMA HwIOBUSCFG_ADMA ++ ++// IOBUS AHB 1 ++#define IO_CKC_BUS_MPE HwIOBUSCFG_MPE ++#define IO_CKC_BUS_TSIF HwIOBUSCFG_TSIF ++#define IO_CKC_BUS_SRAM HwIOBUSCFG_SRAM ++ ++ ++/********************************************************** ++* void IO_CKC_SWRST(unsigned X); ++* Input : X = Bitmap dedicated to each peripheral ++* Return : ++* Description : Make a reset signal for each peripheral. ++* Set a corresponding bit field to make a reset signal to each peripheral. ++**********************************************************/ ++#ifdef TCC92XX ++#else /* TCC92XX */ ++#define IO_CKC_SWRST(X) (HwSWRESET = (X)) ++#endif /* TCC92XX */ ++ ++#ifndef _LINUX_ ++#pragma warning( push ) ++#pragma warning( disable: 4341 ) // enum --> unsigned longlong...X ++#pragma warning( disable: 4309 ) ++#endif ++enum { ++ IO_CKC_TMRX = Hw0, ++ IO_CKC_TMRT = Hw1, ++ IO_CKC_TMRZ = Hw2, ++ IO_CKC_LCD0 = Hw3, ++ IO_CKC_LCD1 = Hw4, ++ IO_CKC_LCDSI = Hw5, ++ IO_CKC_CIFMC = Hw6, ++ IO_CKC_CIFSC = Hw7, ++ IO_CKC_OUT0 = Hw8, ++ IO_CKC_OUT1 = Hw9, ++ IO_CKC_HDMI = Hw10, ++ IO_CKC_SDMMC0 = Hw12, ++ IO_CKC_MSTICK = Hw13, ++ IO_CKC_I2C = Hw14, ++ IO_CKC_UART0 = Hw15, ++ IO_CKC_UART1 = Hw16, ++ IO_CKC_UART2 = Hw17, ++ IO_CKC_UART3 = Hw18, ++ IO_CKC_UART4 = Hw19, ++ IO_CKC_UART5 = Hw20, ++ IO_CKC_GPSB0 = Hw21, ++ IO_CKC_GPSB1 = Hw22, ++ IO_CKC_GPSB2 = Hw23, ++ IO_CKC_GPSB3 = Hw24, ++ IO_CKC_GPSB4 = Hw25, ++ IO_CKC_GPSB5 = Hw26, ++ IO_CKC_ADC = Hw27, // PCK_YYY ++ IO_CKC_SPDIF = Hw28, // PCK_YYY ++ IO_CKC_EHI0 = Hw29, ++ IO_CKC_EHI1 = Hw30, ++ IO_CKC_AUD = Hw31, // PCK_YYY ++ IO_CKC_SDMMC1 = Hw34, ++ IO_CKC_DAI = Hw36 // PCK_YYY ++}; ++#ifndef _LINUX_ ++#pragma warning( pop ) ++#endif ++ ++#define IO_CKC_EnableClock(x) \ ++{ \ ++ if ((x) & IO_CKC_TMRX) \ ++ BITSET(HwCKC->PCLK_TCX, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_TMRT) \ ++ BITSET(HwCKC->PCLK_TCT, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_TMRZ) \ ++ BITSET(HwCKC->PCLK_TCZ, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCD0) \ ++ BITSET(HwCKC->PCLK_LCD0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCD1) \ ++ BITSET(HwCKC->PCLK_LCD1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCDSI) \ ++ BITSET(HwCKC->PCLK_LCDSI, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_CIFMC) \ ++ BITSET(HwCKC->PCLK_CIFMC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_CIFSC) \ ++ BITSET(HwCKC->PCLK_CIFSC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_OUT0) \ ++ BITSET(HwCKC->PCLK_OUT0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_OUT1) \ ++ BITSET(HwCKC->PCLK_OUT1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_HDMI) \ ++ BITSET(HwCKC->PCLK_HDMI, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SDMMC0) \ ++ BITSET(HwCKC->PCLK_SDMMC0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_MSTICK) \ ++ BITSET(HwCKC->PCLK_MSTICK, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_I2C) \ ++ BITSET(HwCKC->PCLK_I2C, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART0) \ ++ BITSET(HwCKC->PCLK_UART0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART1) \ ++ BITSET(HwCKC->PCLK_UART1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART2) \ ++ BITSET(HwCKC->PCLK_UART2, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART3) \ ++ BITSET(HwCKC->PCLK_UART3, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART4) \ ++ BITSET(HwCKC->PCLK_UART4, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART5) \ ++ BITSET(HwCKC->PCLK_UART5, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB0) \ ++ BITSET(HwCKC->PCLK_GPSB0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB1) \ ++ BITSET(HwCKC->PCLK_GPSB1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB2) \ ++ BITSET(HwCKC->PCLK_GPSB2, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB3) \ ++ BITSET(HwCKC->PCLK_GPSB3, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB4) \ ++ BITSET(HwCKC->PCLK_GPSB4, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB5) \ ++ BITSET(HwCKC->PCLK_GPSB5, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_ADC) \ ++ BITSET(HwCKC->PCLK_ADC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SPDIF) \ ++ BITSET(HwCKC->PCLK_SPDIF, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_EHI0) \ ++ BITSET(HwCKC->PCLK_EHI0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_EHI1) \ ++ BITSET(HwCKC->PCLK_EHI1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_AUD) \ ++ BITSET(HwCKC->PCLK_AUD, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SDMMC1) \ ++ BITSET(HwCKC->PCLK_SDMMC1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_DAI) \ ++ BITSET(HwCKC->PCLK_DAI, HwPCK_EN_EN); \ ++} ++ ++#define IO_CKC_DisableClock(x) \ ++{ \ ++ if ((x) & IO_CKC_TMRX) \ ++ BITCLR(HwCKC->PCLK_TCX, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_TMRT) \ ++ BITCLR(HwCKC->PCLK_TCT, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_TMRZ) \ ++ BITCLR(HwCKC->PCLK_TCZ, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCD0) \ ++ BITCLR(HwCKC->PCLK_LCD0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCD1) \ ++ BITCLR(HwCKC->PCLK_LCD1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_LCDSI) \ ++ BITCLR(HwCKC->PCLK_LCDSI, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_CIFMC) \ ++ BITCLR(HwCKC->PCLK_CIFMC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_CIFSC) \ ++ BITCLR(HwCKC->PCLK_CIFSC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_OUT0) \ ++ BITCLR(HwCKC->PCLK_OUT0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_OUT1) \ ++ BITCLR(HwCKC->PCLK_OUT1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_HDMI) \ ++ BITCLR(HwCKC->PCLK_HDMI, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SDMMC0) \ ++ BITCLR(HwCKC->PCLK_SDMMC0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_MSTICK) \ ++ BITCLR(HwCKC->PCLK_MSTICK, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_I2C) \ ++ BITCLR(HwCKC->PCLK_I2C, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART0) \ ++ BITCLR(HwCKC->PCLK_UART0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART1) \ ++ BITCLR(HwCKC->PCLK_UART1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART2) \ ++ BITCLR(HwCKC->PCLK_UART2, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART3) \ ++ BITCLR(HwCKC->PCLK_UART3, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART4) \ ++ BITCLR(HwCKC->PCLK_UART4, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_UART5) \ ++ BITCLR(HwCKC->PCLK_UART5, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB0) \ ++ BITCLR(HwCKC->PCLK_GPSB0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB1) \ ++ BITCLR(HwCKC->PCLK_GPSB1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB2) \ ++ BITCLR(HwCKC->PCLK_GPSB2, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB3) \ ++ BITCLR(HwCKC->PCLK_GPSB3, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB4) \ ++ BITCLR(HwCKC->PCLK_GPSB4, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_GPSB5) \ ++ BITCLR(HwCKC->PCLK_GPSB5, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_ADC) \ ++ BITCLR(HwCKC->PCLK_ADC, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SPDIF) \ ++ BITCLR(HwCKC->PCLK_SPDIF, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_EHI0) \ ++ BITCLR(HwCKC->PCLK_EHI0, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_EHI1) \ ++ BITCLR(HwCKC->PCLK_EHI1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_AUD) \ ++ BITCLR(HwCKC->PCLK_AUD, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_SDMMC1) \ ++ BITCLR(HwCKC->PCLK_SDMMC1, HwPCK_EN_EN); \ ++ if ((x) & IO_CKC_DAI) \ ++ BITCLR(HwCKC->PCLK_DAI, HwPCK_EN_EN); \ ++} ++ ++ ++/************************************************************************ ++* Function Declaration (Clock Controller) ++************************************************************************/ ++/********************************************************** ++* void IO_CKC_EnterStandbyInt(unsigned uMode) ++* ++* Input : uMode = wake-up event selection ++* 0 : using XIN clock (that means program stops here until wake-up event is occurred.) ++* In this mode, only external interrupt can wake up system. but may be unstable while waking up. ++* NOT RECOMMENDED. ++* non-zero : using XTIN clock. ++* In this mode, program continues but polling predefined wake-up interrupt. ++* the wake-up interrupt can be defined by this value of 'uMode' ++* this represents bitmap of wake-up interrupt sources. ++* Return : ++* Description : Enter Standby Mode (All clocks except XTIN are stopped.) ++* This function is located in IO_LIB_INT area and ++* it should be located in the internal SRAM. ++*********************************************************/ ++void IO_CKC_EnterStandbyInt(unsigned uMode); ++ ++enum ++{ ++ SPEED_MODE_0 = 0, ++ #ifdef SPEED_MODE_INCLUDE ++ SPEED_MODE_1, ++ SPEED_MODE_2, ++ SPEED_MODE_3, ++ #endif ++ MAX_SPEED_MODE ++}; ++ ++typedef struct { ++ unsigned uFmaxpll; ++ unsigned uFmaxcpu; ++ unsigned uFmaxbus; ++ unsigned uFpll[3]; // for 32KHz, 44.1KHz, 48KHz ++ ++ /*for chaning max clock by speed mode ++ */ ++ unsigned uHighpll; //unit : 100hz ++ unsigned short uHighcpu; //unit : Mhz ++ unsigned short uHighbus; //unit : Mhz ++} sIO_CKC_SPD_MODE; ++ ++/********************************************************** ++* void IO_CKC_InitVariable(int iFmax, int iHmax); ++* ++* Input : iFmax = Maximum frequency of CPU clock (100Hz unit) ++* iHmax = Maximum frequency of BUS clock (100Hz unit) ++* Return : ++* Description : Initialize Global Variables for Clock Driver ++**********************************************************/ ++#if defined(TCC79XX) || defined(TCC92XX) || defined(TCC89XX) ++ #define IO_CKC_Fmaxcpu PLL_FREQ ++ #define IO_CKC_Fmaxbus (PLL_FREQ/2) ++ ++ #define IO_CKC_Fxin 120000 ++ ++ #define IO_CKC_Fpll_32KHz PLL_FREQ ++ #define IO_CKC_Fpll_44KHz PLL_FREQ ++ #define IO_CKC_Fpll_48KHz PLL_FREQ ++#endif ++ ++/********************************************************** ++* void IO_CKC_InitDRV(void); ++* ++* Input : ++* Output : ++* Return : ++* ++* Description : Initialize Global Variables for Clock Driver ++**********************************************************/ ++void IO_CKC_InitDRV(void); ++ ++/********************************************************** ++* void IO_CKC_DisablePLL(unsigned uCH) ++* ++* Input : uCH = Channel of PLL (0 or 1) ++* Output : ++* Return : ++* ++* Description : ++* ++**********************************************************/ ++void IO_CKC_DisablePLL(unsigned uCH); ++ ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_CKC_SelectSpeedMode(unsigned uSpeedMode); ++* ++* DESCRIPTION : Select System Speed Mode (Supported only by pull-up the supply voltage for CORE) ++* ++* INPUT: ++* uSpeedMode = Index of Speed Mode. (Refer sIO_CKC_SpeedMode[] Table) ++* ++* OUTPUT: int - Return Type ++* = -1 : Requested Speed Mode is not supported. ++* = 0 : Mode change successful. ++* ++* REMARK: created on 2007/6/28 22:31:46 ++**************************************************************************/ ++int IO_CKC_SelectSpeedMode(unsigned uSpeedMode); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_CKC_CalcBUS4CYCLE(unsigned uNewBusFreq); ++* ++* DESCRIPTION : Map real bus clock frequency to reference bus clock frequency ++* Reference bus clock frequency should be always higher or equal than real bus clock ++* to insert marginal cycles for stability. ++* ++* INPUT: ++* uNewBusFreq = Real bus frequency ++* ++* OUTPUT: unsigned - Return Type ++* = Reference bus frequency ++* ++**************************************************************************/ ++unsigned IO_CKC_CalcBUS4CYCLE(unsigned uNewBusFreq); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_CKC_SetCYCLE(unsigned uNewBusFreq, unsigned uPosition); ++* ++* DESCRIPTION : Set Cycle Parameter for Peripherals which use Bus Clock. ++* ++* INPUT: ++* uNewBusFreq = New Bus Clock Frequency (100 Hz unit) ++* uPosition = Indicate position of calling this function ++* 1 : Before changing Bus Clock, 2 : After changing Bus Clock ++* ++* OUTPUT: unsigned - Return Type ++* = Old Bus Clock Frequency ++* (not real bus clock but reference bus clock for calculating cycle parameters) ++* ++**************************************************************************/ ++unsigned IO_CKC_SetCYCLE(unsigned uNewBusFreq, unsigned uPosition); ++ ++/********************************************************** ++* void IO_CKC_AdjustClock(int Fmax, int Vmax, int Hmax, int Fmin, int Vmin, int Hmin, int iFclk, int iVclk, int iHclk); ++* ++* Description : Increasing/Decreasing System Clock (CPU, VCORE, BUS) ++* (iFclk, iVclk, iHclk) means division/multiplication factor (not frequency) ++* ++* INPUT: ++* Fmax = Maximum Frequency for CPU clock ++* Vmax = Maximum Frequency for VCORE clock ++* Hmax = Maximum Frequency for BUS clock ++* Fmin = Minimum Frequency for CPU clock ++* Vmin = Minimum Frequency for VCORE clock ++* Hmin = Minimum Frequency for BUS clock ++* iFclk = CPU clock delta index (1~15 for increasing clock, -1~-15 for decreasing clock, 0 for holding) ++* iVclk = VCore clock delta index (1~15 for increasing clock, -1~-15 for decreasing clock, 0 for holding) ++* iHclk = BUS clock delta index (1~31 for increasing clock, -1~-31 for decreasing clock, 0 for holding) ++* ++* Assumption : Source clock (XIN or PLL) must be alive. ++* Output : ++* Return : ++* ++**********************************************************/ ++void IO_CKC_AdjustClock(int Fmax, int Vmax, int Hmax, int Fmin, int Vmin, int Hmin, int iFclk, int iVclk, int iHclk); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_CKC_GetCurrentBUSClock4Cycle(void); ++* ++* DESCRIPTION : Returns current reference bus clock frequency ++* All the peripherals (like NAND, NOR, HDD, etc.) use bus clock ++* should refer this value to calculate cycle parameters. ++* ++* INPUT: ++* None ++* ++* OUTPUT: unsigned - Return Type ++* = current reference bus clock frequency ++* ++**************************************************************************/ ++unsigned IO_CKC_GetCurrentBUSClock4Cycle(void); ++ ++/********************************************************** ++* void IO_CKC_InitPLL(unsigned uCH, unsigned uPLL); ++* ++* Input : uPLL = target frequency of PLL (100Hz unit) ++* Return : ++* Description : call IO_CKC_SetPLL() according to frequency value ++* currently supported frequency. (default = 240MHz) ++* 240MHz, 120MHz, 248.5714MHz, 203.1428MHz ++* 221.1428MHz, 196.5MHz ++* ++* After PLL set, it is tryed to maintain the frequencies of all clocks. ++* If certain clock is not possible to be maintained, ++* the clock frequency is set as close as previous one. ++**********************************************************/ ++void IO_CKC_InitPLL(unsigned uCH, unsigned uPLL); ++ ++/********************************************************** ++* void IO_CKC_SetPLL(unsigned uCH, int iP, int iM, int iS); ++* ++* Input : iP, iM, iS ++* Return : ++* Description : Set PLL according to PMS value, and wait until PLL is stable. ++* Fpll = Fxin * (iM + 8) / ((iP + 2) * 2^iS) ++* (The combination of (P, M, S) should be confirmed before used) ++* ++* After PLL set, It is tryed to maintain the frequencies of all clocks. ++* If certain clock is not possible to be maintained, ++* the clock frequency is set as close as previous one. ++**********************************************************/ ++void IO_CKC_SetPLL(unsigned uCH, int iP, int iM, int iS); ++ ++/********************************************************** ++* void IO_CKC_SetClock(unsigned uPLLCH, unsigned uCKCCH, int iFclk) ++* ++* Input : uPLLCH = PLL channel index ++* uCKCCH = Clock channel index ++* iFclk = Freq. of uCKCCH Unit., 100Hz unit ++* Assumption : Source clock (XIN or PLL) must be alive. ++* (If XTIN is currently used, make sure XIN or PLL alive before calling this function) ++* Return : ++* Description : Set System Clock ++* If target frequency exceeds its own max frequency (gCKC_Fmax]), ++* the uIO_CKC_error flag is incremented, and system clock is not changed. ++* If the frequency requested can not be set exactly, ++* this function set the frequency as close as possible. ++* (refer to the datasheet for possible system clock relationship.) ++* The system clock source is selected according to the following rule. ++* 1) if (Fclk >= Fpll) PLL is selected. ++* 2) if (Fclk > Fxin) PLL divider is selected. ++* 3) if (Fclk == Fxin) XIN is selected. ++* 4) if (Fclk > Fxtin) XIN divider is selected. ++* 5) if (Fclk == Fxtin) XTIN is selected. ++* 6) other case, XTIN divider is selected. ++**********************************************************/ ++void IO_CKC_SetClock(unsigned uPLLCH, unsigned uCKCCH, int iFclk); ++ ++/********************************************************** ++* void void IO_CKC_SetClockMul(unsigned uPLLCH, unsigned uCKCCH, int iSdiv, int iFdiv, int iSrc) ++* ++* Input : uPLLCH = PLL channel index ++* uCKCCH = Clock channel index ++* iSdiv = System clock division (= Fpll / Fsys) ++* iFdiv = Fsys / Fclk (can be one of 2~32) ++* iSrc = Fsys clock source selection ++* Assumption : Source clock (XIN/XTIN/PLL) must be alive. ++* Output : ++* Return : ++* ++* Description : Set Clock. ++**********************************************************/ ++void IO_CKC_SetClockMul(unsigned uPLLCH, unsigned uCKCCH, int iSdiv, int iFdiv, int iSrc); ++ ++/********************************************************** ++* unsigned IO_CKC_GetMinimumBusClock(unsigned uLCTRL); ++* ++* Input : LCDC LCTRL value ( register or variable ) ++* Assumption : ++* Output : ++* Return : minimum bus clock frequency (100 Hz unit) ++* ++* Description : Get minimum bus clock frequency. ++**********************************************************/ ++unsigned IO_CKC_GetMinimumBusClock(unsigned uLCTRL); ++ ++/********************************************************** ++* void IO_CKC_SetClockDiv(int iFclk, int iHclk, int iSrc); ++* ++* Input : iFclk = Division Factor for CPU clock (acquired by Fsrc / Fcpu) ++* iHclk = Division Factor for BUS clock (acquired by Fcpu / Fbus) ++* iSrc = Clock source definition (same as CKSEL[2:0] of HwCLKCTRL register) ++* Assumption : Source clock (XIN/PLL/XTIN) must be alive. ++* (If XTIN is currently used, make sure XIN or PLL alive before calling this function) ++* Return : ++* Description : Set System Clock (CPU, BUS) as follows. ++* Frequency of CPU clock (Fcpu) = Fsrc / iFclk. (Fsrc = Frequency of source clock selected by iSrc parameter) ++* Frequency of BUS clock (Fbus) = Fcpu / iHclk. ++**********************************************************/ ++#ifdef CPU_CLOCK_DIV_USED ++void IO_CKC_SetClockDiv(int iFdiv, int iHdiv, int iCCKdiv, int iSrc); ++#else ++void IO_CKC_SetClockDiv(int iFdiv, int iHdiv, int iSrc); ++#endif ++ ++/********************************************************** ++* unsigned IO_CKC_GetCurrentBUSClock(void); ++* ++* Input : ++* Return : Frequency of Current BUS Clock (100Hz unit) ++* Description : Return the current bus clock frequency ++**********************************************************/ ++unsigned IO_CKC_GetCurrentBUSClock(void); ++ ++/********************************************************** ++* void IO_CKC_EnterHalt(unsigned uSDEN); ++* ++* Input : uSDEN = option for SDRAM control ++* 0 = don't touch sdram ++* 1 = control SDRAM, (enter self-refresh mode during halt) ++* Return : ++* Description : Enter Halt Mode ++* In Halt mode, only CPU halts until interrupt request occurred. ++************************************************************/ ++void IO_CKC_EnterHalt(unsigned uSDEN); ++void IO_CKC_EnterHalt_Main(void); ++void IO_CKC_EnterHalt_End(void); ++ ++/********************************************************** ++* void IO_CKC_SetRefreshClock(int iFreq); ++* ++* Input : iFreq = Frequency of Refresh Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set Refresh clock frequency and Enable refresh clock ++* It is assumed that the BUS clock freq is larger than half of XIN frequency. ++* The refresh clock is implicitely driven by XIN clock. ++***********************************************************/ ++void IO_CKC_SetRefreshClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetUSBHostClock(void); ++* ++* Input : ++* Return : ++* Description : Enable USB Host Clock, it is fixed to use XIN as USB Host clock ++***********************************************************/ ++void IO_CKC_SetUSBHostClock(void); ++ ++/********************************************************** ++* void IO_CKC_SetI2CClock(int iFreq); ++* ++* Input : iFreq = Frequency of I2C Main Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable I2C main Clock ++* The real I2C clock (SCL) frequency is determined by prescale register of I2C block. ++* The I2C main clock is implicitely driven by XIN clock. ++***********************************************************/ ++void IO_CKC_SetI2CClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetMSCClock(int iFreq); ++* ++* Input : iFreq = Frequency of MemoryStic Controller clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable Memory Stick Controller Clock ++* The memory stic controller clock is implicitely driven by PLL clock. ++***********************************************************/ ++void IO_CKC_SetMSCClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetUA0Clock(int iFreq); ++* void IO_CKC_SetUA1Clock(int iFreq); ++* void IO_CKC_SetUA2Clock(int iFreq); ++* void IO_CKC_SetUA3Clock(int iFreq); ++* ++* Input : iFreq = Frequency of UART clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable UART Clock ++* The baud rate of UART is determined by DL register of UART block ++* The UART clock is implicitely driven by PLL clock. ++***********************************************************/ ++void IO_CKC_SetUartClock(int iCH, int iFreq); ++void IO_CKC_SetUA0Clock(int iFreq); ++void IO_CKC_SetUA1Clock(int iFreq); ++void IO_CKC_SetUA2Clock(int iFreq); ++void IO_CKC_SetUA3Clock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetTimerTClock(int iFreq); ++* ++* Input : iFreq = Frequency of Timer-T clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable Timer-T Clock ++* The timer-T clock manages 6 timer/counters ++* (refer to datasheet) ++* The Timer-T clock is implicitely driven by XIN clock. ++***********************************************************/ ++void IO_CKC_SetTimerTClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetGSIOClock(int iFreq); ++* ++* Input : iFreq = Frequency of GSIO base clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable GSIO base clock ++* The real GSIO clock (SCK) is determined by speed control field of GSCRx register. ++* (refer to datasheet) ++***********************************************************/ ++void IO_CKC_SetGSIOClock(int iFreq); ++ ++ ++/********************************************************** ++* void IO_TC32_SetTIMER(unsigned uCTRL, unsigned uFreq, unsigned uLOADVAL, unsigned uCMP0, unsigned uCMP1); ++* ++* Input : uCTRL = TC32 Control Register (HwTC32EN) value except Pre-scale value. ++* uICTRL = TC32 Interrupt Control Register (HwTC32IRQ) value. ++* uFreq = TC32 counting frequency to set up pre-scale value. (TC32 clock should be set ahead) ++* uLOADVAL = load value (HwTC32LDV) ++* uCMP0 = Match value 0 (HwTC32CMP0). ++* uCMP1 = Match value 1 (HwTC32CMP1). ++* Return : ++* Description : Set TC32 timer (timer is enabled if uFreq > 0, or timer is disabled) ++* If uFreq < Freq(TimerZ clock), then TC32 is counted by TimerZ clock directly. ++**********************************************************/ ++void IO_TC32_SetTIMER(unsigned uCTRL, unsigned uICTRL, unsigned uFreq, unsigned uLOADVAL, unsigned uCMP0, unsigned uCMP1); ++ ++/********************************************************** ++* void IO_CKC_SetTimerZClock(int iFreq); ++* ++* Input : iFreq = Frequency of Timer-Z clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable Timer-Z Clock ++* The timer-Z clock manages TC32 counter block ++* (refer to datasheet) ++* The Timer-Z clock is implicitely driven by XTIN clock. ++***********************************************************/ ++void IO_CKC_SetTimerZClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetTimerXClock(int iFreq); ++* ++* Input : iFreq = Frequency of Timer-X clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable Timer-X Clock ++* The timer-X clock manages watchdog counter block ++* (refer to datasheet) ++* The Timer-X clock is implicitely driven by XIN clock. ++***********************************************************/ ++void IO_CKC_SetTimerXClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetDAIClock(int iFreq); ++* ++* Input : iFreq = Frequency of DAI Main Clock (100Hz unit) ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable DAI Clock ++* The DAI clock should be set appropriately according to audio sampling rate. ++***********************************************************/ ++void IO_CKC_SetDAIClock(int iFreq); ++ ++/********************************************************** ++* unsigned IO_CKC_GetPLLClock(int iFreq); ++* ++* Input : iFreq = Frequency of Audio Sampling Clock (Hz unit) ++* Return : Frequency of PLL (100Hz unit) ++* Description : Get frequency of PLL that is capable to generate iFreq. ++* Unsupported audio sampling rate is regarded as 44100 Hz. ++* Audio Sampling Rate PLL frequency ++* ========================= ++* 44100 Hz & related 203.1428 MHz ++* 48000 Hz & related 221.1428 MHz ++* 32000 Hz & related 196.5000 MHz ++***********************************************************/ ++unsigned IO_CKC_GetPLLClock(int iFreq); ++ ++/********************************************************** ++* unsigned IO_CKC_GetDAIClock(int iFreq, int iOSR); ++* ++* Input : iFreq = Frequency of Audio Sampling Clock (Hz unit) ++* iOSR = Over Sampling Rate. (ex. 256, 384) ++* Return : Frequency of DAI Clock (100Hz unit) ++* Description : Get frequency of DAI clock that is fit to iFreq audio frequency. ++***********************************************************/ ++unsigned IO_CKC_GetDAIClock(int iFreq, int iOSR); ++ ++/********************************************************** ++* void IO_CKC_SetADCClock(int iFreq); ++* ++* Input : iFreq = Frequency of ADC Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Return : ++* Description : Set frequency and Enable ADC Clock ++* The ADC clock is implicitely driven by XIN clock. ++***********************************************************/ ++void IO_CKC_SetADCClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetSDMMCClock(int iCH, int iFreq); ++* ++* Input : iCH = SD/MMC channel index ++* iFreq = Frequency of SDMMC Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++//void IO_CKC_SetSDMMCClock(int iCH, int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetLCDClock(int iCH, int iFreq) ++* ++* Input : iCH = LCD channel index ++* iFreq = Frequency of LCD Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetLCDClock(int iCH, int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetEHIClock(int iFreq, int iCS); ++* ++* Input : iFreq = Frequency of EHI Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* iCS = EHI Channel ( 0 or 1 ) ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetEHIClock(int iFreq, int iCS); ++ ++ ++#ifdef CAMERA_INCLUDE ++/********************************************************** ++* void IO_CKC_SetCAMClock(int iFreq); ++* ++* Input : iFreq = Frequency of CAM Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetCAMClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetCAMScalerClock(int iFreq); ++* ++* Input : iFreq = Frequency of CAM Scaler Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetCAMScalerClock(int iFreq); ++#endif ++ ++/********************************************************** ++* void IO_CKC_SetSPDIFClock(int iFreq); ++* ++* Input : iFreq = Frequency of SPDIF Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetSPDIFClock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_SetSPI0Clock(int iFreq); ++* void IO_CKC_SetSPI1Clock(int iFreq); ++* void IO_CKC_SetSPI2Clock(int iFreq); ++* void IO_CKC_SetSPI3Clock(int iFreq); ++* ++* Input : iFreq = Frequency of SPIS Clock, 100Hz unit ++* Clock disabled if iFreq == 0. ++* Output : ++* Return : ++* ++* Description : Set frequency and Enable Clock ++***********************************************************/ ++void IO_CKC_SetSPI0Clock(int iFreq); ++void IO_CKC_SetSPI1Clock(int iFreq); ++void IO_CKC_SetSPI2Clock(int iFreq); ++void IO_CKC_SetSPI3Clock(int iFreq); ++ ++/********************************************************** ++* void IO_CKC_UpdateFPERI(unsigned uPeri, unsigned uFperi); ++* ++* Input : uPeri = Index of peripheral clock frequency table. ++* uFperi = New Frequency value. ++* Output : ++* Return : ++* ++* Description : updates pIO_CKC_Fpll table with new frequency. ++***********************************************************/ ++void IO_CKC_UpdateFPERI(unsigned uPeri, unsigned uFperi); ++ ++ ++extern unsigned uIO_CKC_Fpll[]; // Current PLL Frequency, 100Hz unit ++extern unsigned uIO_CKC_Fsys[]; ++extern unsigned uIO_CKC_Fclk[]; // Current Frequency, 100Hz unit ++extern unsigned uTMODE0; // image of HwTMODE register. ++extern unsigned uTMODE1; // image of HwTMODE register. ++extern unsigned pIO_CKC_Fperi[]; // Current Peripheral Frequency, 100Hz unit ++extern const sPLL pIO_CKC_PLL[]; // PLL Setting (PMS) Table ++extern unsigned uIO_CKC_FrzClk; // Freeze CPU, BUS Clock ++extern unsigned uIO_CKC_Fmax[]; // Fclk Max Frequency, 100Hz unit ++extern unsigned uIO_CKC_CurSpeedSet; // Current Speed Mode ++extern unsigned uIO_CKC_Fbus4cycle; // Reference Bus Frequency & Period for calculating cycle parameter ++ ++/************************************************************************ ++* ARM ++************************************************************************/ ++/********************************************************** ++* unsigned IO_ARM_DrainWBInt(void); ++* ++* Input : none ++* Return : 0 ++* Description : Drain Write Buffer ++* This function is located in IO_LIB_INT area and ++* it should be located in the internal SRAM. ++**********************************************************/ ++unsigned IO_ARM_DrainWBInt(void); ++ ++/********************************************************** ++* unsigned IO_ARM_CleanCACHEInt(unsigned uDrainWB); ++* ++* Input : uDrainWB = Write Buffer control ++* 1 = Execute Drain Write Buffer ++* Return : 0 ++* Description : Clean Data cache and/or Drain Write Buffer ++* This function is located in IO_LIB_INT area and ++* it should be located in the internal SRAM. ++**********************************************************/ ++unsigned IO_ARM_CleanCACHEInt(unsigned uDrainWB); ++ ++/********************************************************** ++* int IO_ARM_LockICACHE(void *pFPTRstart, void *pFPTRend); ++* ++* Input : pFPTRstart = function start address for locking ++* pFPTRend = function end address for locking ++* Return : -1 = if error ++* n = lock index (n >= 0) ++* Description : Lock the object function into I cache ++* The locked region ++* starts from (pFPTRstart & ~0x7F) and and at (pFPTRend | 0x7F). ++**********************************************************/ ++int IO_ARM_LockICACHE(void *pFPTRstart, void *pFPTRend); ++ ++/********************************************************** ++* unsigned IO_ARM_DrainWB(void); ++* ++* Input : none ++* Return : 0 ++* Description : Drain Write Buffer ++**********************************************************/ ++unsigned IO_ARM_DrainWB(void); ++ ++/********************************************************** ++* unsigned IO_ARM_CleanCACHE(unsigned uDrainWB); ++* ++* Input : uDrainWB = Write Buffer control ++* 1 = Drain write buffer ++* 0 = Don't drain write buffer ++* Return : 0 ++* Description : Clean Data cache (and Drain Write Buffer) ++**********************************************************/ ++unsigned IO_ARM_CleanCACHE(unsigned uDrainWB); ++ ++/********************************************************** ++* unsigned IO_ARM_SetMMU(unsigned uMMU); ++* ++* Input : uMMU = MMU control register value ++* Hw16 = DTCM control (1 = to enable) ++* Hw12 = ICache control (1 = to enable) ++* Hw2 = DCache control (1 = to enable) ++* Hw0 = Protection control (1 = to enable) ++* Return : same as input ++* Description : Set MMU control register ++**********************************************************/ ++unsigned IO_ARM_SetMMU(unsigned); ++ ++/********************************************************** ++* unsigned IO_ARM_GetMMU(void); ++* ++* Input : None ++* Return : current MMU control register (C1 register) value ++* Hw16 = DTCM control (1 = enabled) ++* Hw12 = ICache control (1 = enabled) ++* Hw2 = DCache control (1 = enabled) ++* Hw0 = Protection control (1 = enabled) ++* Description : Get current MMU control register (C1 register) ++**********************************************************/ ++unsigned IO_ARM_GetMMU(void); ++ ++/********************************************************** ++* unsigned IO_ARM_ClearMMU(unsigned); ++* ++* Input : Flag for MMU control ++* Hw16 = DTCM control (1 = to disable) ++* Hw12 = ICache control (1 = to disable) ++* Hw2 = DCache control (1 = to disable) ++* Hw0 = Protection control (1 = to disable) ++* Return : MMU Settings before modifying ++* Description : Clear MMU control flags according to argument ++**********************************************************/ ++unsigned IO_ARM_ClearMMU(unsigned); ++ ++/********************************************************** ++* unsigned IO_ARM_FlushCACHE(void); ++* ++* Input : None ++* Return : 0 ++* Description : Flush Data & Instruction Cache ++**********************************************************/ ++unsigned IO_ARM_FlushCACHE(void); ++ ++/********************************************************** ++* unsigned IO_ARM_FlushICACHE(void); ++* ++* Input : None ++* Return : 0 ++* Description : Flush Instruction Cache ++**********************************************************/ ++unsigned IO_ARM_FlushICACHE(void); ++ ++/********************************************************** ++* unsigned IO_ARM_FlushDCACHE(void); ++* ++* Input : None ++* Return : 0 ++* Description : Flush Data Cache ++**********************************************************/ ++unsigned IO_ARM_FlushDCACHE(void); ++ ++/********************************************************** ++* unsigned IO_ARM_GetICACHE(void); ++* ++* Input : None ++* Return : Current region flags for Inst Cache ++* HwX : Region X flag (1 = instruction cache enabled) ++* Description : Set Region flags for Inst Cache ++**********************************************************/ ++unsigned IO_ARM_GetICACHE(void); ++ ++/********************************************************** ++* unsigned IO_ARM_GetDCACHE(void); ++* ++* Input : None ++* Return : Current region flags for Data Cache ++* HwX : Region X flag (1 = data cache enabled) ++* Description : Set Region flags for Data Cache ++**********************************************************/ ++unsigned IO_ARM_GetDCACHE(void); ++ ++/********************************************************** ++* unsigned IO_ARM_GetWB(void); ++* ++* Input : None ++* Return : Current region flags for Write Buffering ++* HwX : Region X flag (1 = write buffer enabled) ++* Description : Get Region flags for Write Buffering ++**********************************************************/ ++unsigned IO_ARM_GetWB(void); ++ ++/********************************************************** ++* unsigned IO_ARM_SetCPSR(unsigned uCPSR); ++* ++* Input : uCPSR = value for new CPSR ++* Return : same as uCPSR ++* Description : Set the CPSR as uCPSR value ++**********************************************************/ ++unsigned IO_ARM_SetCPSR(unsigned uCPSR); ++ ++/********************************************************** ++* unsigned IO_ARM_GetCPSR(void); ++* ++* Input : None ++* Return : the CPSR register value ++* Description : Get the CPSR register value ++**********************************************************/ ++unsigned IO_ARM_GetCPSR(void); ++ ++/********************************************************** ++* unsigned IO_ARM_SetINT(unsigned uCPSR); ++* ++* Description : same as IO_ARM_SetCPSR() ++**********************************************************/ ++unsigned IO_ARM_SetINT(unsigned uCPSR); ++ ++/********************************************************** ++* unsigned IO_ARM_GetINT(void); ++* ++* Description : same as IO_ARM_GetCPSR() ++**********************************************************/ ++unsigned IO_ARM_GetINT(void); ++ ++/********************************************************** ++* unsigned IO_ARM_EnableFIQ(void); ++* ++* Input : None ++* Return : old CPSR (before FIQ enabled) ++* Description : Enable FIQ ++**********************************************************/ ++unsigned IO_ARM_EnableFIQ(void); ++ ++/********************************************************** ++* unsigned IO_ARM_DisableFIQ(void); ++* ++* Input : None ++* Return : old CPSR (before FIQ disabled) ++* Description : Disable FIQ ++**********************************************************/ ++unsigned IO_ARM_DisableFIQ(void); ++ ++/********************************************************** ++* unsigned IO_ARM_EnableIRQ(void); ++* ++* Input : None ++* Return : old CPSR (before IRQ enabled) ++* Description : Enable IRQ ++**********************************************************/ ++unsigned IO_ARM_EnableIRQ(void); ++ ++/********************************************************** ++* unsigned IO_ARM_DisableIRQ(void); ++* ++* Input : None ++* Return : old CPSR (before IRQ disabled) ++* Description : Disable IRQ ++**********************************************************/ ++unsigned IO_ARM_DisableIRQ(void); ++ ++/********************************************************** ++* unsigned IO_ARM_EnableINT(void); ++* ++* Input : None ++* Return : old CPSR (before Interrupt enabled) ++* Description : Enable IRQ/FIQ Interrupt ++**********************************************************/ ++unsigned IO_ARM_EnableINT(void); ++ ++/********************************************************** ++* unsigned IO_ARM_DisableINT(void); ++* ++* Input : None ++* Return : old CPSR (before Interrupt disabled) ++* Description : Disable IRQ/FIQ Interrupt ++**********************************************************/ ++unsigned IO_ARM_DisableINT(void); ++ ++/************************************************************************ ++* Interrupt Controller ++************************************************************************/ ++extern void IOS_INT_HandleIRQ0(int inum); ++extern void IOS_INT_HandleIRQ1(int inum); ++extern void IOS_INT_HandleIRQ2(int inum); ++extern void IOS_INT_HandleIRQ3(int inum); ++extern void IOS_INT_HandleIRQ4(int inum); ++extern void IOS_INT_HandleIRQ5(int inum); ++extern void IOS_INT_HandleIRQ6(int inum); ++extern void IOS_INT_HandleIRQ7(int inum); ++extern void IOS_INT_HandleIRQ8(int inum); ++extern void IOS_INT_HandleIRQ9(int inum); ++extern void IOS_INT_HandleIRQ10(int inum); ++extern void IOS_INT_HandleIRQ11(int inum); ++extern void IOS_INT_HandleIRQ12(int inum); ++extern void IOS_INT_HandleIRQ13(int inum); ++extern void IOS_INT_HandleIRQ14(int inum); ++extern void IOS_INT_HandleIRQ15(int inum); ++extern void IOS_INT_HandleIRQ16(int inum); ++extern void IOS_INT_HandleIRQ17(int inum); ++extern void IOS_INT_HandleIRQ18(int inum); ++extern void IOS_INT_HandleIRQ19(int inum); ++extern void IOS_INT_HandleIRQ20(int inum); ++extern void IOS_INT_HandleIRQ21(int inum); ++extern void IOS_INT_HandleIRQ22(int inum); ++extern void IOS_INT_HandleIRQ23(int inum); ++extern void IOS_INT_HandleIRQ24(int inum); ++extern void IOS_INT_HandleIRQ25(int inum); ++extern void IOS_INT_HandleIRQ26(int inum); ++extern void IOS_INT_HandleIRQ27(int inum); ++extern void IOS_INT_HandleIRQ28(int inum); ++extern void IOS_INT_HandleIRQ29(int inum); ++extern void IOS_INT_HandleIRQ30(int inum); ++extern void IOS_INT_HandleIRQ31(int inum); ++ ++/********************************************************** ++; unsigned IO_INT_EnableINT(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Enabled ++; ++; Description : Enable IRQ/FIQ Interrupt ++**********************************************************/ ++unsigned IO_INT_EnableINT(void); ++ ++/********************************************************** ++; unsigned IO_INT_EnableIRQ(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Enabled ++; ++; Description : Enable IRQ Interrupt ++**********************************************************/ ++unsigned IO_INT_EnableIRQ(void); ++ ++/********************************************************** ++; unsigned IO_INT_EnableFIQ(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Enabled ++; ++; Description : Enable FIQ Interrupt ++**********************************************************/ ++unsigned IO_INT_EnableFIQ(void); ++ ++/********************************************************** ++; unsigned IO_INT_DisableINT(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Disabled ++; ++; Description : Disable IRQ/FIQ Interrupt ++**********************************************************/ ++unsigned IO_INT_DisableINT(void); ++ ++/********************************************************** ++; unsigned IO_INT_DisableIRQ(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Disabled ++; ++; Description : Disable IRQ Interrupt ++**********************************************************/ ++unsigned IO_INT_DisableIRQ(void); ++ ++/********************************************************** ++; unsigned IO_INT_DisableFIQ(void) ++; ++; Input : None ++; Return : HwALLMSK before Interrupt Disabled ++; ++; Description : Disable FIQ Interrupt ++**********************************************************/ ++unsigned IO_INT_DisableFIQ(void); ++ ++/********************************************************** ++; unsigned IO_INT_RestoreINT(unsigned uMSK) ++; ++; Input : uMSK = Mask value for HwALLMSK ++; Return : uMSK ++; ++; Description : Restore IRQ/FIQ Interrupt ++**********************************************************/ ++unsigned IO_INT_RestoreINT(unsigned uMSK); ++ ++/************************************************************************ ++* Memory Controller ++************************************************************************/ ++/********************************************************** ++* void IO_MC_SetCFGInt(unsigned uCS, unsigned uValue); ++* ++* Input : uCS = 0~4 ++* uValue = register value for corresponding chip select ++* Return : ++* Description : Set the corresponding memory configuration register (HwCSCFG0~3, HwSDCFG) ++* This function is located in IO_LIB_INT area and ++* it should be located in the internal SRAM. ++**********************************************************/ ++void IO_MC_SetCFGInt(unsigned uCS, unsigned uValue); ++ ++/************************************************************************ ++* DMA Controller ++************************************************************************/ ++enum { ++ IO_DMA_CH0, ++ IO_DMA_CH1, ++ IO_DMA_CH2, ++ IO_DMA_CH3, ++ IO_DMA_CH4, ++ IO_DMA_CH5, ++ IO_DMA_CH6, ++ IO_DMA_CH7, ++ IO_DMA_CH8, ++ IO_DMA_CH9, ++ IO_DMA_CH10, ++ IO_DMA_CH11, ++ IO_DMA_CH_MAX ++}; ++ ++#if defined(TCC79XX) || defined(TCC92XX) || defined(TCC89XX) ++ #define IO_DMA_PORTCFG_NFC_READ 0 ++ #define IO_DMA_PORTCFG_NFC_WRITE 0 ++#endif ++ ++#define IO_DMA_EnableDMA(X) { BITSET(((sHwDMA *)(X))->CHCTRL, HwCHCTRL_EN_EN); } ++#define IO_DMA_DisableDMA(X) { BITSET(((sHwDMA *)(X))->CHCTRL, HwCHCTRL_EN_EN); } ++ ++/********************************************************** ++* void IO_DMA_SetCTRL(unsigned uCH, unsigned uCHCTRL); ++* ++* Input : uCH = Channel number (0~2) ++* uValue = DMA control register value of corresponding channel ++* Return : ++* Description : Set the corresponding DMA control register (HwCHCTRL0~1 in General DMA, HwCHCTRL0 in Storage DMA) ++**********************************************************/ ++PGDMACTRL IO_DMA_SetCTRL(unsigned uCH, unsigned uCHCTRL); ++ ++/********************************************************** ++* void IO_DMA_SetDMA(unsigned uCH, void *pSRC, unsigned uSPARAM, ++* void *pDST, unsigned uDPARAM, ++* unsigned uCHCTRL, unsigned uSize); ++* Input : uCH = Channel number (0~2) ++* pSRC = source address ++* uSPARAM = source parameter ++* pDST = destination address ++* uDPARAM = destination parameter ++* uCHCTRL = DMA control register ++* uSize = Transfer size (in byte unit) ++* Return : ++* Description : Set the DMA (and start to transfer) ++**********************************************************/ ++#ifdef TCC79XX ++sHwDMA *IO_DMA_SetDMA( ++ unsigned uCH, ++ void *pSRC, unsigned uSPARAM, ++ void *pDST, unsigned uDPARAM, ++ unsigned uCHCTRL, ++ unsigned uREQSRC, // added for TCC83XX 2007.9.13 ++ unsigned uSize ++ ); ++ ++sHwDMA *IO_DMA_SetDMA_NAND( ++ unsigned uCH, ++ void *pSRC, unsigned uSPARAM, ++ void *pDST, unsigned uDPARAM, ++ unsigned uCHCTRL, ++ unsigned uEXTREQ, ++ unsigned uSize ++); ++#endif ++ ++ ++#define HwCHCTRL_CONT_C Hw15 // DMA transfer begins from C_SADR/C_DADR Address. It must be used after the former transfer has been executed, so that C_SADR and C_DADR contain a meaningful value. ++#define HwCHCTRL_CONT_ST (0) // DMA trnaster begins from ST_SADR/ST_DADR Address ++#define HwCHCTRL_DTM_EN Hw14 // Differential Transfer Mode Enable ++#define HwCHCTRL_DTM_ON Hw14 // Differential Transfer Mode Enable ++#define HwCHCTRL_DTM_OFF (0) // Differential Transfer Mode Disable ++#define HwCHCTRL_SYNC_ON Hw13 // Synchronize HardWare Request ++#define HwCHCTRL_SYNC_OFF (0) // Do not Synchronize HardWare Request ++#define HwCHCTRL_SYNC_EN Hw13 // Synchronize Hardware Request ++#define HwCHCTRL_HRD_W Hw12 // ACK/EOT signals are issued When DMA-Write Operation ++#define HwCHCTRL_LOCK_EN Hw11 // DMA transfer executed with lock transfer ++#define HwCHCTRL_BST_NOARB Hw10 // DMA transfer executed with no arbitration(burst operation) ++#define HwCHCTRL_HRD_WR Hw12 // ACK/EOT signals are issued When DMA-Write Operation ++#define HwCHCTRL_HRD_RD (0) // ACK/EOT signals are issued When DMA-Read Operation ++#define HwCHCTRL_LOCK_ON Hw11 // DMA transfer executed with lock transfer ++#define HwCHCTRL_LOCK_OFF (0) // ++#define HwCHCTRL_BST_BURST Hw10 // DMA transfer executed with no arbitration(burst operation) ++#define HwCHCTRL_BST_ARB (0) // DMA transfer executed wth arbitration ++#define HwCHCTRL_TYPE_SINGE (0) // SINGLE transfer with edge-triggered detection ++#define HwCHCTRL_TYPE_HW Hw8 // HW Transfer ++#define HwCHCTRL_TYPE_SW Hw9 // SW transfer ++#define HwCHCTRL_TYPE_SINGL (Hw9|Hw8) // SINGLE transfer with level-triggered detection ++#define HwCHCTRL_TYPE_SL (Hw9|Hw8) // SINGLE transfer with level-triggered detection ++#define HwCHCTRL_TYPE_SE HwZERO // SINGLE transfer with edge-triggered detection ++ ++#define HwCHCTRL_BSIZE_1 (0) // 1 Burst transfer consists of 1 read or write cycle ++#define HwCHCTRL_BSIZE_2 Hw6 // 1 Burst transfer consists of 2 read or write cycles ++#define HwCHCTRL_BSIZE_4 Hw7 // 1 Burst transfer consists of 4 read or write cycles ++#define HwCHCTRL_BSIZE_8 (Hw6|Hw7) // 1 Burst transfer consists of 8 read or write cycles ++ ++#define HwCHCTRL_WSIZE_8 (0) // Each cycle read or write 8bit data ++#define HwCHCTRL_WSIZE_16 Hw4 // Each cycle read or write 16bit data ++#define HwCHCTRL_WSIZE_32 Hw5 // Each cycle read or write 32bit data ++ ++#define HwCHCTRL_FLAG Hw3 // Clears FLAG to 0 ++#define HwCHCTRL_IEN_ON Hw2 // At the same time the FLAG goes to 1, DMA interrupt request is generated ++#define HwCHCTRL_IEN_EN Hw2 // At the same time the FLAG goes to 1, DMA interrupt request is generated ++#define HwCHCTRL_IEN_OFF ~Hw2 // ++#define HwCHCTRL_REP_EN Hw1 // The DMA channel remains enabled ++#define HwCHCTRL_REP_DIS ~Hw1 // After all of hop transfer has executed, the DMA channel is disabled ++#define HwCHCTRL_EN_ON Hw0 // DMA channel is Enabled ++#define HwCHCTRL_EN_OFF ~Hw0 // DMA channel is terminated and disabled/*}}}*/ ++#define HwCHCTRL_EN_EN Hw0 // DMA channel is enabled. If software type transfer is selected, this bit generates DMA request directly, or if hardware type transfer is used, the selected interrupt request flag generate DMA request ++ ++ ++/************************************************************************ ++* ECC Controller ++************************************************************************/ ++#define IO_ECC_DisableECC() { HwECC_CTRL &= HwECC_CTRL_SE_DIS; } ++#define IO_ECC_EnableECC() { HwECC_CTRL |= HwECC_CTRL_SE_EN; } ++ ++/********************************************************** ++* int IO_ECC_CheckSLC(unsigned char *pcDATA, unsigned char *pcSPARE); ++* ++* Input : pcDATA = start address of data block ++* pcSPARE = start address of spare block ++* Return : 0 = no error or correctable error ++* -1 = uncorrectable error ++* Description : Check ECC and Correct Data Error ++************************************************************/ ++int IO_ECC_CheckSLC(unsigned char *pcDATA, unsigned char *pcSPARE); ++ ++/************************************************************************ ++* NAND Flash Controller ++************************************************************************/ ++#define HwNAND_CMD (pHwND->CMD) ++#define HwNAND_LADR (pHwND->LADR) ++#define HwNAND_DATA (pHwND->WDATA.D32) ++#define HwNAND_SDATA ((cIO_NFC_MEM) ? pHwND->WDATA.D8 : pHwND->SDATA.D32) ++#define HwNAND_SADR (pHwND->SADR) ++ ++#define ECC_BASEPAGE ((unsigned)&HwNAND_DATA) ++ ++typedef struct { // NAND Request Structure ++ unsigned CTRL; ++ unsigned PADDR; // Physical Address ++ unsigned NFCCFG; // image of HwNFC_CTRL register for corresponding request ++ unsigned *PBUF; // Pointer for Page Data ++ void *SBUF; // Pointer for Spare Data ++} sNFC_REQ; ++ ++typedef struct { // NAND Request Master Structure ++ unsigned uSEMA; // Semaphore ++ sNFC_REQ *pReqHead; // request is poped from here. ++ sNFC_REQ *pReqTail; // request is pushed to here. ++} sNFC_REQMST; ++ ++#define REQ_FAIL ((sNFC_REQ *)(-1)) ++ ++// sNFC_REQ.CTRL bit-field definition ++//----------------------------------------------------------------------------------- ++#define REQ_INACTIVE (Hw31) // Inactive, or End of Write Request (1) ++#define REQ_EOR (Hw30) // End of Read Request, but not copied yet. (1) ++#define REQ_ECCERR (Hw29) // Uncorrectable ECC error occurred. (1) ++#define REQ_SPARE (Hw28) // Start from the spare area. (1) ++//----------------------------------------------------------------------------------- ++#define REQ_DISABLE_MK (Hw27) // Disable Writing ECC MARK in data transfer (1) ++#define REQ_ECCEN (Hw26) // Calc ECC in data transfer (1) ++#define REQ_EOW (Hw25) // End of Write Request, but not check OK bit yet. (1) ++#define REQ_WOK (Hw24) // Write OK Flag (1) ++//----------------------------------------------------------------------------------- ++#define REQ_SKIPHCMD (Hw23) // Skip header command process (1) ++#define REQ_SKIPTCMD (Hw22) // Skip tail command process (1) ++#define REQ_SKIPCMD (Hw23|Hw22) ++#define REQ_CPBACK (Hw21) // Copy-Back Enabled. (1) ++#define REQ_CPBACKW (Hw20) // Copy-Back with partial writing. (1) ++//----------------------------------------------------------------------------------- ++#define REQ_SKIP10 (Hw19) // Skip 0x10 command in writePAGE. (1) ++#define REQ_ERASEBLK (Hw18) // Erase Block command. (1) ++#define REQ_PRO_SPARE (Hw17) // Process spare area. (1) ++//----------------------------------------------------------------------------------- ++#define REQ_READY (Hw12) // All settings for Request is ready (1) ++#define REQ_DSIZE_MASK (REQ_READY - 1) // [11:0] = Data Size ++#define REQ_DSIZE(X) ((X)&(REQ_DSIZE_MASK)) ++ ++// uCS bit-field definition ++#define REQ_CSMASK 0x0000000F ++ ++enum { IO_NFC_READ = 0, IO_NFC_WRITE = Hw15}; ++ ++void IO_NFC_InitDRV(void); ++void IO_NFC_OpenREQ(sNFC_REQ *pReq, unsigned uMaxNFC); ++void IO_NFC_CloseREQ(void); ++void IO_NFC_PopREQ(sNFC_REQ *pReq); ++void IO_NFC_EnableREQ(sNFC_REQ *pReq); ++void IO_NFC_IRQHandler(void); ++void IO_NFC_StartREAD(sNFC_REQ *pReq); ++void IO_NFC_ReadPAGE(unsigned *pBuffer, unsigned uDSize); ++void IO_NFC_ReadDATA(unsigned char *pBuffer, unsigned uDSize); ++int IO_NFC_CopyPAGE(unsigned char *pDest, unsigned *pSrc, unsigned uSize); ++sNFC_REQ *IO_NFC_PushRREQ(unsigned uCS, unsigned uPage, unsigned uColumn, unsigned *pSpare, unsigned uSize); ++void IO_NFC_StartWRITE(sNFC_REQ *pReq); ++void IO_NFC_WritePAGE(unsigned *pBuffer, unsigned uDSize); ++void IO_NFC_WriteDATA(unsigned char *pBuffer, unsigned uDSize); ++sNFC_REQ *IO_NFC_PushWREQ( unsigned uCS, unsigned uPage, unsigned uColumn, ++ unsigned *pData, unsigned char *pSpare, unsigned uSize); ++int IO_NFC_CheckWOK(sNFC_REQ *pReq); ++unsigned IO_NFC_LookupID(unsigned uDID); ++unsigned IO_NFC_SetCONFIG(unsigned uType); ++unsigned IO_NFC_MakeNFC(unsigned uCS); ++unsigned IO_NFC_GetID(unsigned uCS); ++unsigned IO_NFC_ResetNAND(unsigned uCS); ++void IO_NFC_SetCYCLE(void); ++void IO_NFC_WaitEOT(sNFC_REQ *pReq); ++ ++extern unsigned uIO_NFC_CONFIG, uIO_NFC_MASK; ++extern unsigned char cIO_NFC_MEM; ++extern PNFC pIO_NFC_HwND; ++ ++#define IO_NFC_MakeMASK(uCS) ((uIO_NFC_CONFIG & (Hw14 << (uCS*16))) ? 0xFFFF : 0xFF) ++ ++#define IO_NFC_SetNFC(uCS) \ ++{ \ ++ if (cIO_NFC_MEM) \ ++ HwCSCFG2 = IO_NFC_MakeNFC(uCS); \ ++ else \ ++ HwNFC_CTRL = IO_NFC_MakeNFC(uCS); \ ++} ++ ++#ifdef TCC79XX ++ #if defined(TCC7900_BOARD) ++ #define GPIO_ND_nCS HwPORTCFG2 ++ #define GPIO_ND_nCS1Bit Hw5 ++ #define GPIO_ND_nCS0Bit Hw4 ++ #define GPIO_ND_nWP HwPORTCFG2 ++ #define GPIO_ND_nWPBit Hw2 ++ #define GPIO_ND_RDY HwPORTCFG2 ++ #define GPIO_ND_RDYBit Hw3 ++ #define GPIO_NFC_nWP HwPORTCFG2 ++ #define GPIO_NFC_nWPBit Hw17 ++ #elif defined(TCC792X_BOARD) ++ #define GPIO_ND_nCS HwPORTCFG2 ++ #define GPIO_ND_nCS1Bit Hw9 ++ #define GPIO_ND_nCS0Bit Hw8 ++ #define GPIO_ND_RDY HwPORTCFG2 ++ #define GPIO_ND_RDYBit Hw14 ++ #endif ++#elif defined(TCC92XX) || defined(TCC89XX) ++ #if defined(TCC9200_BOARD) ++ #define GPIO_ND_nCS HwPORTCFG2 ++ #define GPIO_ND_nCS1Bit Hw9 ++ #define GPIO_ND_nCS0Bit Hw8 ++ #define GPIO_ND_RDY HwPORTCFG2 ++ #define GPIO_ND_RDYBit Hw14 ++ #endif ++#endif ++ ++#define IO_NFC_DisableCS() \ ++{ \ ++ if (cIO_NFC_MEM) \ ++ BITSET(GPIO_ND_nCS, GPIO_ND_nCS1Bit|GPIO_ND_nCS0Bit); \ ++ else \ ++ BITSET(HwNFC_CTRL, HwNFC_CTRL_CFG_NOACT); \ ++} ++ ++#define IO_NFC_EnableCS(uCS) \ ++{ \ ++ if (cIO_NFC_MEM) \ ++ BITSCLR(GPIO_ND_nCS, (uCS) ? GPIO_ND_nCS0Bit: GPIO_ND_nCS1Bit, (uCS) ? GPIO_ND_nCS1Bit: GPIO_ND_nCS0Bit); \ ++ else \ ++ BITSCLR(HwNFC_CTRL, (uCS) ? Hw22: Hw23, (uCS) ? Hw23 : Hw22); \ ++} ++ ++#define IO_NFC_DisableWP() \ ++{ \ ++ if (cIO_NFC_MEM) \ ++ BITSET(GPIO_ND_nWP, GPIO_ND_nWPBit); \ ++ else \ ++ BITSET(GPIO_NFC_nWP, GPIO_NFC_nWPBit); \ ++} ++ ++#define IO_NFC_EnableWP() \ ++{ \ ++ if (cIO_NFC_MEM) \ ++ BITCLR(GPIO_ND_nWP, GPIO_ND_nWPBit); \ ++ else \ ++ BITCLR(GPIO_NFC_nWP, GPIO_NFC_nWPBit); \ ++} ++ ++#define IO_NFC_NotREADY() \ ++ ( (cIO_NFC_MEM) ? ISZERO(GPIO_ND_RDY, GPIO_ND_RDYBit) : ISZERO(HwNFC_CTRL, HwNFC_CTRL_RDY_RDY)) ++ ++#define IO_NFC_WaitSTARDY() { ; } ++ ++void IO_NFC_WaitREADY(void); ++void IO_NFC_WaitREADYForWriteCommand(void); ++ ++#define IO_NFC_WaitDONE(X) { while (ISZERO(HwNFC_IREQ, (X))); } ++ ++#define USE_NFC_DMA ++#define USE_NFC_FIFO // only meaningful when "USE_NFC_DMA" is defined. ++ ++/************************************************************************ ++* DTCM Allocation Manager ++************************************************************************/ ++//#define USE_DYNAMIC_DTCM ++ ++#if defined(TCC79XX) ++ #define DTCM_BASE 0xA0000000 ++ #define DTCM_LIMIT 0xA0002000 ++ #define DTCM_SIZE (DTCM_LIMIT - DTCM_BASE) ++ #define ITCM_SIZE 0x00001000 ++ #define IO_USB_BUFFER0_BASE (DTCM_BASE + 0x1800) ++ #define IO_USB_BUFFER1_BASE (DTCM_BASE + 0x1A00) ++ #define IO_NFC_BUFFER0_BASE (DTCM_BASE + 0x1C00) ++ #define IO_NFC_BUFFER1_BASE (DTCM_BASE + 0x1E00) ++#elif defined(TCC92XX) || defined(TCC89XX) ++ #define DTCM_BASE 0xA0000000 ++ #define DTCM_LIMIT 0xA0004000 ++ #define DTCM_SIZE (DTCM_LIMIT - DTCM_BASE) ++ #define ITCM_SIZE 0x00004000 ++ #define IO_USB_BUFFER0_BASE (DTCM_BASE + 0x1800) ++ #define IO_USB_BUFFER1_BASE (DTCM_BASE + 0x1A00) ++ #define IO_NFC_BUFFER0_BASE (DTCM_BASE + 0x1C00) ++ #define IO_NFC_BUFFER1_BASE (DTCM_BASE + 0x1E00) ++#endif ++ ++ ++#define IO_HDD_BUFFER_BASE IO_NFC_BUFFER0_BASE ++ ++#ifdef USE_DYNAMIC_DTCM ++ #define DTCM_MaskSize (8 * sizeof(unsigned)) // bit width of uDTCM_MAT[] table ++ #define DTCM_Mask ((unsigned)((1 << DTCM_MaskSize) - 1)) // mask pattern of uDTCM_MAT[] table ++ #define DTCM_SIZE 4096 ++ #define DTCM_AUNIT 64 // minimum allocation unit. ++ #define DTCM_MAXBULK (DTCM_SIZE / DTCM_AUNIT) // maximum concurrent allocation. ++ #define DTCM_MATSIZE ((DTCM_SIZE / DTCM_AUNIT) / DTCM_MaskSize) // Bitmap table for each chunk (1 = used, 0 = not-used) ++#endif ++ ++void IO_DTCM_InitDRV(void); ++void *IO_DTCM_Malloc(unsigned uDSize); ++void IO_DTCM_Free(void *pSrc, unsigned uDSize); ++ ++unsigned IO_DTCM_AllocMAT(unsigned uASize); ++unsigned IO_DTCM_FindFMAX(void); ++ ++ ++/************************************************************************ ++* SRAM ADDR ++************************************************************************/ ++#ifdef TCC79XX ++ #define SRAM_BASE 0x00000000 ++ #define SRAM_LIMIT 0x00010000 ++#elif defined(TCC92XX) || defined(TCC89XX) ++ #define SRAM_BASE 0x10000000 ++ #define SRAM_LIMIT 0x00004000 ++#endif ++ ++/************************************************************************ ++* Interrupt Controller ++************************************************************************/ ++#ifdef TCC92XX ++ ++ // Interrupt Enable 0 ++/* ++ #define IO_INT_EHI0 HwINT0_EHI0 ++ #define IO_INT_ECC HwINT0_ECC ++ #define IO_INT_DMA HwINT0_DMA ++ #define IO_INT_TSADC HwINT0_TSADC ++ #define IO_INT_G2D HwINT0_G2D ++ #define IO_INT_3DMMU HwINT0_3DMMU ++ #define IO_INT_3DGP HwINT0_3DGP ++ #define IO_INT_3DPP HwINT0_3DPP ++ #define IO_INT_VCDC HwINT0_VCDC ++ #define IO_INT_JPGD HwINT0_JPGD ++ #define IO_INT_JPGE HwINT0_JPGE ++ #define IO_INT_VIPET HwINT0_VIPET ++ #define IO_INT_LCD1 HwINT0_LCD1 ++ #define IO_INT_LCD0 HwINT0_LCD0 ++ #define IO_INT_CAM HwINT0_CAM ++ #define IO_INT_SC1 HwINT0_SC1 ++ #define IO_INT_SC0 HwINT0_SC0 ++ #define IO_INT_EI11 HwINT0_EI11 ++ #define IO_INT_EI10 HwINT0_EI10 ++ #define IO_INT_EI9 HwINT0_EI9 ++ #define IO_INT_EI8 HwINT0_EI8 ++ #define IO_INT_EI7 HwINT0_EI7 ++ #define IO_INT_EI6 HwINT0_EI6 ++ #define IO_INT_EI5 HwINT0_EI5 ++ #define IO_INT_EI4 HwINT0_EI4 ++ #define IO_INT_EI3 HwINT0_EI3 ++ #define IO_INT_EI2 HwINT0_EI2 ++ #define IO_INT_EI1 HwINT0_EI1 ++ #define IO_INT_EI0 HwINT0_EI0 ++ #define IO_INT_SMUI2C HwINT0_SMUI2C ++ #define IO_INT_TC1 HwINT0_TC1 ++ #define IO_INT_TC0 HwINT0_TC0 ++*/ ++ enum { ++ IO_INT_nTC0, // 0 ++ IO_INT_nTC1, ++ IO_INT_nSMUI2C, ++ IO_INT_nEI0, ++ IO_INT_nEI1, ++ IO_INT_nEI2, // 5 ++ IO_INT_nEI3, ++ IO_INT_nEI4, ++ IO_INT_nEI5, ++ IO_INT_nEI6, ++ IO_INT_nEI7, // 10 ++ IO_INT_nEI8, ++ IO_INT_nEI9, ++ IO_INT_nEI10, ++ IO_INT_nEI11, ++ IO_INT_nSC0, // 15 ++ IO_INT_nSC1, ++ IO_INT_nCAM, ++ IO_INT_nLCD0, ++ IO_INT_nLCD1, ++ IO_INT_nVIPET, // 20 ++ IO_INT_nJPGE, ++ IO_INT_nJPGD, ++ IO_INT_nVCDC, ++ IO_INT_n3DPP, ++ IO_INT_n3DGP, // 25 ++ IO_INT_n3DMMU, ++ IO_INT_nG2D, ++ IO_INT_nTSADC, ++ IO_INT_nDMA, ++ IO_INT_nECC, // 30 ++ IO_INT_nEHI0 ++ }; ++ ++ // Interrupt Enable 1 ++/* ++ #define IO_INT_AEIRQ HwINT1_AEIRQ ++ #define IO_INT_ASIRQ HwINT1_ASIRQ ++ #define IO_INT_AIRQ HwINT1_AIRQ ++ #define IO_INT_APMU HwINT1_APMU ++ #define IO_INT_AUDIO HwINT1_AUDIO ++ #define IO_INT_ADMA HwINT1_ADMA ++ #define IO_INT_DAITX HwINT1_DAITX ++ #define IO_INT_DAIRX HwINT1_DAIRX ++ #define IO_INT_CDRX HwINT1_CDRX ++ #define IO_INT_TSIF1 HwINT1_TSIF1 ++ #define IO_INT_TSIF0 HwINT1_TSIF0 ++ #define IO_INT_GPS2 HwINT1_GPS2 ++ #define IO_INT_GPS1 HwINT1_GPS1 ++ #define IO_INT_GPS0 HwINT1_GPS0 ++ #define IO_INT_UOTG HwINT1_UOTG ++ #define IO_INT_UART HwINT1_UART ++ #define IO_INT_SPDTX HwINT1_SPDTX ++ #define IO_INT_SD1 HwINT1_SD1 ++ #define IO_INT_SD0 HwINT1_SD0 ++ #define IO_INT_RTC HwINT1_RTC ++ #define IO_INT_RMT HwINT1_RMT ++ #define IO_INT_NFG HwINT1_NFC ++ #define IO_INT_MS HwINT1_MS ++ #define IO_INT_MPEFEC HwINT1_MPEFEC ++ #define IO_INT_I2C HwINT1_I2C ++ #define IO_INT_HDD HwINT1_HDD ++ #define IO_INT_GPSB HwINT1_GPSB ++ #define IO_INT_HDMI HwINT1_HDMI ++ #define IO_INT_EHI1 HwINT1_EHI1 ++*/ ++ enum { ++ IO_INT_nEHI1, // 0 ++ IO_INT_nNotUsed0, ++ IO_INT_nHDMI, ++ IO_INT_nNotUsed1, ++ IO_INT_nGPSB, ++ IO_INT_nHDD, // 5 ++ IO_INT_nI2C, ++ IO_INT_nMPEFEC, ++ IO_INT_nMS, ++ IO_INT_nNFC, ++ IO_INT_nRMT, // 10 ++ IO_INT_nRTC, ++ IO_INT_nSD0, ++ IO_INT_nSD1, ++ IO_INT_nSPDTX, ++ IO_INT_nUART, // 15 ++ IO_INT_nUOTG, ++ IO_INT_nNotUsed2, ++ IO_INT_nGPS0, ++ IO_INT_nGPS1, ++ IO_INT_nGPS2, // 20 ++ IO_INT_nTSIF0, ++ IO_INT_nTSIF1, ++ IO_INT_nCDRX, ++ IO_INT_nDAIRX, ++ IO_INT_nDAITX, // 25 ++ IO_INT_nADMA, ++ IO_INT_nAUDIO, ++ IO_INT_nAPMU, ++ IO_INT_nAIRQ, ++ IO_INT_nASIRQ, // 30 ++ IO_INT_nAEIRQ, ++ }; ++ ++#elif defined(TCC79XX) ++ #define IO_INT_HwIEN HwIEN ++ #define IO_INT_HwISTS HwSTS ++ #define IO_INT_HwMSTS HwMSTS ++ #define IO_INT_HwICLR HwCLR ++ #define IO_INT_HwISEL HwSEL ++ #define IO_INT_HwTMODE HwMODE ++ #define IO_INT_HwPOL HwPOL ++ #define IO_INT_HwEXT0 HwINT_EI0 ++ #define IO_INT_HwEXT1 HwINT_EI1 ++ #define IO_INT_HwEXT2 HwINT_EI2 ++ #define IO_INT_HwEXT3 HwINT_EI3 ++ #define IO_INT_HwRTC HwINT_RTC ++ #define IO_INT_HwGPSB HwINT_GPSB ++ #define IO_INT_HwGPSB_CH0 HwINT_GPSB ++ #define IO_INT_HwGPSB_CH1 HwINT_GPSB ++ #define IO_INT_HwGPSB_CH2 HwINT_GPSB ++ #define IO_INT_HwGPSB_CH3 HwINT_GPSB ++ #define IO_INT_HwTIMER (HwINT_TC1 | HwINT_TC0) ++ #define IO_INT_HwTC0 HwINT_TC0 ++ #define IO_INT_HwTC1 HwINT_TC1 ++ #define IO_INT_HwSCORE HwINT_SCORE ++ #define IO_INT_HwSPDTX HwINT_SPDTX ++ #define IO_INT_HwSEL0 HwINT_SEL0 ++ #define IO_INT_HwSEL1 HwINT_SEL1 ++ #define IO_INT_HwSC HwINT_SC ++ #define IO_INT_HwI2C HwINT_I2C ++ #define IO_INT_HwDAIRX HwINT_DAIRX ++ #define IO_INT_HwDAITX HwINT_DAITX ++ #define IO_INT_HwCDIF HwINT_CDRX ++ #define IO_INT_HwEHI HwINT_HPI ++ #define IO_INT_HwUART HwINT_UT ++ #define IO_INT_HwUART0 HwINT_UT ++ #define IO_INT_HwUART1 HwINT_UT ++ #define IO_INT_HwSEL2 HwINT_SEL2 ++ #define IO_INT_HwG2D HwINT_G2D ++ #define IO_INT_HwUSBD HwINT_UD ++ #define IO_INT_HwUSBH HwINT_UH ++ #define IO_INT_HwDMA HwINT_DMA ++ #define IO_INT_HwDMA_CH0 HwINT_DMA ++ #define IO_INT_HwDMA_CH1 HwINT_DMA ++ #define IO_INT_HwDMA_CH2 HwINT_DMA ++ #define IO_INT_HwHDD HwINT_HDD ++ #define IO_INT_HwSEL3 HwINT_SEL3 ++ #define IO_INT_HwNFC HwINT_NFC ++ #define IO_INT_HwSDMMC HwINT_SD ++ #define IO_INT_HwCAM HwINT_CAM ++ #define IO_INT_HwLCD HwINT_LCD ++ #define IO_INT_HwADC HwINT_ADC ++ #define IO_INT_HwSEL4 HwINT_SEL4 ++ #define IO_INT_HwGSIO 0 ++ ++ #define IO_INT_HwVIDEO HwINT_SEL0 ++ #define IO_INT_HwEXT5 HwINT_SEL1 ++ #define IO_INT_HwEHI1 HwINT_SEL2 ++ #define IO_INT_HwMSC HwINT_SEL3 ++ #define IO_INT_HwEXT7 HwINT_SEL4 ++ #define IO_INT_HwUSBDMA HwINT_SEL4 ++ ++ enum { ++ IO_INT_nEI0, // 0 ++ IO_INT_nEI1, ++ IO_INT_nEI2, ++ IO_INT_nEI3, ++ IO_INT_nRTC, ++ IO_INT_nGPSB, // 5 ++ IO_INT_nTC0, ++ IO_INT_nTC1, ++ IO_INT_nVCORE, ++ IO_INT_nSPDTX, ++ IO_INT_nVIDEO, // 10 ++ IO_INT_nEI5, ++ IO_INT_nSC, ++ IO_INT_nI2C, ++ IO_INT_nDAIRX, ++ IO_INT_nDAITX, // 15 ++ IO_INT_nCDRX, ++ IO_INT_nEHI, ++ IO_INT_nUT0, ++ IO_INT_nEHI1, ++ IO_INT_nUDMA, // 20 ++ IO_INT_nUD, ++ IO_INT_nUH, ++ IO_INT_nDMA, ++ IO_INT_nHDD, ++ IO_INT_nMS, // 25 ++ IO_INT_nNFC, ++ IO_INT_nSD, ++ IO_INT_nCAM, ++ IO_INT_nLCD, ++ IO_INT_nADC, // 30 ++ IO_INT_nUSBDMA ++ }; ++#endif ++ ++#if 0 ++#define IO_INT_EnableIRQ(X) \ ++ { \ ++ BITSET(IO_INT_HwISEL, X); \ ++ BITSET(IO_INT_HwIEN, X); \ ++ } ++#define IO_INT_DisableIRQ(X) \ ++ { \ ++ BITCLR(HwIEN, X); \ ++ } ++#endif ++/************************************************************************ ++* EHI Controller ++************************************************************************/ ++#define EHI_MD_68 HwEHCFG_MD_68 ++#define EHI_MD_80 HwEHCFG_MD_80 ++#define EHI_USE_MASK Hw1 ++#define EHI_BW_8 HwEHCFG_BW_8 ++#define EHI_BW_16 HwEHCFG_BW_16 ++#define EHI_USE_RDY HwEHCFG_RDYE_RDY ++#define EHI_USE_IRQ HwEHCFG_RDYE_IRQ ++#define EHI_HIGH_RDY HwZERO ++#define EHI_LOW_RDY HwEHCFG_RDYP ++ ++extern unsigned uEHI_CSCFG, uEHI_TACC; ++extern volatile unsigned *pEHI_CSCFG; ++ ++#ifdef EHIS_TCC77X ++ #define EHIS_HwEHST 0x90000800 // R/W, Status register ++ #define EHIS_HwEHIINT 0x90000804 // R/W, Internal interrupt control register ++ #define EHIS_HwEHEINT 0x90000808 // R/W, External interrupt control register ++ #define EHIS_HwEHA 0x9000080C // R/W, Address register ++ #define EHIS_HwEHAM 0x90000810 // R, Address masking register ++ #define EHIS_HwEHD 0x90000814 // R/W, Data register ++ #define EHIS_HwEHSEM 0x90000818 // R/W, Semaphore register ++ #define EHIS_HwEHCFG 0x9000081C // R/W, Configuration register ++ #define EHIS_HwEHIND 0x90000820 // W, Index register ++ #define EHIS_HwEHRWCS 0x90000824 // R/W, Read/Write Control/Status register ++#endif ++ ++#ifdef EHI_MASTER ++ /********************************************************** ++ * void IO_EHI_InitDRV(unsigned uCONFIG, unsigned uCS, unsigned uMask); ++ * ++ * Input : uCONFIG = Configuration Parameter ++ * Hw0 = 68000 (1), x86 (0) interface ++ * Hw1 = Use Mask (1), Don't used Mask (0) ++ * Hw2 = 8bit (1), 16bit (0) interface ++ * Hw3 = used as Ready signal (1), used as Interrupt signal (0) ++ * Hw4 = Active Low Ready signal (1), Active High Ready signal (0) ++ * uCS = Chip Select number for EHI slave (0~3) ++ * uMask = Address Mask Pattern. ++ * Return : ++ * Description : Initialize EHI I/F module at the Master Site. ++ ************************************************************/ ++ void IO_EHI_InitDRV(unsigned uCONFIG, unsigned uCS, unsigned uMask); ++ ++ /********************************************************** ++ * unsigned IO_EHI_SetSPEED(unsigned uTAcc); ++ * ++ * Input : uTAcc = Access time in nano second ++ * Output : ++ * Return : previous CSCFG value ++ * ++ * Description : Set EHI Access parameter ++ ************************************************************/ ++ unsigned IO_EHI_SetSPEED(unsigned uTAcc); ++ ++ /********************************************************** ++ * unsigned IO_EHI_IncSPEED(int iTAccDelta); ++ * ++ * Input : iTAccDelta = Increment(+)/Decrement(-) of Access time in nano second ++ * Output : ++ * Return : Old TAcc ++ * ++ * Description : Increment EHI Access parameter ++ ************************************************************/ ++ unsigned IO_EHI_IncSPEED(int iTAccDelta); ++ ++ /********************************************************** ++ * void IO_EHI_WriteREG(unsigned uADDR, unsigned uDATA, unsigned uSize); ++ * ++ * Input : uADDR = Address of EHI Register ++ * uDATA = Data for EHI Register ++ * uSize = Register Size in byte. ++ * Return : ++ * Description : Write EHI Register ++ ************************************************************/ ++ void IO_EHI_WriteREG(unsigned uADDR, unsigned uDATA, unsigned uSize); ++ ++ /********************************************************** ++ * unsigned IO_EHI_ReadREG(unsigned uADDR, unsigned uSize); ++ * ++ * Input : uADDR = Address of EHI Register ++ * uSize = Register Size in byte. ++ * Return : Register value ++ * Description : Read EHI Register ++ ************************************************************/ ++ unsigned IO_EHI_ReadREG(unsigned uADDR, unsigned uSize); ++ ++ /********************************************************** ++ * unsigned IO_EHI_ReadST(void); ++ * ++ * Input : ++ * Output : ++ * Return : EHST value ++ * ++ * Description : Read EHST Register ++ ************************************************************/ ++ unsigned IO_EHI_ReadST(void); ++ ++ /********************************************************** ++ * unsigned IO_EHI_WriteDATA(unsigned uADDR, unsigned uParam1, unsigned uParam2); ++ * ++ * Input : uADDR = Address of EHI Slave memory. ++ * uParam1 = Pointer or Data value to write. ++ * uParam2 ++ * [31] = Non-continuous(0), Continuous(1) ++ * [30:0] = Data amount to Transfer (word unit) ++ * Return : 0 ++ * Description : Write data to Memory of Slave ++ ************************************************************/ ++ unsigned IO_EHI_WriteDATA(unsigned uADDR, unsigned uParam1, unsigned uParam2); ++ ++ /********************************************************** ++ * unsigned IO_EHI_ReadDATA(unsigned uADDR, unsigned uParam1, unsigned uParam2); ++ * ++ * Input : uADDR = Address of EHI Slave memory. ++ * uParam1 = Pointer to store read data. ++ * uParam2 ++ * [31] = Non-continuous (0), Continuous (1) transfer. ++ * [30:0] = Data amount to Transfer (word unit) ++ * Return : Data value read or Pointer to bulk of data read. ++ * Description : Read data from Memory of Slave ++ ************************************************************/ ++ unsigned IO_EHI_ReadDATA(unsigned uADDR, unsigned uParam1, unsigned uParam2); ++#else ++ /********************************************************** ++ * void IO_EHI_InitDRVS(unsigned uCONFIG); ++ * ++ * Input : uCONFIG = Configuration Parameter ++ * Hw0 = 68000 (1), x86 (0) interface ++ * Hw2 = 8bit (1), 16bit (0) interface ++ * Hw3 = used as Ready signal (1), used as Interrupt signal (0) ++ * Hw4 = Active Low Ready signal (1), Active High Ready signal (0) ++ * Return : ++ * Description : Initialize EHI I/F module at the Slave Site. ++ ************************************************************/ ++ void IO_EHI_InitDRVS(unsigned uCONFIG); ++#endif ++ ++ ++/************************************************************************ ++* Timer/Counter ++************************************************************************/ ++#if defined(TCC92XX) ++ #define IO_TMR_IREQT0 HwTIREQ_TI0 ++ #define IO_TMR_IREQT1 HwTIREQ_TI1 ++ #define IO_TMR_IREQT2 HwTIREQ_TI2 ++ #define IO_TMR_IREQT3 HwTIREQ_TI3 ++ #define IO_TMR_IREQT4 HwTIREQ_TI4 ++ #define IO_TMR_IREQT5 HwTIREQ_TI5 ++ #define IO_TMR_ClearTIREQ(X) { HwTMR->TIREQ = 1 << (X); } ++#else ++#ifdef TCC79XX ++ #define IO_TMR_IREQT0 HwTIREQ_TI0 ++ #define IO_TMR_IREQT1 HwTIREQ_TI1 ++ #define IO_TMR_IREQT2 HwTIREQ_TI2 ++ #define IO_TMR_IREQT3 HwTIREQ_TI3 ++ #define IO_TMR_IREQT4 HwTIREQ_TI4 ++ #define IO_TMR_IREQT5 HwTIREQ_TI5 ++#endif ++#define IO_TMR_ClearTIREQ(X) { HwTIREQ = 1 << (X); } ++#endif ++ ++/********************************************************** ++* void IO_TMR_SetTIMER(unsigned uCH, unsigned uCTRL, unsigned uTREF, unsigned uTMREF); ++* ++* Input : uCH = Select timer channel. 0~5 is available. ++* uCTRL = Timer Control Register (HwTCFG) value. ++* uTREF = Timer Reference Register (HwTREF) value. ++* uTMREF = Timer Middle Reference Register (HwTMREF) value. ++* Return : ++* Description : Set and Enable a Timer/Counter (timer is automatically enabled regardless of uCTRL value) ++**********************************************************/ ++void IO_TMR_SetTIMER(unsigned uCH, unsigned uCTRL, unsigned uTREF, unsigned uTMREF); ++ ++/********************************************************** ++* unsigned IO_TMR_GetTIMER(unsigned uCH); ++* ++* Input : uCH = Select timer channel. 0~5 is available. ++* Return : Current TCNT value. ++* Description : Get the current count value of channel. ++**********************************************************/ ++unsigned IO_TMR_GetTIMER(unsigned uCH); ++ ++/********************************************************** ++* void IO_TMR_DisableTIMER(unsigned uCH); ++* ++* Input : uCH = Select timer channel. 0~5 is available. ++* Return : ++* Description : Disable a Timer ++**********************************************************/ ++void IO_TMR_DisableTIMER(unsigned uCH); ++ ++/********************************************************** ++* void IO_TMR_EnableTIMER(unsigned uCH); ++* ++* Input : uCH = Select timer channel. 0~5 is available. ++* Return : ++* Description : Enable a Timer ++**********************************************************/ ++void IO_TMR_EnableTIMER(unsigned uCH); ++ ++#define DBG_MAX_MEASURE 32 ++#define START_MEASURE 1 ++#define STOP_MEASURE 0 ++ ++typedef struct ++{ ++ unsigned uStamp; // Time Stamp value at the start time. ++ char *pDescription; // Timer description string. ++ unsigned uPreCH; // Bitmap of Channels that must to be enabled ahead to measure this channel. ++ unsigned uMin; // 1tic ~= 2.67us ++ unsigned uMax; // 1tic ~= 2.67us ++ unsigned long long uSum; // summation of duration ++ unsigned uNum; // Number of durations measured. The average duration is acquired by (uSum / uNum) ++} sDBG_Timer; ++ ++extern sDBG_Timer DBG_Timer[DBG_MAX_MEASURE]; ++extern unsigned uMEA_CTRL, uMEA_STATE; ++ ++/********************************************************** ++* void IO_TMR_InitMEASURE(unsigned uCH); ++* ++* Input : uCH = Select a channel for initialize. (0xFFFFFFFF, 0 ~ 31 are possible, 0xFFFFFFFF means all of channel) ++* (this is not same as physical timer channel number. this uses TIMER channel 4 only) ++* Return : ++* Description : Initialize MEASURE variables. ++* If all of channel should be initialized, use -1 as channel number. ++**********************************************************/ ++void IO_TMR_InitMEASURE(unsigned uCH); ++ ++/********************************************************** ++* void IO_TMR_StartMEASURE(unsigned uCH, char *pDescriptor); ++* ++* Input : uCH = Select a channel for measure. (0 ~ 31 are possible) ++* (this is not same as physical timer channel number. this uses TIMER channel 4 only) ++* pDescriptor = string for describing this channel. ++* Return : ++* Description : Start the timer for measuring a duration. ++* This uses only timer/counter 4. ++* It can measure the min/max/avg time duration of certain operation with limited period. ++**********************************************************/ ++void IO_TMR_StartMEASURE(unsigned uCH, unsigned uPreCH, char *pDescriptor); ++void IO_TMR_StopMEASURE(unsigned uCH); ++void IO_TMR_StartMEASURE_NoIRQCnt(unsigned uCH, unsigned uPreCH, char *pDescriptor); ++unsigned IO_TMR_StopMEASURE_NoIRQCnt(unsigned uCH); ++ ++/********************************************************** ++* void IO_TMR_FinishMEASURE(unsigned uCH); ++* ++* Input : uCH = Select a channel for measure. (0 ~ 31 are possible) ++* (this is not same as physical timer channel number. this uses TIMER channel 4 only) ++* Return : ++* Description : Finish the timer for measuring a duration. ++* This uses only timer/counter 4. ++* It stops measuring, and update min/max/sum/num field. ++**********************************************************/ ++void IO_TMR_FinishMEASURE(unsigned uCH); ++ ++/********************************************************** ++* void IO_TMR_GetMEASURE(unsigned uCH, unsigned *pAvg, unsigned *pNum, unsigned *pMin, unsigned *pMax); ++* ++* Input : uCH = Select a channel for measure. (0 ~ 31 are possible) ++* (this is not same as physical timer channel number. this uses TIMER channel 4 only) ++* pAvg = pointer for containing average time ++* pNum = pointer for containing number of times ++* pMin = pointer for containing minimum time ++* pMax = pointer for containing maximum time ++* *) all pointers can be zero not to contain values. ++* Return : ++* Description : ++**********************************************************/ ++void IO_TMR_GetMEASURE(unsigned uCH, unsigned *pAvg, unsigned *pNum, unsigned *pMin, unsigned *pMax); ++ ++// Time Duration Meter ++#ifndef USE_DOMEASURE ++ #define DoMEASURE(CH, ONOFF, PreCH, Descriptor) {;} ++#else ++ #define DoMEASURE(CH, ONOFF, PreCH, Descriptor) \ ++ { \ ++ if (uMEA_CTRL & (1 << (CH))) \ ++ { \ ++ if ((ONOFF) != 0) \ ++ IO_TMR_StartMEASURE(CH, PreCH, Descriptor); \ ++ else \ ++ IO_TMR_FinishMEASURE(CH); \ ++ } \ ++ } ++#endif ++ ++/********************************************************** ++* unsigned int IO_TMR_Get32bitValue(void); ++* ++* Input : ++* Return : 32-bit Counter Current Value (main counter) ++* Description : ++**********************************************************/ ++unsigned int IO_TMR_Get32bitValue(void); ++ ++ ++/************************************************************************ ++* UART Controller ++************************************************************************/ ++ ++/********************************************************** ++* ++* void IO_UART_Test(unsigned uCH); ++* ++* Input : uCH = channel number (0~2) ++* Output : ++* Return : ++* ++* Description : Test UART functions. ++**********************************************************/ ++void IO_UART_Test(unsigned uCH); ++ ++/********************************************************** ++* ++* void IO_UART_Init(unsigned uCH); ++* ++* Input : uCH = channel number (0~2) ++* Output : ++* Return : ++* ++* Description : Initialize UART registers and UART Clocks. ++**********************************************************/ ++void IO_UART_Init(unsigned uCH); ++ ++/********************************************************** ++* ++* void IO_UART_WriteString(unsigned uCH, const char *ccptrString) ++* ++* Input : uCH = channel number (0~2) ++* ccptrString = string to print ++* Output : ++* Return : ++* ++* Description : print argument string considering '\n' as '\r'+'n'. ++**********************************************************/ ++void IO_UART_WriteString(unsigned uCH, const char *ccptrString); ++ ++/********************************************************** ++* ++* void IO_UART_WriteByte(unsigned uCH, char cChar) ++* ++* Input : uCH = channel number (0~2) ++* cChar = character to print ++* Output : ++* Return : ++* ++* Description : Print one character. Consider '\n' as '\r' + '\n'. ++**********************************************************/ ++void IO_UART_WriteByte(unsigned uCH, char cChar); ++ ++/********************************************************** ++* ++* int IO_UART_InputByte(unsigned uCH, char *cptrChar) ++* ++* Input : uCH = channel number (0~2) ++* cptrChar = pointer for receiving character ++* Output : ++* Return : 0 = there is no input. ++* 1 = there exist at least one byte and it is contained at the *cptrChar. ++* Description : Check there is at least one character in buffer, and if exist, store the code to *cptrChar and return 1. ++* Or return 0. ++**********************************************************/ ++int IO_UART_InputByte(unsigned uCH, char *cptrChar); ++ ++/********************************************************** ++* ++* void IO_UART0_PutExtChar(unsigned uCH, const unsigned char cucChar) ++* ++* Input : uCH = channel number (0~2) ++* cucChar = character code ++* Output : Send one character ++* Return : ++* ++* Description : Print cucChar if cucChar is printable code or print '.' character. ++**********************************************************/ ++void IO_UART_PutExtChar(unsigned uCH, const unsigned char cucChar); ++ ++/********************************************************** ++* ++* char IO_UART_GetChar(unsigned uCH) ++* ++* Input : uCH = channel number (0~2) ++* Output : ++* Return : Received character ++* ++* Description : Wait until at least one character is received & return the code with echoing. ++**********************************************************/ ++char IO_UART_GetChar(unsigned uCH); ++ ++/********************************************************** ++* ++* char IO_UART_GetCh(unsigned uCH) ++* ++* Input : uCH = channel number (0~2) ++* Output : ++* Return : Received character ++* ++* Description : Wait until at least one character is received & return the code without echoing. ++**********************************************************/ ++char IO_UART_GetCh(unsigned uCH); ++ ++ ++/************************************************************************ ++* RTC Controller ++************************************************************************/ ++typedef struct { ++ unsigned char second; // (0 ~ 59) ++ unsigned char minute; // (0 ~ 59) ++ unsigned char hour; // (0 ~ 23) ++ unsigned char day; // Day of Week (SUN=0, MON, TUE, WED, THR, FRI, SAT=6) ++ ++ unsigned char date; // (1 ~ 28,29,30,31) ++ unsigned char month; // (1 ~ 12) ++ unsigned short year; ++} IO_RTC_DATETIME; ++ ++/********************************************************************************** ++* unsigned IO_RTC_Init(unsigned uWUPolarity); ++* ++* Input : ++* Return : 0 ++* Description : Initialize RTC, RTC is disabled. ++* This function should not be called in normal case. ++**********************************************************************************/ ++unsigned IO_RTC_Init(unsigned uWUPolarity); ++ ++/********************************************************************************** ++* unsigned IO_RTC_Start(void); ++* ++* Input : ++* Return : value of RTCCON register after enabled. ++* Description : RTC starts to operate. ++**********************************************************************************/ ++unsigned IO_RTC_Start(void); ++ ++/********************************************************************************** ++* unsigned IO_RTC_Stop(void); ++* ++* Input : ++* Return : value of RTCCON register after disabled. ++* Description : RTC stops to operate. ++**********************************************************************************/ ++unsigned IO_RTC_Stop(void); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetCON(unsigned uRTCCON); ++* ++* Input : uRTCCON = value for RTCCON register. ++* Return : value of RTCCON register after updated. ++* Description : Set RTCCON register as wanted value. ++**********************************************************************************/ ++unsigned IO_RTC_SetCON(unsigned uRTCCON); ++ ++/********************************************************************************** ++* unsigned IO_RTC_GetTIME(IO_RTC_DATETIME *pTime); ++* Input : pTime = structure for getting RTC Time. (each element has decimal (non-BCD) value.) ++* Return : 0 = OK ++* 1 = Read value has some error, and pTime contains predefined initial values ++* for calling IO_RTC_SetTIME(); ++* Description : Get current time of RTC. ++* RTC has no power-on reset feature, it has random value after power-on. ++* It is reported by return value of 1 so user must re-set the current time. ++**********************************************************************************/ ++unsigned IO_RTC_GetTIME(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_IsValidTime(void); ++* ++* Input : void ++* Return : 0 = OK ++* 1 = Read value has some error ++* Description :This function is made to check whether current time setteing is correct or not ++* Maybe this function will be called by only the Janus core and will be used for setting ++* current RTC state(SET or UNSET). ++**********************************************************************************/ ++unsigned IO_RTC_IsValidTime(void); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetTIME(RTC_APP_DATETIME *pTime); ++* ++* Input : pTime = structure for setting RTC Time (refer to IO_RTC_GetTIME()) ++* Return : 0 ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_SetTIME(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetBCDALARM(IO_RTC_DATETIME *pTime, unsigned uCON); ++* ++* Input : pTime = structure for setting RTC Time. (each element has BCD format) ++* uCON = same as HwRTCALM register map (refer to datasheet) ++* Return : 0 ++* Description : Set ALARM time. It is not supported all combination of ALARM time. ++**********************************************************************************/ ++unsigned IO_RTC_SetBCDALARM(IO_RTC_DATETIME *pTime, unsigned uCON); ++ ++/********************************************************************************** ++* unsigned IO_RTC_GetBCDTIME(RTC_APP_DATETIME *pTime); ++* ++* Input : pTime = structure for getting RTC Time. (BCD format) ++* Return : 0 ++* Description : The current time is stored to structure pointed by pTime. ++**********************************************************************************/ ++unsigned IO_RTC_GetBCDTIME(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetBCDTIME(RTC_APP_DATETIME *pTime); ++* ++* Input : pTime = structure for setting RTC Time. (BCD format) ++* Return : 0 ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_SetBCDTIME(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_BCD2DEC( unsigned nBCD ); ++* ++* Input : nBCD = BCD format value ++* Return : Equivalent value of hexa-decimal format ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_BCD2DEC( unsigned nBCD ); ++ ++/********************************************************************************** ++* unsigned IO_RTC_DEC2BCD( unsigned uDEC ); ++* ++* Input : nDEC = hexa-decimal format value ++* Return : Equivalent value of BCD format ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_DEC2BCD( unsigned nDEC ); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetALARM(IO_RTC_DATETIME *pTime); ++* ++* Input : pTime = structure for setting RTC Time. (Hexa-decimal format) ++* Output : ++* Return : 0 = OK ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_SetALARM(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_GetALARM(IO_RTC_DATETIME *pTime); ++* ++* Input : pTime = structure for setting RTC Time. (Hexa-decimal format) ++* Output : ++* Return : 0 = OK ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_GetALARM(IO_RTC_DATETIME *pTime); ++ ++/********************************************************************************** ++* unsigned IO_RTC_WriteREG(volatile unsigned *pReg, unsigned uValue); ++* ++* Input : pReg = Register Address (BCD register address) ++* uValue = Register Value ++* Return : Register Value after writing. ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_WriteREG(volatile unsigned *pReg, unsigned uValue); ++ ++/********************************************************************************** ++* unsigned IO_RTC_GetBCDALARM(RTC_APP_DATETIME *pTime); ++* ++* Input : pTime = structure for setting RTC Time. (BCD format) ++* Output : ++* Return : HwRTCALM value ++* Description : ++**********************************************************************************/ ++unsigned IO_RTC_GetBCDALARM(IO_RTC_DATETIME *pTime); ++ ++/************************************************************************** ++ FUNCTION NAME : IO_RTC_DisableALMINT ++ ++ DESCRIPTION : Disable Alarm Interrupt (ALMINT) ++ ++ INPUT : void - Parameter ++ OUTPUT : void - Return Type ++ REMARK : ++**************************************************************************/ ++void IO_RTC_DisableALMINT(void); ++ ++/********************************************************************************** ++* unsigned IO_RTC_SetWKUP(IO_RTC_DATETIME *pTime, unsigned uActiveMode); ++* ++* Input : pTime = structure for setting RTC Time. (Hexa-decimal format) ++* uActiveMode : 1 = PMWKUP is active HIGH, 0 = PMWKUP is active LOW ++* Output : ++* Return : 0 = OK ++* Description : Set Wakeup Time. (System can be powered off & rebooted by wake-up signal) ++**********************************************************************************/ ++unsigned IO_RTC_SetWKUP(IO_RTC_DATETIME *pTime, unsigned uActiveMode); ++ ++ ++ ++/************************************************************************ ++* Debug Monitor ++************************************************************************/ ++// Print Character for time stamp. ++#define ST_ON '1' ++#define ST_OFF '0' ++#ifndef WINVER ++#ifdef USE_IO_DEBUG ++ //----------definition for GLOBAL monitoring ([7:0] are allocated) ++ #define IO_DBG_Init IO_DBG_Init_ ++ #define IO_DBG_Printf IO_DBG_Printf_ ++ #define IO_DBG_SerialPrintf IO_DBG_SerialPrintf_ ++ #define IO_DBG_Putc IO_DBG_Putc_ ++ #define IO_DBG_TIME HwTCNT4 ++ ++ //----------definition for GLOBAL monitoring ([-:0] are allocated) ++ #define DBG_CTRL_USBD Hw0 ++ #define DBG_CTRL_NFC Hw1 ++ #define DBG_CTRL_DTCM Hw2 ++ #define DBG_CTRL_SSFDC Hw3 ++ #define DBG_CTRL_SSFDC_DRV Hw4 ++ #define DBG_CTRL_FILE Hw5 ++ #define DBG_CTRL_FAT Hw6 ++ #define DBG_CTRL_MP3DEC Hw7 ++ //----------stamp definition ([31:-] are allocated) ++ #define DBG_CTRL_STAMP0 Hw31 ++ #define DBG_CTRL_STAMP1 Hw30 ++ #define DBG_CTRL_STAMP2 Hw29 ++ #define DBG_CTRL_STAMP3 Hw28 ++ #define DBG_CTRL_STAMP4 Hw27 ++ #define DBG_CTRL_STAMP5 Hw26 ++ #define DBG_CTRL_STAMP6 Hw25 ++ #define DBG_CTRL_STAMP7 Hw24 ++#else ++ // Disable All of monitoring functions ++ #define IO_DBG_Init() {;} ++ #define IO_DBG_Printf(...) ++ #define IO_DBG_SerialPrintf(...) ++ #define IO_DBG_Putc ++ #define IO_DBG_TIME 0 ++ ++ #define DBG_CTRL_USBD 0 ++ #define DBG_CTRL_NFC 0 ++ #define DBG_CTRL_DTCM 0 ++ #define DBG_CTRL_SSFDC 0 ++ #define DBG_CTRL_SSFDC_DRV 0 ++ #define DBG_CTRL_FILE 0 ++ #define DBG_CTRL_FAT 0 ++ #define DBG_CTRL_MP3DEC 0 ++ #define DBG_CTRL_STAMP0 0 ++ #define DBG_CTRL_STAMP1 0 ++ #define DBG_CTRL_STAMP2 0 ++ #define DBG_CTRL_STAMP3 0 ++ #define DBG_CTRL_STAMP4 0 ++ #define DBG_CTRL_STAMP5 0 ++ #define DBG_CTRL_STAMP6 0 ++ #define DBG_CTRL_STAMP7 0 ++#endif ++#endif ++#ifdef CHECK_SPEED ++ // Stamp for ++ #define MakeSTAMP0(X) {if (uDBG_CTRL & DBG_CTRL_STAMP0) IO_DBG_Printf("[%05x]T0(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for SSFDC_FS_WriteSector() execution time. ++ #define MakeSTAMP1(X) {if (uDBG_CTRL & DBG_CTRL_STAMP1) IO_DBG_Printf("[%05x]T1(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for SSFDC_WriteSector() execution time. ++ #define MakeSTAMP2(X) {if (uDBG_CTRL & DBG_CTRL_STAMP2) IO_DBG_Printf("[%05x]T2(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for read_file() or write_file() execution time. ++ #define MakeSTAMP3(X) {if (uDBG_CTRL & DBG_CTRL_STAMP3) IO_DBG_Printf("[%05x]T3(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for ++ #define MakeSTAMP4(X) {if (uDBG_CTRL & DBG_CTRL_STAMP4) IO_DBG_Printf("[%05x]T4(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for DISK_WriteSector() execution time. ++ #define MakeSTAMP5(X) {if (uDBG_CTRL & DBG_CTRL_STAMP5) IO_DBG_Printf("[%05x]T5(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for pure NAND Data transfer execution time. ++ #define MakeSTAMP6(X) {if (uDBG_CTRL & DBG_CTRL_STAMP6) IO_DBG_Printf("[%05x]T6(%c)\n", IO_DBG_TIME, X);} ++ ++ // Stamp for SSFDC_IO_R/W() execution time. ++ #define MakeSTAMP7(X) {if (uDBG_CTRL & DBG_CTRL_STAMP7) IO_DBG_Printf("[%05x]T7(%c)\n", IO_DBG_TIME, X);} ++#else ++ #define MakeSTAMP0(X) {;} ++ #define MakeSTAMP1(X) {;} ++ #define MakeSTAMP2(X) {;} ++ #define MakeSTAMP3(X) {;} ++ #define MakeSTAMP4(X) {;} ++ #define MakeSTAMP5(X) {;} ++ #define MakeSTAMP6(X) {;} ++ #define MakeSTAMP7(X) {;} ++#endif ++ ++// definition for USB device monitoring ++#define IO_USBD_Printf if (uDBG_CTRL & DBG_CTRL_USBD) IO_DBG_Printf ++#define IO_USBD_Putc(x) if (uDBG_CTRL & DBG_CTRL_USBD) IO_DBG_Putc(x) ++// definition for NFC monitoring ++#define IO_NFC_Printf if (uDBG_CTRL & DBG_CTRL_NFC) IO_DBG_Printf ++#define IO_NFC_Putc(x) if (uDBG_CTRL & DBG_CTRL_NFC) IO_DBG_Putc(x) ++// definition for DTCM monitoring ++#define IO_DTCM_Printf if (uDBG_CTRL & DBG_CTRL_DTCM) IO_DBG_Printf ++#define IO_DTCM_Putc(x) if (uDBG_CTRL & DBG_CTRL_DTCM) IO_DBG_Putc(x) ++// definition for SSFDC monitoring ++#define IO_SSFDC_Printf if (uDBG_CTRL & DBG_CTRL_SSFDC) IO_DBG_Printf ++#define IO_SSFDC_Putc(x) if (uDBG_CTRL & DBG_CTRL_SSFDC) IO_DBG_Putc(x) ++// definition for SSFDC_DRV monitoring ++#define IO_SSFDC_DRV_Printf if (uDBG_CTRL & DBG_CTRL_SSFDC_DRV) IO_DBG_Printf ++#define IO_SSFDC_DRV_Putc(x) if (uDBG_CTRL & DBG_CTRL_SSFDC_DRV) IO_DBG_Putc(x) ++// definition for FILE monitoring ++#define IO_FILE_Printf if (uDBG_CTRL & DBG_CTRL_FILE) IO_DBG_Printf ++#define IO_FILE_Putc(x) if (uDBG_CTRL & DBG_CTRL_FILE) IO_DBG_Putc(x) ++// definition for FAT monitoring ++#define IO_FAT_Printf if (uDBG_CTRL & DBG_CTRL_FAT) IO_DBG_Printf ++#define IO_FAT_Putc(x) if (uDBG_CTRL & DBG_CTRL_FAT) IO_DBG_Putc(x) ++// definition for MP3DEC monitoring ++#define IO_MP3DEC_Printf if (uDBG_CTRL & DBG_CTRL_MP3DEC) IO_DBG_Printf ++#define IO_MP3DEC_Putc(x) if (uDBG_CTRL & DBG_CTRL_MP3DEC) IO_DBG_Putc(x) ++ ++void IO_DBG_Printf_(char *format, ...); ++void IO_DBG_SerialPrintf_(char *format, ...); ++void IO_DBG_Sprintf(char *dst, char *format, ...); ++void IO_DBG_Putc_(char c); ++void IO_DBG_Init_(void); ++ ++extern const unsigned IO_DBG_CRC_TABLE[256]; ++unsigned IO_DBG_CalcCRC32_s(unsigned crc_in, unsigned data, unsigned size); ++ ++/********************************************************************************** ++* int stod(char *s); ++* ++* Input : s = string of decimal or hexa-decimal format ++* Return : converted value equivalent with s. ++* Description : if input string starts from "0x", it is regarded as hexa-decimal format, ++* or it is regarded as decimal format. ++**********************************************************************************/ ++int stod(char *s); ++ ++extern char cDBG_txbuf[]; // all of string that is printed by IO_DBG_Printf() is stored at this buffer. ++ // this is ring type buffer. ++extern char cDBG_rxbuf[]; ++extern char *p_prtbuf, cDirectPrint; ++extern unsigned uDBG_CTRL, uDBG_txbuf_length; ++ ++ ++/************************************************************************ ++* UART ++************************************************************************/ ++ ++#ifdef TCC92XX ++// Should be fixed. ++/* ++ #define IO_UART_CH 0 ++ ++ #define IO_UART_LSR(X) (((X) == 0) ? HwUART0_UTLSR : ((X) == 1) ? HwUART1_LSR : HwUART2_UTLSR) ++ #define IO_UART_RCVD Hw0 ++ #define IO_UART_TF(X) (((X) == 0) ? HwUART0_UTLSR_TF_NOSTR : ((X) == 1) ? HwUART1_LSR_THRE_ON : HwUART2_UTLSR_TF_NOSTR) ++ #define IO_UART_RXD(X) (((X) == 0) ? HwUART0_UTRXD : ((X) == 1) ? HwUART1_RBR : HwUART2_UTRXD) ++ #define IO_UART_TXD(X) (((X) == 0) ? HwUART0_UTTXD : ((X) == 1) ? HwUART1_THR : HwUART2_UTTXD) ++ #define IO_UART_WaitTXRDY(X) \ ++ { \ ++ if ((X) == 0) \ ++ while (ISONE(HwUART0_UTLSR, HwUART0_UTLSR_TF_NOSTR)); \ ++ else if ((X) == 1) \ ++ while (ISZERO(HwUART1_LSR, HwUART1_LSR_THRE_ON)); \ ++ else if ((X) == 2) \ ++ while (ISONE(HwUART2_UTLSR, HwUART2_UTLSR_TF_NOSTR)); \ ++ } ++ #define IO_UART_WaitRXRDY(X) \ ++ { \ ++ if ((X) == 0) \ ++ while (ISZERO(HwUART0_UTLSR, HwUART0_UTLSR_RA_RECV)); \ ++ else if ((X) == 1) \ ++ while (ISZERO(HwUART1_LSR, HwUART1_LSR_DR_ON)); \ ++ else if ((X) == 2) \ ++ while (ISZERO(HwUART2_UTLSR, HwUART2_UTLSR_RA_RECV)); \ ++ } ++ #define IO_UART_RXRDY(X) ( ((X) == 0) ? HwUART0_UTLSR & IO_UART_RCVD : \ ++ ((X) == 1) ? HwUART1_LSR & IO_UART_RCVD : HwUART2_UTLSR & IO_UART_RCVD ) ++ #define IO_UART_LSR_ERR(X) ( ((X) == 0) ? (HwUART0_UTLSR_FE_ERR | HwUART0_UTLSR_PE_ERR) : \ ++ ((X) == 1) ? (HwUART1_LSR_FE_ON | HwUART1_LSR_PE_ON) : \ ++ (HwUART2_UTLSR_FE_ERR | HwUART2_UTLSR_PE_ERR) ) ++ #define IO_UART_ERR_Frame(X) ( ((X) == 0) ? HwUART0_UTLSR_FE_ERR : \ ++ ((X) == 1) ? HwUART1_LSR_FE_ON : HwUART2_UTLSR_FE_ERR ) ++ #define IO_UART_ERR_Parity(X) ( ((X) == 0) ? HwUART0_UTLSR_PE_ERR : \ ++ ((X) == 1) ? HwUART1_LSR_PE_ON : HwUART2_UTLSR_PE_ERR ) ++*/ ++#endif ++ ++void IO_UART_Test(unsigned uCH); ++void IO_UART_Init(unsigned uCH); ++void IO_UART_WriteString(unsigned uCH, const char *ccptrString); ++void IO_UART_WriteByte(unsigned uCH, char cChar); ++int IO_UART_InputByte(unsigned uCH, char *cptrChar); ++void IO_UART_PutExtChar(unsigned uCH, const unsigned char cucChar); ++char IO_UART_GetChar(unsigned uCH); ++char IO_UART_GetCh(unsigned uCH); ++ ++/************************************************************************ ++* GSIO & SPIS ++************************************************************************/ ++ ++#define IO_GSIO_HwEN Hw31 ++#define IO_GSIO_HwMSB1ST Hw30 ++#define IO_GSIO_HwLSB1ST HwZERO ++#define IO_GSIO_HwWSIZE(X) (((X)-1)*Hw26) ++#define IO_GSIO_HwWSDYNAMIC Hw25 ++#define IO_GSIO_HwDIV(X) ((X) * Hw18) ++#define IO_GSIO_HwWSFIX HwZERO ++#define IO_GSIO_HwPOSSYNC Hw17 ++#define IO_GSIO_HwNEGSYNC HwZERO ++#define IO_GSIO_HwMASKLSCK Hw16 ++#define IO_GSIO_HwIEN Hw15 ++#define IO_GSIO_HwTXDLY(X) ((X)*Hw13) ++#define IO_GSIO_HwFRMACTHIGH Hw12 ++#define IO_GSIO_HwFRMACTLOW HwZERO ++#define IO_GSIO_HwFRMST(X) ((X)*Hw6) ++#define IO_GSIO_HwFRMEND(X) ((X)*Hw0) ++ ++typedef volatile struct ++{ ++ unsigned DO; ++ unsigned DI; ++ unsigned CTRL; ++ unsigned dummy; ++} sHwGSIO; ++ ++#define IO_SPIS_HwTXFIFOCNT(X) (((X)-1)*Hw29) ++#define IO_SPIS_HwRXFIFOCNT(X) (((X)-1)*Hw26) ++#define IO_SPIS_HwISRC_RXCFULL (0*Hw8) ++#define IO_SPIS_HwISRC_RXFEMPTY (1*Hw8) ++#define IO_SPIS_HwISRC_RXFFULL (2*Hw8) ++#define IO_SPIS_HwISRC_TXCFULL (4*Hw8) ++#define IO_SPIS_HwISRC_TXFEMPTY (5*Hw8) ++#define IO_SPIS_HwISRC_TXFFULL (6*Hw8) ++#define IO_SPIS_HwMSB1ST Hw5 ++#define IO_SPIS_HwLSB1ST HwZERO ++#define IO_SPIS_HwWSIZE(X) (((X)/8-1)*Hw3) ++#define IO_SPIS_HwPOSSYNC Hw2 ++#define IO_SPIS_HwNEGSYNC HwZERO ++#define IO_SPIS_HwIEN Hw1 ++#define IO_SPIS_HwEN Hw0 ++typedef struct ++{ ++ unsigned CTRL; ++ unsigned DO; ++ unsigned DI; ++ unsigned dummy; ++} sHwSPIS; ++ ++#define IO_GSIO_WaitBUSY(CH, Tout) { Tout = 300; while (ISONE(HwGSGCR, Hw0 << (CH)) && (Tout --)); } ++#define IO_SPIS_IsRXEMPTY(pSPIS) ISONE((pSPIS)->CTRL, HwSPCTRL_EMP_RX) ++#define IO_SPIS_IsRXFULL(pSPIS) ISONE((pSPIS)->CTRL, HwSPCTRL_FUL_RX) ++#define IO_SPIS_WaitRX(pSPIS, Tout) { Tout = 300; while (IO_SPIS_IsRXEMPTY(pSPIS) && (Tout --)); } ++#define IO_SPIS_IsTXEMPTY(pSPIS) ISONE((pSPIS)->CTRL, HwSPCTRL_EMP_TX) ++#define IO_SPIS_IsTXFULL(pSPIS) ISONE((pSPIS)->CTRL, HwSPCTRL_FUL_TX) ++#define IO_SPIS_WaitTX(pSPIS, Tout) { Tout = 300; while (IO_SPIS_IsTXFULL(pSPIS) && (Tout --)); } ++ ++/********************************************************** ++* void IO_GSIO_InitCH(unsigned uCH, unsigned uCONTROL, unsigned uSCKfreq); ++* ++* Input : uCH = Select GSIO Master channel. 0~1 is available. ++* uCONTROL = GSIO control flags ++* [31] = Enable(1) ++* [30] = MSB First (1) ++* [29:26] = Word Size (bit unit) ++* [25] = Word size is dynamically controlled by GSDO register (1) ++* [17] = Data transition occurs at the SCK rising (1) ++* [16] = Mask out the last SCK (1) ++* [15] = Enable Interrupt (1) ++* [14:13] = Transmission starting delay (1~3 is available) ++* [12] = FRM is high active pulse ++* [11:6] = FRM pulse start position ++* [5:0] = FRM pulse end position ++* uSCKfreq = GSIO SCK clock frequency ++* Return : ++* Description : Set GSIO host channel ++**********************************************************/ ++void IO_GSIO_InitCH(unsigned uCH, unsigned uCONTROL, unsigned uSCKfreq); ++ ++/********************************************************** ++* void IO_SPIS_InitCH(unsigned uCH, unsigned uCONTROL); ++* ++* Input : uCH = Select SPI slave channel. 0 is available. ++* uCONTROL = GSIO control flags ++* [31:29] = TX FIFO count ++* [28:26] = RX FIFO count ++* [10:8] = Interrupt Source Selection ++* 0 : RX FIFO Counter Full ++* 1 : RX FIFO Empty ++* 2 : RX FIFO Full ++* 4 : TX FIFO Counter Full ++* 5 : TX FIFO Empty ++* 6 : TX FIFO Full ++* [5] = MSB First (1) ++* [4:3] = Word Size ++* 0 : 8bit, 1 : 16bit, 2 : 24bit, 3 : 32bit ++* [2] = Data transition occurs at the SCK rising (1) ++* [1] = Enable Interrupt (1) ++* [0] = Enable (1) ++* Return : ++* Description : Set SPI slave channel ++**********************************************************/ ++void IO_SPIS_InitCH(unsigned uCH, unsigned uCONTROL); ++ ++enum ++{ ++ LCD_18BIT_SET, ++ LCD_16BIT_SET, ++ LCD_8BIT_SET ++}; ++ ++ ++/************************************************************************ ++* Mail Box ++************************************************************************/ ++typedef volatile struct { ++ unsigned TXD; ++ unsigned uRsv1[7]; ++ unsigned RXD; ++ unsigned uRsv2[7]; ++ unsigned CTR; ++ unsigned STR; ++} sMBOX; ++ ++enum { ++ MBOX_MAIN, ++ MBOX_SUB ++}; ++ ++ ++///////////////////////////////////////////// ++ ++#if !defined(_LINUX_) ++typedef int (*ICallBack)(int num); ++#endif ++ ++#define ALIGN_UP(X, Y) (((unsigned int)(X)+(unsigned int)(Y)-1) & ~((unsigned int)(Y)-1)) ++ ++ ++/************************************************************************ ++* GPSB ++************************************************************************/ ++typedef struct ++{ ++ volatile unsigned long *BASE; ++ unsigned uFRM, uSCK, uSDI, uSDO; ++ unsigned uMODE; ++} sGPSBPORT; ++ ++typedef struct tag_sGPSBPacket ++{ ++ char TxStatus; // 0=Empty, 1=Valid, 2=Sent ++ char RxStatus; // 0=Empty, 1=Wait, 2=Received ++ char dummy[2]; ++ unsigned CurSize; ++ unsigned *TxBufBASE; ++ unsigned *RxBufBASE; ++} sGPSBPacket; ++ ++typedef struct ++{ ++ unsigned short Num; // total number of packet buffer. ++ unsigned short CurNum; // current number of packet buffer. ++ unsigned short Head; // Head ++ unsigned short Tail; // Tail ++ unsigned MaxSize; // Buffer Max size ++ sGPSBPacket *Pkt; // Packet Array ++} sGPSBPKTManager; ++ ++typedef struct ++{ ++ unsigned char *pBuffer; ++ unsigned short uPktSize; ++ unsigned short uIncSize; ++ int iRemainLength; ++} sGPSBTXManager; ++ ++extern sGPSBPKTManager gGPSBPKTManager[2]; ++extern sGPSBTXManager gGPSBTXManager[2]; ++ ++void IO_GPSB_WaitDONE(sGPSBPORT *pPORT); ++void IO_GPSBSW_DelayLOOP(unsigned uDelay); ++void IO_GPSBSW_SetFRM(sGPSBPORT *pPORT, unsigned uValue); ++void IO_GPSBSW_InvFRM(sGPSBPORT *pPORT); ++void IO_GPSBSW_SetSCK(sGPSBPORT *pPORT, unsigned uValue); ++void IO_GPSBSW_InvSCK(sGPSBPORT *pPORT); ++void IO_GPSBSW_SetSDO(sGPSBPORT *pPORT, unsigned uValue); ++unsigned IO_GPSBSW_GetSDI(sGPSBPORT *pPORT); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* IO_GPSB_ConfigPORT(unsigned uCHPort, unsigned uSDO, unsigned uMode); ++* ++* DESCRIPTION : Configure GPSB Channel and its PORT. ++* ++* INPUT: ++* uCHPort = GPSB Channel & I/O Port number ++* [7:0] = channel number (0 or 1) ++* [8] = I/O PORT number for GPSB Channel ++* GPSB channel 0 can use 3 ports. (port number 0 ~ 2 are used) ++* Port 0 : GPIO_E[19:16] ++* Port 1 : GPIO_A[27:24] ++* Port 2 : GPIO_C[15:12] ++* GPSB channel 1 can only use 1 port. (port number 0 is used) ++* Port 0 : GPIO_E[23:20] ++* ++* uSDOSDI = flag for using SDO or SDI pin ++* [1] = 0 : don't use SDO, 1 : use SDO ++* [0] = 0 : don't use SDI, 1 : use SDI ++* ++* uMode = 0 : for setting PORT as H/W, 1 : for setting PORT as GPIO ++* ++* OUTPUT: ++* 0 = Successful ++* -1 = Illegal configuration. ++* ++* REMARK: created on 2006³â 11¿ù 15ÀÏ ¼ö¿äÀÏ ¿ÀÈÄ 9:02:58 by vizirdo ++**************************************************************************/ ++int IO_GPSB_ConfigPORT(unsigned uCHPort, unsigned uSDO, unsigned uMode); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSB_InitCH(int iCH, unsigned uMode, unsigned uSCKfreq); ++* ++* DESCRIPTION : Initialize GPSB channel for Master mode only. ++* ++* INPUT: ++* iCH = GPSB Channel & I/O Port number ++* [7:0] = channel number (0 or 1) ++* [8] = I/O PORT number for GPSB Channel ++* GPSB channel 0 can use 3 ports. (port number 0 ~ 2 are used) ++* Port 0 : GPIO_E[19:16] ++* Port 1 : GPIO_A[27:24] ++* Port 2 : GPIO_C[15:12] ++* GPSB channel 1 can only use 1 port. (port number 0 is used) ++* Port 0 : GPIO_E[23:20] ++* ++* uMode = Mode control ++* [20] : PCS (0 = CS active low, 1 = CS active high) ++* [17] : PD (0 = RX data on rising edge SCK & TX data on falling edge SCK) ++* (1 = RX data on falling edge SCK & TX data on rising edge SCK) ++* [16] : PCK (0 = SCK starts from 0, 1 = SCK starts from 1) ++* [7] : Data shifting direction control. (0 = MSB first, 1 = LSB first) ++* ++* uSCKfreq = SCK frequency (with 100 Hz unit) ++* uSW = 0 for H/W mode, 1 for S/W mode. ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2006³â 8¿ù 7ÀÏ ¿ù¿äÀÏ ¿ÀÀü 11:35:56 by vizirdo ++**************************************************************************/ ++void IO_GPSB_InitCH(int iCH, unsigned uMode, unsigned uSCKfreq, unsigned uSW); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSB_SendCMD(int iCH, unsigned uCmd, unsigned uCmdBitSize, unsigned uContinuous); ++* ++* DESCRIPTION : Send Command through GPSB port. ++* ++* INPUT: ++* iCH = channel number. (negative for using S/W SPI routine) ++* uCmd = command value ++* uCmdBitSize = bit size of command value. ++* uContinuous = flag for controlling nCS line. ++* if zero, nCS line goes to inactive state after the command value is sent. ++* if non-zero, nCS line remains in active state so additional process for the command can follow. ++* ++* OUTPUT: unsigned - Return Type ++* = response of command ++* ++* REMARK: created on 2006³â 8¿ù 7ÀÏ ¿ù¿äÀÏ ¿ÀÀü 11:36:57 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSB_SendCMD(int iCH, unsigned uCmd, unsigned uCmdBitSize, unsigned uContinuous); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSB_TRxPKT(int iCH, void *pTxBuf, void *pRxBuf, unsigned uLength); ++* ++* DESCRIPTION : Transmit & Receive a packet data. ++* ++* INPUT: ++* iCH = GPSB Channel & I/O Port number (same as IO_GPSB_InitCH) ++* pRxBuf = base address of received data. ++* pTxBuf = base address of transmitting data. ++* uLength = data size (byte unit) ++* ++* OUTPUT: unsigned - Return Type ++* = 0 ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:04:33 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSB_TRxPKT(int iCH, void *pTxBuf, void *pRxBuf, unsigned uLength); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSB_SendDATA(int iCH, unsigned char *pData, unsigned uLength, unsigned uBitConfig); ++* ++* DESCRIPTION : Send data through GPSB port ++* ++* INPUT: ++* iCH = channel number. (negative for using S/W SPI routine) ++* pData = pointer of data to send. ++* uLength = length of data to send. ++* uBitConfig = bit size of GPSB port. ++* ++* OUTPUT: unsigned - Return Type ++* = ++* ++* REMARK: created on 2006³â 8¿ù 7ÀÏ ¿ù¿äÀÏ ¿ÀÀü 11:42:47 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSB_SendDATA(int iCH, unsigned char *pData, unsigned uLength, unsigned uBitConfig); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSB_RecvDATA(int iCH, unsigned char *pData, unsigned uLength, unsigned uBitConfig); ++* ++* DESCRIPTION : Receive data through GPSB port ++* ++* INPUT: ++* iCH = channel number. (negative for using S/W SPI routine) ++* pData = pointer of data to receive. ++* uLength = length of data to receive. ++* uBitConfig = ++* ++* OUTPUT: unsigned - Return Type ++* = ++* ++* REMARK: created on 2006³â 8¿ù 7ÀÏ ¿ù¿äÀÏ ¿ÀÀü 11:44:32 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSB_RecvDATA(int iCH, unsigned char *pData, unsigned uLength, unsigned uBitConfig); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_InitCH(int iCH, unsigned uSDO, unsigned uMode); ++* ++* DESCRIPTION : Initialize GPSB channel for slave mode. ++* ++* INPUT: ++* iCH = GPSB Channel & I/O Port number ++* [7:0] = channel number (0 or 1) ++* [8] = I/O PORT number for GPSB Channel ++* GPSB channel 0 can use 3 ports. (port number 0 ~ 2 are used) ++* Port 0 : GPIO_E[19:16] ++* Port 1 : GPIO_A[27:24] ++* Port 2 : GPIO_C[15:12] ++* GPSB channel 1 can only use 1 port. (port number 0 is used) ++* Port 0 : GPIO_E[23:20] ++* ++* uSDOSDI = flag for using SDO or SDI pin ++* [1] = 0 : don't use SDO, 1 : use SDO ++* [0] = 0 : don't use SDI, 1 : use SDI ++* ++* uMode = GPSB Mode Selection ++* [17] = SDI capture control ++* 0 : SDI captured at rising edge SCK ++* 1 : SDI captured at falling edge SCK ++* [16] = SCK polarity control ++* 0 : SCKI is not inverted ++* 1 : SCKI is inverted ++* [15:14] = should be 3 ++* [12:8] = Bit width - 1 ++* [7] = 0 : MSB first, 1 : LSB first ++* [4] = 1 : continuous transfer mode ++* [2] = should be 1 ++* [0] = 0 : SPI, 1 : SSP ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2006³â 11¿ù 16ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 6:27:55 by vizirdo ++**************************************************************************/ ++void IO_GPSBS_InitCH(int iCH, unsigned uSDO, unsigned uMode); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_ConfigDMA(unsigned uCH, unsigned uINTEN, unsigned uDMACTR, ++* unsigned uPacketSize, unsigned uPacketNum); ++* ++* DESCRIPTION : Configurate a GPSB DMA setting for Transmit/Receive data. ++* GPSB & DMA operation is not yet enabled. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* uDMACTR = DMACTR register value ++* uINTEN = INTEN register value ++* uPacketNum = number of packets ++* uPacketSize = packet size (byte unit) ++* ++* OUTPUT: int - Return Type ++* = 0 : successful ++* = negative : failure ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:08:46 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_ConfigDMA(unsigned uCH, unsigned uINTEN, unsigned uDMACTR, ++ unsigned uPacketSize, unsigned uPacketNum); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_StartRXDMA(unsigned uCH, unsigned uINTMode, unsigned uINTEN, unsigned uDMACTR, ++* unsigned uPacketSize, unsigned uPacketNum, unsigned *pBuffer); ++* ++* DESCRIPTION : Start GPSB RX DMA at slave mode. ++* ++* INPUT: ++* uCH = GPSB channel number (0 or 1) ++* uINTMode = 0 : use edge triggered interrupt, 1 : use level triggered interrupt ++* uINTEN = GPSB.INTEN register value ++* uDMACTR = GPSB.DMACTR register value ++* uPacketSize = 1 packet size in bytes ++* uPacketNum = number of packets which RX DMA manipulate. ++* pBuffer = base of buffer to store RX data ++* ++* OUTPUT: int - Return Type ++* = 0 : setup is successful. ++* = -1 : illegal parameter ++* ++* REMARK: created on 2006³â 11¿ù 16ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 9:29:16 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_StartRXDMA(unsigned uCH, unsigned uINTMode, unsigned uINTEN, unsigned uDMACTR, ++ unsigned uPacketSize, unsigned uPacketNum, unsigned *pBuffer); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_EnablePKTDMA(unsigned uCH, unsigned uPktSize, unsigned *pTxBase, unsigned *pRxBase); ++* ++* DESCRIPTION : Enable GPSB & DMA Operation for packet data transfer. ++* ++* INPUT: ++* uCH = GPSB channel number (0 or 1) ++* uPktSize = packet size (in bytes) ++* pTxBase = base address of transmitting data buffer ++* pRxBase = base address of receiving data buffer ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:11:50 by vizirdo ++**************************************************************************/ ++void IO_GPSBS_EnablePKTDMA(unsigned uCH, unsigned uPktSize, unsigned *pTxBase, unsigned *pRxBase); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_EnableDMA(unsigned uCH, unsigned *pTxBase, unsigned *pRxBase); ++* ++* DESCRIPTION : Enable GPSB & DMA Operation for data transfer. ++* ++* INPUT: ++* uCH = GPSB channel number (0 or 1) ++* pTxBase = base address of transmitting data buffer ++* pRxBase = base address of receiving data buffer ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:11:50 by vizirdo ++**************************************************************************/ ++void IO_GPSBS_EnableDMA(unsigned uCH, unsigned *pTxBase, unsigned *pRxBase); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_DisableDMA(unsigned uCH); ++* ++* DESCRIPTION : Disable DMA Operation ++* ++* INPUT: ++* uCH = GPSB channel number (0 or 1) ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2007/1/25 11:24:46 by vizirdo ++**************************************************************************/ ++void IO_GPSBS_DisableDMA(unsigned uCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_PauseCH(int iCH); ++* ++* DESCRIPTION : Disable H/W Channel. ++* ++* INPUT: ++* iCH = channel number (0 or 1) ++* ++* OUTPUT: void - Return Type ++* ++* REMARK: created on 2006³â 11¿ù 17ÀÏ ±Ý¿äÀÏ ¿ÀÀü 12:25:30 by vizirdo ++**************************************************************************/ ++void IO_GPSBS_PauseCH(int iCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSBS_CheckDATA(int iCH); ++* ++* DESCRIPTION : Check whether RX FIFO is empty or not. ++* ++* INPUT: ++* iCH = channel number (0 or 1) ++* ++* OUTPUT: unsigned - Return Type ++* = 0 : RX FIFO is empty ++* = 1 : RX FIFO is not empty ++* ++* REMARK: created on 2006³â 11¿ù 18ÀÏ Åä¿äÀÏ ¿ÀÈÄ 6:40:50 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSBS_CheckDATA(int iCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSBS_GetDATA(int iCH); ++* ++* DESCRIPTION : Read RX FIFO ++* ++* INPUT: ++* iCH = channel number (0 or 1) ++* ++* OUTPUT: unsigned - Return Type ++* = RX FIFO data. ++* ++* REMARK: created on 2006³â 11¿ù 18ÀÏ Åä¿äÀÏ ¿ÀÈÄ 6:41:38 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSBS_GetDATA(int iCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSBS_SetDATA(int iCH, unsigned uData); ++* ++* DESCRIPTION : Send 1 word to master ++* ++* INPUT: ++* iCH = GPSB Channel number (0 or 1) ++* uData = Word value ++* ++* OUTPUT: unsigned - Return Type ++* = FIFO valid count ++* ++* REMARK: created on 2007/1/25 11:25:53 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSBS_SetDATA(int iCH, unsigned uData); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSBS_IsValidPKT(unsigned uCH); ++* ++* DESCRIPTION : Check Packet Buffer is empty or not. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* ++* OUTPUT: unsigned - Return Type ++* = 0 : Empty, 1 : Not empty ++* ++* REMARK: created on 2006³â 12¿ù 14ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 9:37:16 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSBS_IsValidPKT(unsigned uCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* unsigned IO_GPSBS_IsFullPKT(unsigned uCH); ++* ++* DESCRIPTION : Check Packet Buffer is full or not. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* ++* OUTPUT: unsigned - Return Type ++* = 0 : Not full, 1 : Full ++* ++* REMARK: created on 2006³â 12¿ù 14ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 9:45:53 by vizirdo ++**************************************************************************/ ++unsigned IO_GPSBS_IsFullPKT(unsigned uCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_CheckEmptyPKT(unsigned uCH, char **ppRxBuf, char **ppTxBuf); ++* ++* DESCRIPTION : Check if there exist an empty packet buffer. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* ppRxBuf = pointer to store base address of receiving data (NULL if not needed) ++* ppTxBuf = pointer to store base address of transmitting data (NULL if not needed) ++* ++* OUTPUT: int - Return Type ++* = 1 : there exist an empty packet buffer, and its address is stored to ppRxBuf, ppTxBuf ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:17:36 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_CheckEmptyPKT(unsigned uCH, char **ppRxBuf, char **ppTxBuf); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_PushPKT(unsigned uCH, unsigned char *pTxPKT, unsigned uSize); ++* ++* DESCRIPTION : Push a packet into packet buffer. ++* If pTxPkt == NULL, this packet only receives RX data. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* pTxPKT = base address of transmitting data (NULL if not needed ++* uSize = size of data (in bytes) ++* ++* OUTPUT: int - Return Type ++* = 0 : successful ++* = negative : push failed ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:20:32 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_PushPKT(unsigned uCH, unsigned char *pTxPKT, unsigned uSize); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_CheckValidPKT(unsigned uCH, char **ppRxBuf, char **ppTxBuf); ++* ++* DESCRIPTION : Check if there exist a valid packet buffer ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* ppRxBuf = pointer to store base address of receiving data (NULL if not needed) ++* ppTxBuf = pointer to store base address of transmitting data (NULL if not needed) ++* ++* OUTPUT: int - Return Type ++* = 1 : there exist an valid packet buffer, and its address is stored to ppRxBuf, ppTxBuf ++* = 0 : there is no valid packet. (packet is empty) ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:24:29 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_CheckValidPKT(unsigned uCH, char **ppRxBuf, char **ppTxBuf); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_PopPKT(unsigned uCH, sHwGPSB *pHwGPSB, char *pRxBuf); ++* ++* DESCRIPTION : Pop a packet data and process next packet buffer. if packet buffer is empty, ++* GPSB & DMA operation is disabled. ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* pHwGPSB = register base address for channel 0 or 1 ++* pRxBuf = base address to store just received packet data. ++* ++* OUTPUT: unsigned - Return Type ++* = 0 : there is no data. ++* = 1 : last packet is just processed. GPSB & DMA operation is disabled ++* = 2 : next packet operation starts. ++* ++* REMARK: created on 2006³â 12¿ù 21ÀÏ ¸ñ¿äÀÏ ¿ÀÈÄ 11:42:25 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_PopPKT(unsigned uCH, PGPSB pHwGPSB, char *pRxBuf); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_FlushPKT(unsigned uCH); ++* ++* DESCRIPTION : Remove existing all valid packet data ++* ++* INPUT: ++* uCH = channel number (0 or 1) ++* ++* OUTPUT: int - Return Type ++* = 0 : successful ++* ++* REMARK: created on 2006³â 12¿ù 22ÀÏ ±Ý¿äÀÏ ¿ÀÈÄ 2:24:50 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_FlushPKT(unsigned uCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_InsertPIDEntry(unsigned *pPIDTable, unsigned uPIDLength, int iIndex, unsigned uPIDValue, unsigned uPIDMask); ++* ++* DESCRIPTION : Insert PID entry at PID table ++* ++* INPUT: ++* pPIDTable = base address of PID table ++* uPIDLength = PID table length (0 ~ 63 is valid) ++* iIndex = index of PID table to insert. (if invalid index is used, search empty entry and insert at that index) ++* uPIDValue = PID bit field value ++* uPIDMask = PID Mask bit field value (1 = Masking Enabled, 0 = Masking Disabled) ++* ++* uPIDMask & uPIDValue Format ++* [14] = PayLoad Start bit ++* [13] = Error Flag bit ++* [12:0] = PID value ++* ++* OUTPUT: int - Return Type ++* = 0 ~ (uPIDLength-1) : index value which is selected to insert. ++* = -1 : there is no empty entry ++**************************************************************************/ ++int IO_GPSBS_InsertPIDEntry(unsigned *pPIDTable, unsigned uPIDLength, int iIndex, unsigned uPIDValue, unsigned uPIDMask); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_RemovePIDEntry(unsigned *pPIDTable, unsigned uPIDLength, int iIndex, unsigned uPIDValue, unsigned uPIDMask); ++* ++* DESCRIPTION : Remove PID entry at PID Table ++* ++* INPUT: ++* pPIDTable = base address of PID table ++* uPIDLength = PID table length (0 ~ 63 is valid) ++* iIndex = index of PID table to remove. ++* (if invalid index is used, search matched entry with uPIDValue, uPIDMask and remove that entry) ++* uPIDValue = PID bit field value ++* uPIDMask = PID Mask bit field value (1 = Masking Enabled, 0 = Masking Disabled) ++* ++* uPIDMask & uPIDValue Format ++* [14] = PayLoad Start bit ++* [13] = Error Flag bit ++* [12:0] = PID value ++* ++* OUTPUT: int - Return Type ++* = 0 ~ (uPIDLength-1) : index value which is removed. ++* = -1 : there is no matched entry ++**************************************************************************/ ++int IO_GPSBS_RemovePIDEntry(unsigned *pPIDTable, unsigned uPIDLength, int iIndex, unsigned uPIDValue, unsigned uPIDMask); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* void IO_GPSBS_StartTSIF(unsigned uCH, unsigned *pPIDTable, unsigned uPIDLength, unsigned uMatchPID, unsigned uMatchSync, ++* unsigned *pBuffer, unsigned uPacketSize, unsigned uPacketNum); ++* ++* DESCRIPTION : Start TS I/F DMA mode ++* ++* INPUT: ++* uCH = GPSB Channel Number (0 or 1) ++* pPIDTable = base address of PID table ++* uPIDLength = entry size of PID table (1 ~ 64) ++* uMatchPID = 1 : PID filtering is enabled ++* uMatchSync = 1 : Sync byte matching is enabled ++* pBuffer = base address of RX DMA buffer (= uPacketSize * uPacketNum) ++* uPacketSize = packet size of RX DMA buffer ++* uPacketNum = packet number of RX DMA buffer ++* ++* OUTPUT: void - Return Type ++**************************************************************************/ ++void IO_GPSBS_StartTSIF(unsigned uCH, unsigned *pPIDTable, unsigned uPIDLength, unsigned uMatchPID, unsigned uMatchSync, ++ unsigned *pBuffer, unsigned uPacketSize, unsigned uPacketNum); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_CalcPKTConfig(unsigned uSize, unsigned uPktSize, unsigned *pPktNum); ++* ++* DESCRIPTION : Calculate packet number for uSize & uPktSize. ++* ++* INPUT: ++* uSize = Entire data size ++* uPktSize = 1 packet size ++* pPktNum = pointer to store calculated packet number. ++* ++* OUTPUT: int - Return Type ++* = 1 : uSize is larger than maximum transfer size. ++* = 0 : uSize is less or equal than maximum transfer size. ++* ++* REMARK: created on 2007/1/25 12:7:0 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_CalcPKTConfig(unsigned uSize, unsigned uPktSize, unsigned *pPktNum); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_SendDATA(unsigned uCH, unsigned char *pBuffer, unsigned uSize, unsigned uPktSize); ++* ++* DESCRIPTION : Transmit bulk of data in slave mode. ++* ++* INPUT: ++* uCH = GPSB channel (0 or 1) ++* pBuffer = base address of bulk data. ++* uSize = size of bulk data. ++* uPktSize = 1 packet size for transmitting bulk of data. ++* The Host should have idle time (~= 5ms) at every maximum transfer unit (= uPktSize * 32) ++* and must read uPktSize unit. ++* ++* OUTPUT: int - Return Type ++* = 0 : Transfer begins ++* = negative : invalid parameter ++* ++* REMARK: created on 2007/1/25 12:51:55 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_SendDATA(unsigned uCH, unsigned char *pBuffer, unsigned uSize, unsigned uPktSize); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_GetRemainLength(unsigned uCH); ++* ++* DESCRIPTION : Get the size of data remains. ++* ++* INPUT: ++* uCH = GPSB Channel (0 or 1) ++* ++* OUTPUT: int - Return Type ++* = Size of Data remains. ++* ++* REMARK: created on 2007/1/25 12:56:38 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_GetRemainLength(unsigned uCH); ++ ++/************************************************************************** ++* FUNCTION NAME : ++* ++* int IO_GPSBS_SendNextDATA(unsigned uCH); ++* ++* DESCRIPTION : Process next transfer for sending bulk of data. ++* ++* INPUT: ++* uCH = GPSB Channel (0 or 1) ++* ++* OUTPUT: int - Return Type ++* = 0 : Transfer finished ++* = 1 : Next packet is ready to be transferred ++* ++* REMARK: created on 2007/1/25 12:58:4 by vizirdo ++**************************************************************************/ ++int IO_GPSBS_SendNextDATA(unsigned uCH); ++ ++ ++#endif /* __IO_TCCXXX_H */ +diff --git a/drivers/block/tcc/inc/tnftl/TC_DRV.h b/drivers/block/tcc/inc/tnftl/TC_DRV.h +new file mode 100644 +index 0000000..dc516a8 +--- /dev/null ++++ b/drivers/block/tcc/inc/tnftl/TC_DRV.h +@@ -0,0 +1,1700 @@ ++/**************************************************************************** ++ * FileName : TC_DRV.h ++ * Description : ++ **************************************************************************** ++ * ++ * TCC Version 1.0 ++ * Copyright (c) Telechips, Inc. ++ * ALL RIGHTS RESERVED ++ * ++ ****************************************************************************/ ++ ++#ifndef __TC_DRV_H__ ++#define __TC_DRV_H__ ++ ++#ifndef __IO_TCCXXX_H ++#if defined(_LINUX_) ++#include ++#elif defined(_WINCE_) ++#include "IO_TCCXXX.h" ++#endif ++#endif ++ ++//#include "TCCresource.h" ++ ++/*============================================================================== ++ General DMA ++ ==============================================================================*/ ++ ++#define DRV_GDMA_MAX_HANDLE 27 ++ ++// GDMA Driver Function Definition ++enum ++{ ++ DRV_GDMA_FUNC_INIT, // Driver Initialization : Argument = None ++ DRV_GDMA_FUNC_PROCESS_INTERRUPT, // Process DMA Interrupt : Argument = None ++ ++ DRV_GDMA_FUNC_OPEN, // Open Handle : Argument = (Channel Number, *sDRV_GDMA) ++ DRV_GDMA_FUNC_INSTALL_HANDLER, // Install DMA Interrupt Handler : Argument = (Channel, NewHandler, [* OldHandler]) ++ DRV_GDMA_FUNC_UNINSTALL_HANDLER, // UnInstall DMA Interrupt Handler : Argument = (Channel) ++ ++ DRV_GDMA_FUNC_SETCFG, // Configuration for DMA : Argument = (Handle, ConfigValue, ReqSel) ++ DRV_GDMA_FUNC_PARSECFG, // Parse for DMA Configuration : parameter should be set ahead in structure : Argument = (Handle) ++ DRV_GDMA_FUNC_GETHwDMA, // Get HwDMA Base Address : Argument = (Handle, *sHwDMA) ++ DRV_GDMA_FUNC_ISACTIVE, // Check Activated State : Argument = (Handle) ++ DRV_GDMA_FUNC_SETREG, // Setup DMA Register : Argument = (Handle, SrcBase, SrcInc, SrcMask, DstBase, DstInc, DstMask, DataSize) ++ DRV_GDMA_FUNC_START, // Start DMA Transfer : Argument = (Handle, SrcBase, SrcInc, SrcMask, DstBase, DstInc, DstMask, DataSize) ++ DRV_GDMA_FUNC_WAITDONE, // Wait DMA Transfer Done : Argument = (Handle, [TimeOut Value], [TimeDelay(), TimeDelayFactor]) ++ DRV_GDMA_FUNC_WAITDONE_STOP, // Wait DMA Transfer Done & Stop DMA : Argument = (Handle, [TimeOut Value], [TimeDelay(), TimeDelayFactor]) ++ DRV_GDMA_FUNC_PAUSE, // Pause DMA Operation : Argument = (Handle) ++ DRV_GDMA_FUNC_CONTINUE, // Continue DMA Operation : Argument = (Handle) ++ DRV_GDMA_FUNC_STOP, // Stop DMA Operation -> This channel goes to IDLE state : Argument = (Handle) ++ DRV_GDMA_FUNC_CLOSE, // Close DMA Channel from User : Argument = (Handle) ++ DRV_GDMA_FUNC_MAX ++}; ++ ++// GDMA Driver Status Definition ++enum ++{ ++ DRV_GDMA_STATUS_INVALID, // Not Opened ++ DRV_GDMA_STATUS_IDLE, // Openad but Not Activated ++ DRV_GDMA_STATUS_PAUSE, // Opened & Activated & Pause ++ DRV_GDMA_STATUS_ACTIVE, // Opened & Activated ++ DRV_GDMA_STATUS_MAX ++}; ++ ++// GDMA Driver Data Structure ++typedef struct ++{ ++ U32 CHCFG; ++ U32 REQSEL; ++ ++ U8 CHSTS; ++ U8 BufShiftFactor; ++ U32 HwCHCTRL; ++ U32 HwREQSEL; ++#ifdef TCC89XX ++ PGDMACTRL pHwDMA; ++#else ++ sHwDMA *pHwDMA; ++#endif ++} sDRV_GDMA; ++ ++// GDMA Driver Return Value Definition ++#define DRV_GDMA_ERROR_YES 1 ++#define DRV_GDMA_ERROR_NO 0 ++#define DRV_GDMA_ERROR_OK 0 ++enum ++{ ++ // Error for Driver State ++ DRV_GDMA_ERROR_NOTINIT = (int)0xF0040000, // Non-init Function come before init function ++ DRV_GDMA_ERROR_DUPINIT, // Init function called more than twice ++ ++ // Error for Input Parameter ++ DRV_GDMA_ERROR_INVALID_FUNC, // Function Code is out of range ++ DRV_GDMA_ERROR_INVALID_ARGUMENT, // Number of Argument is out of range ++ DRV_GDMA_ERROR_INVALID_HANDLE, // Handle value is out of range ++ DRV_GDMA_ERROR_INVALID_CH, // Channel value is out of range ++ ++ // Error for Resource Availability ++ DRV_GDMA_ERROR_NOTAVAILABLE_HANDLE, // No available handle ++ DRV_GDMA_ERROR_NOTAVAILABLE_CH, // No available channel ++ ++ // Error for Operating ++ DRV_GDMA_ERROR_TIMEOUT, // Time Out ++ DRV_GDMA_ERROR_NOT_READY, ++ DRV_GDMA_ERROR_NOT_ACTIVE, ++ DRV_GDMA_ERROR_NOT_PAUSE, ++ ++ // Error for Illegal State ++ DRV_GDMA_ERROR_INTERNAL, // Internal Bug ++ ++ DRV_GDMA_ERROR_MAX ++}; ++ ++// GDMA Driver Channel Configuration Definition ++#define DRV_GDMA_CFG_SyncHwReq Hw13 ++#define DRV_GDMA_CFG_ASyncHwReq 0 ++#define DRV_GDMA_CFG_AckAtWrite Hw12 // HwCHCTRL_HRD ++#define DRV_GDMA_CFG_AckAtRead 0 ++#define DRV_GDMA_CFG_LockTransfer Hw11 // HwCHCTRL_LOCK ++#define DRV_GDMA_CFG_NoArbitration Hw10 // HwCHCTRL_BST ++#define DRV_GDMA_CFG_Arbitration 0 ++#define DRV_GDMA_CFG_StartBy_SHIFT 8 ++#define DRV_GDMA_CFG_StartBy(X) ((X)<