From ef0916b547e87abe7f5fb80fbba8273fad7de3c5 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Fri, 31 Aug 2007 08:17:20 +0000 Subject: disapproval of revision '4fb1a7447c5d8ace96a5ac6358c7fe10f0d951c4' --- packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch | 11 - .../gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch | 85 - .../gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch | 189 - .../gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch | 47 - packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch | 35 - packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch | 67 - .../gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch | 20 - .../gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch | 19 - .../gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch | 32 - .../gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch | 68 - .../gcc-4.1.2/arm-crunch-cfldrstr-disable.patch | 67 - .../gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch | 573 -- .../gcc/gcc-4.1.2/arm-crunch-compare-geu.patch | 48 - .../gcc/gcc-4.1.2/arm-crunch-compare-new.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new2.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new3.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new4.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new5.patch | 432 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new6.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-new7.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare-old.patch | 400 -- .../gcc-4.1.2/arm-crunch-compare-unordered.patch | 98 - .../arm-crunch-compare-unordered.patch-z-eq | 98 - packages/gcc/gcc-4.1.2/arm-crunch-compare.patch | 400 -- .../gcc/gcc-4.1.2/arm-crunch-compare.patch-z-eq | 400 -- .../gcc-4.1.2/arm-crunch-condexec-disable.patch | 5547 -------------------- packages/gcc/gcc-4.1.2/arm-crunch-dominance.patch | 12 - .../gcc-4.1.2/arm-crunch-double-nop-before.patch | 459 -- .../gcc-4.1.2/arm-crunch-eabi-ieee754-div.patch | 139 - .../gcc/gcc-4.1.2/arm-crunch-eabi-ieee754.patch | 100 - packages/gcc/gcc-4.1.2/arm-crunch-eabi.patch | 64 - .../arm-crunch-floatsi-disable-single.patch | 38 - .../gcc/gcc-4.1.2/arm-crunch-floatsi-disable.patch | 61 - .../gcc/gcc-4.1.2/arm-crunch-floatunsidf.patch | 37 - packages/gcc/gcc-4.1.2/arm-crunch-fp_consts.patch | 13 - packages/gcc/gcc-4.1.2/arm-crunch-neg.patch | 30 - packages/gcc/gcc-4.1.2/arm-crunch-neg2.patch | 25 - packages/gcc/gcc-4.1.2/arm-crunch-offset.patch | 20 - packages/gcc/gcc-4.1.2/arm-crunch-predicates.patch | 20 - .../gcc/gcc-4.1.2/arm-crunch-predicates2.patch | 10 - .../gcc/gcc-4.1.2/arm-crunch-predicates3.patch | 116 - .../arm-crunch-predicates4-no_cond_exec.patch | 196 - .../gcc/gcc-4.1.2/arm-crunch-predicates4.patch | 196 - packages/gcc/gcc-4.1.2/arm-crunch-saveregs.patch | 153 - packages/gcc/gcc-4.1.2/arm-crunch-scc.patch | 38 - .../gcc-4.1.2/arm-crunch-truncsi-disable-new.patch | 33 - .../gcc/gcc-4.1.2/arm-crunch-truncsi-disable.patch | 56 - packages/gcc/gcc-cross_4.1.2.bb | 2 +- packages/gcc/gcc_4.1.2.bb | 27 +- 49 files changed, 3 insertions(+), 12878 deletions(-) delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new2.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new3.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new4.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new5.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new6.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-new7.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-old.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch-z-eq delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-compare.patch-z-eq delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-condexec-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-dominance.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-double-nop-before.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754-div.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-eabi.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable-single.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-floatunsidf.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-fp_consts.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-neg.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-neg2.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-offset.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-predicates.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-predicates2.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-predicates3.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-predicates4-no_cond_exec.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-predicates4.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-saveregs.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-scc.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable-new.patch delete mode 100644 packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable.patch diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch b/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch deleted file mode 100644 index 3fb0da7670..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000 -+++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000 -@@ -49,7 +49,7 @@ - exit (0); - - c(0x3690000000000000ULL, 0x00000000U); --#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) -+#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__) - /* The ARM always stores FP numbers in big-wordian format, - even when running in little-byteian mode. */ - c(0x0000000136900000ULL, 0x00000001U); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch deleted file mode 100644 index 88eaee322d..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch +++ /dev/null @@ -1,85 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 -@@ -149,7 +149,7 @@ - (match_operand:SI 1 "cirrus_fp_register" "0") - (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") - (match_operand:SI 3 "cirrus_fp_register" "v"))))] -- "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmsc32%?\\t%V0, %V2, %V3" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -305,7 +305,7 @@ - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] -@@ -315,7 +315,7 @@ - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] -@@ -339,7 +339,7 @@ - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] -@@ -349,7 +349,7 @@ - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] ---- gcc-4.1.2/gcc/config/arm/arm.md-trunc 2007-06-15 10:56:13.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:01:22.000000000 +1000 -@@ -3130,7 +3130,7 @@ - (float:SF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); - DONE; -@@ -3142,7 +3142,7 @@ - (float:DF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); - DONE; -@@ -3154,7 +3154,7 @@ - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[0], SImode)) - operands[0] = force_reg (SImode, operands[0]); -@@ -3170,7 +3170,7 @@ - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[1], DFmode)) - operands[1] = force_reg (DFmode, operands[0]); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch deleted file mode 100644 index 537fe2f746..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch +++ /dev/null @@ -1,189 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 -@@ -34,7 +34,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:DI 2 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfadd64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -74,7 +74,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:DI 2 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsub64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -124,7 +124,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") - (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmul64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_dmult") - (set_attr "cirrus" "normal")] -@@ -206,7 +206,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "register_operand" "r")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfrshl64%?\\t%V1, %V0, %s2" - [(set_attr "cirrus" "normal")] - ) -@@ -215,7 +215,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "cirrus_shift_const" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsh64%?\\t%V0, %V1, #%s2" - [(set_attr "cirrus" "normal")] - ) -@@ -224,7 +224,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "cirrus_shift_const" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsh64%?\\t%V0, %V1, #-%s2" - [(set_attr "cirrus" "normal")] - ) -@@ -232,7 +232,7 @@ - (define_insn "*cirrus_absdi2" - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfabs64%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) -@@ -238,11 +238,12 @@ - ) - - ;; This doesn't really clobber ``cc''. Fixme: aldyh. -+;; maybe buggy? - (define_insn "*cirrus_negdi2" - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfneg64%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) -@@ -324,14 +324,14 @@ - (define_insn "floatdisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64s%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - -@@ -376,7 +376,7 @@ - (define_insn "*cirrus_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "* - { - switch (which_alternative) ---- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000 -@@ -357,7 +357,7 @@ - (clobber (reg:CC CC_REGNUM))])] - "TARGET_EITHER" - " -- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) -+ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[0], DImode)) - operands[0] = force_reg (DImode, operands[0]); -@@ -393,7 +393,7 @@ - (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") - (match_operand:DI 2 "s_register_operand" "r, 0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -421,7 +421,7 @@ - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "r,0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -450,7 +450,7 @@ - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "r,0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -838,7 +838,7 @@ - if (TARGET_HARD_FLOAT && TARGET_MAVERICK - && TARGET_ARM - && cirrus_fp_register (operands[0], DImode) -- && cirrus_fp_register (operands[1], DImode)) -+ && cirrus_fp_register (operands[1], DImode) && 0) - { - emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2])); - DONE; -@@ -2599,7 +2599,7 @@ - values to iwmmxt regs and back. */ - FAIL; - } -- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) -+ else if (!TARGET_REALLY_IWMMXT) - FAIL; - " - ) -@@ -4097,7 +4097,7 @@ - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] - "TARGET_ARM -- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) -+ && !(TARGET_HARD_FLOAT && (TARGET_VFP)) - && !TARGET_IWMMXT" - "* - switch (which_alternative) -@@ -4215,7 +4215,6 @@ - [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") - (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] - "TARGET_THUMB -- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" - "* ---- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-26 15:08:04.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-26 15:08:41.000000000 +1000 -@@ -12036,7 +12036,7 @@ - upper 32 bits. This causes gcc all sorts of grief. We can't - even split the registers into pairs because Cirrus SI values - get sign extended to 64bits-- aldyh. */ -- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); -+ return (GET_MODE_CLASS (mode) == MODE_FLOAT); - - if (TARGET_HARD_FLOAT && TARGET_VFP - && IS_VFP_REGNUM (regno)) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch deleted file mode 100644 index 95abf68a60..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch +++ /dev/null @@ -1,47 +0,0 @@ -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000 -@@ -6865,10 +6877,12 @@ - ) - - ;; Cirrus DI compare instruction -+;; This is disabled and left go through ARM core registers, because currently -+;; Crunch coprocessor does only signed comparison. - (define_expand "cmpdi" - [(match_operand:DI 0 "cirrus_fp_register" "") - (match_operand:DI 1 "cirrus_fp_register" "")] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" - "{ - arm_compare_op0 = operands[0]; - arm_compare_op1 = operands[1]; -@@ -6879,7 +6893,7 @@ - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") - (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" - "cfcmp64%?\\tr15, %V0, %V1" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "compare")] -@@ -10105,6 +10119,7 @@ - [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)] - "" - "%@ %0 needed for prologue" -+ [(set_attr "length" "0")] - ) - - -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md 2005-06-25 11:22:41.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-05-15 09:55:29.000000000 +1000 -@@ -348,7 +348,8 @@ - (clobber (match_scratch:DF 2 "=v"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" - "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" -- [(set_attr "length" "8")] -+ [(set_attr "length" "8") -+ (set_attr "cirrus" "normal")] - ) - - (define_insn "*cirrus_truncdfsf2" diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch b/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch deleted file mode 100644 index 227e1cfe04..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch +++ /dev/null @@ -1,35 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 13:26:41.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 13:28:25.000000000 +1000 -@@ -378,8 +378,8 @@ - ) - - (define_insn "*cirrus_arm_movdi" -- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") -- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] -+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,Uy,v") -+ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,Uyi,v,v"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "* - { -@@ -436,8 +436,8 @@ - ) - - (define_insn "*cirrus_movsf_hard_insn" -- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") -- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,Uy,r,r,m") -+ (match_operand:SF 1 "general_operand" "v,UyE,r,v,v,r,mE,r"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" -@@ -458,8 +458,8 @@ - ) - - (define_insn "*cirrus_movdf_hard_insn" -- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") -- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,Uy") -+ (match_operand:DF 1 "general_operand" "Q,r,r,r,UyF,v,mF,r,v,v"))] - "TARGET_ARM - && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch b/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch deleted file mode 100644 index 24357d316e..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch +++ /dev/null @@ -1,67 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 17:16:38.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 17:35:19.000000000 +1000 -@@ -8455,7 +8455,7 @@ - (and:SI (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 2 "s_register_operand" "r")))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" - [(set_attr "conds" "use") - (set_attr "length" "8")] -@@ -8466,7 +8466,7 @@ - (ior:SI (match_operator:SI 2 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "s_register_operand" "0,?r")))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "@ - orr%d2\\t%0, %1, #1 - mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" -@@ -8734,7 +8734,8 @@ - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) -- != CCmode)" -+ != CCmode) -+ && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 7) -@@ -8765,7 +8766,7 @@ - (set (match_operand:SI 7 "s_register_operand" "=r") - (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) - (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 0) -@@ -8790,7 +8791,8 @@ - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) -- != CCmode)" -+ != CCmode) -+ && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) -@@ -8823,7 +8825,7 @@ - (set (match_operand:SI 7 "s_register_operand" "=r") - (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) - (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 0) -@@ -8850,7 +8852,7 @@ - [(match_operand:SI 4 "s_register_operand" "r,r,r") - (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM -+ "TARGET_ARM && !TARGET_MAVERICK - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) - == CCmode)" - "#" diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch deleted file mode 100644 index 01bebf3867..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-07-03 10:53:06.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-07-03 10:53:19.000000000 +1000 -@@ -287,7 +287,7 @@ - (define_insn "*cirrus_abssf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfabss%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) -@@ -295,7 +295,7 @@ - (define_insn "*cirrus_absdf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfabsd%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch deleted file mode 100644 index f9280b18b5..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- gcc-4.2.0/gcc/config/arm/cirrus.md-original 2007-06-25 15:32:01.000000000 +1000 -+++ gcc-4.2.0/gcc/config/arm/cirrus.md 2007-06-25 15:32:14.000000000 +1000 -@@ -325,14 +325,14 @@ - (define_insn "floatdisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64s%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch deleted file mode 100644 index ec09ea16a1..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-15 10:06:24.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 10:07:21.000000000 +1000 -@@ -355,11 +355,12 @@ - (set_attr "cirrus" "normal")] - ) - -+; appears to be buggy - causes 20000320-1.c to fail in execute/ieee - (define_insn "*cirrus_truncdfsf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float_truncate:SF - (match_operand:DF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvtds%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) ---- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2 2007-06-15 10:25:43.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 10:27:01.000000000 +1000 -@@ -3181,11 +3181,12 @@ - - ;; Truncation insns - -+;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md - (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (float_truncate:SF - (match_operand:DF 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - "" - ) - diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch deleted file mode 100644 index 502902df83..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 12:04:15.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 12:09:09.000000000 +1000 -@@ -436,30 +436,29 @@ - ) - - (define_insn "*cirrus_movsf_hard_insn" -- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") -- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,r,m,r,r,m") -+ (match_operand:SF 1 "general_operand" "v,r,v,v,r,mE,r"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" - "@ - cfcpys%?\\t%V0, %V1 -- cfldrs%?\\t%V0, %1 - cfmvsr%?\\t%V0, %1 - cfmvrs%?\\t%0, %V1 - cfstrs%?\\t%V1, %0 - mov%?\\t%0, %1 - ldr%?\\t%0, %1\\t%@ float - str%?\\t%1, %0\\t%@ float" -- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") -- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") -- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") -- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") -- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] -+ [(set_attr "length" " *, *, *, *, 4, 4, 4") -+ (set_attr "type" " *, *, *,store1, *,load1,store1") -+ (set_attr "pool_range" " *, *, *, *, *,4096, *") -+ (set_attr "neg_pool_range" " *, *, *, *, *,4084, *") -+ (set_attr "cirrus" "normal,move,normal,normal,not, not, not")] - ) - - (define_insn "*cirrus_movdf_hard_insn" -- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") -- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,r,m") -+ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,r,v,v"))] - "TARGET_ARM - && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM -@@ -473,17 +472,16 @@ - case 2: return \"#\"; - case 3: case 4: return output_move_double (operands); - case 5: return \"cfcpyd%?\\t%V0, %V1\"; -- case 6: return \"cfldrd%?\\t%V0, %1\"; -- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; -- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; -- case 9: return \"cfstrd%?\\t%V1, %0\"; -+ case 6: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; -+ case 7: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; -+ case 8: return \"cfstrd%?\\t%V1, %0\"; - default: gcc_unreachable (); - } - }" -- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") -- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") -- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") -- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") -- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] -+ [(set_attr "type" "load1,store2, *,store2,load1, *, *, *,store2") -+ (set_attr "length" " 4, 4, 8, 8, 8, 4, 8, 8, 4") -+ (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *") -+ (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *") -+ (set_attr "cirrus" " not, not,not, not, not,normal,move,normal,double")] - ) - diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch deleted file mode 100644 index ae762e97a7..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch +++ /dev/null @@ -1,67 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 12:04:15.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 12:21:57.000000000 +1000 -@@ -436,30 +436,28 @@ - ) - - (define_insn "*cirrus_movsf_hard_insn" -- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") -- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] -+ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,r,r,r,m") -+ (match_operand:SF 1 "general_operand" "v,r,v,r,mE,r"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" - "@ - cfcpys%?\\t%V0, %V1 -- cfldrs%?\\t%V0, %1 - cfmvsr%?\\t%V0, %1 - cfmvrs%?\\t%0, %V1 -- cfstrs%?\\t%V1, %0 - mov%?\\t%0, %1 - ldr%?\\t%0, %1\\t%@ float - str%?\\t%1, %0\\t%@ float" -- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") -- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") -- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") -- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") -- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] -+ [(set_attr "length" " *, *, *, 4, 4, 4") -+ (set_attr "type" " *, *, *, *,load1,store1") -+ (set_attr "pool_range" " *, *, *, *,4096, *") -+ (set_attr "neg_pool_range" " *, *, *, *,4084, *") -+ (set_attr "cirrus" "normal,move,normal,not, not, not")] - ) - - (define_insn "*cirrus_movdf_hard_insn" -- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") -- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,r,m") -+ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,r,v,v"))] - "TARGET_ARM - && TARGET_HARD_FLOAT && TARGET_MAVERICK - && (GET_CODE (operands[0]) != MEM -@@ -473,17 +471,15 @@ - case 2: return \"#\"; - case 3: case 4: return output_move_double (operands); - case 5: return \"cfcpyd%?\\t%V0, %V1\"; -- case 6: return \"cfldrd%?\\t%V0, %1\"; -- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; -- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; -- case 9: return \"cfstrd%?\\t%V1, %0\"; -+ case 6: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; -+ case 7: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; - default: gcc_unreachable (); - } - }" -- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") -- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") -- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") -- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") -- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] -+ [(set_attr "type" "load1,store2, *,store2,load1, *, *, *") -+ (set_attr "length" " 4, 4, 8, 8, 8, 4, 8, 8") -+ (set_attr "pool_range" " *, *, *, *, 252, *, *, *") -+ (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *") -+ (set_attr "cirrus" " not, not,not, not, not,normal,move,normal")] - ) - diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch deleted file mode 100644 index cb0af8546d..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch +++ /dev/null @@ -1,573 +0,0 @@ -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000 -@@ -4,6 +4,7 @@ - Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) - and Martin Simmons (@harleqn.co.uk). - More major hacks by Richard Earnshaw (rearnsha@arm.com). -+ Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com) - - This file is part of GCC. - -@@ -131,9 +132,17 @@ - static bool arm_xscale_rtx_costs (rtx, int, int, int *); - static bool arm_9e_rtx_costs (rtx, int, int, int *); - static int arm_address_cost (rtx); --static bool arm_memory_load_p (rtx); -+// static bool arm_memory_load_p (rtx); - static bool arm_cirrus_insn_p (rtx); --static void cirrus_reorg (rtx); -+// static void cirrus_reorg (rtx); -+static bool arm_mem_access_p (rtx); -+static bool cirrus_dest_regn_p (rtx, int); -+static rtx cirrus_prev_next_mach_insn (rtx, int *, int); -+static rtx cirrus_prev_mach_insn (rtx, int *); -+static rtx cirrus_next_mach_insn (rtx, int *); -+static void cirrus_reorg_branch (rtx); -+static void cirrus_reorg_bug1 (rtx); -+static void cirrus_reorg_bug10_12 (rtx); - static void arm_init_builtins (void); - static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); - static void arm_init_iwmmxt_builtins (void); -@@ -5399,41 +5412,6 @@ - || TREE_CODE (valtype) == COMPLEX_TYPE)); - } - --/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. -- Use by the Cirrus Maverick code which has to workaround -- a hardware bug triggered by such instructions. */ --static bool --arm_memory_load_p (rtx insn) --{ -- rtx body, lhs, rhs;; -- -- if (insn == NULL_RTX || GET_CODE (insn) != INSN) -- return false; -- -- body = PATTERN (insn); -- -- if (GET_CODE (body) != SET) -- return false; -- -- lhs = XEXP (body, 0); -- rhs = XEXP (body, 1); -- -- lhs = REG_OR_SUBREG_RTX (lhs); -- -- /* If the destination is not a general purpose -- register we do not have to worry. */ -- if (GET_CODE (lhs) != REG -- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) -- return false; -- -- /* As well as loads from memory we also have to react -- to loads of invalid constants which will be turned -- into loads from the minipool. */ -- return (GET_CODE (rhs) == MEM -- || GET_CODE (rhs) == SYMBOL_REF -- || note_invalid_constants (insn, -1, false)); --} -- - /* Return TRUE if INSN is a Cirrus instruction. */ - static bool - arm_cirrus_insn_p (rtx insn) -@@ -5452,124 +5433,218 @@ - return attr != CIRRUS_NOT; - } - --/* Cirrus reorg for invalid instruction combinations. */ --static void --cirrus_reorg (rtx first) -+/* Return TRUE if ISN does memory access. */ -+static bool -+arm_mem_access_p (rtx insn) - { -- enum attr_cirrus attr; -- rtx body = PATTERN (first); -- rtx t; -- int nops; -+ enum attr_type attr; - -- /* Any branch must be followed by 2 non Cirrus instructions. */ -- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) -- { -- nops = 0; -- t = next_nonnote_insn (first); -+ /* get_attr aborts on USE and CLOBBER. */ -+ if (!insn -+ || GET_CODE (insn) != INSN -+ || GET_CODE (PATTERN (insn)) == USE -+ || GET_CODE (PATTERN (insn)) == CLOBBER) -+ return 0; - -- if (arm_cirrus_insn_p (t)) -- ++ nops; -+ attr = get_attr_type (insn); - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; -+ return attr == TYPE_LOAD_BYTE -+ || attr == TYPE_LOAD1 || attr == TYPE_LOAD2 || attr == TYPE_LOAD3 || attr == TYPE_LOAD4 -+ || attr == TYPE_F_CVT -+ || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F || attr == TYPE_F_2_R || attr == TYPE_R_2_F -+ || attr == TYPE_F_LOAD || attr == TYPE_F_LOADS || attr == TYPE_F_LOADD -+ || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED -+ || attr == TYPE_STORE1 || attr == TYPE_STORE2 || attr == TYPE_STORE3 || attr == TYPE_STORE4; -+ -+} - -- while (nops --) -- emit_insn_after (gen_nop (), first); -+/* Return TRUE if destination is certain Cirrus register. */ -+static bool -+cirrus_dest_regn_p (rtx body, int regn) -+{ -+ rtx lhs; -+ int reg; -+ lhs = XEXP (body, 0); -+ if (GET_CODE (lhs) != REG) -+ return 0; - -- return; -- } -+ reg = REGNO (lhs); -+ if (REGNO_REG_CLASS (reg) != CIRRUS_REGS) -+ return 0; - -- /* (float (blah)) is in parallel with a clobber. */ -- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) -- body = XVECEXP (body, 0, 0); -+ return reg == regn; -+} -+ -+/* Get previous/next machine instruction during Cirrus workaround scans. -+ Assume worst case (for the purpose of Cirrus workarounds) -+ for JUMP / CALL instructions. */ -+static rtx -+cirrus_prev_next_mach_insn (rtx insn, int *len, int next) -+{ -+ rtx t; -+ int l = 0; - -- if (GET_CODE (body) == SET) -+ /* It seems that we can count only on INSN length. */ -+ for ( ; ; ) - { -- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); -+ if (next) -+ insn = NEXT_INSN (insn); -+ else -+ insn = PREV_INSN (insn); -+ if (!insn) -+ break; - -- /* cfldrd, cfldr64, cfstrd, cfstr64 must -- be followed by a non Cirrus insn. */ -- if (get_attr_cirrus (first) == CIRRUS_DOUBLE) -- { -- if (arm_cirrus_insn_p (next_nonnote_insn (first))) -- emit_insn_after (gen_nop (), first); -+ if (GET_CODE (insn) == INSN) -+ { -+ l = get_attr_length (insn) / 4; -+ if (l) -+ break; -+ } -+ else if (GET_CODE (insn) == JUMP_INSN) -+ { -+ l = 1; -+ t = is_jump_table (insn); -+ if (t) -+ l += get_jump_table_size (t) / 4; -+ break; -+ } -+ else if (GET_CODE (insn) == CALL_INSN) -+ { -+ l = 1; -+ break; -+ } -+ } - -- return; -- } -- else if (arm_memory_load_p (first)) -- { -- unsigned int arm_regno; -+ if (len) -+ *len = l; - -- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, -- ldr/cfmv64hr combination where the Rd field is the same -- in both instructions must be split with a non Cirrus -- insn. Example: -- -- ldr r0, blah -- nop -- cfmvsr mvf0, r0. */ -- -- /* Get Arm register number for ldr insn. */ -- if (GET_CODE (lhs) == REG) -- arm_regno = REGNO (lhs); -- else -- { -- gcc_assert (GET_CODE (rhs) == REG); -- arm_regno = REGNO (rhs); -- } -+ return insn; -+} - -- /* Next insn. */ -- first = next_nonnote_insn (first); -+static rtx -+cirrus_prev_mach_insn (rtx insn, int *len) -+{ -+ return cirrus_prev_next_mach_insn (insn, len, 0); -+} - -- if (! arm_cirrus_insn_p (first)) -- return; -+static rtx -+cirrus_next_mach_insn (rtx insn, int *len) -+{ -+ return cirrus_prev_next_mach_insn (insn, len, 1); -+} - -- body = PATTERN (first); -+/* Cirrus reorg for branch slots. */ -+static void -+cirrus_reorg_branch (rtx insn) -+{ -+ rtx t; -+ int nops, l; - -- /* (float (blah)) is in parallel with a clobber. */ -- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) -- body = XVECEXP (body, 0, 0); -- -- if (GET_CODE (body) == FLOAT) -- body = XEXP (body, 0); -- -- if (get_attr_cirrus (first) == CIRRUS_MOVE -- && GET_CODE (XEXP (body, 1)) == REG -- && arm_regno == REGNO (XEXP (body, 1))) -- emit_insn_after (gen_nop (), first); -+ /* TODO: handle jump-tables. */ -+ t = is_jump_table (insn); -+ if (t) -+ return; -+ -+ /* Any branch must be followed by 2 non Cirrus instructions. */ -+ t = insn; -+ for (nops = 2; nops > 0; ) -+ { -+ if (!cirrus_next_mach_insn (t, 0)) -+ { -+ insn = t; -+ break; -+ } -+ t = cirrus_next_mach_insn (t, &l); -+ if (arm_cirrus_insn_p (t)) -+ break; -+ nops -= l; - -- return; -- } - } - -- /* get_attr cannot accept USE or CLOBBER. */ -- if (!first -- || GET_CODE (first) != INSN -- || GET_CODE (PATTERN (first)) == USE -- || GET_CODE (PATTERN (first)) == CLOBBER) -- return; -+ while (nops-- > 0) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+} - -- attr = get_attr_cirrus (first); -+/* Cirrus reorg for bug #1 (cirrus + cfcmpxx). */ -+static void -+cirrus_reorg_bug1 (rtx insn) -+{ -+ rtx body = PATTERN (insn), body2; -+ rtx t; -+ int i, nops, l; -+ enum attr_cirrus attr; - -- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) -- must be followed by a non-coprocessor instruction. */ -- if (attr == CIRRUS_COMPARE) -+ /* Check if destination or clobber is Cirrus register. */ -+ if (GET_CODE (body) == PARALLEL) - { -- nops = 0; -- -- t = next_nonnote_insn (first); -+ for (i = 0; i < XVECLEN (body, 0); i++) -+ { -+ body2 = XVECEXP (body, 0, i); -+ if (GET_CODE (body2) == SET) -+ { -+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 5; -+ goto fix; -+ } -+ } -+ else if (GET_CODE (body2) == CLOBBER) -+ { -+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 4; -+ goto fix; -+ } -+ } -+ } -+ } -+ else if (GET_CODE (body) == SET) -+ { -+ if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 5; -+ goto fix; -+ } -+ } -+ return; - -- if (arm_cirrus_insn_p (t)) -- ++ nops; -+fix: -+ t = insn; -+ for ( ; nops > 0; ) -+ { -+ t = cirrus_next_mach_insn (t, &l); -+ if (!t) -+ break; -+ if (GET_CODE (t) == JUMP_INSN -+ || GET_CODE (t) == CALL_INSN) -+ { -+ nops -= l; -+ break; -+ } -+ else if (arm_cirrus_insn_p (t)) -+ { -+ attr = get_attr_cirrus (t); -+ if (attr == CIRRUS_COMPARE) -+ break; -+ } -+ nops -= l; -+ } - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; -+ while (nops-- > 0) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+} - -- while (nops --) -- emit_insn_after (gen_nop (), first); -+/* Cirrus reorg for bugs #10 and #12 (data aborts). */ -+static void -+cirrus_reorg_bug10_12 (rtx insn) -+{ -+ rtx t; - -- return; -- } -+ t = cirrus_next_mach_insn (insn, 0); -+ if (arm_cirrus_insn_p (t)) -+ if (TARGET_CIRRUS_D0 || -+ get_attr_cirrus (t) == CIRRUS_DOUBLE) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ - } - - /* Return TRUE if X references a SYMBOL_REF. */ -@@ -7727,7 +7796,7 @@ - { - Mnode * mp; - Mnode * nmp; -- int align64 = 0; -+ int align64 = 0, stuffnop = 0; - - if (ARM_DOUBLEWORD_ALIGN) - for (mp = minipool_vector_head; mp != NULL; mp = mp->next) -@@ -7742,8 +7811,27 @@ - ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", - INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); - -+ /* Check if branch before minipool is already stuffed with nops. */ -+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) -+ { -+ rtx t; -+ -+ t = prev_active_insn (scan); -+ if (GET_CODE (t) != INSN -+ || PATTERN (t) != const0_rtx) -+ stuffnop = 1; -+ } - scan = emit_label_after (gen_label_rtx (), scan); - scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); -+ /* Last instruction was branch, so put two non-Cirrus opcodes. */ -+ if (stuffnop) -+ { -+#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */ -+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+#endif -+ } -+ - scan = emit_label_after (minipool_vector_label, scan); - - for (mp = minipool_vector_head; mp != NULL; mp = nmp) -@@ -8151,15 +8239,38 @@ - gcc_assert (GET_CODE (insn) == NOTE); - minipool_pad = 0; - -+#if TARGET_CIRRUS /* I think this is a double-up */ -+ /* Scan all the insn and fix Cirrus issues. */ -+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) -+ { -+ rtx t, s; -+ -+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) -+ if (arm_mem_access_p (t)) -+ cirrus_reorg_bug10_12 (t); -+ -+ if (TARGET_CIRRUS_D0) -+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) -+ if (arm_cirrus_insn_p (t)) -+ cirrus_reorg_bug1 (t); -+ -+ /* Find last insn. */ -+ for (t = insn; ; t = s) -+ { -+ s = cirrus_next_mach_insn (t, 0); -+ if (!s) -+ break; -+ } -+ /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */ -+ for ( ; t; t = cirrus_prev_mach_insn (t, 0)) -+ if (GET_CODE (t) == JUMP_INSN -+ || GET_CODE (t) == CALL_INSN) -+ cirrus_reorg_branch (t); -+ } -+#endif - /* Scan all the insns and record the operands that will need fixing. */ - for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) - { -- if (TARGET_CIRRUS_FIX_INVALID_INSNS -- && (arm_cirrus_insn_p (insn) -- || GET_CODE (insn) == JUMP_INSN -- || arm_memory_load_p (insn))) -- cirrus_reorg (insn); -- - if (GET_CODE (insn) == BARRIER) - push_minipool_barrier (insn, address); - else if (INSN_P (insn)) -@@ -11755,16 +11910,10 @@ - || get_attr_conds (this_insn) != CONDS_NOCOND) - fail = TRUE; - -- /* A conditional cirrus instruction must be followed by -- a non Cirrus instruction. However, since we -- conditionalize instructions in this function and by -- the time we get here we can't add instructions -- (nops), because shorten_branches() has already been -- called, we will disable conditionalizing Cirrus -- instructions to be safe. */ -- if (GET_CODE (scanbody) != USE -- && GET_CODE (scanbody) != CLOBBER -- && get_attr_cirrus (this_insn) != CIRRUS_NOT) -+ /* To avoid erratic behaviour, we avoid conditional Cirrus -+ instructions when doing workarounds. */ -+ if (arm_cirrus_insn_p(this_insn) -+ && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)) - fail = TRUE; - break; - -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h gcc-4.1.2/gcc/config/arm/arm.h ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h 2005-11-05 01:02:51.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.h 2007-05-15 10:15:05.000000000 +1000 -@@ -5,6 +5,7 @@ - and Martin Simmons (@harleqn.co.uk). - More major hacks by Richard Earnshaw (rearnsha@arm.com) - Minor hacks by Nick Clifton (nickc@cygnus.com) -+ Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com) - - This file is part of GCC. - -@@ -140,7 +141,9 @@ - %{msoft-float:%{mhard-float: \ - %e-msoft-float and -mhard_float may not be used together}} \ - %{mbig-endian:%{mlittle-endian: \ -- %e-mbig-endian and -mlittle-endian may not be used together}}" -+ %e-mbig-endian and -mlittle-endian may not be used together}} \ -+%{mfix-crunch-d0:%{mfix-crunch-d1: \ -+ %e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}" - - #ifndef CC1_SPEC - #define CC1_SPEC "" -@@ -179,6 +182,9 @@ - #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) - #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA) - #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK) -+#define TARGET_CIRRUS (arm_arch_cirrus) -+#define TARGET_CIRRUS_D0 0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */ -+#define TARGET_CIRRUS_D1 1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */ - #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP) - #define TARGET_IWMMXT (arm_arch_iwmmxt) - #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt gcc-4.1.2/gcc/config/arm/arm.opt ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt 2005-11-05 01:02:51.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.opt 2007-05-15 10:09:31.000000000 +1000 -@@ -68,6 +68,14 @@ - Target Report Mask(CIRRUS_FIX_INVALID_INSNS) - Cirrus: Place NOPs to avoid invalid instruction combinations - -+fix-crunch-d0 -+Target Report Mask(ARM_FLAG_CIRRUS_D0) -+Cirrus: workarounds for Crunch coprocessor revision D0 -+ -+fix-crunch-d1 -+Target Report Mask(ARM_FLAG_CIRRUS_D1) -+Cirrus: workarounds for Crunch coprocessor revision D1 -+ - mcpu= - Target RejectNegative Joined - Specify the name of the target CPU -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi gcc-4.1.2/gcc/doc/invoke.texi ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi 2006-09-26 07:21:58.000000000 +1000 -+++ gcc-4.1.2/gcc/doc/invoke.texi 2007-05-15 10:07:04.000000000 +1000 -@@ -408,7 +408,7 @@ - -msingle-pic-base -mno-single-pic-base @gol - -mpic-register=@var{reg} @gol - -mnop-fun-dllimport @gol ---mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol -+-mfix-crunch-d0 -mfix-crunch-d1 @gol - -mpoke-function-name @gol - -mthumb -marm @gol - -mtpcs-frame -mtpcs-leaf-frame @gol -@@ -7435,17 +7435,12 @@ - Specify the register to be used for PIC addressing. The default is R10 - unless stack-checking is enabled, when R9 is used. - --@item -mcirrus-fix-invalid-insns --@opindex mcirrus-fix-invalid-insns --@opindex mno-cirrus-fix-invalid-insns --Insert NOPs into the instruction stream to in order to work around --problems with invalid Maverick instruction combinations. This option --is only valid if the @option{-mcpu=ep9312} option has been used to --enable generation of instructions for the Cirrus Maverick floating --point co-processor. This option is not enabled by default, since the --problem is only present in older Maverick implementations. The default --can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} --switch. -+@item -mfix-crunch-d0 -+@itemx -mfix-crunch-d1 -+@opindex mfix-crunch-d0 -+@opindex mfix-crunch-d1 -+Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions -+D0 and D1 respectively. - - @item -mpoke-function-name - @opindex mpoke-function-name diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch deleted file mode 100644 index 3d27cc1d9d..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch +++ /dev/null @@ -1,48 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-08 06:39:41.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-08 06:41:00.000000000 +1000 -@@ -7125,6 +7125,22 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match GEU for MAVERICK. -+(define_insn "*arm_bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) -+ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ - ; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. - (define_insn "*arm_bunlt" - [(set (pc) -@@ -7240,6 +7256,22 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed GEU for MAVERICK. -+(define_insn "*arm_bgeu_reversed" -+ [(set (pc) -+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ - ; Special pattern to match reversed UNLT for MAVERICK. - (define_insn "*arm_bunlt_reversed" - [(set (pc) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch deleted file mode 100644 index 101288375f..0000000000 --- a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch +++ /dev/null @@ -1,400 +0,0 @@ -diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c ---- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 -@@ -11427,26 +11427,53 @@ - /* These encodings assume that AC=1 in the FPA system control - byte. This allows us to handle all cases except UNEQ and - LTGT. */ -- switch (comp_code) -- { -- case GE: return ARM_GE; -- case GT: return ARM_GT; -- case LE: return ARM_LS; -- case LT: return ARM_MI; -- case NE: return ARM_NE; -- case EQ: return ARM_EQ; -- case ORDERED: return ARM_VC; -- case UNORDERED: return ARM_VS; -- case UNLT: return ARM_LT; -- case UNLE: return ARM_LE; -- case UNGT: return ARM_HI; -- case UNGE: return ARM_PL; -- /* UNEQ and LTGT do not have a representation. */ -- case UNEQ: /* Fall through. */ -- case LTGT: /* Fall through. */ -- default: gcc_unreachable (); -- } -- -+ if (!TARGET_MAVERICK) -+ { -+ switch (comp_code) -+ { -+ case GE: return ARM_GE; -+ case GT: return ARM_GT; -+ case LE: return ARM_LS; -+ case LT: return ARM_MI; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case ORDERED: return ARM_VC; -+ case UNORDERED: return ARM_VS; -+ case UNLT: return ARM_LT; -+ case UNLE: return ARM_LE; -+ case UNGT: return ARM_HI; -+ case UNGE: return ARM_PL; -+ /* UNEQ and LTGT do not have a representation. */ -+ case UNEQ: /* Fall through. */ -+ case LTGT: /* Fall through. */ -+ default: gcc_unreachable (); -+ } -+ } -+ else -+ { -+ /* CIRRUS */ -+ switch (comp_code) -+ { -+#if 1 -+ case GT: return ARM_VS; -+ case LE: return ARM_LE; -+ case LT: return ARM_LT; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case UNLE: return ARM_VC; -+ case UNGT: return ARM_GT; -+ case UNGE: return ARM_GE; -+ case UNEQ: return ARM_PL; -+ case LTGT: return ARM_MI; -+ /* These do not have a representation. */ -+ case GE: /* Fall through. -UNGE wrong atm */ -+ case UNLT: /* Fall through. -LT wrong atm */ -+ case ORDERED: /* Fall through. -AL wrong atm */ -+ case UNORDERED: /* Fall through. -AL wrong atm */ -+#endif -+ default: gcc_unreachable (); -+ } -+ } - case CC_SWPmode: - switch (comp_code) - { -diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md ---- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 -@@ -6952,10 +6952,11 @@ - "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" - ) - -+;broken on cirrus - (define_expand "bge" - [(set (pc) - (if_then_else (ge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM" -+ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" -@@ -6988,6 +6989,7 @@ - "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" - ) - -+; broken on cirrus? - (define_expand "bgeu" - [(set (pc) - (if_then_else (geu (match_dup 1) (const_int 0)) -@@ -7031,14 +7033,15 @@ - (if_then_else (ungt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" - ) - --(define_expand "bunlt" -+; broken for cirrus -+(define_expand "bunlt" - [(set (pc) - (if_then_else (unlt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" -@@ -7049,7 +7052,7 @@ - (if_then_else (unge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7058,7 +7061,7 @@ - (if_then_else (unle (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7069,7 +7072,7 @@ - (if_then_else (uneq (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1]