From 3dd84182dd989ba809bd6cb22d9385d93803b9cc Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Tue, 5 May 2009 22:16:24 +0200 Subject: sane-srcrevs: update linux-bug to get Ethernet fixed --- conf/distro/include/sane-srcrevs.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc index bd78008dd0..5e1a0cabce 100644 --- a/conf/distro/include/sane-srcrevs.inc +++ b/conf/distro/include/sane-srcrevs.inc @@ -111,7 +111,7 @@ SRCREV_pn-libowl ?= "277" SRCREV_pn-libxcalibrate ?= "209d83af61ed38a002c8096377deac292b3e396c" SRCREV_pn-libxosd ?= "627" SRCREV_pn-linux-bfin ?= "3758" -SRCREV_pn-linux-bug ?= "8996" +SRCREV_pn-linux-bug ?= "9048" SRCREV_pn-linux-hackndev-2.6 ?= "1308" SRCREV_pn-linux-ixp4xx ?= "1089" SRCREV_pn-linux-openmoko-2.6.24 ?= "fb42ce6724576fc173faf8abfb04aa2c36d213b7" -- cgit v1.2.3 From 039cc994ff1401acc643b10adf2cba4be75f3d86 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Sat, 16 May 2009 11:15:35 +0200 Subject: fbprogress: BUG only tool to show boot progress on built-in monochrome LCD --- recipes/fbprogress/fbprogress/fbprogress-init | 34 +++++++++++++++++++++++++++ recipes/fbprogress/fbprogress_1.1.bb | 32 +++++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100755 recipes/fbprogress/fbprogress/fbprogress-init create mode 100644 recipes/fbprogress/fbprogress_1.1.bb diff --git a/recipes/fbprogress/fbprogress/fbprogress-init b/recipes/fbprogress/fbprogress/fbprogress-init new file mode 100755 index 0000000000..c1dd3787b1 --- /dev/null +++ b/recipes/fbprogress/fbprogress/fbprogress-init @@ -0,0 +1,34 @@ +#!/bin/sh + +. /etc/init.d/functions + +case "$1" in + start) + # We don't want this script to block the rest of the boot process + if [ "$2" != "background" ]; then + $0 $1 background & + else + . /etc/profile + + echo "Starting FBProgress" + fbprogress.sh & + fi + ;; + + stop) + echo "Stopping FBProgress" + killproc fbprogress.sh + ;; + + restart) + $0 stop + sleep 1 + $0 start + ;; + + *) + echo "usage: $0 { start | stop | restart }" + ;; +esac + +exit 0 diff --git a/recipes/fbprogress/fbprogress_1.1.bb b/recipes/fbprogress/fbprogress_1.1.bb new file mode 100644 index 0000000000..8d603b8a3e --- /dev/null +++ b/recipes/fbprogress/fbprogress_1.1.bb @@ -0,0 +1,32 @@ +DESCRIPTION = "Bug framebuffer progress indicator" +AUTHOR = "Angel Roman" +HOMEPAGE = "http://www.buglabs.net/" +LICENSE = "GPL" +DEPENDS = "freetype zlib virtual/kernel" +SRCREV = "9118" +PR = "r1" + +SRC_URI = "svn://svn.buglabs.net/bug/trunk;module=com.buglabs.bug.native.fbprogress;proto=svn \ + file://fbprogress-init" + +S = "${WORKDIR}/com.buglabs.bug.native.fbprogress" + +inherit update-rc.d + +EXTRA_OEMAKE = "BUG_LINUX_SRC=${STAGING_KERNEL_DIR}" + +do_install() { + install -d ${D}/${sysconfdir}/fbprogress + install -m 0644 ${S}/images/* ${D}/${sysconfdir}/fbprogress/ + install -d ${D}${layout_bindir} + install -m 0755 fbprogress ${D}${layout_bindir} + install -m 0755 fbprogress.sh ${D}${layout_bindir} + install -d ${D}/${sysconfdir}/init.d + install -m 0755 ${WORKDIR}/fbprogress-init ${D}/${sysconfdir}/init.d/fbprogress +} + +PACKAGE_ARCH = "${MACHINE_ARCH}" +COMPATIBLE_MACHINE = "bug" + +INITSCRIPT_NAME = "fbprogress" +INITSCRIPT_PARAMS = "start 01 S . stop 15 0 1 2 3 4 5 6 ." -- cgit v1.2.3 From 91432caba81577cccd57f0eff7b0541763c30a80 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Sat, 16 May 2009 11:17:52 +0200 Subject: sane-srcrevs: bump linux-bug to get recent fixes --- conf/distro/include/sane-srcrevs.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc index 5e1a0cabce..60d53abc71 100644 --- a/conf/distro/include/sane-srcrevs.inc +++ b/conf/distro/include/sane-srcrevs.inc @@ -111,7 +111,7 @@ SRCREV_pn-libowl ?= "277" SRCREV_pn-libxcalibrate ?= "209d83af61ed38a002c8096377deac292b3e396c" SRCREV_pn-libxosd ?= "627" SRCREV_pn-linux-bfin ?= "3758" -SRCREV_pn-linux-bug ?= "9048" +SRCREV_pn-linux-bug ?= "9110" SRCREV_pn-linux-hackndev-2.6 ?= "1308" SRCREV_pn-linux-ixp4xx ?= "1089" SRCREV_pn-linux-openmoko-2.6.24 ?= "fb42ce6724576fc173faf8abfb04aa2c36d213b7" -- cgit v1.2.3 From 7b2b189bbd8472c689df79184b21f94ffa509808 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sat, 16 May 2009 11:22:56 +0200 Subject: checksums: add more checksums --- conf/checksums.ini | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/conf/checksums.ini b/conf/checksums.ini index d8392d1507..d6dd12c9c8 100644 --- a/conf/checksums.ini +++ b/conf/checksums.ini @@ -3910,6 +3910,10 @@ sha256=73f3b92c0f85ab2bf0f9bb18f928a8b84cacdbb459f3a530df540d4ddf134405 md5=7bc5c89870d47c88f407fcfd666c739d sha256=102bb7a5d329dd6831bc8a923fa0b5d7634efa215e3d15377630d9b738df49da +[http://www.kernel.org/pub/linux/network/connman/connman-0.19.tar.gz] +md5=3d61c5db55d225c3efbf4c950dc0842f +sha256=cc4a4b73d8d7b0e19dd2dd274ba91acb67b14c84fc448a921d1359e25e4d2df0 + [ftp://ftp.moblin.org/connman/releases/connman-0.2.tar.gz] md5=bf48aa07d3c1e5fe272c7f139bc01fc9 sha256=eacc3c57cffb411b09d834d2225323cde5676165b5d2fc2a27b16cde98e3ba97 @@ -23190,6 +23194,10 @@ sha256=c750c8180057385eaa0844f1148d6f0223b986da322773195eab44b33b97c19f md5=b2c104938c1c3eb47e7605432bbd3157 sha256=c750c8180057385eaa0844f1148d6f0223b986da322773195eab44b33b97c19f +[http://uim.freedesktop.org/releases/uim/stable/uim-1.3.1.tar.bz2] +md5=2832e23d4778bbacbfa4b49bf642d667 +sha256=ed2cfa15018a4fd2557e875f66fcb3f0b9dabe12fa0700aa2f11cca69c2cb256 + [http://uim.googlecode.com/files/uim-1.3.1.tar.bz2] md5=2832e23d4778bbacbfa4b49bf642d667 sha256=ed2cfa15018a4fd2557e875f66fcb3f0b9dabe12fa0700aa2f11cca69c2cb256 -- cgit v1.2.3 From fc7141029480c45d3bbefa80c441fef39579336b Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sat, 16 May 2009 11:24:00 +0200 Subject: connman update to 0.19 --- recipes/connman/connman_0.19.bb | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 recipes/connman/connman_0.19.bb diff --git a/recipes/connman/connman_0.19.bb b/recipes/connman/connman_0.19.bb new file mode 100644 index 0000000000..b8d86613b8 --- /dev/null +++ b/recipes/connman/connman_0.19.bb @@ -0,0 +1,35 @@ +require connman.inc + +EXTRA_OECONF += "\ + --disable-gtk-doc \ + --enable-debug \ + --enable-threads \ + --enable-loopback \ + --enable-ethernet \ + --enable-wifi \ + --disable-wimax \ + --enable-bluetooth \ + --enable-udhcp \ + --enable-dhclient \ + --enable-resolvconf \ + --enable-dnsproxy \ + --disable-novatel \ + --disable-huawei \ + --disable-hso \ + --enable-ppp \ +# needs udev >= 129 + --disable-udev \ + --disable-polkit \ + --enable-client \ + --enable-fake \ +# --with-udhcpc=PROGRAM \ +# --with-dhclient=PROGRAM \ +# --with-resolvconf=PROGRAM \ +# --with-pppd=PROGRAM \ +" + +SRC_URI = "\ + http://www.kernel.org/pub/linux/network/connman/connman-${PV}.tar.gz \ + file://connman \ +" + -- cgit v1.2.3 From d4cfee07a130b45236b9ba479a9a23eca9fb9018 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sat, 16 May 2009 11:38:56 +0200 Subject: mtd-utils-natice 1.2.0+git: raise default pref for angstrom --- recipes/mtd/mtd-utils-native_1.2.0+git.bb | 1 + 1 file changed, 1 insertion(+) diff --git a/recipes/mtd/mtd-utils-native_1.2.0+git.bb b/recipes/mtd/mtd-utils-native_1.2.0+git.bb index 6135d7f4d0..85692a0e91 100644 --- a/recipes/mtd/mtd-utils-native_1.2.0+git.bb +++ b/recipes/mtd/mtd-utils-native_1.2.0+git.bb @@ -1,5 +1,6 @@ # Doesn't build for everyone, errors range from missing includes to linking errors DEFAULT_PREFERENCE = "-1" +DEFAULT_PREFERENCE_angstrom = "1" require mtd-utils_${PV}.bb require mtd-utils-native.inc -- cgit v1.2.3 From b4e29757971085a7f089bd106ec7d6223e753112 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sat, 16 May 2009 12:00:51 +0200 Subject: connman-gnome: add (default disabled) git version --- recipes/connman/connman-gnome_git.bb | 28 ++++++++++++++++++++++++++++ recipes/connman/files/connman-applet.desktop | 2 +- 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 recipes/connman/connman-gnome_git.bb diff --git a/recipes/connman/connman-gnome_git.bb b/recipes/connman/connman-gnome_git.bb new file mode 100644 index 0000000000..cd244b84ca --- /dev/null +++ b/recipes/connman/connman-gnome_git.bb @@ -0,0 +1,28 @@ +DESCRIPTION = "gtk frontend for connman" +HOMEPAGE = "http://www.moblin.org/projects/projects_connman.php" +SECTION = "libs/network" +LICENSE = "GPL" +DEPENDS = "gtk+ dbus" + +RRECOMMENDS_${PN} = "connman connman-plugin-ethernet connman-plugin-loopback connman-plugin-udhcp connman-plugin-wifi" + +PV = "0.5+git" +PR_append = ".gitr${SRCREV}" + +DEFAULT_PREFERENCE = "-1" + +SRCREV = "0059a16915d65880e3f9892a8f0a25f65968260e" +SRC_URI = "\ + git://git.kernel.org/pub/scm/network/connman/connman-gnome.git;protocol=git \ + file://connman-applet.desktop" + +S = "${WORKDIR}/git" + + +inherit autotools gtk-icon-cache + +do_install_append() { + install -d ${D}${datadir}/applications/ + install ${WORKDIR}/connman-applet.desktop ${D}${datadir}/applications/ +} + diff --git a/recipes/connman/files/connman-applet.desktop b/recipes/connman/files/connman-applet.desktop index ad17682507..83d96ee67d 100644 --- a/recipes/connman/files/connman-applet.desktop +++ b/recipes/connman/files/connman-applet.desktop @@ -6,5 +6,5 @@ Icon=stock_internet Exec=connman-applet Terminal=false Type=Application -Categories=Network;GTK +Categories=Network;GTK; -- cgit v1.2.3 From fa1039ef168f11906fdac1690f3462b39e057a66 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Sat, 16 May 2009 12:03:53 +0200 Subject: linux-kirkwood: update to 2.6.29.2 --- conf/machine/include/kirkwood.inc | 2 +- recipes/linux/linux-kirkwood_2.6.29.1.bb | 21 --------------------- recipes/linux/linux-kirkwood_2.6.29.2.bb | 21 +++++++++++++++++++++ 3 files changed, 22 insertions(+), 22 deletions(-) delete mode 100644 recipes/linux/linux-kirkwood_2.6.29.1.bb create mode 100644 recipes/linux/linux-kirkwood_2.6.29.2.bb diff --git a/conf/machine/include/kirkwood.inc b/conf/machine/include/kirkwood.inc index f58feb686c..8f995899c9 100644 --- a/conf/machine/include/kirkwood.inc +++ b/conf/machine/include/kirkwood.inc @@ -11,7 +11,7 @@ USE_DEVFS = "0" PREFERRED_PROVIDER_virtual/bootloader = "" PREFERRED_PROVIDER_virtual/kernel = "linux-kirkwood" -MACHINE_KERNEL_PR = "r1" +MACHINE_KERNEL_PR = "r2" IMAGE_FSTYPES += "tar.gz ubi" SERIAL_CONSOLE = "ttyS0 115200" diff --git a/recipes/linux/linux-kirkwood_2.6.29.1.bb b/recipes/linux/linux-kirkwood_2.6.29.1.bb deleted file mode 100644 index 531f520497..0000000000 --- a/recipes/linux/linux-kirkwood_2.6.29.1.bb +++ /dev/null @@ -1,21 +0,0 @@ -DESCRIPTION = "Linux Kernel for Marvell Kirkwood based devices" -SECTION = "kernel" -LICENSE = "GPL" -COMPATIBLE_MACHINE = "sheevaplug" - -require linux.inc - -# Change MACHINE_KERNEL_PR in conf/machine/include/kirkwood.inc -PV = "2.6.29.1" -PR_append = "+gitr${SRCREV}" -#PV = "2.6.28+2.6.29rc7-${PR}+gitr${SRCREV}" - -SRCREV = "f66f1d49e6d8617a07b07681c684083e48547eef" -SRC_URI = "git://git.marvell.com/orion.git;protocol=git;branch=stable-2.6.29 \ - file://fw.patch;patch=1 \ - file://defconfig \ - " - -S = "${WORKDIR}/git" - -KERNEL_IMAGETYPE ?= "uImage" diff --git a/recipes/linux/linux-kirkwood_2.6.29.2.bb b/recipes/linux/linux-kirkwood_2.6.29.2.bb new file mode 100644 index 0000000000..0e349362db --- /dev/null +++ b/recipes/linux/linux-kirkwood_2.6.29.2.bb @@ -0,0 +1,21 @@ +DESCRIPTION = "Linux Kernel for Marvell Kirkwood based devices" +SECTION = "kernel" +LICENSE = "GPL" +COMPATIBLE_MACHINE = "sheevaplug" + +require linux.inc + +# Change MACHINE_KERNEL_PR in conf/machine/include/kirkwood.inc +PV = "2.6.29.2" +PR_append = "+gitr${SRCREV}" +#PV = "2.6.28+2.6.29rc7-${PR}+gitr${SRCREV}" + +SRCREV = "10a12868405319fbf114af2bde9789aa64c34144" +SRC_URI = "git://git.marvell.com/orion.git;protocol=git;branch=stable-2.6.29 \ + file://fw.patch;patch=1 \ + file://defconfig \ + " + +S = "${WORKDIR}/git" + +KERNEL_IMAGETYPE ?= "uImage" -- cgit v1.2.3 From f7cda20ffc2bd30fbb7db898cbffc5d273bb9bb8 Mon Sep 17 00:00:00 2001 From: Sergey Lapin Date: Thu, 14 May 2009 17:03:10 +0400 Subject: at91bootstrap: generalization of recipes --- recipes/at91bootstrap/at91bootstrap.inc | 21 +++++++++++++++++++++ recipes/at91bootstrap/at91bootstrap_2.10.bb | 28 ++-------------------------- recipes/at91bootstrap/at91bootstrap_2.4.bb | 7 ++----- 3 files changed, 25 insertions(+), 31 deletions(-) create mode 100644 recipes/at91bootstrap/at91bootstrap.inc diff --git a/recipes/at91bootstrap/at91bootstrap.inc b/recipes/at91bootstrap/at91bootstrap.inc new file mode 100644 index 0000000000..2160f64fbc --- /dev/null +++ b/recipes/at91bootstrap/at91bootstrap.inc @@ -0,0 +1,21 @@ +DESCRIPTION = "at91bootstrap: loaded into internal SRAM by AT91 BootROM" +SECTION = "bootloaders" + +SRC_URI = "ftp://www.at91.com/pub/buildroot/${PN}-${PV}.tar.bz2 \ + file://defconfig \ + " +S = "${WORKDIR}/${PN}-${PV}" +PACKAGE_ARCH = "${MACHINE_ARCH}" +EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOY_DIR_IMAGE} REVISION=${PR}" + +do_compile () { + unset LDFLAGS + unset CFLAGS + unset CPPFLAGS + + rm -Rf ${S}/binaries + cp ${S}/../defconfig ${S}/.config + oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" + oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" boot + oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" install +} diff --git a/recipes/at91bootstrap/at91bootstrap_2.10.bb b/recipes/at91bootstrap/at91bootstrap_2.10.bb index a652f1b155..a68d8ef581 100644 --- a/recipes/at91bootstrap/at91bootstrap_2.10.bb +++ b/recipes/at91bootstrap/at91bootstrap_2.10.bb @@ -1,26 +1,2 @@ -DESCRIPTION = "at91bootstrap: loaded into internal SRAM by AT91 BootROM" -SECTION = "bootloaders" - -SRC_URI = "ftp://www.at91.com/pub/buildroot/${PN}-${PV}.tar.bz2 \ - file://defconfig \ - " - -AT91BOOTSTRAP_FLAGS ?= "" - -S = "${WORKDIR}/${PN}-${PV}" - -PACKAGE_ARCH = "${MACHINE_ARCH}" -EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOY_DIR_IMAGE} REVISION=${PR}" - -do_compile () { - unset LDFLAGS - unset CFLAGS - unset CPPFLAGS - - rm -Rf ${S}/binaries - cp ${S}/../defconfig ${S}/.config - oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" - oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" boot - oe_runmake AT91_CUSTOM_FLAGS="${AT91BOOTSTRAP_FLAGS}" install -} - +PR = "r1" +require at91bootstrap.inc diff --git a/recipes/at91bootstrap/at91bootstrap_2.4.bb b/recipes/at91bootstrap/at91bootstrap_2.4.bb index 69c7d6c19b..e2ba34ed57 100644 --- a/recipes/at91bootstrap/at91bootstrap_2.4.bb +++ b/recipes/at91bootstrap/at91bootstrap_2.4.bb @@ -1,4 +1,4 @@ -DESCRIPTION = "at91bootstrap" +require at91bootstrap.inc SRC_URI = "ftp://www.at91.com/pub/buildroot/${PN}-${PV}.tar.bz2 \ " SRC_URI_append_afeb9260 = " file://0001-Generic-code-changes.patch;patch=1 \ @@ -6,8 +6,7 @@ SRC_URI_append_afeb9260 = " file://0001-Generic-code-changes.patch;patch=1 \ file://0003-AFEB9260-board-support.patch;patch=1 \ file://0004-AFEB9260-133-board-support.patch;patch=1" -PR = "r4" -SECTION = "bootloaders" +PR = "r5" AT91BOOTSTRAP_MACHINE ?= "${MACHINE}" AT91BOOTSTRAP_FLAGS ?= "" @@ -16,8 +15,6 @@ AT91BOOTSTRAP_MEMORY ?= "dataflash" AT91BOOTSTRAP_IMAGE = "at91bootstrap-${MACHINE}-${AT91BOOTSTRAP_MEMORY}-${PV}-${PR}.bin" AT91BOOTSTRAP_SYMLINK = "at91bootstrap.bin" -S = "${WORKDIR}/${PN}-${PV}" - PACKAGE_ARCH = "${MACHINE_ARCH}" EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} MEMORY=${AT91BOOTSTRAP_MEMORY}" -- cgit v1.2.3 From 090d693fff91912acbd0c380a975fb712b71e1c6 Mon Sep 17 00:00:00 2001 From: Sergey Lapin Date: Thu, 14 May 2009 17:05:24 +0400 Subject: at91bootstrap: added v2.11 --- .../at91bootstrap-2.11/0001-AFEB9260-support.patch | 1357 ++++++++++++++++++++ .../at91bootstrap-2.11/afeb9260-166/defconfig | 94 ++ recipes/at91bootstrap/at91bootstrap_2.11.bb | 7 + 3 files changed, 1458 insertions(+) create mode 100644 recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support.patch create mode 100644 recipes/at91bootstrap/at91bootstrap-2.11/afeb9260-166/defconfig create mode 100644 recipes/at91bootstrap/at91bootstrap_2.11.bb diff --git a/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support.patch b/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support.patch new file mode 100644 index 0000000000..1b13a590ff --- /dev/null +++ b/recipes/at91bootstrap/at91bootstrap-2.11/0001-AFEB9260-support.patch @@ -0,0 +1,1357 @@ +From 9d253ab04ceaea4aeebf397e3397c2088f08bd87 Mon Sep 17 00:00:00 2001 +From: slapin +Date: Sun, 10 May 2009 02:16:44 +0400 +Subject: [PATCH] AFEB9260 support + + +Signed-off-by: Sergey Lapin +--- + Config.in | 5 +- + Makefile | 2 +- + board/Config.in | 47 +++++- + board/afeb9260/afeb9260.c | 246 +++++++++++++++++++++++++++++ + board/afeb9260/afeb9260.h | 126 +++++++++++++++ + board/afeb9260/afeb9260_defconfig | 94 +++++++++++ + board/afeb9260/old/afeb9260.c | 240 ++++++++++++++++++++++++++++ + board/afeb9260/old/afeb9260.mk | 8 + + board/afeb9260/old/dataflash/afeb9260.h | 127 +++++++++++++++ + board/afeb9260/old/nandflash/afeb9260ek.h | 151 ++++++++++++++++++ + board/afeb9260/old/pll.h | 35 ++++ + board/board_cpp.mk | 25 +++ + driver/Config.in.dataflash | 2 +- + driver/dataflash.c | 2 +- + include/part.h | 6 + + 15 files changed, 1105 insertions(+), 11 deletions(-) + create mode 100644 board/afeb9260/afeb9260.c + create mode 100644 board/afeb9260/afeb9260.h + create mode 100644 board/afeb9260/afeb9260_defconfig + create mode 100644 board/afeb9260/old/afeb9260.c + create mode 100644 board/afeb9260/old/afeb9260.mk + create mode 100644 board/afeb9260/old/dataflash/afeb9260.h + create mode 100644 board/afeb9260/old/nandflash/afeb9260ek.h + create mode 100644 board/afeb9260/old/pll.h + +diff --git a/Config.in b/Config.in +index e187a27..d7f7a3b 100644 +--- a/Config.in ++++ b/Config.in +@@ -109,4 +109,7 @@ config CONFIG_USER_HW_INIT + help + Initialize Hardware + +- ++config CONFIG_THUMB ++ bool "Build in thumb mode" ++ help ++ Build code in thumb mode +diff --git a/Makefile b/Makefile +index 32bd556..8a53e94 100644 +--- a/Makefile ++++ b/Makefile +@@ -189,7 +189,7 @@ include driver/driver_cpp.mk + # -lgcc : tells the linker to tie in newlib + LDFLAGS+=-nostartfiles -Map=result/$(BOOT_NAME).map --cref + #LDFLAGS+=-lc -lgcc +-LDFLAGS+=-T elf32-littlearm.lds -Ttext $(LINK_ADDR) ++LDFLAGS+=-T elf32-littlearm.lds --gc-sections -Ttext $(LINK_ADDR) + + all: $(obj) $(AT91BOOTSTRAP) .config filesize + +diff --git a/board/Config.in b/board/Config.in +index 074018a..1c2168b 100644 +--- a/board/Config.in ++++ b/board/Config.in +@@ -92,6 +92,17 @@ config CONFIG_AT91CAP9ADK + help + Use the AT91CAP9ADK Development board + ++config CONFIG_AFEB9260 ++ bool "afeb9260" ++ select CONFIG_SDRAM ++ select ALLOW_DATAFLASH ++ select ALLOW_NANDFLASH ++ select ALLOW_CPU_CLK_166MHZ ++ select ALLOW_CPU_CLK_180MHZ ++ select ALLOW_CRYSTAL_18_432MHZ ++ help ++ Use the AFEB9260 Development board ++ + endchoice + + config CONFIG_CHIP +@@ -103,6 +114,7 @@ config CONFIG_CHIP + default "AT91SAM9XE" if CONFIG_AT91SAM9XEEK + default "AT91SAM9G20" if CONFIG_AT91SAM9G20EK + default "AT91CAP9" if CONFIG_AT91CAP9ADK ++ default "AT91SAM9260" if CONFIG_AFEB9260 + help + Name of the board, A Board Support package + (BSP) must be available. +@@ -116,6 +128,7 @@ config CONFIG_BOARD + default "at91sam9xeek" if CONFIG_AT91SAM9XEEK + default "at91sam9g20ek" if CONFIG_AT91SAM9G20EK + default "at91cap9adk" if CONFIG_AT91CAP9ADK ++ default "afeb9260" if CONFIG_AFEB9260 + help + Name of the board, A Board Support package + (BSP) must be available. +@@ -129,6 +142,7 @@ config CONFIG_MACH_TYPE + default "0x44B" if CONFIG_AT91SAM9XEEK + default "0x658" if CONFIG_AT91SAM9G20EK + default "1442" if CONFIG_AT91CAP9ADK ++ default "1859" if CONFIG_AFEB9260 + help + + config CONFIG_LINK_ADDR +@@ -141,6 +155,7 @@ config CONFIG_LINK_ADDR + default "0x200000" if CONFIG_AT91SAM9G20EK + default "0x000000" if CONFIG_AT91CAP9ADK && CONFIG_DATAFLASH + default "0x100000" if CONFIG_AT91CAP9ADK && CONFIG_FLASH ++ default "0x200000" if CONFIG_AFEB9260 + default "0x200000" + help + +@@ -153,11 +168,13 @@ config CONFIG_TOP_OF_MEMORY + default "0x301000" if CONFIG_AT91SAM9XEEK + default "0x301000" if CONFIG_AT91SAM9G20EK + default "0x108000" if CONFIG_AT91CAP9ADK ++ default "0x301000" if CONFIG_AFEB9260 + help + + config CONFIG_BOOTSTRAP_MAXSIZE + string + default "4096" if CONFIG_AT91SAM9260EK ++ default "4096" if CONFIG_AFEB9260 + default "16384" + + choice +@@ -212,6 +229,14 @@ choice + prompt "CPU clock" + default CONFIG_CPU_CLK_200MHZ + ++config CONFIG_CPU_CLK_166MHZ ++ bool "166 MHz" ++ depends on ALLOW_CPU_CLK_166MHZ ++ ++config CONFIG_CPU_CLK_180MHZ ++ bool "180 MHz" ++ depends on ALLOW_CPU_CLK_180MHZ ++ + config CONFIG_CPU_CLK_200MHZ + bool "200 MHz" + depends on ALLOW_CPU_CLK_200MHZ +@@ -231,6 +256,12 @@ config CONFIG_CPU_CLK_400MHZ + + endchoice + ++config ALLOW_CPU_CLK_166MHZ ++ bool ++ ++config ALLOW_CPU_CLK_180MHZ ++ bool ++ + config ALLOW_CPU_CLK_200MHZ + bool + +@@ -251,10 +282,18 @@ config DISABLE_CPU_CLK_240MHZ + choice + prompt "Bus Speed" + default CONFIG_BUS_SPEED_133MHZ +- depends on CONFIG_AT91SAM9G20EK ++ depends on CONFIG_AT91SAM9G20EK || CONFIG_AFEB9260 + help + Select the speed of the bus + ++config CONFIG_BUS_SPEED_83MHZ ++ bool "83 MHz" ++ depends on CONFIG_AFEB9260 ++ ++config CONFIG_BUS_SPEED_90MHZ ++ bool "90 MHz" ++ depends on CONFIG_AFEB9260 ++ + config CONFIG_BUS_SPEED_100MHZ + bool "100 MHz" + depends on CONFIG_AT91SAM9G20EK +@@ -264,9 +303,3 @@ config CONFIG_BUS_SPEED_133MHZ + depends on CONFIG_AT91SAM9G20EK + + endchoice +- +- +- +- +- +- +diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c +new file mode 100644 +index 0000000..4e11b6b +--- /dev/null ++++ b/board/afeb9260/afeb9260.c +@@ -0,0 +1,246 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : at91sam9260ek.c ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ * ODi Nov 9th : dstp #3507 "Bad PIO descriptors in at91samxxxek.c" ++ *----------------------------------------------------------------------------- ++ */ ++#include "part.h" ++#include "main.h" ++#include "gpio.h" ++#include "pmc.h" ++#include "debug.h" ++#include "memory.h" ++ ++static inline unsigned int get_cp15(void) ++{ ++ unsigned int value; ++ __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value)); ++ return value; ++} ++ ++static inline void set_cp15(unsigned int value) ++{ ++ __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value)); ++} ++ ++#ifdef CONFIG_HW_INIT ++/*----------------------------------------------------------------------------*/ ++/* \fn hw_init */ ++/* \brief This function performs very low level HW initialization */ ++/* This function is invoked as soon as possible during the c_startup */ ++/* The bss segment must be initialized */ ++/*----------------------------------------------------------------------------*/ ++void hw_init(void) ++{ ++ unsigned int cp15; ++ ++ /* Disable watchdog */ ++ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); ++ ++ /* At this stage the main oscillator is supposed to be enabled ++ * PCK = MCK = MOSC */ ++ ++ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ ++ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* PCK = PLLA = 2 * MCK */ ++ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); ++ /* Switch MCK on PLLA output */ ++ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure PLLB */ ++ pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure CP15 */ ++ cp15 = get_cp15(); ++ cp15 |= I_CACHE; ++ set_cp15(cp15); ++ ++ /* Configure the PIO controller */ ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0)); ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0)); ++ ++ /* Configure the EBI Slave Slot Cycle to 64 */ ++ writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3)); ++ ++#ifdef CONFIG_DEBUG ++ /* Enable Debug messages on the DBGU */ ++ dbg_init(BAUDRATE(MASTER_CLOCK, 115200)); ++ header(); ++#endif /* CONFIG_DEBUG */ ++ ++#ifdef CONFIG_SDRAM ++ /* Initialize the matrix */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++#if defined(CONFIG_BUS_SPEED_83MHZ) || defined(CONFIG_BUS_SPEED_90MHZ) ++/* CLK= 11ns */ ++/* TWR = tDPL = 2 2CLK always */ ++/* TRC = tRC = 65ns = 6 clk */ ++/* TRP = tRP = 20ns = 2 clk */ ++/* TRCD = tRCD = 20ns = 2 clk */ ++/* TRAS = tRAS = 45ns = 5 clk */ ++/* TXSR = tRRC = 65ns = 6 clk */ ++ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_6 | /* *7 */ ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_5 | /* *5 */ ++ AT91C_SDRAMC_TXSR_6, /* *8 */ /* Control Register */ ++ 710, AT91C_SDRAMC_MD_SDRAM); /* Refresh Timer Register */ ++#else ++ /* Configure SDRAM Controller */ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_7 | ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_5 | ++ AT91C_SDRAMC_TXSR_8, /* Control Register */ ++ (MASTER_CLOCK * 7)/1000000, /* Refresh Timer Register */ ++ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ ++#endif ++ ++#endif /* CONFIG_SDRAM */ ++} ++#endif /* CONFIG_HW_INIT */ ++ ++#ifdef CONFIG_SDRAM ++/*------------------------------------------------------------------------------*/ ++/* \fn sdramc_hw_init */ ++/* \brief This function performs SDRAMC HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void sdramc_hw_init(void) ++{ ++ /* Configure PIOs */ ++/* const struct pio_desc sdramc_pio[] = { ++ {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++*/ ++ /* Configure the SDRAMC PIO controller to output PCK0 */ ++/* pio_setup(sdramc_pio); */ ++ ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0)); ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0)); ++ ++} ++#endif /* CONFIG_SDRAM */ ++ ++#ifdef CONFIG_DATAFLASH ++/*------------------------------------------------------------------------------*/ ++/* \fn df_hw_init */ ++/* \brief This function performs DataFlash HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void df_hw_init(void) ++{ ++ writel(0xf, 0xfffff444); ++ writel(0xf, 0xfffff460); ++ writel(0xf, 0xfffff470); ++ writel(0xf, 0xfffff404); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0)); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0)); ++} ++#endif /* CONFIG_DATAFLASH */ ++ ++/* We init NAND regardless of whatever */ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_hw_init */ ++/* \brief NandFlash HW init */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_hw_init(void) ++{ ++ /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++ /* Configure SMC CS3 */ ++ writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3); ++ writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3); ++ writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE) , AT91C_BASE_SMC + SMC_CYCLE3); ++ writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | ++ AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF) , AT91C_BASE_SMC + SMC_CTRL3); ++ ++ /* Configure the PIO controller */ ++ writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC); ++ ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0)); ++} ++ ++ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_cfg_16bits_dbw_init */ ++/* \brief Configure SMC in 16 bits mode */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_cfg_16bits_dbw_init(void) ++{ ++ writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3); ++} ++ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_cfg_8bits_dbw_init */ ++/* \brief Configure SMC in 8 bits mode */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_cfg_8bits_dbw_init(void) ++{ ++ writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3); ++} +diff --git a/board/afeb9260/afeb9260.h b/board/afeb9260/afeb9260.h +new file mode 100644 +index 0000000..7310c0f +--- /dev/null ++++ b/board/afeb9260/afeb9260.h +@@ -0,0 +1,126 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : afeb9260.h ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ *----------------------------------------------------------------------------- ++ */ ++#ifndef _AFEB9260_H ++#define _AFEB9260_H ++ ++/* ******************************************************************* */ ++/* PMC Settings */ ++/* */ ++/* The main oscillator is enabled as soon as possible in the c_startup */ ++/* and MCK is switched on the main oscillator. */ ++/* PLL initialization is done later in the hw_init() function */ ++/* ******************************************************************* */ ++#if defined(CONFIG_CPU_CLK_200MHZ) ++#define MASTER_CLOCK (198656000/2) ++#define PLLA_SETTINGS 0x2060BF09 ++#endif ++ ++#if defined(CONFIG_CPU_CLK_166MHZ) ++#define PLLA_SETTINGS 0x25ceBFa5 /* 166MHz */ ++#define MASTER_CLOCK (165999709/2) /* 166MHz MCK=83MHz*/ ++#endif ++ ++#if defined(CONFIG_CPU_CLK_180MHZ) ++#define PLLA_SETTINGS 0x2125BF1E /* 180MHz */ ++#define MASTER_CLOCK (179999198/2) /* 180MHz MCK=90MHz */ ++#endif ++ ++#define TOP_OF_MEMORY 0x301000 ++#define PLL_LOCK_TIMEOUT 1000000 ++ ++#define PLLB_SETTINGS 0x10483F0E ++ ++/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ ++#define MCKR_SETTINGS (AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2) ++#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS) ++ ++/* ******************************************************************* */ ++/* DataFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_BASE_SPI AT91C_BASE_SPI0 ++#define AT91C_ID_SPI AT91C_ID_SPI0 ++ ++/* AC characteristics */ ++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ ++#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ ++#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ ++ ++#define DF_CS_SETTINGS (AT91C_SPI_NCPHA | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) ++ ++/* ******************************************************************* */ ++/* NandFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_SMARTMEDIA_BASE 0x40000000 ++ ++#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */ ++#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */ ++ ++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0) ++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0) ++ ++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13)) ++ ++ ++/* ******************************************************************** */ ++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ ++/* Please refer to SMC section in AT91SAM datasheet to learn how */ ++/* to generate these values. */ ++/* ******************************************************************** */ ++#define AT91C_SM_NWE_SETUP (1 << 0) ++#define AT91C_SM_NCS_WR_SETUP (0 << 8) ++#define AT91C_SM_NRD_SETUP (1 << 16) ++#define AT91C_SM_NCS_RD_SETUP (0 << 24) ++ ++#define AT91C_SM_NWE_PULSE (3 << 0) ++#define AT91C_SM_NCS_WR_PULSE (3 << 8) ++#define AT91C_SM_NRD_PULSE (3 << 16) ++#define AT91C_SM_NCS_RD_PULSE (3 << 24) ++ ++#define AT91C_SM_NWE_CYCLE (5 << 0) ++#define AT91C_SM_NRD_CYCLE (5 << 16) ++#define AT91C_SM_TDF (2 << 16) ++ ++#endif /* _AT91SAM9260EK_H */ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/board/afeb9260/afeb9260_defconfig b/board/afeb9260/afeb9260_defconfig +new file mode 100644 +index 0000000..bf8b6f9 +--- /dev/null ++++ b/board/afeb9260/afeb9260_defconfig +@@ -0,0 +1,94 @@ ++# ++# Automatically generated make config: don't edit ++# Sun May 10 01:26:05 2009 ++# ++HAVE_DOT_CONFIG=y ++CONFIG_BOARDNAME="afeb9260" ++# CONFIG_AT91SAM9260EK is not set ++# CONFIG_AT91SAM9261EK is not set ++# CONFIG_AT91SAM9263EK is not set ++# CONFIG_AT91SAM9RLEK is not set ++# CONFIG_AT91SAM9XEEK is not set ++# CONFIG_AT91SAM9G20EK is not set ++# CONFIG_AT91CAP9ADK is not set ++CONFIG_AFEB9260=y ++CONFIG_CHIP="AT91SAM9260" ++CONFIG_BOARD="afeb9260" ++CONFIG_MACH_TYPE="1859" ++CONFIG_LINK_ADDR="0x200000" ++CONFIG_TOP_OF_MEMORY="0x301000" ++CONFIG_BOOTSTRAP_MAXSIZE="4096" ++# CONFIG_CRYSTAL_12_000MHZ is not set ++# CONFIG_CRYSTAL_16_000MHZ is not set ++# CONFIG_CRYSTAL_16_36766MHZ is not set ++CONFIG_CRYSTAL_18_432MHZ=y ++ALLOW_CRYSTAL_18_432MHZ=y ++CONFIG_CRYSTAL="CRYSTAL_18_432MHZ" ++CONFIG_CPU_CLK_166MHZ=y ++# CONFIG_CPU_CLK_180MHZ is not set ++# CONFIG_CPU_CLK_200MHZ is not set ++# CONFIG_CPU_CLK_240MHZ is not set ++# CONFIG_CPU_CLK_266MHZ is not set ++# CONFIG_CPU_CLK_400MHZ is not set ++ALLOW_CPU_CLK_166MHZ=y ++ALLOW_CPU_CLK_180MHZ=y ++# DISABLE_CPU_CLK_240MHZ is not set ++CONFIG_BUS_SPEED_83MHZ=y ++# CONFIG_BUS_SPEED_90MHZ is not set ++# CONFIG_BUS_SPEED_100MHZ is not set ++# CONFIG_BUS_SPEED_133MHZ is not set ++ ++# ++# Memory selection ++# ++CONFIG_SDRAM=y ++# CONFIG_SDDRC is not set ++# CONFIG_DDR2 is not set ++ALLOW_DATAFLASH=y ++# ALLOW_FLASH is not set ++ALLOW_NANDFLASH=y ++# ALLOW_SDCARD is not set ++# ALLOW_PSRAM is not set ++# ALLOW_SDRAM_16BIT is not set ++# CONFIG_RAM_32MB is not set ++CONFIG_RAM_64MB=y ++# CONFIG_RAM_128MB is not set ++# CONFIG_RAM_256MB is not set ++CONFIG_DATAFLASH=y ++# CONFIG_FLASH is not set ++# CONFIG_NANDFLASH is not set ++# CONFIG_SDCARD is not set ++CONFIG_MEMORY="dataflash" ++ ++# ++# SPI configuration ++# ++CONFIG_SPI_CLK=33000000 ++# CONFIG_SPI_BOOT_CS0 is not set ++CONFIG_SPI_BOOT_CS1=y ++# DATAFLASHCARD_ON_CS0 is not set ++# DATAFLASHCARD_ON_CS1 is not set ++# DATAFLASHCARD_ON_CS2 is not set ++# DATAFLASHCARD_ON_CS3 is not set ++# CONFIG_DATAFLASHCARD is not set ++CONFIG_CARD_SUFFIX="" ++CONFIG_SPI_BOOT="AT91C_SPI_PCS1_DATAFLASH" ++CONFIG_SPI_MODE_0=y ++# CONFIG_SPI_MODE_1 is not set ++# CONFIG_SPI_MODE_2 is not set ++# CONFIG_SPI_MODE_3 is not set ++CONFIG_SPI_MODE=0 ++CONFIG_PROJECT="dataflash" ++CONFIG_LOAD_UBOOT=y ++# CONFIG_LOAD_64KB is not set ++# CONFIG_LOAD_1MB is not set ++# CONFIG_LOAD_4MB is not set ++CONFIG_IMG_ADDRESS="0x00008400" ++CONFIG_IMG_SIZE="0x00040000" ++CONFIG_JUMP_ADDR="0x23F00000" ++CONFIG_APP_CHECK=y ++# CONFIG_LONG_TEST is not set ++CONFIG_DEBUG=y ++CONFIG_HW_INIT=y ++# CONFIG_USER_HW_INIT is not set ++CONFIG_THUMB=y +diff --git a/board/afeb9260/old/afeb9260.c b/board/afeb9260/old/afeb9260.c +new file mode 100644 +index 0000000..81c0919 +--- /dev/null ++++ b/board/afeb9260/old/afeb9260.c +@@ -0,0 +1,240 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * - Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the disclaimer below in the documentation and/or ++ * other materials provided with the distribution. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : at91sam9260ek.c ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ * ODi Nov 9th : dstp #3507 "Bad PIO descriptors in at91samxxxek.c" ++ *----------------------------------------------------------------------------- ++ */ ++#include "../../include/part.h" ++#include "../../include/gpio.h" ++#include "../../include/pmc.h" ++#include "../../include/debug.h" ++#include "../../include/sdramc.h" ++#include "../../include/main.h" ++#ifdef CFG_NANDFLASH ++#include "../../include/nandflash.h" ++#endif ++#ifdef CFG_DATAFLASH ++#include "../../include/dataflash.h" ++#endif ++#ifdef CFG_FLASH ++#include "../../include/flash.h" ++#endif ++ ++/* We init NAND regardless of whatever */ ++/*------------------------------------------------------------------------------*/ ++/* \fn nandflash_hw_init */ ++/* \brief NandFlash HW init */ ++/*------------------------------------------------------------------------------*/ ++void nandflash_hw_init(void) ++{ ++ /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++ /* Configure SMC CS3 */ ++ writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3); ++ writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3); ++ writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE) , AT91C_BASE_SMC + SMC_CYCLE3); ++ writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | ++ AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF) , AT91C_BASE_SMC + SMC_CTRL3); ++ ++ /* Configure the PIO controller */ ++ writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC); ++ ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0)); ++ writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0)); ++ writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0)); ++ writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0)); ++} ++ ++ ++#ifdef CFG_HW_INIT ++/*----------------------------------------------------------------------------*/ ++/* \fn hw_init */ ++/* \brief This function performs very low level HW initialization */ ++/* This function is invoked as soon as possible during the c_startup */ ++/* The bss segment must be initialized */ ++/*----------------------------------------------------------------------------*/ ++void hw_init(void) ++{ ++ /* Disable watchdog */ ++ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); ++ ++ /* At this stage the main oscillator is supposed to be enabled ++ * PCK = MCK = MOSC */ ++ ++ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ ++ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */ ++ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure PLLB */ ++ pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); ++ ++ /* Configure the PIO controller */ ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0)); ++ writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0)); ++ ++#ifdef CFG_DEBUG ++ /* Enable Debug messages on the DBGU */ ++ dbg_init(BAUDRATE(MASTER_CLOCK, 115200)); ++ ++ dbg_print("AT91 bootstrap loading from 0x8400\n\r"); ++#endif /* CFG_DEBUG */ ++ ++#ifdef CFG_SDRAM ++ /* Initialize the matrix */ ++ writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA); ++ ++ /* Configure SDRAM Controller */ ++ ++#define HYNIX ++ ++//#define MICRON ++#ifdef MICRON ++#define MICRON_REFRESH 1420 /* 15.625 us / 11 ns @ 180 Mhz*/ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_12 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | // 1 CLK+7ns ++ AT91C_SDRAMC_TRC_7 | // 60 ns ++ AT91C_SDRAMC_TRP_3 | // 15 ns ++ AT91C_SDRAMC_TRCD_3 | // 15 ns ++ AT91C_SDRAMC_TRAS_7 | // 37-120 ns ++ AT91C_SDRAMC_TXSR_7, /* 67ns */ /* Control Register */ ++ /* 600 700 735 */ MICRON_REFRESH /* 740 1536*/ ); /* Refresh Timer Register */ ++ ++#endif ++/* ++HY57V561620BT-H ++ *CAS lat *tRCD *tRAS *tRC *tRP tAC tOH ++133 2 2 6 8 2 5.4ns 2.7ns ++125 3 3 6 9 3 6ns 3ns ++100 2 2 5 7 2 6ns 3ns ++ ++*/ ++#ifdef HYNIX ++#if defined(PLLA_180MHz) ++/* CLK= 11ns */ ++/* TWR = tDPL = 2 2CLK always */ ++/* TRC = tRC = 65ns = 6 clk */ ++/* TRP = tRP = 20ns = 2 clk */ ++/* TRCD = tRCD = 20ns = 2 clk */ ++/* TRAS = tRAS = 45ns = 5 clk */ ++/* TXSR = tRRC = 65ns = 6 clk */ ++ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_6 | /* *7 */ ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_5 | /* *5 */ ++ AT91C_SDRAMC_TXSR_6, /* *8 */ /* Control Register */ ++ 710); /* Refresh Timer Register */ ++ ++#elif defined(PLLA_120MHz) ++/* CLK= 16ns, MCLK=60MHz */ ++/* TWR = tDPL = 2 2CLK always */ ++/* TRC = tRC = 65ns = 4 clk */ ++/* TRP = tRP = 20ns = 2 clk */ ++/* TRCD = tRCD = 20ns = 2 clk */ ++/* TRAS = tRAS = 45ns = 3 clk */ ++/* TXSR = tRRC = 65ns = 4 clk */ ++ ++ sdram_init( AT91C_SDRAMC_NC_9 | ++ AT91C_SDRAMC_NR_13 | ++ AT91C_SDRAMC_CAS_2 | ++ AT91C_SDRAMC_NB_4_BANKS | ++ AT91C_SDRAMC_DBW_32_BITS | ++ AT91C_SDRAMC_TWR_2 | ++ AT91C_SDRAMC_TRC_4 | ++ AT91C_SDRAMC_TRP_2 | ++ AT91C_SDRAMC_TRCD_2 | ++ AT91C_SDRAMC_TRAS_3 | /* *5 */ ++ AT91C_SDRAMC_TXSR_4, /* *8 */ /* Control Register */ ++ 1032); /* Refresh Timer Register */ ++#else ++#error define PLLA180MHz ++#endif ++#endif /* HYNIX */ ++#endif /* CFG_SDRAM */ ++ ++#ifdef CFG_FLASH ++ flash_hw_init(); ++#endif ++ nandflash_hw_init(); ++} ++#endif /* CFG_HW_INIT */ ++ ++#ifdef CFG_SDRAM ++/*------------------------------------------------------------------------------*/ ++/* \fn sdramc_hw_init */ ++/* \brief This function performs SDRAMC HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void sdramc_hw_init(void) ++{ ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0)); ++ writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0)); ++ ++} ++#endif /* CFG_SDRAM */ ++ ++#ifdef CFG_DATAFLASH ++ ++/*------------------------------------------------------------------------------*/ ++/* \fn df_hw_init */ ++/* \brief This function performs DataFlash HW initialization */ ++/*------------------------------------------------------------------------------*/ ++void df_hw_init(void) ++{ ++ writel(0xf, 0xfffff444); ++ writel(0xf, 0xfffff460); ++ writel(0xf, 0xfffff470); ++ writel(0xf, 0xfffff404); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0)); ++ writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0)); ++} ++#endif /* CFG_DATAFLASH */ ++ +diff --git a/board/afeb9260/old/afeb9260.mk b/board/afeb9260/old/afeb9260.mk +new file mode 100644 +index 0000000..88c2f64 +--- /dev/null ++++ b/board/afeb9260/old/afeb9260.mk +@@ -0,0 +1,8 @@ ++# Target name (case sensitive!!!) ++TARGET=AFEB9260 ++# Board name (case sensitive!!!) ++BOARD=afeb9260 ++# Link Address and Top_of_Memory ++LINK_ADDR=0x200000 ++TOP_OF_MEMORY=0x301000 ++ +diff --git a/board/afeb9260/old/dataflash/afeb9260.h b/board/afeb9260/old/dataflash/afeb9260.h +new file mode 100644 +index 0000000..8e60faa +--- /dev/null ++++ b/board/afeb9260/old/dataflash/afeb9260.h +@@ -0,0 +1,127 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaiimer below. ++ * ++ * - Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the disclaimer below in the documentation and/or ++ * other materials provided with the distribution. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : at91sam9260ek.h ++ * Object : ++ * Creation : NLe Jul 13th 2006 ++ *----------------------------------------------------------------------------- ++ */ ++#ifndef _AFEB9260_H ++#define _AFEB9260_H ++#include "spi.h" ++#include "pll.h" ++ ++/* ******************************************************************* */ ++/* DataFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_BASE_SPI AT91C_BASE_SPI0 ++#define AT91C_ID_SPI AT91C_ID_SPI0 ++ ++/* SPI CLOCK */ ++#define AT91C_SPI_CLK 5000000 ++/* AC characteristics */ ++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ ++#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ ++#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ ++ ++#define DF_CS_SETTINGS ((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) ++ ++ ++/* ******************************************************************* */ ++/* BootStrap Settings */ ++/* */ ++/* ******************************************************************* */ ++#define MACH_TYPE 0x44B /* AT91SAM9260-EK */ ++ ++#define IMG_ADDRESS 0x8400 /* Image Address in DataFlash */ ++ ++#if defined(IMG_SIZE) ++#warning "IMG_SIZE redefined" ++#else ++#define IMG_SIZE 0x39000 /* Image Size in DataFlash */ ++#endif ++ ++#if defined(JUMP_ADDR) ++#warning "JUMP_ADDR redefined" ++#else ++#define JUMP_ADDR 0x21F00000 /* Final Jump Address */ ++#endif ++ ++/* ******************************************************************* */ ++/* NandFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_SMARTMEDIA_BASE 0x40000000 ++ ++#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */ ++#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */ ++ ++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0) ++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0) ++ ++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13)) ++ ++ ++/* ******************************************************************** */ ++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ ++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ ++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ ++/* to generate these values. */ ++/* ******************************************************************** */ ++ ++#define AT91C_SM_NWE_SETUP (2 << 0) ++#define AT91C_SM_NCS_WR_SETUP (2 << 8) ++#define AT91C_SM_NRD_SETUP (2 << 16) ++#define AT91C_SM_NCS_RD_SETUP (2 << 24) ++ ++#define AT91C_SM_NWE_PULSE (4 << 0) ++#define AT91C_SM_NCS_WR_PULSE (4 << 8) ++#define AT91C_SM_NRD_PULSE (4 << 16) ++#define AT91C_SM_NCS_RD_PULSE (4 << 24) ++ ++#define AT91C_SM_NWE_CYCLE (8 << 0) ++#define AT91C_SM_NRD_CYCLE (8 << 16) ++ ++#define AT91C_SM_TDF (2 << 16) ++ ++ ++ ++/* ******************************************************************* */ ++/* Application Settings */ ++/* ******************************************************************* */ ++#define CFG_DEBUG ++#define CFG_DATAFLASH ++#define CFG_SDRAM ++#define CFG_HW_INIT ++ ++ ++#endif /* _AT91SAM9260EK_H */ +diff --git a/board/afeb9260/old/nandflash/afeb9260ek.h b/board/afeb9260/old/nandflash/afeb9260ek.h +new file mode 100644 +index 0000000..752ae0a +--- /dev/null ++++ b/board/afeb9260/old/nandflash/afeb9260ek.h +@@ -0,0 +1,151 @@ ++/* ---------------------------------------------------------------------------- ++ * ATMEL Microcontroller Software Support - ROUSSET - ++ * ---------------------------------------------------------------------------- ++ * Copyright (c) 2006, Atmel Corporation ++ ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * - Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the disclaimer below. ++ * ++ * - Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the disclaimer below in the documentation and/or ++ * other materials provided with the distribution. ++ * ++ * Atmel's name may not be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE ++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, ++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ---------------------------------------------------------------------------- ++ * File Name : at91sam9260ek.h ++ * Object : ++ * Creation : NLe Sep 28th 2006 ++ *----------------------------------------------------------------------------- ++ */ ++#ifndef _AFEB9260_H ++#define _AFEB9260_H ++#include "spi.h" ++#include "pll.h" ++ ++/* ******************************************************************* */ ++/* DataFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_BASE_SPI AT91C_BASE_SPI0 ++#define AT91C_ID_SPI AT91C_ID_SPI0 ++ ++/* SPI CLOCK */ ++#define AT91C_SPI_CLK 5000000 ++/* AC characteristics */ ++/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ ++#define DATAFLASH_TCSS (0x1a << 16) /* 250ns min (tCSS) <=> 12/48000000 = 250ns */ ++#define DATAFLASH_TCHS (0x1 << 24) /* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */ ++ ++#define DF_CS_SETTINGS ((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8)) ++ ++ ++/* ******************************************************************* */ ++/* NandFlash Settings */ ++/* */ ++/* ******************************************************************* */ ++#define AT91C_SMARTMEDIA_BASE 0x40000000 ++ ++#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */ ++#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */ ++ ++#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0) ++#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0) ++ ++#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13)) ++ ++ ++/* ******************************************************************** */ ++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ ++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ ++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ ++/* to generate these values. */ ++/* ******************************************************************** */ ++ ++#define AT91C_SM_NWE_SETUP (2 << 0) ++#define AT91C_SM_NCS_WR_SETUP (2 << 8) ++#define AT91C_SM_NRD_SETUP (2 << 16) ++#define AT91C_SM_NCS_RD_SETUP (2 << 24) ++ ++#define AT91C_SM_NWE_PULSE (4 << 0) ++#define AT91C_SM_NCS_WR_PULSE (4 << 8) ++#define AT91C_SM_NRD_PULSE (4 << 16) ++#define AT91C_SM_NCS_RD_PULSE (4 << 24) ++ ++#define AT91C_SM_NWE_CYCLE (8 << 0) ++#define AT91C_SM_NRD_CYCLE (8 << 16) ++ ++#define AT91C_SM_TDF (2 << 16) ++ ++ ++/* ******************************************************************** */ ++/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/ ++/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000. */ ++/* Please refer to SMC section in AT91SAM9261 datasheet to learn how */ ++/* to generate these values. */ ++/* ******************************************************************** */ ++/*#define AT91C_SM_NWE_SETUP (0 << 0) ++#define AT91C_SM_NCS_WR_SETUP (0 << 8) ++#define AT91C_SM_NRD_SETUP (0 << 16) ++#define AT91C_SM_NCS_RD_SETUP (0 << 24) ++ ++#define AT91C_SM_NWE_PULSE (2 << 0) ++#define AT91C_SM_NCS_WR_PULSE (3 << 8) ++#define AT91C_SM_NRD_PULSE (2 << 16) ++#define AT91C_SM_NCS_RD_PULSE (3 << 24) ++ ++#define AT91C_SM_NWE_CYCLE (3 << 0) ++#define AT91C_SM_NRD_CYCLE (3 << 16) ++ ++#define AT91C_SM_TDF (1 << 16) ++*/ ++ ++/* ******************************************************************* */ ++/* BootStrap Settings */ ++/* */ ++/* ******************************************************************* */ ++#define MACH_TYPE 0x44B /* AT91SAM9260-EK */ ++ ++#define IMG_ADDRESS 0x20000 /* Image Address in NandFlash */ ++ ++#if defined(IMG_SIZE) ++#warning "IMG_SIZE redefined" ++#else ++#define IMG_SIZE 0x30000 /* Image Size in NandFlash */ ++#endif ++ ++#if defined(JUMP_ADDR) ++#warning "JUMP_ADDR redefined" ++#else ++#define JUMP_ADDR 0x23F00000 /* Final Jump Address */ ++#endif ++ ++/* ******************************************************************* */ ++/* Application Settings */ ++/* ******************************************************************* */ ++#define CFG_DEBUG ++#undef CFG_DATAFLASH ++ ++#define CFG_NANDFLASH ++#undef NANDFLASH_SMALL_BLOCKS /* NANDFLASH_LARGE_BLOCKS used instead */ ++ ++#define CFG_HW_INIT ++#define CFG_SDRAM ++ ++#endif /* _AT91SAM9260EK_H */ +diff --git a/board/afeb9260/old/pll.h b/board/afeb9260/old/pll.h +new file mode 100644 +index 0000000..6d20299 +--- /dev/null ++++ b/board/afeb9260/old/pll.h +@@ -0,0 +1,35 @@ ++/* ******************************************************************* */ ++/* PMC Settings */ ++/* */ ++/* The main oscillator is enabled as soon as possible in the c_startup */ ++/* and MCK is switched on the main oscillator. */ ++/* PLL initialization is done later in the hw_init() function */ ++/* ******************************************************************* */ ++#define PLL_LOCK_TIMEOUT 1000000 ++ ++#define PLLA_180MHz ++ ++#ifdef PLLA_200MHz ++#define PLLA_SETTINGS 0x2060BF09 ++#define MASTER_CLOCK (198656000/2) ++#endif ++ ++#ifdef PLLA_180MHz ++#define PLLA_SETTINGS 0x2125BF1E /* 180MHz */ ++#define MASTER_CLOCK (179999198/2) /* 180MHz MCK=90MHz */ ++#endif ++ ++#ifdef PLLA_120MHz ++//#define PLLA_SETTINGS 0x2125BF2d /* 120MHz */ ++/