From 022c55ed2377493c8774165d0fb2c124b91c3cc1 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Tue, 11 Nov 2008 16:06:06 +0100 Subject: linux-omap git: update DSS2 patches and attempt to fix ASoC --- ...cumentation-for-OMAP2-3-display-subsystem.patch | 6 +- ...-New-display-subsystem-driver-for-OMAP2-3.patch | 6255 +++++++++++++++++--- ...MAPFB-fb-driver-for-new-display-subsystem.patch | 2850 +++++++++ .../0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch | 1254 ---- .../0006-DSS-Add-generic-DVI-panel.patch | 219 + .../0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch | 519 -- .../0007-DSS-DSI-support-for-OMAP2-3-DSS.patch | 3047 ---------- .../0007-DSS-support-for-Beagle-Board.patch | 184 + ...DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch | 453 ++ ...MAPFB-fb-driver-for-new-display-subsystem.patch | 2821 --------- .../0009-DSS-Add-generic-DVI-panel.patch | 189 - .../0009-DSS-support-for-OMAP3-SDP-board.patch | 441 ++ .../0010-DSS-support-for-Beagle-Board.patch | 182 - .../0011-DSS-support-for-OMAP3-SDP-board.patch | 441 -- packages/linux/linux-omap/beagleboard/defconfig | 10 +- packages/linux/linux-omap/fix-asoc.diff | 130 + packages/linux/linux-omap_git.bb | 16 +- 17 files changed, 9862 insertions(+), 9155 deletions(-) create mode 100644 packages/linux/linux-omap/0005-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch delete mode 100644 packages/linux/linux-omap/0005-DSS-RFBI-support-for-OMAP2-3-DSS.patch create mode 100644 packages/linux/linux-omap/0006-DSS-Add-generic-DVI-panel.patch delete mode 100644 packages/linux/linux-omap/0006-DSS-TV-out-support-for-OMAP2-3-DSS.patch delete mode 100644 packages/linux/linux-omap/0007-DSS-DSI-support-for-OMAP2-3-DSS.patch create mode 100644 packages/linux/linux-omap/0007-DSS-support-for-Beagle-Board.patch create mode 100644 packages/linux/linux-omap/0008-DSS-BEAGLE-Enable-DSS-in-beagle-defconfig.patch delete mode 100644 packages/linux/linux-omap/0008-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch delete mode 100644 packages/linux/linux-omap/0009-DSS-Add-generic-DVI-panel.patch create mode 100644 packages/linux/linux-omap/0009-DSS-support-for-OMAP3-SDP-board.patch delete mode 100644 packages/linux/linux-omap/0010-DSS-support-for-Beagle-Board.patch delete mode 100644 packages/linux/linux-omap/0011-DSS-support-for-OMAP3-SDP-board.patch create mode 100644 packages/linux/linux-omap/fix-asoc.diff diff --git a/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch b/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch index 59c15cee7d..4946bda5e7 100644 --- a/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch +++ b/packages/linux/linux-omap/0003-DSS-Documentation-for-OMAP2-3-display-subsystem.patch @@ -1,4 +1,4 @@ -From 7a7fe8f7530bf5c7f3714acbe9a5ec8cf80c3d0c Mon Sep 17 00:00:00 2001 +From 58be9dfad433036ff46ed883c3bc77fca88079f7 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Tue, 4 Nov 2008 15:08:07 +0200 Subject: [PATCH] DSS: Documentation for OMAP2/3 display subsystem @@ -11,7 +11,7 @@ Signed-off-by: Tomi Valkeinen diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS new file mode 100644 -index 0000000..b0cc980 +index 0000000..387bb73 --- /dev/null +++ b/Documentation/arm/OMAP/DSS @@ -0,0 +1,239 @@ @@ -41,7 +41,7 @@ index 0000000..b0cc980 +- Use CPU to update RFBI or DSI output +- OMAP DISPC planes +- RGB16, RGB24 packed, RGB24 unpacked -+- YUV2, UYVY ++- YUV2, UYVY +- Scaling +- Adjusting DSS FCK to find a good pixel clock +- Use DSI DPLL to create DSS FCK diff --git a/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch b/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch index febfc48c4d..509f34697a 100644 --- a/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch +++ b/packages/linux/linux-omap/0004-DSS-New-display-subsystem-driver-for-OMAP2-3.patch @@ -1,32 +1,36 @@ -From 0cd726d12358cfe8d80fc0a309bb0c0732c716f0 Mon Sep 17 00:00:00 2001 +From 5a4331bf757fdec0ceb72bf40f7e46ce5c404e2d Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen -Date: Tue, 4 Nov 2008 16:52:12 +0200 +Date: Tue, 11 Nov 2008 13:52:25 +0200 Subject: [PATCH] DSS: New display subsystem driver for OMAP2/3 -DSI, RFBI and VENC are separate patches - Signed-off-by: Tomi Valkeinen --- arch/arm/plat-omap/Kconfig | 2 + arch/arm/plat-omap/Makefile | 2 + - arch/arm/plat-omap/dss/Kconfig | 66 ++ + arch/arm/plat-omap/dss/Kconfig | 66 + arch/arm/plat-omap/dss/Makefile | 6 + - arch/arm/plat-omap/dss/dispc.c | 1667 +++++++++++++++++++++++++++++ - arch/arm/plat-omap/dss/display.c | 781 ++++++++++++++ - arch/arm/plat-omap/dss/dpi.c | 303 ++++++ - arch/arm/plat-omap/dss/dss.c | 547 ++++++++++ - arch/arm/plat-omap/dss/dss.h | 240 +++++ - arch/arm/plat-omap/dss/sdi.c | 154 +++ - arch/arm/plat-omap/include/mach/display.h | 458 ++++++++ - 11 files changed, 4226 insertions(+), 0 deletions(-) + arch/arm/plat-omap/dss/dispc.c | 1720 ++++++++++++++++ + arch/arm/plat-omap/dss/display.c | 775 ++++++++ + arch/arm/plat-omap/dss/dpi.c | 323 +++ + arch/arm/plat-omap/dss/dsi.c | 3022 +++++++++++++++++++++++++++++ + arch/arm/plat-omap/dss/dss.c | 547 ++++++ + arch/arm/plat-omap/dss/dss.h | 254 +++ + arch/arm/plat-omap/dss/rfbi.c | 1234 ++++++++++++ + arch/arm/plat-omap/dss/sdi.c | 157 ++ + arch/arm/plat-omap/dss/venc.c | 515 +++++ + arch/arm/plat-omap/include/mach/display.h | 458 +++++ + 14 files changed, 9081 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-omap/dss/Kconfig create mode 100644 arch/arm/plat-omap/dss/Makefile create mode 100644 arch/arm/plat-omap/dss/dispc.c create mode 100644 arch/arm/plat-omap/dss/display.c create mode 100644 arch/arm/plat-omap/dss/dpi.c + create mode 100644 arch/arm/plat-omap/dss/dsi.c create mode 100644 arch/arm/plat-omap/dss/dss.c create mode 100644 arch/arm/plat-omap/dss/dss.h + create mode 100644 arch/arm/plat-omap/dss/rfbi.c create mode 100644 arch/arm/plat-omap/dss/sdi.c + create mode 100644 arch/arm/plat-omap/dss/venc.c create mode 100644 arch/arm/plat-omap/include/mach/display.h diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig @@ -54,7 +58,7 @@ index 1259846..2740497 100644 +obj-y += dss/ diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig new file mode 100644 -index 0000000..150cd24 +index 0000000..ef0b5d9 --- /dev/null +++ b/arch/arm/plat-omap/dss/Kconfig @@ -0,0 +1,66 @@ @@ -107,8 +111,8 @@ index 0000000..150cd24 + +config OMAP2_DSS_MIN_FCK_PER_PCK + int "Minimum FCK/PCK ratio (for scaling)" -+ range 1 32 -+ default 4 ++ range 0 32 ++ default 0 + help + This can be used to adjust the minimum FCK/PCK ratio. + @@ -116,7 +120,7 @@ index 0000000..150cd24 + n x PCK. Video plane scaling requires higher FCK than + normally. + -+ If this is set to 1, there's no extra constraint on the ++ If this is set to 0, there's no extra constraint on the + DISPC FCK. However, the FCK will at minimum be + 2xPCK (if active matrix) or 3xPCK (if passive matrix). + @@ -138,10 +142,10 @@ index 0000000..e98c6c1 +omap-dss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o diff --git a/arch/arm/plat-omap/dss/dispc.c b/arch/arm/plat-omap/dss/dispc.c new file mode 100644 -index 0000000..8f5da2d +index 0000000..6d06082 --- /dev/null +++ b/arch/arm/plat-omap/dss/dispc.c -@@ -0,0 +1,1667 @@ +@@ -0,0 +1,1720 @@ +/* + * linux/arch/arm/plat-omap/dss/dispc.c + * @@ -255,8 +259,8 @@ index 0000000..8f5da2d + DISPC_IRQ_OCP_ERR | \ + DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ + DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_SYNC_LOST) -+/*DISPC_IRQ_SYNC_LOST_DIGIT*/ ++ DISPC_IRQ_SYNC_LOST | \ ++ DISPC_IRQ_SYNC_LOST_DIGIT) + +#define DISPC_MAX_NR_ISRS 8 + @@ -1240,91 +1244,135 @@ index 0000000..8f5da2d + panel->acbi, panel->acb); +} + -+unsigned long dispc_calc_clock_div(int is_tft, int pck, int *fck_div, ++void find_lck_pck_divs(int is_tft, unsigned long req_pck, unsigned long fck, + int *lck_div, int *pck_div) +{ -+ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); -+ unsigned long pcd_min = is_tft ? 2 : 3; -+ unsigned long best_pck = 0; -+ int best_fd = 9, best_ld = 1, best_pd = 2; -+ int fd, ld, pd; ++ int pcd_min = is_tft ? 2 : 3; ++ unsigned long best_pck; ++ int best_ld, cur_ld; ++ int best_pd, cur_pd; + -+ for (fd = 16; fd > 0; --fd) { -+ unsigned long fck = prate / fd * 2; -+ -+ if (fck > DISPC_MAX_FCK) -+ continue; ++ best_pck = 0; ++ best_ld = 0; ++ best_pd = 0; + -+#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK -+ if (fck < pck * CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK) -+ continue; -+#endif -+ for (ld = 1; ld <= 255; ++ld) { -+ unsigned long lck = fck / ld; ++ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { ++ unsigned long lck = fck / cur_ld; + -+ for (pd = pcd_min; pd <= 255; ++pd) { -+ int p = lck / pd; ++ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) { ++ unsigned long pck = lck / cur_pd; + -+ if (abs(p - pck) < abs(best_pck - pck)) { -+ best_pck = p; -+ best_fd = fd; -+ best_ld = ld; -+ best_pd = pd; -+ } ++ if (abs(pck - req_pck) < abs(best_pck - req_pck)) { ++ best_pck = pck; ++ best_ld = cur_ld; ++ best_pd = cur_pd; + -+ if (p == pck) ++ if (pck == req_pck) + goto found; -+ -+ if (p < pck) -+ break; + } + -+ if (lck / pcd_min < pck) ++ if (pck < req_pck) + break; + } ++ ++ if (lck / pcd_min < req_pck) ++ break; + } + +found: -+ *fck_div = best_fd; + *lck_div = best_ld; + *pck_div = best_pd; -+ -+ return prate / best_fd * 2; +} + -+void dispc_set_clock_div(int fck_div, int lck_div, int pck_div) ++int dispc_calc_clock_div(int is_tft, unsigned long req_pck, ++ struct dispc_clock_info *cinfo) +{ -+ unsigned long prate; ++ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); ++ struct dispc_clock_info cur, best; ++ int match = 0; ++ int min_fck_per_pck; ++ ++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; ++ ++ if (min_fck_per_pck && ++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) { ++ DSSERR("Requested pixel clock not possible with the current " ++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " ++ "the constraint off.\n"); ++ min_fck_per_pck = 0; ++ } + -+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); ++retry: ++ memset(&cur, 0, sizeof(cur)); ++ memset(&best, 0, sizeof(best)); + -+ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div); -+ dispc_set_lcd_divisor(lck_div, pck_div); ++ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) { ++ cur.fck = prate / cur.fck_div * 2; + -+#ifdef DEBUG -+ { -+ unsigned long fck, lck, pck; -+ fck = prate / fck_div * 2; -+ lck = fck / lck_div; -+ pck = lck / pck_div; ++ if (cur.fck > DISPC_MAX_FCK) ++ continue; ++ ++ if (min_fck_per_pck && ++ cur.fck < req_pck * min_fck_per_pck) ++ continue; ++ ++ match = 1; ++ ++ find_lck_pck_divs(is_tft, req_pck, cur.fck, ++ &cur.lck_div, &cur.pck_div); ++ ++ cur.lck = cur.fck / cur.lck_div; ++ cur.pck = cur.lck / cur.pck_div; + -+ DSSDBG("dpll4_m4 = %ld\n", prate); -+ DSSDBG("fck = %ld (%d)\n", fck, fck_div); -+ DSSDBG("lck = %ld (%d)\n", lck, lck_div); -+ DSSDBG("pck = %ld (%d)\n", pck, pck_div); ++ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) { ++ best = cur; ++ ++ if (cur.pck == req_pck) ++ goto found; ++ } + } -+#endif ++ ++found: ++ if (!match) { ++ if (min_fck_per_pck) { ++ DSSERR("Could not find suitable clock settings.\n" ++ "Turning FCK/PCK constraint off and" ++ "trying again.\n"); ++ min_fck_per_pck = 0; ++ goto retry; ++ } ++ ++ DSSERR("Could not find suitable clock settings.\n"); ++ ++ return -EINVAL; ++ } ++ ++ if (cinfo) ++ *cinfo = best; ++ ++ return 0; +} + -+int dispc_pixel_clock_valid(int pixel_clock) ++int dispc_set_clock_div(struct dispc_clock_info *cinfo) +{ -+ int fck_div, lck_div, pck_div; -+ unsigned long fck; ++ unsigned long prate; ++ int r; + -+ fck = dispc_calc_clock_div(1, pixel_clock * 1000, -+ &fck_div, &lck_div, &pck_div); ++ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); ++ ++ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div); ++ ++ if (r) ++ return r; ++ ++ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div); + -+ return fck > 0; ++ DSSDBG("dpll4_m4 = %ld\n", prate); ++ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); ++ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div); ++ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div); ++ ++ return 0; +} + +int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) @@ -1431,8 +1479,23 @@ index 0000000..8f5da2d + int i; + u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS); + static int errors; ++ u32 handledirqs = 0; + -+ if (irqstatus & DISPC_IRQ_MASK_ERROR) { ++#ifdef DEBUG ++ print_irq_status(irqstatus); ++#endif ++ ++ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { ++ if (!registered_isr[i].isr) ++ continue; ++ if (registered_isr[i].mask & irqstatus) { ++ registered_isr[i].isr(registered_isr[i].arg, ++ irqstatus); ++ handledirqs |= registered_isr[i].mask; ++ } ++ } ++ ++ if (irqstatus & ~handledirqs & DISPC_IRQ_MASK_ERROR) { + if (printk_ratelimit()) { + DSSERR("dispc irq error status %04x\n", + irqstatus); @@ -1444,17 +1507,6 @@ index 0000000..8f5da2d + dispc_enable_digit_out(0); + } + } -+#ifdef DEBUG -+ print_irq_status(irqstatus); -+#endif -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ if (!registered_isr[i].isr) -+ continue; -+ if (registered_isr[i].mask & irqstatus) -+ registered_isr[i].isr(registered_isr[i].arg, -+ irqstatus); -+ } + + /* ack the interrupt */ + dispc_write_reg(DISPC_IRQSTATUS, irqstatus); @@ -1480,6 +1532,11 @@ index 0000000..8f5da2d +{ + memset(registered_isr, 0, sizeof(registered_isr)); + ++ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, ++ * so clear it */ ++ dispc_write_reg(DISPC_IRQSTATUS, ++ dispc_read_reg(DISPC_IRQSTATUS)); ++ + /* We'll handle these always */ + dispc_write_reg(DISPC_IRQENABLE, DISPC_IRQ_MASK_ERROR); +} @@ -1811,10 +1868,10 @@ index 0000000..8f5da2d + diff --git a/arch/arm/plat-omap/dss/display.c b/arch/arm/plat-omap/dss/display.c new file mode 100644 -index 0000000..86f7d39 +index 0000000..4d7238f --- /dev/null +++ b/arch/arm/plat-omap/dss/display.c -@@ -0,0 +1,781 @@ +@@ -0,0 +1,775 @@ +/* + * linux/arch/arm/plat-omap/dss/display.c + * @@ -1843,7 +1900,6 @@ index 0000000..86f7d39 +#include +#include +#include -+#include +#include +#include + @@ -2230,11 +2286,6 @@ index 0000000..86f7d39 + dispc_enable_plane(ovl->id, 1); + } + -+ /* XXX if autoidle is enabled, we have to wait here a bit. -+ * Otherwise if we issue GOLCD too soon after lcd enable, -+ * we get sync lost. Why? */ -+ mdelay(100); -+ + dispc_go(mgr->id); + + return 0; @@ -2598,10 +2649,10 @@ index 0000000..86f7d39 +EXPORT_SYMBOL(omap_dss_unregister_panel); diff --git a/arch/arm/plat-omap/dss/dpi.c b/arch/arm/plat-omap/dss/dpi.c new file mode 100644 -index 0000000..d121b52 +index 0000000..2261288 --- /dev/null +++ b/arch/arm/plat-omap/dss/dpi.c -@@ -0,0 +1,303 @@ +@@ -0,0 +1,323 @@ +/* + * linux/arch/arm/plat-omap/dss/dpi.c + * @@ -2674,23 +2725,32 @@ index 0000000..d121b52 + } +#else + { -+ int fck_div; -+ fck = dispc_calc_clock_div(is_tft, -+ panel->timings.pixel_clock*1000, -+ &fck_div, &lck_div, &pck_div); ++ struct dispc_clock_info cinfo; ++ dispc_calc_clock_div(is_tft, panel->timings.pixel_clock*1000, ++ &cinfo); + -+ if (fck == 0) { -+ DSSERR("Requested pixel clock is not possible\n"); ++ if (dispc_set_clock_div(&cinfo)) { ++ DSSERR("Failed to set DSS clocks\n"); + return; + } + -+ dispc_set_clock_div(fck_div, lck_div, pck_div); ++ fck = cinfo.fck; ++ lck_div = cinfo.lck_div; ++ pck_div = cinfo.pck_div; + } +#endif + + pck = fck / lck_div / pck_div / 1000; + -+ panel->timings.pixel_clock = pck; ++ if (pck != panel->timings.pixel_clock) { ++ DSSWARN("Could not find exact pixel clock. Requested %d KHz, " ++ "got %lu KHz.\n", ++ panel->timings.pixel_clock, ++ pck); ++ ++ panel->timings.pixel_clock = pck; ++ } ++ + DSSDBG("fck %lu, lck_div %d, pck_div %d\n", fck, lck_div, pck_div); +#ifdef DEBUG + { @@ -2830,6 +2890,9 @@ index 0000000..d121b52 +static int dpi_check_timings(struct omap_display *display, + struct omap_video_timings *timings) +{ ++ int is_tft; ++ int r; ++ + if (timings->hsw < 1 || timings->hsw > 64 || + timings->hfp < 1 || timings->hfp > 256 || + timings->hbp < 1 || timings->hbp > 256) { @@ -2841,8 +2904,16 @@ index 0000000..d121b52 + return -EINVAL; + } + -+ if (!dispc_pixel_clock_valid(timings->pixel_clock)) -+ return -EINVAL; ++ ++ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0; ++ ++#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL ++ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000, 0); ++#else ++ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000, 0); ++#endif ++ if (r) ++ return r; + + return 0; +} @@ -2905,21 +2976,18 @@ index 0000000..d121b52 +{ +} + -diff --git a/arch/arm/plat-omap/dss/dss.c b/arch/arm/plat-omap/dss/dss.c +diff --git a/arch/arm/plat-omap/dss/dsi.c b/arch/arm/plat-omap/dss/dsi.c new file mode 100644 -index 0000000..da0364b +index 0000000..980be39 --- /dev/null -+++ b/arch/arm/plat-omap/dss/dss.c -@@ -0,0 +1,547 @@ ++++ b/arch/arm/plat-omap/dss/dsi.c +@@ -0,0 +1,3022 @@ +/* -+ * linux/arch/arm/plat-omap/dss/dss.c ++ * linux/arch/arm/plat-omap/dss/dsi.c + * + * Copyright (C) 2008 Nokia Corporation + * Author: Tomi Valkeinen + * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. @@ -2933,783 +3001,5068 @@ index 0000000..da0364b + * this program. If not, see . + */ + -+#define DSS_SUBSYS_NAME "DSS" ++#define DSS_SUBSYS_NAME "DSI" + +#include -+#include +#include +#include ++#include +#include -+#include +#include -+#include ++#include ++#include ++#include + ++#include +#include -+#include -+#include "dss.h" -+ -+#define DSS_BASE 0x48050000 + -+struct dss_reg { -+ u16 idx; -+}; ++#include "dss.h" + -+#define DSS_REG(idx) ((const struct dss_reg) { idx }) ++/*#define VERBOSE*/ ++/*#define VERBOSE_IRQ*/ ++/*#define MEASURE_PERF*/ ++ ++#define DSI_BASE 0x4804FC00 ++ ++struct dsi_reg { u16 idx; }; ++ ++#define DSI_REG(idx) ((const struct dsi_reg) { idx }) ++ ++/* DSI Protocol Engine */ ++ ++#define DSI_REVISION DSI_REG(0x0000) ++#define DSI_SYSCONFIG DSI_REG(0x0010) ++#define DSI_SYSSTATUS DSI_REG(0x0014) ++#define DSI_IRQSTATUS DSI_REG(0x0018) ++#define DSI_IRQENABLE DSI_REG(0x001C) ++#define DSI_CTRL DSI_REG(0x0040) ++#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) ++#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) ++#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) ++#define DSI_CLK_CTRL DSI_REG(0x0054) ++#define DSI_TIMING1 DSI_REG(0x0058) ++#define DSI_TIMING2 DSI_REG(0x005C) ++#define DSI_VM_TIMING1 DSI_REG(0x0060) ++#define DSI_VM_TIMING2 DSI_REG(0x0064) ++#define DSI_VM_TIMING3 DSI_REG(0x0068) ++#define DSI_CLK_TIMING DSI_REG(0x006C) ++#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) ++#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) ++#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) ++#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) ++#define DSI_VM_TIMING4 DSI_REG(0x0080) ++#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) ++#define DSI_VM_TIMING5 DSI_REG(0x0088) ++#define DSI_VM_TIMING6 DSI_REG(0x008C) ++#define DSI_VM_TIMING7 DSI_REG(0x0090) ++#define DSI_STOPCLK_TIMING DSI_REG(0x0094) ++#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) ++#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) ++#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) ++#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) ++#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) ++#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) ++#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) ++ ++/* DSIPHY_SCP */ ++ ++#define DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) ++#define DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) ++#define DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) ++#define DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) ++ ++/* DSI_PLL_CTRL_SCP */ ++ ++#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) ++#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) ++#define DSI_PLL_GO DSI_REG(0x300 + 0x0008) ++#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) ++#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) + -+#define DSS_REVISION DSS_REG(0x0000) -+#define DSS_SYSCONFIG DSS_REG(0x0010) -+#define DSS_SYSSTATUS DSS_REG(0x0014) -+#define DSS_IRQSTATUS DSS_REG(0x0018) -+#define DSS_CONTROL DSS_REG(0x0040) -+#define DSS_SDI_CONTROL DSS_REG(0x0044) -+#define DSS_PLL_CONTROL DSS_REG(0x0048) -+#define DSS_SDI_STATUS DSS_REG(0x005C) ++#define REG_GET(idx, start, end) \ ++ FLD_GET(dsi_read_reg(idx), start, end) + +#define REG_FLD_MOD(idx, val, start, end) \ -+ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) ++ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) ++ ++/* Global interrupts */ ++#define DSI_IRQ_VC0 (1 << 0) ++#define DSI_IRQ_VC1 (1 << 1) ++#define DSI_IRQ_VC2 (1 << 2) ++#define DSI_IRQ_VC3 (1 << 3) ++#define DSI_IRQ_WAKEUP (1 << 4) ++#define DSI_IRQ_RESYNC (1 << 5) ++#define DSI_IRQ_PLL_LOCK (1 << 7) ++#define DSI_IRQ_PLL_UNLOCK (1 << 8) ++#define DSI_IRQ_PLL_RECALL (1 << 9) ++#define DSI_IRQ_COMPLEXIO_ERR (1 << 10) ++#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) ++#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) ++#define DSI_IRQ_TE_TRIGGER (1 << 16) ++#define DSI_IRQ_ACK_TRIGGER (1 << 17) ++#define DSI_IRQ_SYNC_LOST (1 << 18) ++#define DSI_IRQ_LDO_POWER_GOOD (1 << 19) ++#define DSI_IRQ_TA_TIMEOUT (1 << 20) ++#define DSI_IRQ_ERROR_MASK \ ++ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ ++ DSI_IRQ_TA_TIMEOUT) ++#define DSI_IRQ_CHANNEL_MASK 0xf ++ ++/* Virtual channel interrupts */ ++#define DSI_VC_IRQ_CS (1 << 0) ++#define DSI_VC_IRQ_ECC_CORR (1 << 1) ++#define DSI_VC_IRQ_PACKET_SENT (1 << 2) ++#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) ++#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) ++#define DSI_VC_IRQ_BTA (1 << 5) ++#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) ++#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) ++#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) ++#define DSI_VC_IRQ_ERROR_MASK \ ++ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ ++ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ ++ DSI_VC_IRQ_FIFO_TX_UDF) ++ ++/* ComplexIO interrupts */ ++#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) ++#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) ++#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) ++#define DSI_CIO_IRQ_ERRESC1 (1 << 5) ++#define DSI_CIO_IRQ_ERRESC2 (1 << 6) ++#define DSI_CIO_IRQ_ERRESC3 (1 << 7) ++#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) ++#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) ++#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) ++#define DSI_CIO_IRQ_STATEULPS1 (1 << 15) ++#define DSI_CIO_IRQ_STATEULPS2 (1 << 16) ++#define DSI_CIO_IRQ_STATEULPS3 (1 << 17) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) ++#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) ++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) ++#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) ++ ++#define DSI_DT_DCS_SHORT_WRITE_0 0x05 ++#define DSI_DT_DCS_SHORT_WRITE_1 0x15 ++#define DSI_DT_DCS_READ 0x06 ++#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 ++#define DSI_DT_NULL_PACKET 0x09 ++#define DSI_DT_DCS_LONG_WRITE 0x39 ++ ++#define DSI_DT_RX_ACK_WITH_ERR 0x02 ++#define DSI_DT_RX_DCS_LONG_READ 0x1c ++#define DSI_DT_RX_SHORT_READ_1 0x21 ++#define DSI_DT_RX_SHORT_READ_2 0x22 ++ ++#define FINT_MAX 2100000 ++#define FINT_MIN 750000 ++#define REGN_MAX (1 << 7) ++#define REGM_MAX ((1 << 11) - 1) ++#define REGM3_MAX (1 << 4) ++#define REGM4_MAX (1 << 4) ++ ++enum fifo_size { ++ DSI_FIFO_SIZE_0 = 0, ++ DSI_FIFO_SIZE_32 = 1, ++ DSI_FIFO_SIZE_64 = 2, ++ DSI_FIFO_SIZE_96 = 3, ++ DSI_FIFO_SIZE_128 = 4, ++}; + -+static struct { -+ void __iomem *base; ++static struct ++{ ++ void __iomem *base; + -+ struct clk *dss_ick; ++ struct clk *dss_ick; + struct clk *dss1_fck; + struct clk *dss2_fck; -+ struct clk *dss_54m_fck; -+ struct clk *dss_96m_fck; -+} dss; -+ -+static inline void dss_write_reg(const struct dss_reg idx, u32 val) -+{ -+ __raw_writel(val, dss.base + idx.idx); -+} -+ -+static inline u32 dss_read_reg(const struct dss_reg idx) -+{ -+ return __raw_readl(dss.base + idx.idx); -+} + -+void dss_sdi_init(int datapairs) -+{ -+ u32 l; -+ -+ BUG_ON(datapairs > 3 || datapairs < 1); ++ unsigned long dsi1_pll_fclk; /* Hz */ ++ unsigned long dsi2_pll_fclk; /* Hz */ ++ unsigned long dsiphy; /* Hz */ ++ unsigned long ddr_clk; /* Hz */ + -+ l = dss_read_reg(DSS_SDI_CONTROL); -+ l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ -+ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ -+ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ -+ dss_write_reg(DSS_SDI_CONTROL, l); ++ struct { ++ enum fifo_size fifo_size; ++ int dest_per; /* destination peripheral 0-3 */ ++ } vc[4]; + -+ l = dss_read_reg(DSS_PLL_CONTROL); -+ l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ -+ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ -+ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ -+ dss_write_reg(DSS_PLL_CONTROL, l); ++ struct mutex lock; + -+ /* Reset SDI PLL */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ -+ udelay(1); /* wait 2x PCLK */ ++ struct completion bta_completion; + -+ /* Lock SDI PLL */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ ++ spinlock_t update_lock; ++ int update_ongoing; ++ int update_syncers; ++ struct completion update_completion; ++ struct work_struct framedone_work; + -+ /* Waiting for PLL lock request to complete */ -+ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) -+ ; ++ enum omap_dss_update_mode update_mode; ++ int use_te; ++ int framedone_scheduled; /* helps to catch strange framedone bugs */ + -+ /* Clearing PLL_GO bit */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); ++ struct { ++ struct omap_display *display; ++ int x, y, w, h; ++ int bytespp; ++ } update_region; + -+ /* Waiting for PLL to lock */ -+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) -+ ; ++#ifdef MEASURE_PERF ++ ktime_t measure_time; ++ int measure_frames; ++#endif ++} dsi; + -+ dispc_lcd_enable_signal(1); + -+ /* Waiting for SDI reset to complete */ -+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) -+ ; ++static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) ++{ ++ __raw_writel(val, dsi.base + idx.idx); +} + -+static int get_dss_clocks(void) ++static inline u32 dsi_read_reg(const struct dsi_reg idx) +{ -+ const struct { -+ struct clk **clock; -+ char *omap2_name; -+ char *omap3_name; -+ } clocks[5] = { -+ { &dss.dss_ick, "dss_ick", "dss_ick" }, /* L3 & L4 ick */ -+ { &dss.dss1_fck, "dss1_fck", "dss1_alwon_fck" }, -+ { &dss.dss2_fck, "dss2_fck", "dss2_alwon_fck" }, -+ { &dss.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" }, -+ { &dss.dss_96m_fck, NULL, "dss_96m_fck" }, -+ }; ++ return __raw_readl(dsi.base + idx.idx); ++} + -+ int r = 0; -+ int i; -+ const int num_clocks = 5; ++static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, ++ int value) ++{ ++ int t = 1000; + -+ for (i = 0; i < num_clocks; i++) -+ *clocks[i].clock = NULL; ++ while (REG_GET(idx, bitnum, bitnum) != value) { ++ if (--t == 0) ++ return !value; ++ } + -+ for (i = 0; i < num_clocks; i++) { -+ struct clk *clk; -+ const char *clk_name; ++ return value; ++} + -+ clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name -+ : clocks[i].omap2_name; + -+ if (!clk_name) -+ continue; ++#ifdef MEASURE_PERF ++static void start_measuring(void) ++{ ++ dsi.measure_time = ktime_get(); ++} + -+ clk = clk_get(NULL, clk_name); ++static void end_measuring(const char *name) ++{ ++ ktime_t t; ++ u32 total_bytes; ++ u32 us; ++ const int numframes = 100; + -+ if (IS_ERR(clk)) { -+ DSSERR("can't get clock %s", clk_name); -+ r = PTR_ERR(clk); -+ goto err; -+ } ++ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED) ++ return; + -+ DSSDBG("clk %s, rate %ld\n", -+ clk_name, clk_get_rate(clk)); ++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) { ++ dsi.measure_frames++; ++ if (dsi.measure_frames < numframes) ++ return; ++ dsi.measure_frames = 0; ++ } + -+ *clocks[i].clock = clk; ++ t = ktime_get(); ++ t = ktime_sub(t, dsi.measure_time); ++ us = (u32)ktime_to_us(t); ++ if (us == 0) ++ us = 1; ++ ++ total_bytes = dsi.update_region.w * ++ dsi.update_region.h * ++ dsi.update_region.bytespp; ++ ++ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) { ++ DSSINFO("%s update: %d frames in %u us, %u frames/sec\n", ++ name, numframes, ++ us, ++ 1000*1000 / us); ++ } else { ++ DSSINFO("%s update in %u us (%u Hz), %u bytes, %u kbytes/sec\n", ++ name, ++ us, ++ 1000*1000 / us, ++ total_bytes, ++ total_bytes * 1000 / us); + } ++} ++#else ++#define start_measuring() ++#define end_measuring(x) ++#endif + -+ return 0; + -+err: -+ for (i = 0; i < num_clocks; i++) { -+ if (!IS_ERR(*clocks[i].clock)) -+ clk_put(*clocks[i].clock); -+ } + -+ return r; -+} + -+static void put_dss_clocks(void) ++static void print_irq_status(u32 status) +{ -+ if (dss.dss_96m_fck) -+ clk_put(dss.dss_96m_fck); -+ clk_put(dss.dss_54m_fck); -+ clk_put(dss.dss1_fck); -+ clk_put(dss.dss2_fck); -+ clk_put(dss.dss_ick); -+} ++#ifndef VERBOSE_IRQ ++ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) ++ return; ++#endif ++ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); + -+struct clk *get_dss_ick(void) -+{ -+ return dss.dss_ick; ++#define PIS(x) \ ++ if (status & DSI_IRQ_##x) \ ++ printk(#x " "); ++#ifdef VERBOSE_IRQ ++ PIS(VC0); ++ PIS(VC1); ++ PIS(VC2); ++ PIS(VC3); ++#endif ++ PIS(WAKEUP); ++ PIS(RESYNC); ++ PIS(PLL_LOCK); ++ PIS(PLL_UNLOCK); ++ PIS(PLL_RECALL); ++ PIS(COMPLEXIO_ERR); ++ PIS(HS_TX_TIMEOUT); ++ PIS(LP_RX_TIMEOUT); ++ PIS(TE_TRIGGER); ++ PIS(ACK_TRIGGER); ++ PIS(SYNC_LOST); ++ PIS(LDO_POWER_GOOD); ++ PIS(TA_TIMEOUT); ++#undef PIS ++ ++ printk("\n"); +} + -+struct clk *get_dss1_fck(void) ++static void print_irq_status_vc(int channel, u32 status) +{ -+ return dss.dss1_fck; -+} ++#ifndef VERBOSE_IRQ ++ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) ++ return; ++#endif ++ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); + -+struct clk *get_dss2_fck(void) -+{ -+ return dss.dss2_fck; ++#define PIS(x) \ ++ if (status & DSI_VC_IRQ_##x) \ ++ printk(#x " "); ++ PIS(CS); ++ PIS(ECC_CORR); ++#ifdef VERBOSE_IRQ ++ PIS(PACKET_SENT); ++#endif ++ PIS(FIFO_TX_OVF); ++ PIS(FIFO_RX_OVF); ++ PIS(BTA); ++ PIS(ECC_NO_CORR); ++ PIS(FIFO_TX_UDF); ++ PIS(PP_BUSY_CHANGE); ++#undef PIS ++ printk("\n"); +} + -+struct clk *get_tv_fck(void) ++static void print_irq_status_cio(u32 status) +{ -+ return dss.dss_54m_fck; ++ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); ++ ++#define PIS(x) \ ++ if (status & DSI_CIO_IRQ_##x) \ ++ printk(#x " "); ++ PIS(ERRSYNCESC1); ++ PIS(ERRSYNCESC2); ++ PIS(ERRSYNCESC3); ++ PIS(ERRESC1); ++ PIS(ERRESC2); ++ PIS(ERRESC3); ++ PIS(ERRCONTROL1); ++ PIS(ERRCONTROL2); ++ PIS(ERRCONTROL3); ++ PIS(STATEULPS1); ++ PIS(STATEULPS2); ++ PIS(STATEULPS3); ++ PIS(ERRCONTENTIONLP0_1); ++ PIS(ERRCONTENTIONLP1_1); ++ PIS(ERRCONTENTIONLP0_2); ++ PIS(ERRCONTENTIONLP1_2); ++ PIS(ERRCONTENTIONLP0_3); ++ PIS(ERRCONTENTIONLP1_3); ++ PIS(ULPSACTIVENOT_ALL0); ++ PIS(ULPSACTIVENOT_ALL1); ++#undef PIS ++ ++ printk("\n"); +} + -+struct clk *get_96m_fck(void) ++static int debug_irq; ++ ++/* called from dss */ ++void dsi_irq_handler(void) +{ -+ return dss.dss_96m_fck; ++ u32 irqstatus, vcstatus, ciostatus; ++ int i; ++ ++ irqstatus = dsi_read_reg(DSI_IRQSTATUS); ++ ++ if (irqstatus & DSI_IRQ_ERROR_MASK) { ++ DSSERR("DSI error, irqstatus %x\n", irqstatus); ++ print_irq_status(irqstatus); ++ } else if (debug_irq) { ++ print_irq_status(irqstatus); ++ } ++ ++ for (i = 0; i < 4; ++i) { ++ if ((irqstatus & (1< 30*1000*1000) ++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */ + -+ /* autoidle */ -+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); ++ return 0; ++} + -+ /* Select DPLL */ -+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); + -+#ifdef CONFIG_OMAP2_DSS_VENC -+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ -+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ -+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ -+#endif ++enum dsi_pll_power_state { ++ DSI_PLL_POWER_OFF = 0x0, ++ DSI_PLL_POWER_ON_HSCLK = 0x1, ++ DSI_PLL_POWER_ON_ALL = 0x2, ++ DSI_PLL_POWER_ON_DIV = 0x3, ++}; + -+ r = request_irq(INT_24XX_DSS_IRQ, dss_irq_handler, -+ 0, "OMAP DSS", NULL); ++static int dsi_pll_power(enum dsi_pll_power_state state) ++{ ++ int t = 0; + -+ if (r < 0) { -+ DSSERR("omap2 dss: request_irq failed\n"); -+ goto fail2; -+ } ++ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ + -+ rev = dss_read_reg(DSS_REVISION); -+ printk(KERN_INFO "OMAP DSS rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); ++ /* PLL_PWR_STATUS */ ++ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { ++ udelay(1); ++ if (t++ > 1000) { ++ DSSERR("DSI: Failed to set DSI PLL power mode to %d\n", ++ state); ++ return -ENODEV; ++ } ++ } + -+ disable_dss_clocks(); + return 0; -+ -+fail2: -+ disable_dss_clocks(); -+ put_dss_clocks(); -+fail1: -+ iounmap(dss.base); -+fail0: -+ return r; +} + -+void dss_exit(void) ++int dsi_pll_calc_pck(int is_tft, unsigned long req_pck, ++ struct dsi_clock_info *cinfo) +{ -+ int c; ++ struct dsi_clock_info cur, best; ++ int min_fck_per_pck; ++ int match = 0; + -+ free_irq(INT_24XX_DSS_IRQ, NULL); ++ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; + -+ /* these should be removed at some point */ -+ c = clk_get_usecount(dss.dss_ick); -+ if (c > 0) { -+ DSSERR("warning: dss_ick usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(dss.dss_ick); ++ if (min_fck_per_pck && ++ req_pck * min_fck_per_pck > DISPC_MAX_FCK) { ++ DSSERR("Requested pixel clock not possible with the current " ++ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " ++ "the constraint off.\n"); ++ min_fck_per_pck = 0; + } + -+ c = clk_get_usecount(dss.dss1_fck); -+ if (c > 0) { -+ DSSERR("warning: dss1_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(dss.dss1_fck); -+ } ++ DSSDBG("dsi_pll_calc\n"); + -+ c = clk_get_usecount(dss.dss2_fck); -+ if (c > 0) { -+ DSSERR("warning: dss2_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(dss.dss2_fck); -+ } ++retry: ++ memset(&best, 0, sizeof(best)); + -+ c = clk_get_usecount(dss.dss_54m_fck); -+ if (c > 0) { -+ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(dss.dss_54m_fck); -+ } ++ memset(&cur, 0, sizeof(cur)); ++ cur.clkin = clk_get_rate(dsi.dss2_fck); ++ cur.use_dss2_fck = 1; ++ cur.highfreq = 0; + -+ if (dss.dss_96m_fck) { -+ c = clk_get_usecount(dss.dss_96m_fck); -+ if (c > 0) { -+ DSSERR("warning: dss_96m_fck usecount %d, disabling\n", -+ c); -+ while (c-- > 0) -+ clk_disable(dss.dss_96m_fck); -+ } -+ } ++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ ++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ ++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ ++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { ++ if (cur.highfreq == 0) ++ cur.fint = cur.clkin / cur.regn; ++ else ++ cur.fint = cur.clkin / (2 * cur.regn); + -+ put_dss_clocks(); ++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) ++ continue; + -+ iounmap(dss.base); -+} ++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ ++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { ++ unsigned long a, b; + ++ a = 2 * cur.regm * (cur.clkin/1000); ++ b = cur.regn * (cur.highfreq + 1); ++ cur.dsiphy = a / b * 1000; + ++ if (cur.dsiphy > 1800 * 1000 * 1000) ++ break; + -+static int omap_dss_probe(struct platform_device *pdev) -+{ -+ struct omap_dss_platform_data *pdata = pdev->dev.platform_data; ++ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ ++ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; ++ ++cur.regm3) { ++ cur.dispc_fck = cur.dsiphy / cur.regm3; + -+ int r; ++ /* this will narrow down the search a bit, ++ * but still give pixclocks below what was ++ * requested */ ++ if (cur.dispc_fck < req_pck) ++ break; + -+ r = dss_init(); -+ if (r) { -+ DSSERR("Failed to initialize DSS\n"); -+ goto fail0; -+ } ++ if (cur.dispc_fck > DISPC_MAX_FCK) ++ continue; + -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ r = rfbi_init(); -+ if (r) { -+ DSSERR("Failed to initialize rfbi\n"); -+ goto fail0; -+ } -+#endif ++ if (min_fck_per_pck && ++ cur.dispc_fck < req_pck * min_fck_per_pck) ++ continue; + -+ r = dpi_init(); -+ if (r) { -+ DSSERR("Failed to initialize dpi\n"); -+ goto fail0; -+ } ++ match = 1; ++ ++ find_lck_pck_divs(is_tft, req_pck, ++ cur.dispc_fck, ++ &cur.lck_div, ++ &cur.pck_div); ++ ++ cur.lck = cur.dispc_fck / cur.lck_div; ++ cur.pck = cur.lck / cur.pck_div; ++ ++ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) { ++ best = cur; ++ ++ if (cur.pck == req_pck) ++ goto found; ++ } ++ } ++ } ++ } ++found: ++ if (!match) { ++ if (min_fck_per_pck) { ++ DSSERR("Could not find suitable clock settings.\n" ++ "Turning FCK/PCK constraint off and" ++ "trying again.\n"); ++ min_fck_per_pck = 0; ++ goto retry; ++ } ++ ++ DSSERR("Could not find suitable clock settings.\n"); ++ ++ return -EINVAL; ++ } ++ ++ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */ ++ /* hardcoded 48MHz for now. what should it be? */ ++ best.regm4 = best.dsiphy / 48000000; ++ if (best.regm4 > REGM4_MAX) ++ best.regm4 = REGM4_MAX; ++ best.dsi_fck = best.dsiphy / best.regm4; ++ ++ if (cinfo) ++ *cinfo = best; ++ ++ return 0; ++} ++ ++static int dsi_pll_calc_datafreq(unsigned long datafreq, ++ struct dsi_clock_info *cinfo) ++{ ++ struct dsi_clock_info cur, best; ++ const int use_dss2_fck = 1; ++ ++ DSSDBG("dsi_pll_calc_datarate\n"); ++ ++ memset(&best, 0, sizeof(best)); ++ ++ memset(&cur, 0, sizeof(cur)); ++ cur.use_dss2_fck = use_dss2_fck; ++ if (use_dss2_fck) { ++ cur.clkin = clk_get_rate(dsi.dss2_fck); ++ cur.highfreq = 0; ++ } else { ++ cur.clkin = dispc_pclk_rate(); ++ if (cur.clkin < 32000000) ++ cur.highfreq = 0; ++ else ++ cur.highfreq = 1; ++ } ++ ++ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ ++ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ ++ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ ++ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { ++ if (cur.highfreq == 0) ++ cur.fint = cur.clkin / cur.regn; ++ else ++ cur.fint = cur.clkin / (2 * cur.regn); ++ ++ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) ++ continue; ++ ++ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ ++ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { ++ unsigned long a, b; ++ ++ a = 2 * cur.regm * (cur.clkin/1000); ++ b = cur.regn * (cur.highfreq + 1); ++ cur.dsiphy = a / b * 1000; ++ ++ if (cur.dsiphy > 1800 * 1000 * 1000) ++ break; ++ ++ if (abs(cur.dsiphy - datafreq) < ++ abs(best.dsiphy - datafreq)) { ++ best = cur; ++ /* DSSDBG("best %ld\n", best.dsiphy); */ ++ } ++ ++ if (cur.dsiphy == datafreq) ++ goto found; ++ } ++ } ++found: ++ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ ++ /* hardcoded 48MHz for now. what should it be? */ ++ best.regm3 = best.dsiphy / (48000000); ++ if (best.regm3 > REGM3_MAX) ++ best.regm3 = REGM3_MAX; ++ best.dispc_fck = best.dsiphy / best.regm3; ++ ++ /* DSI2_PLL_FCLK(MHz) = DSIPHY(MHz) / regm4 < 173MHz */ ++ /* hardcoded 48MHz for now. what should it be? */ ++ best.regm4 = best.dsiphy / (48000000); ++ if (best.regm4 > REGM4_MAX) ++ best.regm4 = REGM4_MAX; ++ best.dsi_fck = best.dsiphy / best.regm4; ++ ++ if (cinfo) ++ *cinfo = best; ++ ++ return 0; ++} ++ ++int dsi_pll_program(struct dsi_clock_info *cinfo) ++{ ++ int r = 0; ++ u32 l; ++ ++ DSSDBG("dsi_pll_program\n"); ++ ++ enable_clocks(1); ++ ++ dsi.dsiphy = cinfo->dsiphy; ++ dsi.ddr_clk = dsi.dsiphy / 4; ++ dsi.dsi1_pll_fclk = cinfo->dispc_fck; ++ dsi.dsi2_pll_fclk = cinfo->dsi_fck; ++ ++ DSSDBG("DSI Fint %ld\n", cinfo->fint); ++ ++ DSSDBG("clkin (%s) rate %ld, highfreq %d\n", ++ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", ++ cinfo->clkin, ++ cinfo->highfreq); ++ ++ /* DSIPHY == CLKIN4DDR */ ++ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n", ++ cinfo->regm, ++ cinfo->regn, ++ cinfo->clkin, ++ cinfo->highfreq + 1, ++ cinfo->dsiphy); ++ ++ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", ++ dsi.dsiphy / 1000 / 1000 / 2); ++ ++ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk); ++ ++ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", ++ cinfo->regm3, cinfo->dispc_fck); ++ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", ++ cinfo->regm4, cinfo->dsi_fck); ++ ++ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ ++ ++ l = dsi_read_reg(DSI_PLL_CONFIGURATION1); ++ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ ++ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ ++ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ ++ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */ ++ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */ ++ dsi_write_reg(DSI_PLL_CONFIGURATION1, l); ++ ++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2); ++ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */ ++ /* DSI_PLL_CLKSEL */ ++ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11); ++ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */ ++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ ++ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ ++ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ ++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l); ++ ++ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ ++ ++ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { ++ DSSERR("dsi pll go bit not going down.\n"); ++ r = -EIO; ++ goto err; ++ } ++ ++ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { ++ DSSERR("DSI: cannot lock PLL\n"); ++ r = -EIO; ++ goto err; ++ } ++ ++ l = dsi_read_reg(DSI_PLL_CONFIGURATION2); ++ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ ++ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ ++ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ ++ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ ++ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ ++ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ ++ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ ++ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ ++ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ ++ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ ++ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ ++ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ ++ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ ++ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ ++ dsi_write_reg(DSI_PLL_CONFIGURATION2, l); ++ ++ DSSDBG("PLL config done\n"); ++err: ++ enable_clocks(0); ++ ++ return r; ++} ++ ++int dsi_pll_init(int enable_hsclk, int enable_hsdiv) ++{ ++ int r = 0; ++ enum dsi_pll_power_state pwstate; ++ struct dispc_clock_info cinfo; ++ ++ DSSDBG("PLL init\n"); ++ ++ enable_clocks(1); ++ dsi_enable_pll_clock(1); ++ ++ /* configure dispc fck and pixel clock to something sane */ ++ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo); ++ if (r) ++ return r; ++ ++ r = dispc_set_clock_div(&cinfo); ++ if (r) ++ return r; ++ ++ /* PLL does not come out of reset without this... */ ++ dispc_pck_free_enable(1); ++ ++ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { ++ DSSERR("DSI: PLL not coming out of reset.\n"); ++ r = -ENODEV; ++ goto err; ++ } ++ ++ /* ... but if left on, we get problems when planes do not ++ * fill the whole display. No idea about this XXX */ ++ dispc_pck_free_enable(0); ++ ++ if (enable_hsclk && enable_hsdiv) ++ pwstate = DSI_PLL_POWER_ON_ALL; ++ else if (enable_hsclk) ++ pwstate = DSI_PLL_POWER_ON_HSCLK; ++ else if (enable_hsdiv) ++ pwstate = DSI_PLL_POWER_ON_DIV; ++ else ++ pwstate = DSI_PLL_POWER_OFF; ++ ++ r = dsi_pll_power(pwstate); ++ ++ if (r) ++ goto err; ++ ++ enable_clocks(0); ++ ++ DSSDBG("PLL init done\n"); ++ ++ return 0; ++err: ++ enable_clocks(0); ++ dsi_enable_pll_clock(0); ++ return r; ++} ++ ++void dsi_pll_uninit(void) ++{ ++ dsi_pll_power(DSI_PLL_POWER_OFF); ++ dsi_enable_pll_clock(0); ++ DSSDBG("PLL uninit done\n"); ++} ++ ++unsigned long dsi_get_dsi1_pll_rate(void) ++{ ++ return dsi.dsi1_pll_fclk; ++} ++ ++unsigned long dsi_get_dsi2_pll_rate(void) ++{ ++ return dsi.dsi2_pll_fclk; ++} ++ ++ssize_t dsi_print_clocks(char *buf, ssize_t size) ++{ ++ ssize_t l = 0; ++ int clksel; ++ ++ enable_clocks(1); ++ ++ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11); ++ ++ l += snprintf(buf + l, size - l, "- dsi -\n"); ++ ++ l += snprintf(buf + l, size - l, "dsi fclk source = %s\n", ++ dss_get_dsi_clk_source() == 0 ? ++ "dss1_alwon_fclk" : "dsi2_pll_fclk"); ++ ++ l += snprintf(buf + l, size - l, "dsi pll source = %s\n", ++ clksel == 0 ? ++ "dss2_alwon_fclk" : "pclkfree"); ++ ++ l += snprintf(buf + l, size - l, ++ "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n", ++ dsi.dsiphy, dsi.ddr_clk); ++ ++ l += snprintf(buf + l, size - l, ++ "dsi1_pll_fck\t%lu (%s)\n" ++ "dsi2_pll_fck\t%lu (%s)\n", ++ dsi.dsi1_pll_fclk, ++ dss_get_dispc_clk_source() == 0 ? "off" : "on", ++ dsi.dsi2_pll_fclk, ++ dss_get_dsi_clk_source() == 0 ? "off" : "on"); ++ ++ enable_clocks(0); ++ ++ return l; ++} ++ ++ ++enum dsi_complexio_power_state { ++ DSI_COMPLEXIO_POWER_OFF = 0x0, ++ DSI_COMPLEXIO_POWER_ON = 0x1, ++ DSI_COMPLEXIO_POWER_ULPS = 0x2, ++}; ++ ++static int dsi_complexio_power(enum dsi_complexio_power_state state) ++{ ++ int t = 0; ++ ++ /* PWR_CMD */ ++ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); ++ ++ /* PWR_STATUS */ ++ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { ++ udelay(1); ++ if (t++ > 1000) { ++ DSSERR("DSI: failed to set complexio power state to " ++ "%d\n", state); ++ return -ENODEV; ++ } ++ } ++ ++ return 0; ++} ++ ++static void dsi_complexio_config(struct omap_display *display) ++{ ++ u32 r; ++ ++ int clk_lane = display->hw_config.u.dsi.clk_lane; ++ int data1_lane = display->hw_config.u.dsi.data1_lane; ++ int data2_lane = display->hw_config.u.dsi.data2_lane; ++ int clk_pol = display->hw_config.u.dsi.clk_pol; ++ int data1_pol = display->hw_config.u.dsi.data1_pol; ++ int data2_pol = display->hw_config.u.dsi.data2_pol; ++ ++ r = dsi_read_reg(DSI_COMPLEXIO_CFG1); ++ r = FLD_MOD(r, clk_lane, 2, 0); ++ r = FLD_MOD(r, clk_pol, 3, 3); ++ r = FLD_MOD(r, data1_lane, 6, 4); ++ r = FLD_MOD(r, data1_pol, 7, 7); ++ r = FLD_MOD(r, data2_lane, 10, 8); ++ r = FLD_MOD(r, data2_pol, 11, 11); ++ dsi_write_reg(DSI_COMPLEXIO_CFG1, r); ++ ++ /* The configuration of the DSI complex I/O (number of data lanes, ++ position, differential order) should not be changed while ++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for ++ the hardware to take into account a new configuration of the complex ++ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to ++ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, ++ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set ++ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the ++ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the ++ DSI complex I/O configuration is unknown. */ ++ ++ /* ++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0); ++ REG_FLD_MOD(DSI_CTRL, 0, 0, 0); ++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); ++ REG_FLD_MOD(DSI_CTRL, 1, 0, 0); ++ */ ++} ++ ++static inline int ns2ddr(int ns) ++{ ++ /* convert time in ns to ddr ticks, rounding up */ ++ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000; ++} ++ ++static void dsi_complexio_timings(void) ++{ ++ u32 r; ++ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; ++ u32 tlpx_half, tclk_trail, tclk_zero; ++ u32 tclk_prepare; ++ ++ /* calculate timings */ ++ ++ /* 1 * DDR_CLK = 2 * UI */ ++ ++ /* min 40ns + 4*UI max 85ns + 6*UI */ ++ ths_prepare = ns2ddr(59) + 2; ++ ++ /* min 145ns + 10*UI */ ++ ths_prepare_ths_zero = ns2ddr(145) + 5; ++ ++ /* min max(8*UI, 60ns+4*UI) */ ++ ths_trail = max(4, ns2ddr(60) + 2); ++ ++ /* min 100ns */ ++ ths_exit = ns2ddr(100); ++ ++ /* tlpx min 50n */ ++ tlpx_half = ns2ddr(25); ++ ++ /* min 60ns */ ++ tclk_trail = ns2ddr(60); ++ ++ /* min 38ns, max 95ns */ ++ tclk_prepare = ns2ddr(38); ++ ++ /* min tclk-prepare + tclk-zero = 300ns */ ++ tclk_zero = ns2ddr(300 - 38); ++ ++#ifdef VERBOSE ++ DSSDBG("ths_prepare %d, ths_prepare_ths_zero %d\n", ++ ths_prepare, ths_prepare_ths_zero); ++ DSSDBG("ths_trail %d, ths_exit %d\n", ths_trail, ths_exit); ++ ++ ++ DSSDBG("tlpx_half %d, tclk_trail %d, tclk_zero %d\n", tlpx_half, ++ tclk_trail, tclk_zero); ++ DSSDBG("tclk_prepare %d\n", tclk_prepare); ++#endif ++ ++ /* program timings */ ++ ++ r = dsi_read_reg(DSIPHY_CFG0); ++ r = FLD_MOD(r, ths_prepare, 31, 24); ++ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); ++ r = FLD_MOD(r, ths_trail, 15, 8); ++ r = FLD_MOD(r, ths_exit, 7, 0); ++ dsi_write_reg(DSIPHY_CFG0, r); ++ ++ r = dsi_read_reg(DSIPHY_CFG1); ++ r = FLD_MOD(r, tlpx_half, 22, 16); ++ r = FLD_MOD(r, tclk_trail, 15, 8); ++ r = FLD_MOD(r, tclk_zero, 7, 0); ++ dsi_write_reg(DSIPHY_CFG1, r); ++ ++ r = dsi_read_reg(DSIPHY_CFG2); ++ r = FLD_MOD(r, tclk_prepare, 7, 0); ++ dsi_write_reg(DSIPHY_CFG2, r); ++} ++ ++ ++static int dsi_complexio_init(struct omap_display *display) ++{ ++ int r = 0; ++ ++ DSSDBG("dsi_complexio_init\n"); ++ ++ /* CIO_CLK_ICG, enable L3 clk to CIO */ ++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); ++ ++ if (wait_for_bit_change(DSIPHY_CFG5, 30, 1) != 1) { ++ DSSERR("DSI: ComplexIO PHY not coming out of reset.\n"); ++ r = -ENODEV; ++ goto err; ++ } ++ ++ dsi_complexio_config(display); ++ ++ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); ++ ++ if (r) ++ goto err; ++ ++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { ++ DSSERR("DSI: ComplexIO not coming out of reset.\n"); ++ r = -ENODEV; ++ goto err; ++ } ++ ++ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) { ++ DSSERR("DSI: ComplexIO LDO power down.\n"); ++ r = -ENODEV; ++ goto err; ++ } ++ ++ dsi_complexio_timings(); ++ ++ /* ++ The configuration of the DSI complex I/O (number of data lanes, ++ position, differential order) should not be changed while ++ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the ++ hardware to recognize a new configuration of the complex I/O (done ++ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow ++ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next ++ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] ++ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN ++ bit to 1. If the sequence is not followed, the DSi complex I/O ++ configuration is undetermined. ++ */ ++ dsi_if_enable(1); ++ dsi_if_enable(0); ++ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ ++ dsi_if_enable(1); ++ dsi_if_enable(0); ++ ++ DSSDBG("CIO init done\n"); ++err: ++ return r; ++} ++ ++static void dsi_complexio_uninit(void) ++{ ++ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); ++} ++ ++ ++ ++static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, ++ enum fifo_size size3, enum fifo_size size4) ++{ ++ u32 r = 0; ++ int add = 0; ++ int i; ++ ++ dsi.vc[0].fifo_size = size1; ++ dsi.vc[1].fifo_size = size2; ++ dsi.vc[2].fifo_size = size3; ++ dsi.vc[3].fifo_size = size4; ++ ++ for (i = 0; i < 4; i++) { ++ u8 v; ++ int size = dsi.vc[i].fifo_size; ++ ++ if (add + size > 4) { ++ DSSERR("DSI: Illegal FIFO configuration\n"); ++ BUG(); ++ } ++ ++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); ++ r |= v << (8 * i); ++ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ ++ add += size; ++ } ++ ++ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); ++} ++ ++static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, ++ enum fifo_size size3, enum fifo_size size4) ++{ ++ u32 r = 0; ++ int add = 0; ++ int i; ++ ++ dsi.vc[0].fifo_size = size1; ++ dsi.vc[1].fifo_size = size2; ++ dsi.vc[2].fifo_size = size3; ++ dsi.vc[3].fifo_size = size4; ++ ++ for (i = 0; i < 4; i++) { ++ u8 v; ++ int size = dsi.vc[i].fifo_size; ++ ++ if (add + size > 4) { ++ DSSERR("DSI: Illegal FIFO configuration\n"); ++ BUG(); ++ } ++ ++ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); ++ r |= v << (8 * i); ++ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ ++ add += size; ++ } ++ ++ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); ++} ++ ++static int dsi_force_tx_stop_mode_io(void) ++{ ++ u32 r; ++ ++ r = dsi_read_reg(DSI_TIMING1); ++ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ ++ dsi_write_reg(DSI_TIMING1, r); ++ ++ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { ++ DSSERR("TX_STOP bit not going down\n"); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static void dsi_vc_print_status(int channel) ++{ ++ u32 r; ++ ++ r = dsi_read_reg(DSI_VC_CTRL(channel)); ++ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, " ++ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ", ++ channel, ++ FLD_GET(r, 5, 5), ++ FLD_GET(r, 6, 6), ++ FLD_GET(r, 15, 15), ++ FLD_GET(r, 16, 16), ++ FLD_GET(r, 20, 20)); ++ ++ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS); ++ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff); ++} ++ ++static void dsi_vc_config(int channel) ++{ ++ u32 r; ++ ++ DSSDBG("dsi_vc_config %d\n", channel); ++ ++ r = dsi_read_reg(DSI_VC_CTRL(channel)); ++ ++ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ ++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ ++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ ++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ ++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ ++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ ++ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ ++ ++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ ++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ ++ ++ dsi_write_reg(DSI_VC_CTRL(channel), r); ++} ++ ++static void dsi_vc_config_vp(int channel) ++{ ++ u32 r; ++ ++ DSSDBG("dsi_vc_config_vp\n"); ++ ++ r = dsi_read_reg(DSI_VC_CTRL(channel)); ++ ++ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */ ++ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ ++ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ ++ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ ++ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ ++ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ ++ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */ ++ ++ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ ++ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ ++ ++ dsi_write_reg(DSI_VC_CTRL(channel), r); ++} ++ ++ ++static int dsi_vc_enable(int channel, int enable) ++{ ++ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable); ++ ++ enable = enable ? 1 : 0; ++ ++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); ++ ++ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { ++ DSSERR("Failed to set dsi_vc_enable to %d\n", enable); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static void dsi_vc_enable_hs(int channel, int enable) ++{ ++ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); ++ ++ dsi_vc_enable(channel, 0); ++ dsi_if_enable(0); ++ ++ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); ++ ++ dsi_vc_enable(channel, 1); ++ dsi_if_enable(1); ++ ++ dsi_force_tx_stop_mode_io(); ++} ++ ++static void dsi_vc_flush_long_data(int channel) ++{ ++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { ++ u32 val; ++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); ++ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", ++ (val >> 0) & 0xff, ++ (val >> 8) & 0xff, ++ (val >> 16) & 0xff, ++ (val >> 24) & 0xff); ++ } ++} ++ ++static u16 dsi_vc_flush_receive_data(int channel) ++{ ++ /* RX_FIFO_NOT_EMPTY */ ++ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { ++ u32 val; ++ u8 dt; ++ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); ++ DSSDBG("\trawval %#08x\n", val); ++ dt = FL