diff options
Diffstat (limited to 'recipes/u-boot/u-boot-git/beagleboard/0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch')
| -rw-r--r-- | recipes/u-boot/u-boot-git/beagleboard/0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/recipes/u-boot/u-boot-git/beagleboard/0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch b/recipes/u-boot/u-boot-git/beagleboard/0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch new file mode 100644 index 0000000000..d2c6abba75 --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0028-OMAP3-fix-and-clean-up-L2-cache-enable-disable-funct.patch @@ -0,0 +1,112 @@ +From c18bda32fdb048ea38b7ff579f365ea8858053d7 Mon Sep 17 00:00:00 2001 +From: Mans Rullgard <mans@mansr.com> +Date: Wed, 14 Apr 2010 12:08:00 +0100 +Subject: [PATCH 28/37] OMAP3: fix and clean up L2 cache enable/disable functions + +On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode, +so an SMC call to the ROM monitor is required. On later versions, +and on newer devices, this bit is banked and we can set it directly. + +The code checked only the ES revision of the chip, and hence incorrectly +used the ROM call on ES1.0 versions of other devices. + +This patch adds a check for chip family as well as revision, and also +removes some code duplication between the enable and disable functions. + +Signed-off-by: Mans Rullgard <mans@mansr.com> +--- + cpu/arm_cortexa8/omap3/cache.S | 74 +++++++++++----------------------------- + 1 files changed, 20 insertions(+), 54 deletions(-) + +diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S +index 0f63815..16afb5d 100644 +--- a/cpu/arm_cortexa8/omap3/cache.S ++++ b/cpu/arm_cortexa8/omap3/cache.S +@@ -128,64 +128,30 @@ finished_inval: + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +- +-l2_cache_enable: +- push {r0, r1, r2, lr} +- @ ES2 onwards we can disable/enable L2 ourselves ++l2_cache_set: ++ push {r4-r6, lr} ++ mov r5, r0 + bl get_cpu_rev +- cmp r0, #CPU_3XX_ES20 +- blt l2_cache_disable_EARLIER_THAN_ES2 +- mrc 15, 0, r3, cr1, cr0, 1 +- orr r3, r3, #2 +- mcr 15, 0, r3, cr1, cr0, 1 +- b l2_cache_enable_END +-l2_cache_enable_EARLIER_THAN_ES2: +- @ Save r0, r12 and restore them after usage +- mov r3, ip +- str r3, [sp, #4] +- mov r3, r0 +- @ ++ mov r4, r0 ++ bl get_cpu_family ++ @ ES2 onwards we can disable/enable L2 ourselves ++ cmp r0, #CPU_OMAP34XX ++ cmpeq r4, #CPU_3XX_ES10 ++ mrc 15, 0, r0, cr1, cr0, 1 ++ bic r0, r0, #2 ++ orr r0, r0, r5, lsl #1 ++ mcreq 15, 0, r0, cr1, cr0, 1 + @ GP Device ROM code API usage here + @ r12 = AUXCR Write function and r0 value +- @ + mov ip, #3 +- mrc 15, 0, r0, cr1, cr0, 1 +- orr r0, r0, #2 +- @ SMI instruction to call ROM Code API +- .word 0xe1600070 +- mov r0, r3 +- mov ip, r3 +- str r3, [sp, #4] +-l2_cache_enable_END: +- pop {r1, r2, r3, pc} ++ @ SMCNE instruction to call ROM Code API ++ .word 0x11600070 ++ pop {r4-r6, pc} + ++l2_cache_enable: ++ mov r0, #1 ++ b l2_cache_set + + l2_cache_disable: +- push {r0, r1, r2, lr} +- @ ES2 onwards we can disable/enable L2 ourselves +- bl get_cpu_rev +- cmp r0, #CPU_3XX_ES20 +- blt l2_cache_disable_EARLIER_THAN_ES2 +- mrc 15, 0, r3, cr1, cr0, 1 +- bic r3, r3, #2 +- mcr 15, 0, r3, cr1, cr0, 1 +- b l2_cache_disable_END +-l2_cache_disable_EARLIER_THAN_ES2: +- @ Save r0, r12 and restore them after usage +- mov r3, ip +- str r3, [sp, #4] +- mov r3, r0 +- @ +- @ GP Device ROM code API usage here +- @ r12 = AUXCR Write function and r0 value +- @ +- mov ip, #3 +- mrc 15, 0, r0, cr1, cr0, 1 +- bic r0, r0, #2 +- @ SMI instruction to call ROM Code API +- .word 0xe1600070 +- mov r0, r3 +- mov ip, r3 +- str r3, [sp, #4] +-l2_cache_disable_END: +- pop {r1, r2, r3, pc} ++ mov r0, #0 ++ b l2_cache_set +-- +1.6.6.1 + |