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-rw-r--r--packages/u-boot/u-boot-1.3.2/boc01/001-090115-SPI.patch90
-rw-r--r--packages/u-boot/u-boot-1.3.2/boc01/007-090112-CAPSENSE.patch546
-rw-r--r--packages/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch157
-rw-r--r--packages/u-boot/u-boot_1.3.2.bb8
4 files changed, 797 insertions, 4 deletions
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/001-090115-SPI.patch b/packages/u-boot/u-boot-1.3.2/boc01/001-090115-SPI.patch
new file mode 100644
index 0000000000..96b624b3a1
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/001-090115-SPI.patch
@@ -0,0 +1,90 @@
+Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c
+===================================================================
+--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c 2009-01-15 10:51:45.000000000 +0100
++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c 2009-01-15 12:18:31.000000000 +0100
+@@ -28,6 +28,7 @@
+ #endif
+ #include <pci.h>
+ #include <mpc83xx.h>
++#include <spi.h>
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -107,3 +108,29 @@
+ #endif
+ }
+ #endif
++
++
++/*
++ * The following are used to control the SPI chip selects for the SPI command.
++ */
++#ifdef CONFIG_HARD_SPI
++
++void spi_rfid_chipsel(int cs)
++{
++ if(cs)
++ gpio_clear(14);
++ else
++ gpio_set(14);
++}
++
++/*
++ * The SPI command uses this table of functions for controlling the SPI
++ * chip selects.
++ */
++spi_chipsel_type spi_chipsel[] = {
++ spi_rfid_chipsel,
++};
++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
++
++#endif /* CONFIG_HARD_SPI */
++
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2009-01-15 10:51:51.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2009-01-15 12:16:57.000000000 +0100
+@@ -369,6 +369,7 @@
+ #define CONFIG_CMD_PCI
+ #define CONFIG_CMD_NAND
+ #define CONFIG_CMD_JFFS2
++#define CONFIG_CMD_SPI
+
+ #if defined(CFG_RAMBOOT)
+ #undef CONFIG_CMD_ENV
+@@ -386,6 +387,11 @@
+ #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:384k(uboot),64k(env)"
+
+
++/* SPI */
++#define CONFIG_MPC8XXX_SPI
++#define CONFIG_HARD_SPI /* SPI with hardware support */
++#undef CONFIG_SOFT_SPI /* SPI bit-banged */
++
+ /*
+ * Miscellaneous configurable options
+ */
+Index: u-boot-1.3.2/drivers/spi/mpc8xxx_spi.c
+===================================================================
+--- u-boot-1.3.2.orig/drivers/spi/mpc8xxx_spi.c 2009-01-15 10:52:30.000000000 +0100
++++ u-boot-1.3.2/drivers/spi/mpc8xxx_spi.c 2009-01-15 10:53:23.000000000 +0100
+@@ -34,6 +34,8 @@
+ #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
+ #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
+ #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
++#define SPI_MODE_DIV16 (0x80000000 >> 4) /*Divide by 16. */
++#define SPI_MODE_LEN_8 (0x00700000) /*0111 8-bit characters*/
+
+ #define SPI_TIMEOUT 1000
+
+@@ -45,9 +47,7 @@
+ * SPI pins on the MPC83xx are not muxed, so all we do is initialize
+ * some registers
+ */
+- spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
+- spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+- (16.67MHz typ.) */
++ spi->mode = SPI_MODE_DIV16 |SPI_MODE_LEN_8| SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
+ spi->event = 0xffffffff; /* Clear all SPI events */
+ spi->mask = 0x00000000; /* Mask all SPI interrupts */
+ spi->com = 0; /* LST bit doesn't do anything, so disregard */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/007-090112-CAPSENSE.patch b/packages/u-boot/u-boot-1.3.2/boc01/007-090112-CAPSENSE.patch
new file mode 100644
index 0000000000..cc176f20b1
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/007-090112-CAPSENSE.patch
@@ -0,0 +1,546 @@
+Index: u-boot-1.3.2/common/cmd_capsense.c
+===================================================================
+--- /dev/null
++++ u-boot-1.3.2/common/cmd_capsense.c
+@@ -0,0 +1,105 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * CapSense Express touch-sensing buttons
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++
++#include <capsense.h>
++#include <i2c.h>
++
++#define ARG_SENSOR_NUMBER 1
++
++#define ARG_CMD 1
++#define ARG_OLD_ADDRESS 2
++
++
++int do_capsense (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
++{
++ int i;
++ unsigned char sensors[] = CONFIG_CAPSENSE_SENSORS;
++ int old_bus, old_address;
++ char port[2];
++ /* switch to correct I2C bus */
++ old_bus = I2C_GET_BUS();
++ I2C_SET_BUS(CFG_CAPSENSE_BUS_NUM);
++
++ /*
++ * Loop through sensors, read
++ * state, and output it.
++ */
++ if(argc==1)
++ {
++ port[0]=capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,0);
++ port[1]=capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,1);
++ capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,1);
++ printf ("P0 0x%02x 0x%02x\n",port[0],port[1]);
++ for (i = 0; i < 8; i++)
++ {
++ if(sensors[0]&(1<<i))
++ {
++ printf ("GP0[%d]: %i\n",i,port[0]&(1<<i)?1:0);
++ }
++ if(sensors[1]&(1<<i))
++ {
++ printf ("GP1[%d]: %i\n",i,port[1]&(1<<i)?1:0);
++ }
++
++ }
++ }
++ else
++ {
++ if ( strncmp(argv[ARG_CMD], "config", 3) == 0 ) {
++ if ( argc == 3 ) {
++ old_address=simple_strtoul (argv[ARG_OLD_ADDRESS], NULL, 10);
++ if ( capsense_change_i2c_address(old_address, CONFIG_CAPSENSE_I2C_ADDRESS) != 0 )
++ printf("failed to change i2c address\n");
++ else
++ printf("i2c address changed to 0x%02X\n", CONFIG_CAPSENSE_I2C_ADDRESS);
++ }
++
++ capsense_config(CONFIG_CAPSENSE_I2C_ADDRESS);
++ capsense_store_nvm(CONFIG_CAPSENSE_I2C_ADDRESS);
++ }
++ else {
++ printf ("Usage:\n%s\n", cmdtp->help);
++ }
++ }
++
++ /* switch back to original I2C bus */
++ I2C_SET_BUS(old_bus);
++
++ return 0;
++} /* do_capsense() */
++
++
++/***************************************************/
++
++U_BOOT_CMD(
++ capsense, 4, 1, do_capsense,
++ "capsense - CapSense Express touch-sensing buttons\n",
++ "capsense\n Read state of the CapSense Express touch-sensing buttons.\n"
++ "capsense config [<old i2c address>]\n Setup default capsense configuration.\n"
++ );
+Index: u-boot-1.3.2/common/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/common/Makefile
++++ u-boot-1.3.2/common/Makefile
+@@ -50,6 +50,7 @@ endif
+ COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+ COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o
+ COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
++COBJS-$(CONFIG_CMD_CAPSENSE) += cmd_capsense.o
+ COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+ COBJS-y += cmd_eeprom.o
+ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
+Index: u-boot-1.3.2/drivers/i2c/CY8C201xx.c
+===================================================================
+--- /dev/null
++++ u-boot-1.3.2/drivers/i2c/CY8C201xx.c
+@@ -0,0 +1,289 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * CapSense Express touch-sensing buttons
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_CAPSENSE_CY8C201XX
++
++#include <i2c.h>
++#include <capsense.h>
++
++int capsense_read(int address, int reg)
++{
++ int dlen;
++ uchar data[2];
++
++ /*
++ * Validate 'reg' param
++ */
++ if ( (reg < 0) || (reg > 0xA1) )
++ return -1;
++
++ /*
++ * Prepare to handle 1 byte result.
++ */
++ dlen = 1;
++
++ /*
++ * Now try to read the register.
++ */
++ if (i2c_read(address, reg, 1, data, dlen) != 0)
++ return -1;
++
++ return (int)data[0];
++}
++
++
++int capsense_write(int address, int reg, int val)
++{
++ int dlen;
++ uchar data[2];
++
++ /*
++ * Validate 'reg' param
++ */
++ if((reg < 0) || (reg > 0xA1))
++ return -1;
++
++ /*
++ * Handle 1 byte values.
++ */
++ dlen = 1;
++ data[0] = (char)(val & 0xff);
++
++ /*
++ * Write value to register.
++ */
++ if (i2c_write(address, reg, 1, data, dlen) != 0)
++ return 1;
++
++ return 0;
++}
++
++
++int capsense_write_N(int address, int reg, char *data, int dlen)
++{
++ /*
++ * Validate 'reg' param
++ */
++ if ( (reg < 0) || (reg > 0xA1) )
++ return -1;
++
++ /*
++ * Write value to register.
++ */
++ if ( i2c_write(address, reg, 1, data, dlen) != 0 )
++ return 1;
++
++ return 0;
++}
++
++
++int capsense_get_state(int address,char port)
++{
++ return capsense_read(address,CAPSENSE_REG_READ_STATUS+port);
++}
++
++
++int capsense_change_i2c_address(char old_address,char new_address)
++{
++ unsigned char data[4];
++ int read_address;
++ printf("capsense change i2c address\n");
++ //checking if the I2C address is in the limits ( I2C address can have a value from 0 to 127 )
++ if((old_address>0x7F)||(new_address>0x7F))
++ {
++ printf("I2C address is not in the limits\n");
++ return 1;
++ }
++
++ //reading old capsence address
++ read_address=capsense_read(old_address, CAPSENSE_REG_I2C_ADDR_DM);
++ if(read_address==0xFFFFFFFF)
++ {
++ printf("error reading old capsence address\n");
++ return 1; //capsense do not respond at new address
++ }
++
++ if((read_address&0x7F)!=old_address)
++ {
++ printf("reading old capsence address failed\n");
++ return 1; //Capsense not respond correctly
++ }
++
++ //writing command for unlocking the I2C device address lock
++ data[0]=0x3C;
++ data[1]=0xA5;
++ data[2]=0x69;
++ if(capsense_write_N(old_address, CAPSENSE_REG_I2C_DEV_LOCK, data , 3)!=0)
++ {
++ printf("writing command for unlocking the I2C device address lock failed\n");
++ return 1;
++ }
++
++ //writing the new I2C address to the device I2C address register
++ if(capsense_write(old_address, CAPSENSE_REG_I2C_ADDR_DM,new_address|0x80)!=0)
++ {
++ printf("writing the new I2C address to the device I2C address register failed\n");
++ return 1;
++ }
++
++ //writing command for locking the I2C device address lock
++ data[0]=0x96;
++ data[1]=0x5A;
++ data[2]=0xC3;
++ if(capsense_write_N(old_address, CAPSENSE_REG_I2C_DEV_LOCK, data , 3)!=0)
++ {
++ printf("writing command for locking the I2C device failed\n");
++ return 1;
++ }
++
++ //reading new capsence address
++ read_address=capsense_read(new_address, CAPSENSE_REG_I2C_ADDR_DM);
++ if(read_address==0xFFFFFFFF)
++ {
++ printf("capsense do not respond at new address\n");
++ return 1; //capsense do not respond at new address
++ }
++
++ return 0;
++}
++
++
++static char data_GPIO_ENABLE[] = {
++ 0x00, 0x00 // GPIO_ENABLE
++};
++
++static char data_CS_ENABLE[] = {
++ 0x1D, 0x10, // CS_ENABLE
++ 0x02, 0x0F, // GPIO_ENABLE
++ 0x00, 0x00, // INVERSION_MASK
++ 0x00, 0x00, // INT_MASK
++ 0x1F, 0x1F, // STATUS_HOLD_MSK
++ 0x00, 0x02, 0x00, 0x00, // DM_PULL_UP0, DM_STRONG0, DM_HIGHZ0, DM_OD_LOW0
++ 0x00, 0x0F, 0x00, 0x00, // DM_PULL_UP1, DM_STRONG1, DM_HIGHZ1, DM_OD_LOW1
++};
++
++static char data_OUTPUT_PORT[] = {
++ 0x00, 0x00 // OUTPUT_PORT
++};
++
++static char data_OP_SEL[] = {
++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_00
++ 0x80, 0x01, 0x00, 0x00, 0x00, // OP_SEL_01
++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_02
++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_03
++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_04
++ 0x80, 0x10, 0x00, 0x00, 0x00, // OP_SEL_10
++ 0x80, 0x08, 0x00, 0x00, 0x00, // OP_SEL_11
++ 0x80, 0x04, 0x00, 0x00, 0x00, // OP_SEL_12
++ 0x80, 0x00, 0x10, 0x00, 0x00, // OP_SEL_13
++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_14
++};
++
++static char data_CS_NOISE_TH[] = {
++ 0x28, // CS_NOISE_TH
++ 0x64, // CS_BL_UPD_TH
++ 0xA0, // CS_SETL_TIME
++ 0x22, // CS_OTH_SET
++ 0x0A, // CS_HYSTERESIS
++ 0x03, // CS_DEBOUNCE
++ 0x14, // CS_NEG_NOISE_TH
++ 0x14, // CS_LOW_BL_RST
++ 0x00, // CS_FILTERING
++};
++
++static char data_CS_SCAN_POS[] = {
++ 0x00, 0x00, 0x00, 0x00, 0x00, // CS_SCAN_POS_0x
++ 0x00, 0x00, 0x00, 0x00, 0x00, // CS_SCAN_POS_1x
++ 0x32, 0x00, 0x32, 0x32, 0x32, // CS_FINGER_TH_0x
++ 0x00, 0x00, 0x00, 0x00, 0x32, // CS_FINGER_TH_1x
++ 0x08, 0x00, 0x08, 0x08, 0x08, // CS_IDAC_0x
++ 0x00, 0x00, 0x00, 0x00, 0x08 // CS_IDAC_1x
++};
++
++static char data_SLEEP[] = {
++ 0x00, // SLEEP_PIN
++ 0x20, // SLEEP_CTRL
++ 0x00, // SLEEP_SA_CTR
++};
++
++int capsense_config(char address)
++{
++ printf("Setting default capsense configuration at i2c address 0x%02X...\n", address);
++
++ //entering setup operation mode
++ if ( capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_SETUP_OPERATION_MODE) != 0 ) {
++ printf("CAPSENSE_COMMAND_REG SETUP_OPERATION_MODE\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_GPIO_ENABLE, data_GPIO_ENABLE, sizeof(data_GPIO_ENABLE)) != 0 ) {
++ printf("CAPSENSE_REG_GPIO_ENABLE\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_CS_ENABLE, data_CS_ENABLE, sizeof(data_CS_ENABLE)) != 0 ) {
++ printf("CAPSENSE_REG_CS_ENABLE\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_OUTPUT_PORT, data_OUTPUT_PORT, sizeof(data_OUTPUT_PORT)) != 0 ) {
++ printf("CAPSENSE_REG_OUTPUT_PORT\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_OP_SEL_0, data_OP_SEL, sizeof(data_OP_SEL)) != 0 ) {
++ printf("CAPSENSE_REG_OP_SEL_0\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_CS_NOISE_TH, data_CS_NOISE_TH, sizeof(data_CS_NOISE_TH)) != 0 ) {
++ printf("CAPSENSE_REG_CS_NOISE_TH\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_CS_SCAN_POS, data_CS_SCAN_POS, sizeof(data_CS_SCAN_POS)) != 0 ) {
++ printf("CAPSENSE_REG_CS_SCAN_POS\n");
++ return 1;
++ }
++ if ( capsense_write_N(address, CAPSENSE_REG_SLEEP_PIN, data_SLEEP, sizeof(data_SLEEP)) != 0 ) {
++ printf("CAPSENSE_REG_SLEEP_PIN\n");
++ return 1;
++ }
++ if ( capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_NORMAL_OPERATION_MODE) != 0 ) {
++ printf("CAPSENSE_COMMAND_REG NORMAL_OPERATION_MODE\n");
++ return 1;
++ }
++
++ printf("...done.\n");
++
++ return 0;
++}
++
++void capsense_store_nvm(char address)
++{
++ //storing the new current configuration to NVM
++ printf("Storing capsense configuration to NVM\n");
++ capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_STORE_TO_NVM);
++}
++
++#endif /* CONFIG_CAPSENSE_CY8C201XX */
+Index: u-boot-1.3.2/drivers/i2c/Makefile
+===================================================================
+--- u-boot-1.3.2.orig/drivers/i2c/Makefile
++++ u-boot-1.3.2/drivers/i2c/Makefile
+@@ -29,6 +29,7 @@ COBJS-y += fsl_i2c.o
+ COBJS-y += omap1510_i2c.o
+ COBJS-y += omap24xx_i2c.o
+ COBJS-y += tsi108_i2c.o
++COBJS-y += CY8C201xx.o
+
+ COBJS := $(COBJS-y)
+ SRCS := $(COBJS:.o=.c)
+Index: u-boot-1.3.2/include/capsense.h
+===================================================================
+--- /dev/null
++++ u-boot-1.3.2/include/capsense.h
+@@ -0,0 +1,95 @@
++/*
++ * (C) Copyright 2008
++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USCY8C201xx.c:234:A
++ */
++
++/*
++ * CapSense Express touch-sensing buttons.
++ */
++#ifndef _CAPSENSE_H_
++#define _CAPSENSE_H_
++
++#if defined(CONFIG_CAPSENSE_CY8C201XX)
++
++#define CONFIG_CAPSENSE /* We have a Capsense */
++
++#ifndef CONFIG_CAPSENSE_SENSORS
++/*config for CY3218-CAPEXP1*/
++#define CONFIG_CAPSENSE_LED {0x05,0x02} // port 0-{0,3} port 1-{2}
++#define CONFIG_CAPSENSE_SENSOR {0x02,0x0C} // port 0-{2} port 1-{3,4}
++#endif
++#endif /* CONFIG_CAPSENSE_SENSORS */
++
++extern int capsense_read(int address, int reg);
++extern int capsense_write(int address, int reg, int val);
++extern int capsense_get_state(int address,char port);
++extern int capsense_change_i2c_address(char old_address,char new_address);
++extern int capsense_config(char address);
++extern void capsense_store_nvm(char address);
++#endif
++
++#if !defined(CFG_CAPSENSE_BUS_NUM)
++#define CFG_CAPSENSE_BUS_NUM 1
++
++//-----------------------------------------------
++// Register Map and corresponding constants
++//-----------------------------------------------
++
++
++#define CAPSENSE_REG_STATUS_PORT 0x02
++#define CAPSENSE_REG_OUTPUT_PORT 0x04
++#define CAPSENSE_REG_CS_ENABLE 0x06
++#define CAPSENSE_REG_GPIO_ENABLE 0x08
++#define CAPSENSE_REG_INVERSION_MASK 0x0A
++#define CAPSENSE_REG_INT_MASK 0x0C
++#define CAPSENSE_REG_STATUS_HOLD_MSK 0x0E
++#define CAPSENSE_REG_DRIVE_MODE 0x10
++#define CAPSENSE_REG_OP_SEL_0 0x1C
++#define CAPSENSE_REG_OP_SEL_1 0x35
++#define CAPSENSE_REG_CS_NOISE_TH 0x4E
++#define CAPSENSE_REG_CS_SETL_TIME 0x50
++#define CAPSENSE_REG_CS_OTH_SET 0x51
++#define CAPSENSE_REG_CS_HYSTERESIS 0x52
++#define CAPSENSE_REG_CS_DEBOUNCE 0x53
++#define CAPSENSE_REG_CS_NEG_NOISE_TH 0x54
++#define CAPSENSE_REG_CS_SCAN_POS 0x57
++#define CAPSENSE_REG_CS_FINGER_TH 0x61
++#define CAPSENSE_REG_CS_IDAC 0x6B
++#define CAPSENSE_REG_CS_SLID_CONFIG 0x75
++#define CAPSENSE_REG_CS_SLID_MUL 0x77
++#define CAPSENSE_REG_I2C_DEV_LOCK 0x79
++#define CAPSENSE_REG_DEVICE_ID 0x7A
++#define CAPSENSE_REG_I2C_ADDR_DM 0x7C
++#define CAPSENSE_REG_SLEEP_PIN 0x7E
++#define CAPSENSE_REG_SLEEP_CTRL 0x7F
++#define CAPSENSE_REG_SLEEP_SA_CTR 0x80
++#define CAPSENSE_REG_CS_READ_BUTTON 0x81
++#define CAPSENSE_REG_CS_READ_BL 0x82
++#define CAPSENSE_REG_READ_STATUS 0x88
++#define CAPSENSE_REG_READ_CEN_POS 0x8A
++
++#define CAPSENSE_COMMAND_REG 0xA0
++
++#define CAPSENSE_CMD_STORE_TO_NVM 0x01
++#define CAPSENSE_CMD_NORMAL_OPERATION_MODE 0x07
++#define CAPSENSE_CMD_SETUP_OPERATION_MODE 0x08
++
++#endif /* _CAPSENSE_H_ */
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h
+@@ -407,6 +407,13 @@
+ #define CFG_DTT_MAX_TEMP 70
+ #define CFG_DTT_MIN_TEMP -30
+
++/*Capsense touch sensing buttons (Cpe board)*/
++#define CONFIG_CMD_CAPSENSE
++#define CONFIG_CAPSENSE_CY8C201XX 1
++#define CONFIG_CAPSENSE_I2C_ADDRESS 0x25
++#define CONFIG_CAPSENSE_LEDS {0x02,0x0F} // port 0-{1} port 1-{0,1,2,3}
++#define CONFIG_CAPSENSE_SENSORS {0x1D,0x10} // port 0-{0,2,3,4} port 1-{4}
++
+ /*
+ * Miscellaneous configurable options
+ */
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch b/packages/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch
new file mode 100644
index 0000000000..faa8a3a0be
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch
@@ -0,0 +1,157 @@
+Index: u-boot-1.3.2/drivers/net/tsec.c
+===================================================================
+--- u-boot-1.3.2.orig/drivers/net/tsec.c 2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/net/tsec.c 2009-01-07 15:09:40.000000000 +0100
+@@ -179,6 +179,12 @@
+ priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
+ priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+
++ /* Init MACCFG2 */
++ priv->regs->maccfg2 = MACCFG2_INIT_SETTINGS;
++
++ /* Init ECNTRL */
++ priv->regs->ecntrl = ECNTRL_INIT_SETTINGS;
++
+ #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
+@@ -204,7 +210,7 @@
+ /* Make sure the controller is stopped */
+ tsec_halt(dev);
+
+- /* Init MACCFG2. Defaults to GMII */
++ /* Init MACCFG2 */
+ regs->maccfg2 = MACCFG2_INIT_SETTINGS;
+
+ /* Init ECNTRL */
+@@ -868,7 +874,11 @@
+ if(priv->phyinfo)
+ phy_run_commands(priv, priv->phyinfo->startup);
+
++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY
++ priv->link = 1;
++#else
+ adjust_link(dev);
++#endif
+
+ /* Enable Transmit and Receive */
+ regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
+@@ -1318,6 +1328,21 @@
+ }
+ };
+
++/* a non-manageable PHY interface */
++struct phy_info phy_info_null = {
++ 0,
++ "Non-manageable PHY",
++ 0,
++ (struct phy_cmd[]) { /* config */
++ {miim_end,}
++ },
++ (struct phy_cmd[]) { /* startup */
++ {miim_end,}
++ },
++ (struct phy_cmd[]) { /* shutdown */
++ {miim_end,}
++ }
++};
+
+ uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
+ {
+@@ -1473,6 +1498,10 @@
+ */
+ struct phy_info *get_phy_info(struct eth_device *dev)
+ {
++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY
++ debug("%s: Using non-manageable PHY interface\n", dev->name);
++ return &phy_info_null;
++#else
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ uint phy_reg, phy_ID;
+ int i;
+@@ -1503,6 +1532,7 @@
+ }
+
+ return theInfo;
++#endif // CONFIG_TSEC_NON_MANAGEABLE_PHY
+ }
+
+ /* Execute the given series of commands on the given device's
+Index: u-boot-1.3.2/drivers/net/tsec.h
+===================================================================
+--- u-boot-1.3.2.orig/drivers/net/tsec.h 2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/net/tsec.h 2009-01-07 15:09:40.000000000 +0100
+@@ -56,11 +56,11 @@
+ #define MACCFG1_SYNCD_TX_EN 0x00000002
+ #define MACCFG1_TX_EN 0x00000001
+
+-#define MACCFG2_INIT_SETTINGS 0x00007205
+ #define MACCFG2_FULL_DUPLEX 0x00000001
+ #define MACCFG2_IF 0x00000300
+ #define MACCFG2_GMII 0x00000200
+ #define MACCFG2_MII 0x00000100
++#define MACCFG2_INIT_SETTINGS (0x00007005 | MACCFG2_MII)
+
+ #define ECNTRL_INIT_SETTINGS 0x00001000
+ #define ECNTRL_TBI_MODE 0x00000020
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2009-01-07 15:09:39.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2009-01-07 15:11:17.000000000 +0100
+@@ -246,8 +246,8 @@
+ #define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+-#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
+-#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
++#define CFG_NS16550_COM1 (CFG_IMMR+0x4600)
++#define CFG_NS16550_COM2 (CFG_IMMR+0x4500)
+
+ /* Use the HUSH parser */
+ #define CFG_HUSH_PARSER
+@@ -302,6 +302,7 @@
+ * TSEC configuration
+ */
+ #define CONFIG_TSEC_ENET /* TSEC ethernet support */
++#define CONFIG_TSEC_NON_MANAGEABLE_PHY /* Non-manageable PHY interface */
+
+ #ifndef CONFIG_NET_MULTI
+ #define CONFIG_NET_MULTI 1
+@@ -313,12 +314,12 @@
+ #define CONFIG_TSEC1_NAME "TSEC0"
+ #define CONFIG_TSEC2 1
+ #define CONFIG_TSEC2_NAME "TSEC1"
+-#define TSEC1_PHY_ADDR 0x1c
+-#define TSEC2_PHY_ADDR 4
+-#define TSEC1_FLAGS TSEC_GIGABIT
+-#define TSEC2_FLAGS TSEC_GIGABIT
++#define TSEC1_PHY_ADDR 0 //0x1c
++#define TSEC2_PHY_ADDR 0 //4
++#define TSEC1_FLAGS TSEC_REDUCED //TSEC_GIGABIT
++#define TSEC2_FLAGS TSEC_REDUCED //TSEC_GIGABIT
+ #define TSEC1_PHYIDX 0
+-#define TSEC2_PHYIDX 0
++#define TSEC2_PHYIDX 1 //0
+
+ /* Options are: TSEC[0-1] */
+ #define CONFIG_ETHPRIME "TSEC1"
+@@ -472,8 +473,8 @@
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+- HRCWH_TSEC1M_IN_RGMII |\
+- HRCWH_TSEC2M_IN_RGMII |\
++ HRCWH_TSEC1M_IN_MII |\
++ HRCWH_TSEC2M_IN_MII |\
+ HRCWH_BIG_ENDIAN |\
+ HRCWH_LALE_NORMAL)
+
+@@ -482,7 +483,7 @@
+ #define CFG_WATCHDOG_VALUE 0xFFFF
+
+ /* System IO Config */
+-#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
++#define CFG_SICRH 0 //(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+ #define CFG_SICRL (SICRL_USBDR |SICRL_LBC) /* Enable Internal USB Phy */
+
+ #define CFG_HID0_INIT 0x000000000
diff --git a/packages/u-boot/u-boot_1.3.2.bb b/packages/u-boot/u-boot_1.3.2.bb
index 3df4c17969..003838a670 100644
--- a/packages/u-boot/u-boot_1.3.2.bb
+++ b/packages/u-boot/u-boot_1.3.2.bb
@@ -2,7 +2,7 @@ require u-boot.inc
DEFAULT_PREFERENCE = "-1"
-PR = "r8"
+PR = "r9"
SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2"
@@ -22,12 +22,12 @@ SRC_URI_append_boc01 = "\
file://mpc8313e-rdb-nand.patch;patch=1 \
file://mpc8313e-rdb-mtdparts.patch;patch=1 \
file://mpc8313e-rdb-eeprom.patch;patch=1 \
- file://001-081209-SPI.patch;patch=1 \
+ file://001-090115-SPI.patch;patch=1 \
file://002-081212-GPIO.patch;patch=1 \
file://003-081205-DTT_LM73.patch;patch=1 \
file://006-081211-EEPROM_M24C32.patch;patch=1 \
- file://007-081212-CAPSENSE.patch;patch=1 \
- file://008-081211-TSEC.patch;patch=1 \
+ file://007-090112-CAPSENSE.patch;patch=1 \
+ file://008-090107-TSEC.patch;patch=1 \
file://009-081212-EXIO.patch;patch=1 \
file://010-081212-LCD.patch;patch=1 \
file://011-081211-CMD_TEST.patch;patch=1 \
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 19:43:55 +0000