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-rw-r--r--packages/ixp4xx/ixp-osal-2.0/le.patch340
-rw-r--r--packages/ixp4xx/ixp-osal_2.0.bb3
-rw-r--r--packages/ixp4xx/ixp4xx-csr-2.0/le.patch696
-rw-r--r--packages/ixp4xx/ixp4xx-csr_2.0.bb3
4 files changed, 1040 insertions, 2 deletions
diff --git a/packages/ixp4xx/ixp-osal-2.0/le.patch b/packages/ixp4xx/ixp-osal-2.0/le.patch
new file mode 100644
index 0000000000..c941bbc318
--- /dev/null
+++ b/packages/ixp4xx/ixp-osal-2.0/le.patch
@@ -0,0 +1,340 @@
+diff -bBdurN hannes/ixp_osal/include/IxOsalAssert.h merged/ixp_osal/include/IxOsalAssert.h
+--- ixp_osal/include/IxOsalAssert.h 2005-04-17 20:56:26.000000000 -0700
++++ ixp_osal/include/IxOsalAssert.h 2005-10-07 15:08:43.119207986 -0700
+@@ -70,6 +70,9 @@
+ * This will be conditionally compiled out and
+ * may be used for test purposes.
+ */
++#ifndef __ARMEB__
++#define IX_OSAL_ENSURE_ON
++#endif /* ! __ARMEB__ */
+ #ifdef IX_OSAL_ENSURE_ON
+ #define IX_OSAL_ENSURE(c, str) do { \
+ if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
+@@ -79,5 +82,14 @@
+ #define IX_OSAL_ENSURE(c, str)
+ #endif
+
++#ifndef __ARMEB__
++#ifdef DEBUG_ACDC
++#define TRACE() printk("ixp400: %s(): line %d\n", __FUNCTION__, __LINE__)
++#define PRINTK(args...) printk(args...)
++#else
++#define TRACE() while (0) {}
++#define PRINTK(args...) while (0) {}
++#endif
++#endif /* ! __ARMEB__ */
+
+ #endif /* IX_OSAL_ASSERT_H */
+diff -bBdurN hannes/ixp_osal/include/modules/ioMem/IxOsalMemAccess.h merged/ixp_osal/include/modules/ioMem/IxOsalMemAccess.h
+--- ixp_osal/include/modules/ioMem/IxOsalMemAccess.h 2005-04-17 20:56:25.000000000 -0700
++++ ixp_osal/include/modules/ioMem/IxOsalMemAccess.h 2005-10-07 15:08:43.115207734 -0700
+@@ -84,7 +84,12 @@
+
+ #elif defined (IX_OSAL_LINUX_LE)
+
++#ifndef __ARMEB__
++//#define IX_SDRAM_LE_DATA_COHERENT
++#define IX_SDRAM_LE_ADDRESS_COHERENT
++#else /* __ARMEB__ */
+ #define IX_SDRAM_LE_DATA_COHERENT
++#endif /* __ARMEB__ */
+
+ #elif defined (IX_OSAL_WINCE_LE)
+
+@@ -232,7 +237,11 @@
+ Redefine per OS if dynamic memory maps are used
+ and I/O memory is accessed via functions instead of raw pointer access. */
+
++#ifndef __ARMEB__
++#define IX_OSAL_READ_LONG_COOKIE(wCookie) (BARF; readl((UINT32) (wCookie) ))
++#else /* __ARMEB__ */
+ #define IX_OSAL_READ_LONG_COOKIE(wCookie) (readl((UINT32) (wCookie) ))
++#endif /* __ARMEB__ */
+ #define IX_OSAL_READ_SHORT_COOKIE(sCookie) (readw((UINT32) (sCookie) ))
+ #define IX_OSAL_READ_BYTE_COOKIE(bCookie) (readb((UINT32) (bCookie) ))
+ #define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (writel(wData, (UINT32) (wCookie) ))
+@@ -343,7 +352,11 @@
+ #include <asm/io.h>
+ #endif /* ndef __wince */
+
++#ifndef __ARMEB__
++#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr); BARF;
++#else /* __ARMEB__ */
+ #define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr)
++#endif /* __ARMEB__ */
+ #define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_COOKIE(sAddr)
+ #define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_COOKIE(bAddr)
+ #define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
+diff -bBdurN hannes/ixp_osal/os/linux/include/core/IxOsalOs.h merged/ixp_osal/os/linux/include/core/IxOsalOs.h
+--- ixp_osal/os/linux/include/core/IxOsalOs.h 2005-10-07 09:29:02.388729473 -0700
++++ ixp_osal/os/linux/include/core/IxOsalOs.h 2005-10-07 15:08:43.127208490 -0700
+@@ -53,10 +53,16 @@
+ #error "Uncached memory not supported in linux environment"
+ #endif
+
++#ifndef __ARMEB__
++#include <linux/config.h>
++#include <linux/version.h>
++#endif /* ! __ARMEB__ */
+ #include <linux/cache.h>
+ #include <linux/mm.h>
++#ifdef __ARMEB__
+ #include <linux/config.h>
+ #include <linux/version.h>
++#endif /* __ARMEB__ */
+ #include <asm/pgalloc.h>
+
+ /**
+@@ -67,21 +73,41 @@
+
+ #define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr) ((addr) ? phys_to_virt((unsigned int)(addr)) : 0)
+
++
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++#ifndef __ARMEB__
++extern void ix_dcache_invalidate_range(unsigned long start, unsigned long size)
++;
++extern void ix_dcache_flush_range(unsigned long start, unsigned long size);
++
++#else /* __ARMEB__ */
+ /*
+ * 2.6 kernels do not export the required cache functions.
+ */
+ extern void ixOsalCacheInvalidateRange(unsigned long start, unsigned long size);
+ extern void ixOsalCacheFlushRange(unsigned long start, unsigned long size);
++#endif /* __ARMEB__ */
+
++#ifndef __ARMEB__
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) ( ix_dcache_invalidate_range((__u32)addr, (__u32)addr + size ))
++#else /* __ARMEB__ */
+ #define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) \
+ ixOsalCacheInvalidateRange((unsigned long)addr, (unsigned long)addr + size)
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) \
+ ixOsalCacheFlushRange((unsigned long)addr, (unsigned long)addr + size )
++#endif /* __ARMEB__ */
+
++#ifndef __ARMEB__
++#define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( ix_dcache_flush_range((__u32)addr, (__u32)addr + size ))
++#endif /* ! __ARMEB__ */
+ #else
++#ifndef __ARMEB__
++#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) ( invalidate_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* ! __ARMEB__ */
+
++#ifdef __ARMEB__
+ #define IX_OSAL_OS_CACHE_INVALIDATE(addr, size) ( invalidate_dcache_range((__u32)addr, (__u32)addr + size ))
++#endif /* __ARMEB__ */
+ #define IX_OSAL_OS_CACHE_FLUSH(addr, size) ( clean_dcache_range((__u32)addr, (__u32)addr + size ))
+ #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
+
+diff -bBdurN hannes/ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h merged/ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h
+--- ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h 2005-10-07 09:29:02.392729725 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400.h 2005-10-07 15:08:43.147209748 -0700
+@@ -110,6 +149,9 @@
+ #define IX_OSAL_IXP400_NPEB_VIRT_BASE IXP425_NPEB_BASE_VIRT
+ #define IX_OSAL_IXP400_NPEC_VIRT_BASE IXP425_NPEC_BASE_VIRT
+ #define IX_OSAL_IXP400_PERIPHERAL_VIRT_BASE IXP425_PERIPHERAL_BASE_VIRT
++#ifndef __ARMEB__
++#define IX_OSAL_IXP400_QMGR_VIRT_BASE IXP425_QMGR_BASE_VIRT
++#endif /* ! __ARMEB__ */
+ #define IX_OSAL_IXP400_OSTS_VIRT_BASE IXP425_TIMER_BASE_VIRT
+ #define IX_OSAL_IXP400_USB_VIRT_BASE IXP425_USB_BASE_VIRT
+ #define IX_OSAL_IXP400_EXP_CFG_VIRT_BASE IXP425_EXP_CFG_BASE_VIRT
+diff -bBdurN hannes/ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h merged/ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h
+--- ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h 2005-04-17 20:56:27.000000000 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/IxOsalOsIxp400CustomizedMapping.h 2005-10-07 15:08:43.147209748 -0700
+@@ -171,7 +171,12 @@
+ ***************************/
+ #if (IX_COMPONENT_NAME == ix_qmgr)
+
++#ifndef __ARMEB__
++//#define IX_OSAL_LE_DC_MAPPING
++#define IX_OSAL_LE_AC_MAPPING
++#else /* __ARMEB__ */
+ #define IX_OSAL_LE_DC_MAPPING
++#endif /* __ARMEB__ */
+
+ #endif /* qmgr */
+
+diff -bBdurN hannes/ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h merged/ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h
+--- ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h 2005-10-07 09:29:02.392729725 -0700
++++ ixp_osal/os/linux/include/platforms/ixp400/ixp425/IxOsalOsIxp425Sys.h 2005-10-07 15:08:43.143209496 -0700
+@@ -85,6 +85,17 @@
+ * Queue Manager
+ */
+ {
++#ifndef __ARMEB__
++ IX_OSAL_DYNAMIC_MAP, /* type */
++ IX_OSAL_IXP400_QMGR_PHYS_BASE, /* physicalAddress */
++ IX_OSAL_IXP400_QMGR_MAP_SIZE, /* size */
++ 0,
++ ixOsalLinuxMemMap, /* mapFunction */
++ ixOsalLinuxMemUnmap, /* unmapFunction */
++ 0,
++ IX_OSAL_BE | IX_OSAL_LE_AC, /* endianType */
++ "qMgr" /* name */
++#else /* __ARMEB__ */
+ #ifdef IXP425_QMGR_BASE_VIRT
+ IX_OSAL_STATIC_MAP, /* type */
+ IX_OSAL_IXP400_QMGR_PHYS_BASE, /* physicalAddress */
+@@ -103,6 +114,7 @@
+ 0, /* refCount */
+ IX_OSAL_BE | IX_OSAL_LE_DC, /* endianType */
+ "qMgr" /* name */
++#endif /* __ARMEB__ */
+ },
+
+ /*
+diff -bBdurN hannes/ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c merged/ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c
+--- ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c 2005-10-07 09:29:02.388729473 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsCacheMMU.c 2005-10-07 15:08:43.159210503 -0700
+@@ -210,6 +210,7 @@
+ free_pages ((unsigned int) memptr, order);
+ }
+ }
++#ifdef __ARMEB__
+
+
+ /*
+@@ -266,3 +267,4 @@
+ #undef IX_CLM
+
+ #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) */
++#endif /* __ARMEB__ */
+diff -bBdurN hannes/ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c merged/ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c
+--- ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c 2005-10-07 09:29:02.388729473 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsMsgQ.c 2005-10-07 15:08:43.159210503 -0700
+@@ -48,6 +48,9 @@
+ #include <linux/spinlock.h>
+ #include <linux/ipc.h>
+ #include <linux/msg.h>
++#ifndef __ARMEB__
++#include <linux/spinlock.h>
++#endif /* ! __ARMEB__ */
+ #include <linux/interrupt.h>
+
+ #include "IxOsal.h"
+diff -bBdurN hannes/ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c merged/ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c
+--- ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c 2005-10-07 09:29:02.388729473 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsSemaphore.c 2005-10-07 15:08:43.163210755 -0700
+@@ -46,6 +46,9 @@
+ */
+
+ #include <linux/slab.h>
++#ifndef __ARMEB__
++//#include <asm-arm/hardirq.h>
++#endif /* ! __ARMEB__ */
+ #include <linux/hardirq.h>
+ #include "IxOsal.h"
+
+@@ -93,7 +96,11 @@
+ {
+
+ IX_STATUS ixStatus = IX_SUCCESS;
++#ifndef __ARMEB__
++ UINT32 timeoutTime;
++#else /* __ARMEB__ */
+ unsigned long timeoutTime;
++#endif /* __ARMEB__ */
+
+ if (sid == NULL)
+ {
+diff -bBdurN hannes/ixp_osal/os/linux/src/core/IxOsalOsServices.c merged/ixp_osal/os/linux/src/core/IxOsalOsServices.c
+--- ixp_osal/os/linux/src/core/IxOsalOsServices.c 2005-10-07 09:29:02.392729725 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsServices.c 2005-10-07 15:08:43.163210755 -0700
+@@ -90,8 +89,12 @@
+ /*
+ * General interrupt handler
+ */
++#ifndef __ARMEB__
++static irqreturn_t ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
++#else /* __ARMEB__ */
+ static irqreturn_t
+ ixOsalOsIsrProxy (int irq, void *dev_id, struct pt_regs *regs)
++#endif /* __ARMEB__ */
+ {
+ IxOsalInfoType *isr_proxy_info = (IxOsalInfoType *) dev_id;
+
+@@ -197,12 +200,20 @@
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+ unsigned long flags;
+ local_irq_save(flags);
++#ifndef __ARMEB__
++ return (int)flags;
++#endif /* __ARMEB__ */
+ #else
+ UINT32 flags;
+ save_flags (flags);
+ cli ();
++#ifndef __ARMEB__
++ return flags;
++#endif /* ! __ARMEB__ */
+ #endif
++#ifdef __ARMEB__
+ return (UINT32)flags;
++#endif /* __ARMEB__ */
+ }
+
+ /* Enable interrupts and task scheduling,
+@@ -212,11 +223,15 @@
+ PUBLIC void
+ ixOsalIrqUnlock (UINT32 lockKey)
+ {
+-# if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++#ifndef __ARMEB__
++ local_irq_restore(lockKey);
++#else /* __ARMEB__ */
+ local_irq_restore((unsigned long)lockKey);
+-# else
++#endif /* __ARMEB__ */
++#else
+ restore_flags (lockKey);
+-# endif
++#endif
+ }
+
+ PUBLIC UINT32
+@@ -341,7 +356,11 @@
+ PUBLIC void
+ ixOsalSleep (UINT32 milliseconds)
+ {
++#ifndef __ARMEB__
++ if (milliseconds != 0)
++#else /* __ARMEB__ */
+ if (milliseconds*HZ >= 1000)
++#endif /* __ARMEB__ */
+ {
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout ((milliseconds * HZ) / 1000);
+diff -bBdurN hannes/ixp_osal/os/linux/src/core/IxOsalOsSymbols.c merged/ixp_osal/os/linux/src/core/IxOsalOsSymbols.c
+--- ixp_osal/os/linux/src/core/IxOsalOsSymbols.c 2005-10-07 09:29:02.388729473 -0700
++++ ixp_osal/os/linux/src/core/IxOsalOsSymbols.c 2005-10-07 15:08:43.167211007 -0700
+@@ -64,10 +64,12 @@
+
+ EXPORT_SYMBOL (ixOsalCacheDmaMalloc);
+ EXPORT_SYMBOL (ixOsalCacheDmaFree);
++#ifdef __ARMEB__
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
+ EXPORT_SYMBOL (ixOsalCacheInvalidateRange);
+ EXPORT_SYMBOL (ixOsalCacheFlushRange);
+ #endif
++#endif /* __ARMEB__ */
+
+ EXPORT_SYMBOL (ixOsalThreadCreate);
+ EXPORT_SYMBOL (ixOsalThreadStart);
+diff -bBdurN hannes/ixp_osal/include/modules/ioMem/IxOsalIoMem.h merged/ixp_osal/include/modules/ioMem/IxOsalIoMem.h
+--- ixp_osal/include/modules/ioMem/IxOsalIoMem.h 2005-04-17 20:56:25.000000000 -0700
++++ ixp_osal/include/modules/ioMem/IxOsalIoMem.h 2005-10-07 16:20:27.786083595 -0700
+@@ -105,8 +105,8 @@
+ #endif /* ndef __wince */
+
+ #define IX_OSAL_SWAP_SHORT(sData) ((sData >> 8) | ((sData & 0xFF) << 8))
+-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
+-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr) ((bAddr) ^ 0x3)
++#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((UINT16*)((UINT32)(sAddr) ^ 0x2))
++#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr) ((UINT8*)((UINT32)(bAddr) ^ 0x3))
+
+ #define IX_OSAL_BE_XSTOBUSL(wData) (wData)
+ #define IX_OSAL_BE_XSTOBUSS(sData) (sData)
diff --git a/packages/ixp4xx/ixp-osal_2.0.bb b/packages/ixp4xx/ixp-osal_2.0.bb
index 68ead18215..828cc025ff 100644
--- a/packages/ixp4xx/ixp-osal_2.0.bb
+++ b/packages/ixp4xx/ixp-osal_2.0.bb
@@ -21,8 +21,9 @@ LICENSE_HOMEPAGE = "http://www.intel.com/design/network/products/npfamily/ixp425
SRC_URI = "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400AccessLibrary-2_0.zip"
SRC_URI += "file://Makefile.patch;patch=1"
SRC_URI += "file://2.6.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
S = "${WORKDIR}/ixp_osal"
-PR = "r1"
+PR = "r2"
COMPATIBLE_HOST = "^arm.*-linux.*"
diff --git a/packages/ixp4xx/ixp4xx-csr-2.0/le.patch b/packages/ixp4xx/ixp4xx-csr-2.0/le.patch
new file mode 100644
index 0000000000..f1f0e09ff8
--- /dev/null
+++ b/packages/ixp4xx/ixp4xx-csr-2.0/le.patch
@@ -0,0 +1,696 @@
+diff -bBdurN hannes/ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h merged/ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h
+--- ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h 2005-10-07 09:28:48.147833350 -0700
++++ ixp400_xscale_sw/src/codelets/dmaAcc/IxDmaAccCodelet_p.h 2005-10-07 15:08:42.343159153 -0700
+@@ -113,7 +113,11 @@
+ * @return IX_FAIL - Error initialising codelet
+ */
+ IX_STATUS
++#ifndef __ARMEB__
++ixDmaAccCodeletInit(IxDmaNpeId npeId);
++#else /* __ARMEB__ */
+ ixDmaAccCodeletInit(IxNpeDlNpeId npeId);
++#endif /* __ARMEB__ */
+
+ /**
+ * @fn ixDmaAccCodeletTestPerform( UINT16 transferLength,
+diff -bBdurN hannes/ixp400_xscale_sw/src/ethAcc/IxEthAccDataPlane.c merged/ixp400_xscale_sw/src/ethAcc/IxEthAccDataPlane.c
+--- ixp400_xscale_sw/src/ethAcc/IxEthAccDataPlane.c 2005-04-17 20:55:12.000000000 -0700
++++ ixp400_xscale_sw/src/ethAcc/IxEthAccDataPlane.c 2005-10-07 15:08:42.511169725 -0700
+@@ -59,6 +59,16 @@
+ #include "IxEthAcc_p.h"
+ #include "IxEthAccQueueAssign_p.h"
+
++#ifndef __ARMEB__
++#ifdef DEBUG_ACDC
++#define TRACE printk("%s: %s(): line %d\n", "IxEth", __FUNCTION__, __LINE__)
++#define PRINTK(args...) printk(args)
++#else
++#define TRACE while (0) {}
++#define PRINTK(args...) while (0) {}
++#endif
++
++#endif /* ! __ARMEB__ */
+ extern PUBLIC IxEthAccMacState ixEthAccMacState[];
+ extern PUBLIC UINT32 ixEthAccNewSrcMask;
+
+@@ -252,7 +262,13 @@
+
+ if (qEntry != 0)
+ {
++#ifndef __ARMEB__
++ PRINTK("qEntry = %p %d ",qEntry, mask);
++#endif /* ! __ARMEB__ */
+ /* mask NPE bits (e.g. priority, port ...) */
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ qEntry &= mask;
+
+ #if IX_ACC_DRAM_PHYS_OFFSET != 0
+@@ -270,6 +286,14 @@
+
+ /* preload the cacheline used by xscale */
+ IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
++#ifndef __ARMEB__
++ PRINTK("%p\n", mbufPtr );
++
++#if 0
++ {int junk = *(int*)mbufPtr;
++ printk("j=%d\n", junk);}
++#endif
++#endif /* ! __ARMEB__ */
+ }
+ else
+ {
+@@ -506,15 +530,30 @@
+ ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
+ {
+ UINT32 len;
++#ifndef __ARMEB__
++ TRACE;
++ PRINTK("mbuf=%p\n", mbuf);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* endianess swap for tci and flags
+ note: this is done only once, even for chained buffers */
+ IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* test for unchained mbufs */
+ if (IX_ETHACC_NE_NEXT(mbuf) == 0)
+ {
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ /* unchained mbufs */
+ IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
+
+@@ -531,11 +570,19 @@
+ IX_OSAL_MBUF *ptr = mbuf;
+ IX_OSAL_MBUF *nextPtr;
+ UINT32 frmLen;
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* convert the frame length */
+ frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
+ IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
++#ifndef __ARMEB__
++ PRINTK("frm len %d\n", frmLen);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* chained mbufs */
+ do
+ {
+@@ -547,6 +594,9 @@
+
+ /* get the next pointer */
+ PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
++#ifndef __ARMEB__
++ PRINTK("nextptr %p\n", nextPtr);
++#endif /* ! __ARMEB__ */
+ if (nextPtr != NULL)
+ {
+ nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
+@@ -558,6 +608,9 @@
+ ptr = nextPtr;
+ }
+ while (ptr != NULL);
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ }
+ }
+
+@@ -1449,7 +1502,11 @@
+ {
+ UINT32 flags;
+ IxEthDBStatus result;
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ #ifndef NDEBUG
+ /* Prudent to at least check the port is within range */
+ if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
+@@ -1461,18 +1518,33 @@
+ return FALSE;
+ }
+ #endif
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* convert fields from mbuf header */
+ ixEthAccMbufFromRxQ(mbufPtr);
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* check about any special processing for this frame */
+ flags = IX_ETHACC_NE_FLAGS(mbufPtr);
+ if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
+ {
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ /* "best case" scenario : nothing special to do for this frame */
+ return TRUE;
+ }
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* if a new source MAC address is detected by the NPE,
+ * update IxEthDB with the portId and the MAC address.
+ */
+@@ -1501,7 +1573,11 @@
+ RX_STATS_INC(portId, rxUnlearnedMacAddress);
+ }
+ }
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* check if this frame should have been filtered
+ * by the NPE and take the appropriate action
+ */
+@@ -1542,7 +1618,11 @@
+ /* indicate that frame should not be subjected to further processing */
+ return FALSE;
+ }
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ return TRUE;
+ }
+
+@@ -1588,6 +1668,9 @@
+ */
+ IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
+
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ do
+ {
+ /*
+@@ -1602,7 +1685,12 @@
+ rxQReadStatus = ixQMgrQBurstRead(qId,
+ IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
+ qEntryPtr);
++#ifndef __ARMEB__
++ // TRACE;
++ PRINTK("rxQReadStatus = %d\n", rxQReadStatus);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ #ifndef NDEBUG
+ if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
+ && (rxQReadStatus != IX_SUCCESS))
+@@ -1623,9 +1711,16 @@
+ nextQEntry = *qEntryPtr;
+ nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
+ IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
++#ifndef __ARMEB__
++ // TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ while(nextQEntry != 0)
+ {
++#ifndef __ARMEB__
++ int res;
++#endif /* ! __ARMEB__ */
+ /* get the next entry */
+ qEntry = nextQEntry;
+ mbufPtr = nextMbufPtr;
+@@ -1648,7 +1743,11 @@
+ nextQEntry = *(++qEntryPtr);
+ nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
+ IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /*
+ * Get Port and Npe ID from message.
+ */
+@@ -1659,7 +1758,12 @@
+ /* process frame, check the return code and skip the remaining of
+ * the loop if the frame is to be filtered out
+ */
++#ifndef __ARMEB__
++ res = ixEthRxFrameProcess(portId, mbufPtr);
++ if (res)
++#else /* __ARMEB__ */
+ if (ixEthRxFrameProcess(portId, mbufPtr))
++#endif /* __ARMEB__ */
+ {
+ /* destination portId for this packet */
+ destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
+@@ -1682,7 +1786,11 @@
+ callbackId);
+ }
+ }
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /*
+ * increment priority stats
+ */
+@@ -1696,6 +1804,9 @@
+ /*
+ * Call user level callback.
+ */
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
+ ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
+ mbufPtr,
+@@ -1703,6 +1814,9 @@
+ }
+ }
+ } while (rxQReadStatus == IX_SUCCESS);
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ }
+
+ /**
+@@ -2092,10 +2206,19 @@
+
+ do{
+ qEntryPtr = txDoneQEntry;
++#ifndef __ARMEB__
++ // TRACE;
++#endif /* ! __ARMEB__ */
+ txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
+ IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
+ qEntryPtr);
++#ifndef __ARMEB__
++ if (txDoneQReadStatus == 0 && qEntryPtr[0] == 0)
++ return;
++ PRINTK("txDoneQReadStatus %d\n", txDoneQReadStatus);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ #ifndef NDEBUG
+ if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
+ && (txDoneQReadStatus != IX_SUCCESS))
+@@ -2113,6 +2236,9 @@
+
+ while(qEntry != 0)
+ {
++#ifndef __ARMEB__
++ TRACE;
++#endif /* ! __ARMEB__ */
+ mbufPtr = ixEthAccEntryFromQConvert(qEntry,
+ IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
+
+@@ -2126,7 +2252,11 @@
+ return;
+ }
+ #endif
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* endianness conversions and stats updates */
+ ixEthAccMbufFromTxQ(mbufPtr);
+
+@@ -2151,14 +2281,22 @@
+ #endif
+
+ TX_STATS_INC(portId,txDoneClientCallback);
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /*
+ * Call user level callback.
+ */
+ ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
+ ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
+ mbufPtr);
++#ifndef __ARMEB__
++ TRACE;
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* move to next queue entry */
+ qEntry = *(++qEntryPtr);
+
+diff -bBdurN hannes/ixp400_xscale_sw/src/ethAcc/IxEthAccMii.c merged/ixp400_xscale_sw/src/ethAcc/IxEthAccMii.c
+--- ixp400_xscale_sw/src/ethAcc/IxEthAccMii.c 2005-04-17 20:55:13.000000000 -0700
++++ ixp400_xscale_sw/src/ethAcc/IxEthAccMii.c 2005-10-07 15:08:42.515169976 -0700
+@@ -94,6 +94,12 @@
+ (mdioCommand >> 24) & 0xff);
+ }
+
++#ifndef __ARMEB__
++#if defined(IX_OSAL_LINUX_LE)
++//#error it is defined
++#endif
++
++#endif /* ! __ARMEB__ */
+ PRIVATE void
+ ixEthAccMdioCmdRead(UINT32 *data)
+ {
+@@ -241,6 +246,9 @@
+
+ while(miiTimeout)
+ {
++#ifndef __ARMEB__
++ ixOsalSleep(ixEthAccMiiAccessTimeout);
++#endif /* ! __ARMEB__ */
+
+ ixEthAccMdioCmdRead(&regval);
+
+@@ -249,7 +257,9 @@
+ break;
+ }
+ /* Sleep for a while */
++#ifdef __ARMEB__
+ ixOsalSleep(ixEthAccMiiAccessTimeout);
++#endif /* __ARMEB__ */
+ miiTimeout--;
+ }
+
+@@ -321,6 +331,9 @@
+
+ while(miiTimeout)
+ {
++#ifndef __ARMEB__
++ ixOsalSleep(ixEthAccMiiAccessTimeout);
++#endif /* ! __ARMEB__ */
+
+ ixEthAccMdioCmdRead(&regval);
+
+@@ -330,7 +343,9 @@
+ break;
+ }
+ /* Sleep for a while */
++#ifdef __ARMEB__
+ ixOsalSleep(ixEthAccMiiAccessTimeout);
++#endif /* __ARMEB__ */
+ miiTimeout--;
+ }
+
+diff -bBdurN hannes/ixp400_xscale_sw/src/ethAcc/include/IxEthAccMac_p.h merged/ixp400_xscale_sw/src/ethAcc/include/IxEthAccMac_p.h
+--- ixp400_xscale_sw/src/ethAcc/include/IxEthAccMac_p.h 2005-04-17 20:56:03.000000000 -0700
++++ ixp400_xscale_sw/src/ethAcc/include/IxEthAccMac_p.h 2005-10-07 15:08:42.467166956 -0700
+@@ -46,7 +46,11 @@
+ #define IxEthAccMac_p_H
+
+ #include "IxOsal.h"
++#ifndef __ARMEB__
++#define BIT(x) (1 << (x))
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ #define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
+ #define IX_ETH_ACC_NUM_PORTS 3
+ #define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
+diff -bBdurN hannes/ixp400_xscale_sw/src/ethMii/IxEthMii.c merged/ixp400_xscale_sw/src/ethMii/IxEthMii.c
+--- ixp400_xscale_sw/src/ethMii/IxEthMii.c 2005-04-17 20:55:18.000000000 -0700
++++ ixp400_xscale_sw/src/ethMii/IxEthMii.c 2005-10-07 15:08:42.575173752 -0700
+@@ -110,6 +110,14 @@
+ /*Need to read the register twice here to flush PHY*/
+ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, &regvalId1);
+ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, &regvalId1);
++#ifndef __ARMEB__
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, &regvalId1);
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, &regvalId1);
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, &regvalId1);
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, &regvalId2);
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, &regvalId2);
++ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, &regvalId2);
++#endif /* ! __ARMEB__ */
+ ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, &regvalId2);
+ ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
+ if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
+diff -bBdurN hannes/ixp400_xscale_sw/src/ethMii/IxEthMii_p.h merged/ixp400_xscale_sw/src/ethMii/IxEthMii_p.h
+--- ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 2005-04-17 20:55:18.000000000 -0700
++++ ixp400_xscale_sw/src/ethMii/IxEthMii_p.h 2005-10-07 15:08:42.579174004 -0700
+@@ -52,7 +52,11 @@
+
+ #ifndef IxEthMii_p_H
+ #define IxEthMii_p_H
++#ifndef __ARMEB__
++#define BIT(x) (1 << (x))
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+
+ /* MII definitions - these have been verified against the LXT971 and
+ LXT972 PHYs*/
+diff -bBdurN hannes/ixp400_xscale_sw/src/include/IxQMgr.h merged/ixp400_xscale_sw/src/include/IxQMgr.h
+--- ixp400_xscale_sw/src/include/IxQMgr.h 2005-04-17 20:55:31.000000000 -0700
++++ ixp400_xscale_sw/src/include/IxQMgr.h 2005-10-07 15:08:42.723183066 -0700
+@@ -96,8 +96,13 @@
+
+ #else
+
++#ifndef __ARMEB__
++#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_AC
++#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_AC
++#else /* __ARMEB__ */
+ #define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
+ #define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
++#endif /* __ARMEB__ */
+
+ #endif
+
+@@ -1340,7 +1345,11 @@
+ {
+ /* get the queue status */
+ UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
++#ifndef __ARMEB__
++ PRINTK("Qstatus %d\n", status);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ if (status & infoPtr->qUflowStatBitMask)
+ {
+ /* clear the underflow status bit if it was set */
+diff -bBdurN hannes/ixp400_xscale_sw/src/include/IxTypes.h merged/ixp400_xscale_sw/src/include/IxTypes.h
+--- ixp400_xscale_sw/src/include/IxTypes.h 2005-10-07 09:28:48.151833601 -0700
++++ ixp400_xscale_sw/src/include/IxTypes.h 2005-10-07 15:08:42.735183821 -0700
+@@ -79,10 +79,12 @@
+ #endif
+ #endif
+
++#ifdef __ARMEB__
+ #ifndef BIT
+ #define BIT(x) ((1)<<(x))
+ #endif
+
++#endif /* __ARMEB__ */
+ #include "IxOsalBackward.h"
+
+ #endif /* IxTypes_H */
+diff -bBdurN hannes/ixp400_xscale_sw/src/osServices/IxOsServices.c merged/ixp400_xscale_sw/src/osServices/IxOsServices.c
+--- ixp400_xscale_sw/src/osServices/IxOsServices.c 2005-04-17 20:55:38.000000000 -0700
++++ ixp400_xscale_sw/src/osServices/IxOsServices.c 2005-10-07 15:08:42.827189611 -0700
+@@ -172,3 +172,61 @@
+ ixOsalYield ();
+ }
+
++#ifndef __ARMEB__
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
++
++/*
++ * 2.6 kernels do not export the required cache management routines so
++ * reimplement them here.
++ */
++
++#define _IX_STR(x) #x
++#define IX_STR(x) _IX_STR(x)
++#define IX_CLM IX_STR(IX_XSCALE_CACHE_LINE_SIZE-1)
++
++/*
++ * IX_ACC_DATA_CACHE_INVALIDATE(addr, size)
++ */
++void
++ix_dcache_invalidate_range(unsigned long start, unsigned long size)
++{
++ __asm__
++ (" tst %0, #" IX_CLM "\n"
++ " mcrne p15, 0, %0, c7, c10, 1 @ clean D cache line\n"
++ " bic %0, %0, #" IX_CLM "\n"
++ " tst %1, #" IX_CLM "\n"
++ " mcrne p15, 0, %1, c7, c10, 1 @ clean D cache line\n"
++ "1: mcr p15, 0, %0, c7, c6, 1 @ invalidate D cache line\n"
++ " add %0, %0, #" IX_STR(IX_XSCALE_CACHE_LINE_SIZE) "\n"
++ " cmp %0, %1\n"
++ " blo 1b\n"
++ " mcr p15, 0, %0, c7, c10, 4 @ drain write & fill buffer\n"
++ : /* no output */
++ : "r"(start), "r"(size)
++ : "cc");
++}
++
++/*
++ * IX_ACC_DATA_CACHE_FLUSH(addr, size)
++ */
++void
++ix_dcache_flush_range(unsigned long start, unsigned long size)
++{
++ __asm__
++ (" bic %0, %0, #" IX_CLM "\n"
++ "1: mcr p15, 0, %0, c7, c10, 1 @ clean D cache line\n"
++ " add %0, %0, #" IX_STR(IX_XSCALE_CACHE_LINE_SIZE) "\n"
++ " cmp %0, %1\n"
++ " blo 1b\n"
++ " mcr p15, 0, %0, c7, c10, 4 @ drain write & fill buffer\n"
++ : /* no output */
++ : "r"(start), "r"(size)
++ : "cc");
++}
++
++#undef _IX_STR
++#undef IX_STR
++#undef IX_CLM
++
++#endif
++#endif /* ! __ARMEB__ */
+diff -bBdurN hannes/ixp400_xscale_sw/src/osServices/IxOsServicesSymbols.c merged/ixp400_xscale_sw/src/osServices/IxOsServicesSymbols.c
+--- ixp400_xscale_sw/src/osServices/IxOsServicesSymbols.c 2005-04-17 20:55:39.000000000 -0700
++++ ixp400_xscale_sw/src/osServices/IxOsServicesSymbols.c 2005-10-07 15:08:42.827189611 -0700
+@@ -74,6 +74,11 @@
+ EXPORT_SYMBOL (ixOsServYield);
+ EXPORT_SYMBOL (ixOsalOsIxp400BackwardPoolInit);
+ EXPORT_SYMBOL (ixOsalOsIxp400BackwardMbufPoolGet);
++#ifndef __ARMEB__
++EXPORT_SYMBOL(ix_dcache_invalidate_range);
++EXPORT_SYMBOL(ix_dcache_flush_range);
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ #endif /* __linux */
+
+diff -bBdurN hannes/ixp400_xscale_sw/src/oslinux/IxLinuxInit.c merged/ixp400_xscale_sw/src/oslinux/IxLinuxInit.c
+--- ixp400_xscale_sw/src/oslinux/IxLinuxInit.c 2005-10-07 14:55:03.931659764 -0700
++++ ixp400_xscale_sw/src/oslinux/IxLinuxInit.c 2005-10-07 15:08:42.831189862 -0700
+@@ -99,6 +99,9 @@
+ /* Init and cleanup functions for module */
+ static int __init ixp400_sw_init_module(void)
+ {
++#ifndef __ARMEB__
++ ixOsalLogLevelSet(IX_OSAL_LOG_LVL_ALL);
++#endif /* ! __ARMEB__ */
+ /* Add initialization code here */
+ #ifdef DEBUG
+ printk("\n\n"__FUNCTION__": addr=%p\n\n", ixp400_sw_init_module);
+diff -bBdurN hannes/ixp400_xscale_sw/src/qmgr/IxQMgrInit.c merged/ixp400_xscale_sw/src/qmgr/IxQMgrInit.c
+--- ixp400_xscale_sw/src/qmgr/IxQMgrInit.c 2005-04-17 20:55:44.000000000 -0700
++++ ixp400_xscale_sw/src/qmgr/IxQMgrInit.c 2005-10-07 15:08:42.923195652 -0700
+@@ -84,13 +84,25 @@
+
+ /* Initialise the QCfg component */
+ ixQMgrQCfgInit ();
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* Initialise the Dispatcher component */
+ ixQMgrDispatcherInit ();
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* Initialise the Access component */
+ ixQMgrQAccessInit ();
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* Initialization complete */
+ qMgrIsInitialized = TRUE;
+
+diff -bBdurN hannes/ixp400_xscale_sw/src/qmgr/IxQMgrQCfg.c merged/ixp400_xscale_sw/src/qmgr/IxQMgrQCfg.c
+--- ixp400_xscale_sw/src/qmgr/IxQMgrQCfg.c 2005-04-17 20:55:45.000000000 -0700
++++ ixp400_xscale_sw/src/qmgr/IxQMgrQCfg.c 2005-10-07 15:08:42.931196155 -0700
+@@ -150,7 +150,11 @@
+ ixQMgrQCfgInit (void)
+ {
+ int loopIndex;
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
+ {
+ /* info for code inlining */
+@@ -167,10 +171,18 @@
+ ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
+ ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
+ }
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* Initialise the AqmIf component */
+ ixQMgrAqmIfInit ();
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ /* Reset all queues to have queue name = NULL, entry size = 0 and
+ * isConfigured = false
+ */
+@@ -188,11 +200,23 @@
+
+ /* Statistics */
+ stats.wmSetCnt = 0;
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ ixOsalMutexInit(&ixQMgrQCfgMutex);
++#ifndef __ARMEB__
++ TRACE();
++#else /* __ARMEB__ */
+
++#endif /* __ARMEB__ */
+ cfgInitialized = TRUE;
+ }
+
diff --git a/packages/ixp4xx/ixp4xx-csr_2.0.bb b/packages/ixp4xx/ixp4xx-csr_2.0.bb
index ba0d9ff8e1..49eba4f1e1 100644
--- a/packages/ixp4xx/ixp4xx-csr_2.0.bb
+++ b/packages/ixp4xx/ixp4xx-csr_2.0.bb
@@ -24,9 +24,10 @@ SRC_URI += "http://www.intel.com/Please-Read-The-BB-File/IPL_ixp400NpeLibrary-2_
SRC_URI += "file://Makefile.patch;patch=1"
SRC_URI += "file://2.6.patch;patch=1"
SRC_URI += "file://2.6.14.patch;patch=1"
+SRC_URI += "file://le.patch;patch=1"
DEPENDS = "ixp-osal"
S = "${WORKDIR}/ixp400_xscale_sw"
-PR = "r1"
+PR = "r2"
COMPATIBLE_HOST = "^arm.*-linux.*"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 10:37:09 +0000