diff options
| -rw-r--r-- | recipes/u-boot/u-boot-1.2.0/dm355-leopard.diff | 950 | ||||
| -rw-r--r-- | recipes/u-boot/u-boot_1.2.0.bb | 2 |
2 files changed, 2 insertions, 950 deletions
diff --git a/recipes/u-boot/u-boot-1.2.0/dm355-leopard.diff b/recipes/u-boot/u-boot-1.2.0/dm355-leopard.diff index b614522f42..d37041fb99 100644 --- a/recipes/u-boot/u-boot-1.2.0/dm355-leopard.diff +++ b/recipes/u-boot/u-boot-1.2.0/dm355-leopard.diff @@ -65,8 +65,6 @@ cpu/arm926ejs/config.mk | 4 cpu/arm926ejs/interrupts.c | 148 cpu/arm926ejs/interrupts.c.orig | 191 - doc/README.SBC8560 | 57 - doc/README.sbc8560 | 53 drivers/Makefile | 4 drivers/davinci_i2c.c | 296 drivers/davinci_i2c.h | 87 @@ -159,14 +157,12 @@ include/asm/u-boot.h | 60 include/config.h | 2 include/config.mk | 3 - include/configs/SBC8560.h | 410 - include/configs/davinci.h | 222 include/configs/dm355_evm.h | 227 include/configs/dm355_ipnc.h | 234 include/configs/dm355_leopard.h | 234 include/configs/dm700.h | 204 include/configs/omap2420h4.h | 2 - include/configs/sbc8560.h | 408 + include/flash.h | 2 include/linux/mtd/nand.h | 190 include/linux/mtd/nand_ids.h | 1 @@ -11430,7 +11426,7 @@ diff -Nurd u-boot-1.2.0/board/dm355_leopard/dm355_leopard.c u-boot-1.2.0-leopard +#define PLL1_POSTDIV *(volatile unsigned int *)0x01C40928 +#define PLL1_PLLDIV4 *(volatile unsigned int *)0x01C40960 +#define SYSTEM_MISC *(volatile unsigned int *)0x01C40038 -+#define MACH_DM355_LEOPARD 1381 ++#define MACH_DM355_LEOPARD 2138 + +#define W_SETUP 0x1 //0~f +#define W_STROBE 0x3 //0~3f @@ -19001,124 +18997,6 @@ diff -Nurd u-boot-1.2.0/cpu/arm926ejs/interrupts.c.orig u-boot-1.2.0-leopard/cpu +} + +#endif /* CONFIG_INTEGRATOR */ -diff -Nurd u-boot-1.2.0/doc/README.SBC8560 u-boot-1.2.0-leopard/doc/README.SBC8560 ---- u-boot-1.2.0/doc/README.SBC8560 1969-12-31 21:00:00.000000000 -0300 -+++ u-boot-1.2.0-leopard/doc/README.SBC8560 2007-12-04 07:50:40.000000000 -0300 -@@ -0,0 +1,57 @@ -+The port was tested on Wind River System Sbc8560 board -+<www.windriver.com>. U-Boot was installed on the flash memory of the -+CPU card (no the SODIMM). -+ -+NOTE: Please configure uboot compile to the proper PCI frequency and -+setup the appropriate DIP switch settings. -+ -+SBC8560 board: -+ -+Make sure boards switches are set to their appropriate conditions. -+Refer to the Engineering Reference Guide ERG-00300-002. Of particular -+importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which -+select the on-board FLASH device (Intel 28F128Jx); 2) The settings -+for the Clock SW9 (33 MHz or 66 MHz). -+ -+ Note: SW9 Settings: 66 MHz -+ 4:1 ratio CCB clocks:SYSCLK -+ 3:1 ration e500 Core:CCB -+ pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on -+ Note: SW9 Settings: 33 MHz -+ 8:1 ratio CCB clocks:SYSCLK -+ 3:1 ration e500 Core:CCB -+ pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on -+ -+ -+Flashing the FLASH device with the "Wind River ICE": -+ -+1) Properly connect and configure the Wind River ICE to the target -+ JTAG port. This includes running the SBC8560 register script. Make -+ sure target memory can be read and written. -+ -+2) Build the u-boot image: -+ make distclean -+ make SBC8560_66_config or SBC8560_33_config -+ make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all -+ -+ Note: reference is made to the ELDK3.0 compiler. Further, it seems -+ the ppc_8xx compiler is required for the 85xx (no 85xx -+ designated compiler in ELDK3.0) -+ -+3) Convert the uboot (.elf) file to a uboot.bin file (using -+ visionClick converter). The bin file should be converted from -+ fffc0000 to ffffffff -+ -+4) Setup the Flash Utility (tools menu) for: -+ -+ Do a "dc clr" [visionClick] to load the default register settings -+ Determine the clock speed of the PCI bus and set SW9 accordingly -+ Note: the speed of the PCI bus defaults to the slowest PCI card -+ PlayBack the "default" register file for the SBC8560 -+ Select the uboot.bin file with zero bias -+ Select the initialize Target prior to programming -+ Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm -+ Select the erase base address from FFFC0000 to FFFFFFFF -+ Select the start address from 0 with size of 4000 -+ -+5) Erase and Program -diff -Nurd u-boot-1.2.0/doc/README.sbc8560 u-boot-1.2.0-leopard/doc/README.sbc8560 ---- u-boot-1.2.0/doc/README.sbc8560 2007-01-06 20:13:11.000000000 -0300 -+++ u-boot-1.2.0-leopard/doc/README.sbc8560 1969-12-31 21:00:00.000000000 -0300 -@@ -1,53 +0,0 @@ --The port was tested on Wind River System Sbc8560 board <www.windriver.com>. --U-Boot was installed on the flash memory of the CPU card (no the SODIMM). -- --NOTE: Please configure uboot compile to the proper PCI frequency and --setup the appropriate DIP switch settings. -- --SBC8560 board: -- --Make sure boards switches are set to their appropriate conditions. --Refer to the Engineering Reference Guide ERG-00300-002. Of particular --importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which --select the on-board FLASH device (Intel 28F128Jx); 2) The settings --for the Clock SW9 (33 MHz or 66 MHz). -- -- Note: SW9 Settings: 66 MHz -- 4:1 ratio CCB clocks:SYSCLK -- 3:1 ration e500 Core:CCB -- pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on -- Note: SW9 Settings: 33 MHz -- 8:1 ratio CCB clocks:SYSCLK -- 3:1 ration e500 Core:CCB -- pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on -- -- --Flashing the FLASH device with the "Wind River ICE": -- --1) Properly connect and configure the Wind River ICE to the -- target JTAG port. This includes running the SBC8560 register script. -- Make sure target memory can be read and written. -- --2) Build the u-boot image: -- make distclean -- make SBC8560_66_config or SBC8560_33_config -- make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all -- -- Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler -- should suffice. -- --3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter). -- The bin file should be converted from fffc0000 to ffffffff -- --4) Setup the Flash Utility (tools menu) for: -- -- Determine the clock speed of the PCI bus and set SW9 accordingly -- Note: the speed of the PCI bus defaults to the slowest PCI card -- PlayBack the "default" register file for the SBC8560 -- Select the uboot.bin file with zero bias -- Select the initialize Target prior to programming -- Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm -- Select the erase base address from FFFC0000 to FFFFFFFF -- Select the start address from 0 with size of 4000 -- --5) Erase and Program diff -Nurd u-boot-1.2.0/drivers/Makefile u-boot-1.2.0-leopard/drivers/Makefile --- u-boot-1.2.0/drivers/Makefile 2007-01-06 20:13:11.000000000 -0300 +++ u-boot-1.2.0-leopard/drivers/Makefile 2008-01-05 03:40:50.000000000 -0300 @@ -45550,420 +45428,6 @@ diff -Nurd u-boot-1.2.0/include/config.mk u-boot-1.2.0-leopard/include/config.mk +ARCH = arm +CPU = arm926ejs +BOARD = dm355_leopard -diff -Nurd u-boot-1.2.0/include/configs/SBC8560.h u-boot-1.2.0-leopard/include/configs/SBC8560.h ---- u-boot-1.2.0/include/configs/SBC8560.h 2007-01-06 20:13:11.000000000 -0300 -+++ u-boot-1.2.0-leopard/include/configs/SBC8560.h 1969-12-31 21:00:00.000000000 -0300 -@@ -1,410 +0,0 @@ --/* -- * (C) Copyright 2002,2003 Motorola,Inc. -- * Xianghua Xiao <X.Xiao@motorola.com> -- * -- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. -- * Added support for Wind River SBC8560 board -- * -- * See file CREDITS for list of people who contributed to this -- * project. -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of -- * the License, or (at your option) any later version. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -- * MA 02111-1307 USA -- */ -- --/* mpc8560ads board configuration file */ --/* please refer to doc/README.mpc85xx for more info */ --/* make sure you change the MAC address and other network params first, -- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file -- */ -- --#ifndef __CONFIG_H --#define __CONFIG_H -- --#if XXX --#define DEBUG /* General debug */ --#define ET_DEBUG --#endif --#define TSEC_DEBUG -- --/* High Level Configuration Options */ --#define CONFIG_BOOKE 1 /* BOOKE */ --#define CONFIG_E500 1 /* BOOKE e500 family */ --#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ --#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ -- -- --#define CONFIG_CPM2 1 /* has CPM2 */ --#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ -- --#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ -- --#define CONFIG_TSEC_ENET /* tsec ethernet support */ --#undef CONFIG_PCI /* pci ethernet support */ --#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -- -- --#define CONFIG_ENV_OVERWRITE -- --/* Using Localbus SDRAM to emulate flash before we can program the flash, -- * normally you need a flash-boot image(u-boot.bin), if so undef this. -- */ --#undef CONFIG_RAM_AS_FLASH -- --#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ -- #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ --#else -- #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ --#endif -- --/* below can be toggled for performance analysis. otherwise use default */ --#define CONFIG_L2_CACHE /* toggle L2 cache */ --#undef CONFIG_BTB /* toggle branch predition */ --#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ -- --#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -- --#undef CFG_DRAM_TEST /* memory test, takes time */ --#define CFG_MEMTEST_START 0x00200000 /* memtest region */ --#define CFG_MEMTEST_END 0x00400000 -- --#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ -- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ -- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) --#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." --#endif -- --/* -- * Base addresses -- Note these are effective addresses where the -- * actual resources get mapped (not physical addresses) -- */ --#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -- --#if XXX -- #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ --#else -- #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ --#endif --#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -- --#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ --#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE --#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ --#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ -- --#undef CONFIG_DDR_ECC /* only for ECC DDR module */ --#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -- --#if defined(CONFIG_MPC85xx_REV1) -- #define CONFIG_DDR_DLL /* possible DLL fix needed */ --#endif -- --#undef CONFIG_CLOCKS_IN_MHZ -- --#if defined(CONFIG_RAM_AS_FLASH) -- #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ -- #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ -- #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ -- #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ --#else /* Boot from real Flash */ -- #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ -- #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ -- #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ -- #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ --#endif --#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ -- --/* local bus definitions */ --#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ --#define CFG_OR1_PRELIM 0xfc000ff7 -- --#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ --#define CFG_OR2_PRELIM 0x00000000 -- --#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ --#define CFG_OR3_PRELIM 0xfc000cc1 -- --#if defined(CONFIG_RAM_AS_FLASH) -- #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ --#else -- #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ --#endif --#define CFG_OR4_PRELIM 0xfc000cc1 -- --#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ --#if 1 -- #define CFG_OR5_PRELIM 0xff000ff7 --#else -- #define CFG_OR5_PRELIM 0xff0000f0 --#endif -- --#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ --#define CFG_OR6_PRELIM 0xfc000ff7 --#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ --#define CFG_LBC_LBCR 0x00000000 --#define CFG_LBC_LSRT 0x20000000 --#define CFG_LBC_MRTPR 0x20000000 --#define CFG_LBC_LSDMR_1 0x2861b723 --#define CFG_LBC_LSDMR_2 0x0861b723 --#define CFG_LBC_LSDMR_3 0x0861b723 --#define CFG_LBC_LSDMR_4 0x1861b723 --#define CFG_LBC_LSDMR_5 0x4061b723 -- --/* just hijack the MOT BCSR def for SBC8560 misc devices */ --#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) --/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ -- --#define CONFIG_L1_INIT_RAM --#define CFG_INIT_RAM_LOCK 1 --#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ --#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -- --#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ --#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) --#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -- --#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ --#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ -- --/* Serial Port */ --#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ --#undef CONFIG_CONS_NONE /* define if console on something else */ -- --#define CONFIG_CONS_INDEX 1 --#undef CONFIG_SERIAL_SOFTWARE_FIFO --#define CFG_NS16550 --#define CFG_NS16550_SERIAL --#define CFG_NS16550_REG_SIZE 1 --#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ --#define CONFIG_BAUDRATE 9600 -- --#define CFG_BAUDRATE_TABLE \ -- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -- --#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) --#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) -- --/* Use the HUSH parser */ --#define CFG_HUSH_PARSER --#ifdef CFG_HUSH_PARSER --#define CFG_PROMPT_HUSH_PS2 "> " --#endif -- --/* I2C */ --#define CONFIG_HARD_I2C /* I2C with hardware support*/ --#undef CONFIG_SOFT_I2C /* I2C bit-banged */ --#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ --#define CFG_I2C_SLAVE 0x7F --#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -- --#define CFG_PCI_MEM_BASE 0xC0000000 --#define CFG_PCI_MEM_PHYS 0xC0000000 --#define CFG_PCI_MEM_SIZE 0x10000000 -- --#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ -- --# define CONFIG_NET_MULTI 1 --# define CONFIG_MII 1 /* MII PHY management */ --# define CONFIG_MPC85xx_TSEC1 --# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" --# define TSEC1_PHY_ADDR 25 --# define TSEC1_PHYIDX 0 --/* Options are: TSEC0 */ --# define CONFIG_ETHPRIME "TSEC0" -- -- --#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -- -- #undef CONFIG_ETHER_NONE /* define if ether on something else */ -- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ -- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ -- -- #if (CONFIG_ETHER_INDEX == 2) -- /* -- * - Rx-CLK is CLK13 -- * - Tx-CLK is CLK14 -- * - Select bus for bd/buffers -- * - Full duplex -- */ -- #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -- #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -- #define CFG_CPMFCR_RAMTYPE 0 -- #define CFG_FCC_PSMR (FCC_PSMR_FDE) -- -- #elif (CONFIG_ETHER_INDEX == 3) -- /* need more definitions here for FE3 */ -- #endif /* CONFIG_ETHER_INDEX */ -- -- #define CONFIG_MII /* MII PHY management */ -- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -- /* -- * GPIO pins used for bit-banged MII communications -- */ -- #define MDIO_PORT 2 /* Port C */ -- #define MDIO_ACTIVE (iop->pdir |= 0x00400000) -- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -- #define MDIO_READ ((iop->pdat & 0x00400000) != 0) -- -- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ -- else iop->pdat &= ~0x00400000 -- -- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ -- else iop->pdat &= ~0x00200000 -- -- #define MIIDELAY udelay(1) -- --#endif -- --/*----------------------------------------------------------------------- -- * FLASH and environment organization -- */ -- --#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ --#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ --#if 0 --#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ --#define CFG_FLASH_PROTECTION /* use hardware protection */ --#endif --#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ --#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -- --#undef CFG_FLASH_CHECKSUM --#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ --#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ -- --#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -- --#if 0 --/* XXX This doesn't work and I don't want to fix it */ --#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -- #define CFG_RAMBOOT --#else -- #undef CFG_RAMBOOT --#endif --#endif -- --/* Environment */ --#if !defined(CFG_RAMBOOT) -- #if defined(CONFIG_RAM_AS_FLASH) -- #define CFG_ENV_IS_NOWHERE -- #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) -- #define CFG_ENV_SIZE 0x2000 -- #else -- #define CFG_ENV_IS_IN_FLASH 1 -- #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) -- #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ -- #endif --#else -- #define CFG_NO_FLASH 1 /* Flash is not usable now */ -- #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -- #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -- #define CFG_ENV_SIZE 0x2000 --#endif -- --#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" --/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ --#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" --#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ -- --#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ --#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- --#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) -- #if defined(CONFIG_PCI) -- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ -- CFG_CMD_PING | CFG_CMD_I2C) & \ -- ~(CFG_CMD_ENV | \ -- CFG_CMD_LOADS )) -- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) -- #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ -- CFG_CMD_PING | CFG_CMD_I2C) & \ -- ~(CFG_CMD_ENV)) -- #endif --#else -- #if defined(CONFIG_PCI) -- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ -- CFG_CMD_PING | CFG_CMD_I2C) -- #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) -- #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ -- CFG_CMD_PING | CFG_CMD_I2C) -- #endif --#endif -- --#include <cmd_confdefs.h> -- --#undef CONFIG_WATCHDOG /* watchdog disabled */ -- --/* -- * Miscellaneous configurable options -- */ --#define CFG_LONGHELP /* undef to save memory */ --#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ --#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ --#else -- #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ --#endif --#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ --#define CFG_MAXARGS 16 /* max number of command args */ --#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ --#define CFG_LOAD_ADDR 0x1000000 /* default load address */ --#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -- --/* -- * For booting Linux, the board info and command line data -- * have to be in the first 8 MB of memory, since this is -- * the maximum mapped by the Linux kernel during initialization. -- */ --#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -- --/* Cache Configuration */ --#define CFG_DCACHE_SIZE 32768 --#define CFG_CACHELINE_SIZE 32 --#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ --#endif -- --/* -- * Internal Definitions -- * -- * Boot Flags -- */ --#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ --#define BOOTFLAG_WARM 0x02 /* Software reboot */ -- --#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ --#endif -- --/*Note: change below for your network setting!!! */ --#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) --# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a --# define CONFIG_HAS_ETH1 --# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b --# define CONFIG_HAS_ETH2 --# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c --#endif -- --#define CONFIG_SERVERIP YourServerIP --#define CONFIG_IPADDR YourTargetIP --#define CONFIG_GATEWAYIP YourGatewayIP --#define CONFIG_NETMASK 255.255.255.0 --#define CONFIG_HOSTNAME SBC8560 --#define CONFIG_ROOTPATH YourRootPath --#define CONFIG_BOOTFILE YourImageName -- --#endif /* __CONFIG_H */ diff -Nurd u-boot-1.2.0/include/configs/davinci.h u-boot-1.2.0-leopard/include/configs/davinci.h --- u-boot-1.2.0/include/configs/davinci.h 1969-12-31 21:00:00.000000000 -0300 +++ u-boot-1.2.0-leopard/include/configs/davinci.h 2007-12-04 07:50:49.000000000 -0300 @@ -47117,418 +46581,6 @@ diff -Nurd u-boot-1.2.0/include/configs/omap2420h4.h u-boot-1.2.0-leopard/includ #ifdef CONFIG_APTIX #define V_SCLK 1500000 -diff -Nurd u-boot-1.2.0/include/configs/sbc8560.h u-boot-1.2.0-leopard/include/configs/sbc8560.h ---- u-boot-1.2.0/include/configs/sbc8560.h 1969-12-31 21:00:00.000000000 -0300 -+++ u-boot-1.2.0-leopard/include/configs/sbc8560.h 2007-12-04 07:50:50.000000000 -0300 -@@ -0,0 +1,408 @@ -+/* -+ * (C) Copyright 2002,2003 Motorola,Inc. -+ * Xianghua Xiao <X.Xiao@motorola.com> -+ * -+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. -+ * Added support for Wind River SBC8560 board -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+/* mpc8560ads board configuration file */ -+/* please refer to doc/README.mpc85xx for more info */ -+/* make sure you change the MAC address and other network params first, -+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+/* High Level Configuration Options */ -+#define CONFIG_BOOKE 1 /* BOOKE */ -+#define CONFIG_E500 1 /* BOOKE e500 family */ -+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -+#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ -+ -+ -+#define CONFIG_CPM2 1 /* has CPM2 */ -+#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ -+ -+/* XXX flagging this as something I might want to delete */ -+#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ -+ -+#define CONFIG_TSEC_ENET /* tsec ethernet support */ -+#undef CONFIG_PCI /* pci ethernet support */ -+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -+ -+ -+#define CONFIG_ENV_OVERWRITE -+ -+/* Using Localbus SDRAM to emulate flash before we can program the flash, -+ * normally you need a flash-boot image(u-boot.bin), if so undef this. -+ */ -+#undef CONFIG_RAM_AS_FLASH -+ -+#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ -+ #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -+#else -+ #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -+#endif -+ -+/* below can be toggled for performance analysis. otherwise use default */ -+#define CONFIG_L2_CACHE /* toggle L2 cache */ -+#undef CONFIG_BTB /* toggle branch predition */ -+#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ -+ -+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -+ -+#undef CFG_DRAM_TEST /* memory test, takes time */ -+#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -+#define CFG_MEMTEST_END 0x00400000 -+ -+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ -+ defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ -+ defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -+#endif -+ -+/* -+ * Base addresses -- Note these are effective addresses where the -+ * actual resources get mapped (not physical addresses) -+ */ -+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -+ -+#if XXX -+ #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -+#else -+ #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -+#endif -+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -+ -+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -+#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -+#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ -+ -+#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -+#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -+ -+#if defined(CONFIG_MPC85xx_REV1) -+ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -+#endif -+ -+#undef CONFIG_CLOCKS_IN_MHZ -+ -+#if defined(CONFIG_RAM_AS_FLASH) -+ #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ -+ #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ -+ #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ -+ #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -+#else /* Boot from real Flash */ -+ #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ -+ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ -+ #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ -+ #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -+#endif -+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ -+ -+/* local bus definitions */ -+#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -+#define CFG_OR1_PRELIM 0xfc000ff7 -+ -+#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -+#define CFG_OR2_PRELIM 0x00000000 -+ -+#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -+#define CFG_OR3_PRELIM 0xfc000cc1 -+ -+#if defined(CONFIG_RAM_AS_FLASH) -+ #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -+#else -+ #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -+#endif -+#define CFG_OR4_PRELIM 0xfc000cc1 -+ -+#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -+#if 1 -+ #define CFG_OR5_PRELIM 0xff000ff7 -+#else -+ #define CFG_OR5_PRELIM 0xff0000f0 -+#endif -+ -+#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -+#define CFG_OR6_PRELIM 0xfc000ff7 -+#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -+#define CFG_LBC_LBCR 0x00000000 -+#define CFG_LBC_LSRT 0x20000000 -+#define CFG_LBC_MRTPR 0x20000000 -+#define CFG_LBC_LSDMR_1 0x2861b723 -+#define CFG_LBC_LSDMR_2 0x0861b723 -+#define CFG_LBC_LSDMR_3 0x0861b723 -+#define CFG_LBC_LSDMR_4 0x1861b723 -+#define CFG_LBC_LSDMR_5 0x4061b723 -+ -+/* just hijack the MOT BCSR def for SBC8560 misc devices */ -+#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -+/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ -+ -+#define CONFIG_L1_INIT_RAM -+#define CFG_INIT_RAM_LOCK 1 -+#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -+ -+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -+ -+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ -+ -+/* Serial Port */ -+#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -+#undef CONFIG_CONS_NONE /* define if console on something else */ -+ -+#define CONFIG_CONS_INDEX 1 -+#undef CONFIG_SERIAL_SOFTWARE_FIFO -+#define CFG_NS16550 -+#define CFG_NS16550_SERIAL -+#define CFG_NS16550_REG_SIZE 1 -+#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -+#define CONFIG_BAUDRATE 9600 -+ -+#define CFG_BAUDRATE_TABLE \ -+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -+ -+#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -+#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) -+ -+/* Use the HUSH parser */ -+#define CFG_HUSH_PARSER -+#ifdef CFG_HUSH_PARSER -+#define CFG_PROMPT_HUSH_PS2 "> " -+#endif -+ -+/* -+ * I2C -+ */ -+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -+#define CONFIG_HARD_I2C /* I2C with hardware support*/ -+#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -+#define CFG_I2C_SLAVE 0x7F -+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -+#define CFG_I2C_OFFSET 0x3000 -+ -+#define CFG_PCI_MEM_BASE 0xC0000000 -+#define CFG_PCI_MEM_PHYS 0xC0000000 -+#define CFG_PCI_MEM_SIZE 0x10000000 -+ -+#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ -+ -+# define CONFIG_NET_MULTI 1 -+# define CONFIG_MII 1 /* MII PHY management */ -+# define CONFIG_MPC85xx_TSEC1 -+# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -+# define TSEC1_PHY_ADDR 25 -+# define TSEC1_PHYIDX 0 -+/* Options are: TSEC0 */ -+# define CONFIG_ETHPRIME "TSEC0" -+ -+#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -+ -+ #undef CONFIG_ETHER_NONE /* define if ether on something else */ -+ #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ -+ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ -+ -+ #if (CONFIG_ETHER_INDEX == 2) -+ /* -+ * - Rx-CLK is CLK13 -+ * - Tx-CLK is CLK14 -+ * - Select bus for bd/buffers -+ * - Full duplex -+ */ -+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -+ #define CFG_CPMFCR_RAMTYPE 0 -+ #define CFG_FCC_PSMR (FCC_PSMR_FDE) -+ -+ #elif (CONFIG_ETHER_INDEX == 3) -+ /* need more definitions here for FE3 */ -+ #endif /* CONFIG_ETHER_INDEX */ -+ -+ #define CONFIG_MII /* MII PHY management */ -+ #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -+ /* -+ * GPIO pins used for bit-banged MII communications -+ */ -+ #define MDIO_PORT 2 /* Port C */ -+ #define MDIO_ACTIVE (iop->pdir |= 0x00400000) -+ #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -+ #define MDIO_READ ((iop->pdat & 0x00400000) != 0) -+ -+ #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ -+ else iop->pdat &= ~0x00400000 -+ -+ #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ -+ else iop->pdat &= ~0x00200000 -+ -+ #define MIIDELAY udelay(1) -+ -+#endif -+ -+/*----------------------------------------------------------------------- -+ * FLASH and environment organization -+ */ -+ -+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -+#if 0 -+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -+#define CFG_FLASH_PROTECTION /* use hardware protection */ -+#endif -+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -+ -+#undef CFG_FLASH_CHECKSUM -+#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -+#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ -+ -+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -+ -+#if 0 -+/* XXX This doesn't work and I don't want to fix it */ -+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -+ #define CFG_RAMBOOT -+#else -+ #undef CFG_RAMBOOT -+#endif -+#endif -+ -+/* Environment */ -+#if !defined(CFG_RAMBOOT) -+ #if defined(CONFIG_RAM_AS_FLASH) -+ #define CFG_ENV_IS_NOWHERE -+ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) -+ #define CFG_ENV_SIZE 0x2000 -+ #else -+ #define CFG_ENV_IS_IN_FLASH 1 -+ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) -+ #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ -+ #endif -+#else -+ #define CFG_NO_FLASH 1 /* Flash is not usable now */ -+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -+ #define CFG_ENV_SIZE 0x2000 -+#endif -+ -+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -+/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -+#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -+#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ -+ -+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -+ -+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) -+ #if defined(CONFIG_PCI) -+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ -+ CFG_CMD_PING | CFG_CMD_I2C) & \ -+ ~(CFG_CMD_ENV | \ -+ CFG_CMD_LOADS )) -+ #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) -+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ -+ CFG_CMD_PING | CFG_CMD_I2C) & \ -+ ~(CFG_CMD_ENV)) -+ #endif -+#else -+ #if defined(CONFIG_PCI) -+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ -+ CFG_CMD_PING | CFG_CMD_I2C) -+ #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) -+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ -+ CFG_CMD_PING | CFG_CMD_I2C) -+ #endif -+#endif -+ -+#include <cmd_confdefs.h> -+ -+#undef CONFIG_WATCHDOG /* watchdog disabled */ -+ -+/* -+ * Miscellaneous configurable options -+ */ -+#define CFG_LONGHELP /* undef to save memory */ -+#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -+#else -+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -+#endif -+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -+#define CFG_MAXARGS 16 /* max number of command args */ -+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -+#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -+ -+/* -+ * For booting Linux, the board info and command line data -+ * have to be in the first 8 MB of memory, since this is -+ * the maximum mapped by the Linux kernel during initialization. -+ */ -+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -+ -+/* Cache Configuration */ -+#define CFG_DCACHE_SIZE 32768 -+#define CFG_CACHELINE_SIZE 32 -+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -+ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -+#endif -+ -+/* -+ * Internal Definitions -+ * -+ * Boot Flags -+ */ -+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -+#define BOOTFLAG_WARM 0x02 /* Software reboot */ -+ -+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -+ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -+ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -+#endif -+ -+/*Note: change below for your network setting!!! */ -+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -+# define CONFIG_ETHADDR 00:01:af:07:9b:8a -+# define CONFIG_HAS_ETH1 -+# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -+# define CONFIG_HAS_ETH2 -+# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c -+#endif -+ -+#define CONFIG_SERVERIP 192.168.0.131 -+#define CONFIG_IPADDR 192.168.0.105 -+#define CONFIG_GATEWAYIP 0.0.0.0 -+#define CONFIG_NETMASK 255.255.255.0 -+#define CONFIG_HOSTNAME SBC8560 -+#define CONFIG_ROOTPATH /home/ppc -+#define CONFIG_BOOTFILE pImage -+ -+#endif /* __CONFIG_H */ diff -Nurd u-boot-1.2.0/include/flash.h u-boot-1.2.0-leopard/include/flash.h --- u-boot-1.2.0/include/flash.h 2007-01-06 20:13:11.000000000 -0300 +++ u-boot-1.2.0-leopard/include/flash.h 2007-12-04 07:50:42.000000000 -0300 diff --git a/recipes/u-boot/u-boot_1.2.0.bb b/recipes/u-boot/u-boot_1.2.0.bb index 3f5cfa5310..edcb1b1415 100644 --- a/recipes/u-boot/u-boot_1.2.0.bb +++ b/recipes/u-boot/u-boot_1.2.0.bb @@ -14,7 +14,7 @@ SRC_URI_append_lsppchd = "file://u-boot-kurobox.patch;patch=1 \ file://u-boot-kurobox-fdt.patch;patch=1 \ file://defconfig_lsppchg" -SRC_URI_append_dm355-leopard = "file://dm355-leopard.diff" +SRC_URI_append_dm355-leopard = " file://dm355-leopard.diff;patch=1" do_compile_prepend_lsppchg () { cp ${WORKDIR}/defconfig_lsppchg ${S}/include/configs/linkstation.h |