qemu_0.12.3.bb : add two patches from git to fix cp15 access

Found these were needed when upgrading to gcc 4.5.0/glibc 2.10.1 combo

3 files changed, 197 insertions, 0 deletions

diff --git a/recipes/qemu/qemu-0.12.3/3f26c1227e3b08010f2a65379cecf4cb4b5933fa.patch b/recipes/qemu/qemu-0.12.3/3f26c1227e3b08010f2a65379cecf4cb4b5933fa.patch
new file mode 100644
index 0000000000..143b0059ae
--- /dev/null
+++ b/recipes/qemu/qemu-0.12.3/3f26c1227e3b08010f2a65379cecf4cb4b5933fa.patch
@@ -0,0 +1,134 @@
+From 3f26c1227e3b08010f2a65379cecf4cb4b5933fa Mon Sep 17 00:00:00 2001
+From: Riku Voipio <riku.voipio@nokia.com>
+Date: Mon, 25 Jan 2010 13:17:32 +0000
+Subject: target-arm: refactor cp15.c13 register access
+
+Access the cp15.c13 TLS registers directly with TCG ops instead of with
+a slow helper. If the the cp15 read/write was not TLS register access,
+fall back to the cp15 helper.
+
+This makes accessing __thread variables in linux-user when apps are compiled
+with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
+already checked in cp15_user_ok.
+
+While at it, make the cp15.c13 Thread ID registers available only on
+ARMv6K and newer.
+
+Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
+---
+diff --git a/target-arm/helper.c b/target-arm/helper.c
+index b3aec99..27001e8 100644
+--- a/target-arm/helper.c
++++ b/target-arm/helper.c
+@@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
+ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
+ {
+     cpu_abort(env, "cp15 insn %08x\n", insn);
+-    return 0;
+ }
+ 
+ /* These should probably raise undefined insn exceptions.  */
+@@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
+               tlb_flush(env, 0);
+             env->cp15.c13_context = val;
+             break;
+-        case 2:
+-            env->cp15.c13_tls1 = val;
+-            break;
+-        case 3:
+-            env->cp15.c13_tls2 = val;
+-            break;
+-        case 4:
+-            env->cp15.c13_tls3 = val;
+-            break;
+         default:
+             goto bad_reg;
+         }
+@@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
+             return env->cp15.c13_fcse;
+         case 1:
+             return env->cp15.c13_context;
+-        case 2:
+-            return env->cp15.c13_tls1;
+-        case 3:
+-            return env->cp15.c13_tls2;
+-        case 4:
+-            return env->cp15.c13_tls3;
+         default:
+             goto bad_reg;
+         }
+diff --git a/target-arm/translate.c b/target-arm/translate.c
+index 5cf3e06..786c329 100644
+--- a/target-arm/translate.c
++++ b/target-arm/translate.c
+@@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn)
+     return 0;
+ }
+ 
++static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
++{
++    TCGv tmp;
++    int cpn = (insn >> 16) & 0xf;
++    int cpm = insn & 0xf;
++    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
++
++    if (!arm_feature(env, ARM_FEATURE_V6K))
++        return 0;
++
++    if (!(cpn == 13 && cpm == 0))
++        return 0;
++
++    if (insn & ARM_CP_RW_BIT) {
++        tmp = new_tmp();
++        switch (op) {
++        case 2:
++            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
++            break;
++        case 3:
++            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
++            break;
++        case 4:
++            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
++            break;
++        default:
++            dead_tmp(tmp);
++            return 0;
++        }
++        store_reg(s, rd, tmp);
++
++    } else {
++        tmp = load_reg(s, rd);
++        switch (op) {
++        case 2:
++            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
++            break;
++        case 3:
++            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
++            break;
++        case 4:
++            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
++            break;
++        default:
++            return 0;
++        }
++        dead_tmp(tmp);
++    }
++    return 1;
++}
++
+ /* Disassemble system coprocessor (cp15) instruction.  Return nonzero if
+    instruction is not defined.  */
+ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
+@@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
+         return 0;
+     }
+     rd = (insn >> 12) & 0xf;
++
++    if (cp15_tls_load_store(env, s, insn, rd))
++        return 0;
++
+     tmp2 = tcg_const_i32(insn);
+     if (insn & ARM_CP_RW_BIT) {
+         tmp = new_tmp();
+--
+cgit v0.8.2.1
diff --git a/recipes/qemu/qemu-0.12.3/c5883be23519921254c6940873ee8db04979c20a.patch b/recipes/qemu/qemu-0.12.3/c5883be23519921254c6940873ee8db04979c20a.patch
new file mode 100644
index 0000000000..bbdab11101
--- /dev/null
+++ b/recipes/qemu/qemu-0.12.3/c5883be23519921254c6940873ee8db04979c20a.patch
@@ -0,0 +1,61 @@
+From c5883be23519921254c6940873ee8db04979c20a Mon Sep 17 00:00:00 2001
+From: Paul Brook <paul@codesourcery.com>
+Date: Tue, 23 Feb 2010 14:45:16 +0000
+Subject: ARM CP15 tls fix
+
+Fix temporary handling in cp15 tls register load/store.
+
+Signed-off-by: Paul Brook <paul@codesourcery.com>
+---
+diff --git a/target-arm/translate.c b/target-arm/translate.c
+index 8b3b12d..ac04996 100644
+--- a/target-arm/translate.c
++++ b/target-arm/translate.c
+@@ -2469,19 +2469,17 @@ static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, ui
+         return 0;
+ 
+     if (insn & ARM_CP_RW_BIT) {
+-        tmp = new_tmp();
+         switch (op) {
+         case 2:
+-            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
++            tmp = load_cpu_field(cp15.c13_tls1);
+             break;
+         case 3:
+-            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
++            tmp = load_cpu_field(cp15.c13_tls2);
+             break;
+         case 4:
+-            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
++            tmp = load_cpu_field(cp15.c13_tls3);
+             break;
+         default:
+-            dead_tmp(tmp);
+             return 0;
+         }
+         store_reg(s, rd, tmp);
+@@ -2490,18 +2488,18 @@ static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, ui
+         tmp = load_reg(s, rd);
+         switch (op) {
+         case 2:
+-            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1));
++            store_cpu_field(tmp, cp15.c13_tls1);
+             break;
+         case 3:
+-            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2));
++            store_cpu_field(tmp, cp15.c13_tls2);
+             break;
+         case 4:
+-            tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3));
++            store_cpu_field(tmp, cp15.c13_tls3);
+             break;
+         default:
++            dead_tmp(tmp);
+             return 0;
+         }
+-        dead_tmp(tmp);
+     }
+     return 1;
+ }
+--
+cgit v0.8.2.1
diff --git a/recipes/qemu/qemu_0.12.3.bb b/recipes/qemu/qemu_0.12.3.bb
index b7d52c2e24..1ce7c589fe 100644
--- a/recipes/qemu/qemu_0.12.3.bb
+++ b/recipes/qemu/qemu_0.12.3.bb
@@ -18,6 +18,8 @@ SRC_URI = "\
     file://fix_segfault.patch;patch=1 \
     file://fix_baum_c_compilation.patch;patch=1 \
     file://fix_fortify_source_compilation.patch;patch=1 \
+    file://3f26c1227e3b08010f2a65379cecf4cb4b5933fa.patch;patch=1 \
+    file://c5883be23519921254c6940873ee8db04979c20a.patch;patch=1 \
     "
 
 SRC_URI[qemu-0.12.3.sha256sum] = "3ce26f8fb0a59418b2064a26bac4b40ea4e493acbc3df7ad5932635477fade4b"