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authorKoen Kooi <koen@openembedded.org>2009-09-02 22:13:29 +0200
committerKoen Kooi <koen@openembedded.org>2009-09-02 22:14:08 +0200
commit5777be68163ae84a340a252e59069d722aa534cb (patch)
tree506a2c5cd9c77e9efb95db674d99b5cc158ee1b9 /recipes/linux/linux-omap-2.6.29/cache
parentea7e5a05c4c6c29df5682d92a056cb722969b5a0 (diff)
linux-omap-* 2.6.29: add l1 cache performance tweak from l-a-k ml
* also sync patch between pm and regular kernels
Diffstat (limited to 'recipes/linux/linux-omap-2.6.29/cache')
-rw-r--r--recipes/linux/linux-omap-2.6.29/cache/copy-page-tweak.patch169
-rw-r--r--recipes/linux/linux-omap-2.6.29/cache/l1cache-shift.patch115
2 files changed, 284 insertions, 0 deletions
diff --git a/recipes/linux/linux-omap-2.6.29/cache/copy-page-tweak.patch b/recipes/linux/linux-omap-2.6.29/cache/copy-page-tweak.patch
new file mode 100644
index 0000000000..9da374041c
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.29/cache/copy-page-tweak.patch
@@ -0,0 +1,169 @@
+Path: news.gmane.org!not-for-mail
+From: "Kirill A. Shutemov" <kirill@shutemov.name>
+Newsgroups: gmane.linux.ports.arm.kernel
+Subject: [PATCH] ARM: copy_page.S: take into account the size of the cache line
+Date: Wed, 2 Sep 2009 20:19:58 +0300
+Lines: 92
+Approved: news@gmane.org
+Message-ID: <1251911998-3112-1-git-send-email-kirill__11898.5180197798$1251901300$gmane$org@shutemov.name>
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+Cc: Bityutskiy Artem <Artem.Bityutskiy@nokia.com>,
+ "Kirill A. Shutemov" <kirill@shutemov.name>,
+ Siarhei Siamashka <siarhei.siamashka@nokia.com>,
+ Moiseichuk Leonid <leonid.moiseichuk@nokia.com>,
+ Koskinen Aaro <aaro.koskinen@nokia.com>
+To: linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org
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+
+Optimized version of copy_page() was written with assumption that cache
+line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes.
+
+This patch tries to generalize copy_page() to work with any cache line
+size if cache line size is multiple of 16 and page size is multiple of
+two cache line size.
+
+After this optimization we've got ~25% speedup on OMAP3(tested in
+userspace).
+
+There is test for kernelspace which trigger copy-on-write after fork():
+
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+
+ #define BUF_SIZE (10000*4096)
+ #define NFORK 200
+
+ int main(int argc, char **argv)
+ {
+ char *buf = malloc(BUF_SIZE);
+ int i;
+
+ memset(buf, 0, BUF_SIZE);
+
+ for(i = 0; i < NFORK; i++) {
+ if (fork()) {
+ wait(NULL);
+ } else {
+ int j;
+
+ for(j = 0; j < BUF_SIZE; j+= 4096)
+ buf[j] = (j & 0xFF) + 1;
+ break;
+ }
+ }
+
+ free(buf);
+ return 0;
+ }
+
+Before optimization this test takes ~66 seconds, after optimization
+takes ~56 seconds.
+
+Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
+Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
+---
+ arch/arm/lib/copy_page.S | 16 ++++++++--------
+ 1 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S
+index 6ae04db..6ee2f67 100644
+--- a/arch/arm/lib/copy_page.S
++++ b/arch/arm/lib/copy_page.S
+@@ -12,8 +12,9 @@
+ #include <linux/linkage.h>
+ #include <asm/assembler.h>
+ #include <asm/asm-offsets.h>
++#include <asm/cache.h>
+
+-#define COPY_COUNT (PAGE_SZ/64 PLD( -1 ))
++#define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
+
+ .text
+ .align 5
+@@ -26,17 +27,16 @@
+ ENTRY(copy_page)
+ stmfd sp!, {r4, lr} @ 2
+ PLD( pld [r1, #0] )
+- PLD( pld [r1, #32] )
++ PLD( pld [r1, #L1_CACHE_BYTES] )
+ mov r2, #COPY_COUNT @ 1
+ ldmia r1!, {r3, r4, ip, lr} @ 4+1
+-1: PLD( pld [r1, #64] )
+- PLD( pld [r1, #96] )
+-2: stmia r0!, {r3, r4, ip, lr} @ 4
+- ldmia r1!, {r3, r4, ip, lr} @ 4+1
+- stmia r0!, {r3, r4, ip, lr} @ 4
+- ldmia r1!, {r3, r4, ip, lr} @ 4+1
++1: PLD( pld [r1, #2 * L1_CACHE_BYTES])
++ PLD( pld [r1, #3 * L1_CACHE_BYTES])
++2:
++ .rept (2 * L1_CACHE_BYTES / 16 - 1)
+ stmia r0!, {r3, r4, ip, lr} @ 4
+ ldmia r1!, {r3, r4, ip, lr} @ 4
++ .endr
+ subs r2, r2, #1 @ 1
+ stmia r0!, {r3, r4, ip, lr} @ 4
+ ldmgtia r1!, {r3, r4, ip, lr} @ 4
+--
+1.6.4.2
diff --git a/recipes/linux/linux-omap-2.6.29/cache/l1cache-shift.patch b/recipes/linux/linux-omap-2.6.29/cache/l1cache-shift.patch
new file mode 100644
index 0000000000..e58d49c7a3
--- /dev/null
+++ b/recipes/linux/linux-omap-2.6.29/cache/l1cache-shift.patch
@@ -0,0 +1,115 @@
+Path: news.gmane.org!not-for-mail
+From: "Kirill A. Shutemov" <kirill@shutemov.name>
+Newsgroups: gmane.linux.ports.arm.kernel
+Subject: [PATCH 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line
+ size
+Date: Wed, 2 Sep 2009 19:11:52 +0300
+Lines: 39
+Approved: news@gmane.org
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+Cc: Bityutskiy Artem <Artem.Bityutskiy@nokia.com>,
+ "Kirill A. Shutemov" <kirill@shutemov.name>,
+ Siarhei Siamashka <siarhei.siamashka@nokia.com>,
+ Moiseichuk Leonid <leonid.moiseichuk@nokia.com>,
+ Koskinen Aaro <aaro.koskinen@nokia.com>
+To: linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org
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+
+Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
+It's not true at least for CPUs based on Cortex-A8.
+
+List of CPUs with cache line size != 32 should be expanded later.
+
+Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
+---
+ arch/arm/include/asm/cache.h | 2 +-
+ arch/arm/mm/Kconfig | 5 +++++
+ 2 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
+index feaa75f..2ee7743 100644
+--- a/arch/arm/include/asm/cache.h
++++ b/arch/arm/include/asm/cache.h
+@@ -4,7 +4,7 @@
+ #ifndef __ASMARM_CACHE_H
+ #define __ASMARM_CACHE_H
+
+-#define L1_CACHE_SHIFT 5
++#define L1_CACHE_SHIFT (CONFIG_ARM_L1_CACHE_SHIFT)
+ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+ /*
+diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
+index 83c025e..3c37d4c 100644
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -771,3 +771,8 @@ config CACHE_XSC3L2
+ select OUTER_CACHE
+ help
+ This option enables the L2 cache on XScale3.
++
++config ARM_L1_CACHE_SHIFT
++ int
++ default 6 if ARCH_OMAP3
++ default 5
+--
+1.6.3.4