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authorJohn Klug <john.klug@multitech.com>2021-10-29 10:45:43 -0500
committerJohn Klug <john.klug@multitech.com>2021-11-12 12:00:50 -0600
commitfdc6f30e9da19f19669ecfc6c66d02abf9057959 (patch)
tree1f30ba77204c5307aea4bf1ab4f73ff77495aa5c /io-module/at91gpio.h
parent0e772e1a11a545571232de6387699b73ac3278bf (diff)
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MTCDT-0.2 with PCA9557 support
Diffstat (limited to 'io-module/at91gpio.h')
-rw-r--r--io-module/at91gpio.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/io-module/at91gpio.h b/io-module/at91gpio.h
index c2f8a77..f9b527d 100644
--- a/io-module/at91gpio.h
+++ b/io-module/at91gpio.h
@@ -179,4 +179,40 @@
#define AT91_PIN_PE30 (0x80 + 30)
#define AT91_PIN_PE31 (0x80 + 31)
+/* MTCDT-0.2 I2C I/O Port expanders
+ * ARCH_NR_GPIOS is set to 512 in
+ * gpio.h if it is not set in
+ * the kernel configuration with
+ * CONFIG_ARCH_NR_GPIO. If that number
+ * ever chnages, the BASE integer will
+ * change as well. 512 - 8 = 504 */
+#define PCA9557_0_BASE 504 // i2c address 0x18
+#define PCA9557_0_IO0 (PCA9557_0_BASE + 0)
+#define PCA9557_0_IO1 (PCA9557_0_BASE + 1)
+#define PCA9557_0_IO2 (PCA9557_0_BASE + 2)
+#define PCA9557_0_IO3 (PCA9557_0_BASE + 3)
+#define PCA9557_0_IO4 (PCA9557_0_BASE + 4)
+#define PCA9557_0_IO5 (PCA9557_0_BASE + 5)
+#define PCA9557_0_IO6 (PCA9557_0_BASE + 6)
+#define PCA9557_0_IO7 (PCA9557_0_BASE + 7)
+
+/* This value depends on order of discovery.
+ * This controller has a higher address on
+ * the I2C bus and the pins are assigned
+ * in the order of discovery from highest
+ * to lowest pin numbers.
+ *
+ * GPIO numbers can be verified by
+ * examining /sys/kernel/debug/gpio.
+ */
+#define PCA9557_1_BASE 496 // i2c address 0x19
+#define PCA9557_1_IO0 (PCA9557_1_BASE + 0)
+#define PCA9557_1_IO1 (PCA9557_1_BASE + 1)
+#define PCA9557_1_IO2 (PCA9557_1_BASE + 2)
+#define PCA9557_1_IO3 (PCA9557_1_BASE + 3)
+#define PCA9557_1_IO4 (PCA9557_1_BASE + 4)
+#define PCA9557_1_IO5 (PCA9557_1_BASE + 5)
+#define PCA9557_1_IO6 (PCA9557_1_BASE + 6)
+#define PCA9557_1_IO7 (PCA9557_1_BASE + 7)
+
#endif