From f7c611e12ab924475c1f6c3b81a915e516e04186 Mon Sep 17 00:00:00 2001 From: Harsh Sharma Date: Fri, 25 Oct 2019 11:10:37 -0500 Subject: added ap port config and fpga flash requirements for mtcdt3 --- src/mts_fpga_reg.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mts_fpga_reg.h') diff --git a/src/mts_fpga_reg.h b/src/mts_fpga_reg.h index 8efc191..7803802 100644 --- a/src/mts_fpga_reg.h +++ b/src/mts_fpga_reg.h @@ -35,10 +35,14 @@ typedef struct mts { #define SPI_DEV_PATH_AP2 "/dev/spidev32765.2" #define SPI_DEV_PATH_MTCAP "/dev/spidev0.1" #define SPI_DEV_PATH_MTCDT "/dev/spidev0.0" +#define SPI_DEV_PATH_MTCDT3_AP1 "/dev/spidev0.0" +#define SPI_DEV_PATH_MTCDT3_AP2 "/dev/spidev1.0" #define MTCDT "MTAC-LORA-1.5" +#define MTCDT3 "MTCDT3B-0.0" #define MTCAP "MTCAP-LORA-1.5" #define HW_FILE "/sys/devices/platform/mts-io/hw-version" #define MTCDT_DEFAULT_FILE "/usr/lib/mts-flash-binaries/mtcdt-fpga-v31.hex" +#define MTCDT3_DEFAULT_FILE "/usr/lib/mts-flash-binaries/mtcdt3-fpga-v35.hex" #define MTCAP_DEFAULT_FILE "/usr/lib/mts-flash-binaries/mtcap-fpga-v31.hex" #define CRESET "/sys/devices/platform/mts-io/lora/creset" #define CRESET_AP1 "/sys/devices/platform/mts-io/ap1/creset" @@ -46,6 +50,11 @@ typedef struct mts { #define MTAC_HW_VERSION "/sys/devices/platform/mts-io/lora/hw-version" #define MTAC_HW_VERSION_AP1 "/sys/devices/platform/mts-io/ap1/hw-version" #define MTAC_HW_VERSION_AP2 "/sys/devices/platform/mts-io/ap2/hw-version" +#define MTCDT3_HW_VERSION_AP1 "/sys/devices/platform/mts-io/lora/hw-version" +#define MTCDT3_HW_VERSION_AP2 "/sys/devices/platform/mts-io/lora-2/hw-version" +#define MTCDT3_CRESET_AP1 "/sys/devices/platform/mts-io/lora/creset" +#define MTCDT3_CRESET_AP2 "/sys/devices/platform/mts-io/lora-2/creset" + /* -------------------------------------------------------------------------- */ /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ -- cgit v1.2.3