summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--recipes-bsp/multitech/mts-id-eeprom.inc9
-rw-r--r--recipes-bsp/multitech/mts-io-sysfs_0.1.8.bb2
2 files changed, 3 insertions, 8 deletions
diff --git a/recipes-bsp/multitech/mts-id-eeprom.inc b/recipes-bsp/multitech/mts-id-eeprom.inc
index d93f020..3d166f6 100644
--- a/recipes-bsp/multitech/mts-id-eeprom.inc
+++ b/recipes-bsp/multitech/mts-id-eeprom.inc
@@ -4,7 +4,7 @@ SECTION = "console/utils"
PRIORITY = "optional"
LICENSE = "GPLv2+"
LIC_FILES_CHKSUM = "file://COPYING;md5=94d55d512a9ba36caa9b7df079bae19f"
-INC_PR = "r3"
+INC_PR = "r4"
DEPENDS = "mts-io openssl"
RDEPENDS_${PN} =+ "bash"
@@ -20,14 +20,9 @@ TARGET_CFLAGS_append_mtcdt3hs = " -D MTCDT3B"
SRCREV = "${PV}"
-<<<<<<< HEAD
-SRC_URI = "git://git.multitech.net/mts-id-eeprom.git;protocol=git \
-SRC_URI_append_mtcdt = " file://mtcdt-fpga-v31.hex file://mtcdt-fpga-v33.hex"
-=======
SRC_URI = "git://git.multitech.net/mts-id-eeprom.git;protocol=git"
SRC_URI_append_mtcdt = " file://mtcdt-fpga-v31.hex file://mtcdt-fpga-v35.hex"
->>>>>>> cf4351d... update mts-id-eeprom to 0.5.2 on ext git, add v35 FPGA for MTAC-LORA-H
-SRC_URI_append_mtcap = " file://mtcap-fpga-v31.hex file://mtcap-fpga-v33.hex"
+SRC_URI_append_mtcap = " file://mtcap-fpga-v31.hex file://mtcap-fpga-v35.hex"
S = "${WORKDIR}/git"
diff --git a/recipes-bsp/multitech/mts-io-sysfs_0.1.8.bb b/recipes-bsp/multitech/mts-io-sysfs_0.1.8.bb
index 074ce11..97b099d 100644
--- a/recipes-bsp/multitech/mts-io-sysfs_0.1.8.bb
+++ b/recipes-bsp/multitech/mts-io-sysfs_0.1.8.bb
@@ -12,7 +12,7 @@ PR = "r0"
SRCREV = "${PV}"
-SRC_URI = "git://git.multitech.net/mts-io-sysfs.git;protocol=git;branch=master \
+SRC_URI = "git://git.multitech.net/mts-io-sysfs;protocol=git;branch=master \
file://mts-io-sysfs.init"
S = "${WORKDIR}/git"