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| author | Jesse Gilles <jgilles@multitech.com> | 2014-11-04 11:23:21 -0600 |
|---|---|---|
| committer | Jesse Gilles <jgilles@multitech.com> | 2014-11-04 11:23:21 -0600 |
| commit | 812befa503067ad2bae5de58962ff38321c369ca (patch) | |
| tree | b472b5118f62e97f760a5b23f3a72130e5ce235b /recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch | |
| download | meta-multitech-812befa503067ad2bae5de58962ff38321c369ca.tar.gz meta-multitech-812befa503067ad2bae5de58962ff38321c369ca.tar.bz2 meta-multitech-812befa503067ad2bae5de58962ff38321c369ca.zip | |
initial commit with MTCDT support
Diffstat (limited to 'recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch')
| -rw-r--r-- | recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch b/recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch new file mode 100644 index 0000000..0f41ac4 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-2012.10/u-boot-2012.10-sam9x5-eth-mii-fix.patch @@ -0,0 +1,27 @@ +Index: git/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +=================================================================== +--- git.orig/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c 2013-02-11 10:22:35.000000000 -0600 ++++ git/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c 2013-02-11 10:32:59.652182120 -0600 +@@ -206,14 +206,14 @@ + #ifndef CONFIG_RMII + /* Only emac0 support MII */ + if (has_emac0()) { +- at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ +- at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ +- at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ +- at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ +- at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ +- at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ +- at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ +- at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ ++ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ ++ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ ++ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ ++ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ ++ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ ++ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ ++ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ ++ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + } + #endif + } |