Move bootstrap to ONFI compatible 3.8.12

23 files changed, 1260 insertions, 463 deletions

diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp
deleted file mode 100644
index f31477d..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp
+++ /dev/null
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
deleted file mode 100644
index 6f007b9..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-Index: at91bootstrap-3.5.2/Makefile
-===================================================================
---- at91bootstrap-3.5.2.orig/Makefile	2013-02-08 14:38:40.660054339 -0600
-+++ at91bootstrap-3.5.2/Makefile	2013-02-08 14:41:30.626272862 -0600
-@@ -359,4 +359,15 @@
- 
- PHONY+=tarball tarballx
- 
-+install:
-+	-install -d $(DESTDIR)
-+	install $(AT91BOOTSTRAP) $(DESTDIR)/$(IMAGE)
-+	-rm -f $(DESTDIR)/$(SYMLINK)
-+	(cd ${DESTDIR} ; \
-+	ln -sf ${IMAGE} ${SYMLINK} \
-+	)
-+
-+
-+PHONY+=install
-+
- .PHONY: $(PHONY)
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch
deleted file mode 100644
index e5dd013..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2015-12-21 15:42:05.498892917 -0600
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2015-12-22 14:53:59.151521592 -0600
-@@ -46,6 +46,9 @@
- 
- #include "onewire_info.h"
- 
-+#define RTC_SCCR   0x1C
-+#define RTC_IDR    0x24
-+
- #ifdef CONFIG_USER_HW_INIT
- extern void hw_init_hook(void);
- #endif
-@@ -207,6 +210,12 @@
- #ifdef CONFIG_USER_HW_INIT
- 	hw_init_hook();
- #endif
-+
-+	/* disable all RTC interrupts and clear status register.
-+	 * Prevents possible Linux lockup due to unexpected RTC interrupt
-+	 */
-+	writel(0xFF, RTC_IDR + AT91C_BASE_RTC);
-+	writel(0xFF, RTC_SCCR + AT91C_BASE_RTC);
- }
- #endif /* #ifdef CONFIG_HW_INIT */
- 
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
deleted file mode 100644
index 92a3a3b..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-Index: git/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
-===================================================================
---- git.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2015-01-13 13:31:45.162884794 -0600
-+++ git/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2015-01-13 13:45:17.967816395 -0600
-@@ -1,6 +1,6 @@
- #
- # Automatically generated make config: don't edit
--# Thu Apr 11 16:45:29 2013
-+# Tue Jan 13 13:09:23 2015
- #
- HAVE_DOT_CONFIG=y
- CONFIG_BOARDNAME="at91sam9x5ek"
-@@ -42,7 +42,7 @@
- ALLOW_PIO3=y
- CONFIG_HAS_PIO3=y
- CPU_HAS_PMECC=y
--CONFIG_LOAD_ONE_WIRE=y
-+# CONFIG_LOAD_ONE_WIRE is not set
- # CONFIG_MMC_SUPPORT is not set
- 
- #
-@@ -60,8 +60,8 @@
- # ALLOW_SDRAM_16BIT is not set
- # CONFIG_RAM_32MB is not set
- # CONFIG_RAM_64MB is not set
--CONFIG_RAM_128MB=y
--# CONFIG_RAM_256MB is not set
-+# CONFIG_RAM_128MB is not set
-+CONFIG_RAM_256MB=y
- # CONFIG_RAM_512MB is not set
- # CONFIG_DATAFLASH is not set
- # CONFIG_FLASH is not set
-@@ -81,8 +81,8 @@
- #
- # PMECC Configuration
- #
--CONFIG_PMECC_CORRECT_BITS_2=y
--# CONFIG_PMECC_CORRECT_BITS_4 is not set
-+# CONFIG_PMECC_CORRECT_BITS_2 is not set
-+CONFIG_PMECC_CORRECT_BITS_4=y
- # CONFIG_PMECC_CORRECT_BITS_8 is not set
- # CONFIG_PMECC_CORRECT_BITS_12 is not set
- # CONFIG_PMECC_CORRECT_BITS_24 is not set
-@@ -101,7 +101,7 @@
- # CONFIG_LOAD_64KB is not set
- CONFIG_IMG_ADDRESS="0x00040000"
- CONFIG_IMG_SIZE="0x00080000"
--CONFIG_JUMP_ADDR="0x26F00000"
-+CONFIG_JUMP_ADDR="0x2EF00000"
- 
- #
- # U-Boot Image Storage Setup
-@@ -116,4 +116,4 @@
- # CONFIG_USER_HW_INIT is not set
- CONFIG_THUMB=y
- CONFIG_SCLK=y
--CONFIG_DISABLE_WATCHDOG=y
-+# CONFIG_DISABLE_WATCHDOG is not set
-Index: git/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- git.orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 15:49:54.143358228 -0500
-+++ git/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 17:07:51.999219741 -0500
-@@ -53,6 +53,32 @@
- extern void hw_init_hook(void);
- #endif
- 
-+
-+static void initialize_mt_gpio(void)
-+{
-+ 	/* Configure DBGU pins */
-+	const struct pio_desc mt_gpio_pins[] = {
-+		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
-+		 * B A20-A25 until bootstrap shuts them down.
-+                 * This code prevents these pins from being used
-+                 * during boot, since we do not
-+                 * need these pins to boot the system and we
-+                 * do not want resets to toggle needlessly.
-+		 */
-+		{"WFBT-RESET",AT91C_PIN_PD(14), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
-+		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
-+        };
-+
-+	pio_configure(mt_gpio_pins);
-+}
-+
-+
- static void at91_dbgu_hw_init(void)
- {
- 	/* Configure DBGU pins */
-@@ -198,6 +223,9 @@
- 	slowclk_enable_osc32();
- #endif
- 
-+        /* Initialize MT GPIO */
-+        initialize_mt_gpio();
-+
- 	/* Initialize dbgu */
- 	initialize_dbgu();
- 
-@@ -322,10 +350,8 @@
- 
- 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
- 	reg |= AT91C_EBI_CS3A_SM;
--	if (get_cm_rev() == 'A')
--		reg &= ~AT91C_EBI_NFD0_ON_D16;
--	else
--		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
-+	/* MTCDT */
-+	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
- 
- 	reg &= ~AT91C_EBI_DRV;
- 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
-@@ -355,9 +381,7 @@
- 		AT91C_BASE_SMC + SMC_CTRL3);
- 
- 	/* Configure the PIO controller */
--	if (get_cm_rev() == 'A')
--		pio_configure(nand_pins_lo);
--	else
-+	/* MTCDT */
- 		pio_configure(nand_pins_hi);
- 
- 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch
deleted file mode 100644
index 0a7600d..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-11 05:07:35.000000000 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-29 15:13:01.390913836 -0500
-@@ -42,7 +42,8 @@
- ALLOW_PIO3=y
- CONFIG_HAS_PIO3=y
- CPU_HAS_PMECC=y
--CONFIG_LOAD_ONE_WIRE=y
-+# MTS: don't load one wire
-+# CONFIG_LOAD_ONE_WIRE is not set
- # CONFIG_MMC_SUPPORT is not set
- 
- #
-@@ -81,8 +82,8 @@
- #
- # PMECC Configuration
- #
--CONFIG_PMECC_CORRECT_BITS_2=y
--# CONFIG_PMECC_CORRECT_BITS_4 is not set
-+# CONFIG_PMECC_CORRECT_BITS_2 is not set
-+CONFIG_PMECC_CORRECT_BITS_4=y
- # CONFIG_PMECC_CORRECT_BITS_8 is not set
- # CONFIG_PMECC_CORRECT_BITS_12 is not set
- # CONFIG_PMECC_CORRECT_BITS_24 is not set
-@@ -116,4 +117,5 @@
- # CONFIG_USER_HW_INIT is not set
- CONFIG_THUMB=y
- CONFIG_SCLK=y
--CONFIG_DISABLE_WATCHDOG=y
-+# MTS: don't disable watchdog
-+# CONFIG_DISABLE_WATCHDOG is not set
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 15:49:54.143358228 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 17:31:57.691176941 -0500
-@@ -53,6 +53,31 @@
- extern void hw_init_hook(void);
- #endif
- 
-+
-+static void initialize_mt_gpio(void)
-+{
-+ 	/* Configure DBGU pins */
-+	const struct pio_desc mt_gpio_pins[] = {
-+		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
-+		 * B A20-A25 until bootstrap shuts them down.
-+                 * This code prevents these pins from being used
-+                 * during boot, since we do not
-+                 * need these pins to boot the system and we
-+                 * do not want resets to toggle needlessly.
-+		 */
-+		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
-+		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
-+        };
-+
-+	pio_configure(mt_gpio_pins);
-+}
-+
-+
- static void at91_dbgu_hw_init(void)
- {
- 	/* Configure DBGU pins */
-@@ -198,6 +223,9 @@
- 	slowclk_enable_osc32();
- #endif
- 
-+        /* Initialize MT GPIO */
-+        initialize_mt_gpio();
-+
- 	/* Initialize dbgu */
- 	initialize_dbgu();
- 
-@@ -322,10 +350,8 @@
- 
- 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
- 	reg |= AT91C_EBI_CS3A_SM;
--	if (get_cm_rev() == 'A')
--		reg &= ~AT91C_EBI_NFD0_ON_D16;
--	else
--		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
-+	/* MTR */
-+	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
- 
- 	reg &= ~AT91C_EBI_DRV;
- 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
-@@ -355,9 +381,7 @@
- 		AT91C_BASE_SMC + SMC_CTRL3);
- 
- 	/* Configure the PIO controller */
--	if (get_cm_rev() == 'A')
--		pio_configure(nand_pins_lo);
--	else
-+	/* MTR2 */
- 		pio_configure(nand_pins_hi);
- 
- 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch
deleted file mode 100644
index 912a891..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2015-09-29 09:55:07.335113881 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2015-09-29 10:13:19.397489104 -0500
-@@ -81,7 +81,8 @@
- 			| AT91C_DDRC2_CAS_3              /* CAS Latency 3 */
- 			| AT91C_DDRC2_NB_BANKS_8         /* 8 banks */
- 			| AT91C_DDRC2_DLL_RESET_DISABLED /* DLL not reset */
--			| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
-+			| AT91C_DDRC2_DIC_DS		 /* Low DDR Drive Strength */
-+			| AT91C_DDRC2_DECOD_INTERLEAVED);/* Interleaved decode*/
- 
- 	/*
- 	 * Make sure to uncomment the following line if the DDR controller
-Index: at91bootstrap-3.5.3/main.c
-===================================================================
---- at91bootstrap-3.5.3.orig/main.c	2013-04-11 05:07:35.000000000 -0500
-+++ at91bootstrap-3.5.3/main.c	2015-09-29 10:10:21.354971492 -0500
-@@ -68,12 +68,15 @@
- {
- 	char *version = "AT91Bootstrap";
- 	char *ver_num = " "AT91BOOTSTRAP_VERSION" ("COMPILE_TIME")";
-+	char *feature = "DDR Drive Strength: low";
- 
- 	dbgu_print("\n\r");
- 	dbgu_print("\n\r");
- 	dbgu_print(version);
- 	dbgu_print(ver_num);
- 	dbgu_print("\n\r");
-+	dbgu_print(feature);
-+	dbgu_print("\n\r");
- 	dbgu_print("\n\r");
- }
- 
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch
deleted file mode 100644
index 01920c2..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-Index: at91bootstrap-3.5.3/driver/debug.c
-===================================================================
---- at91boostrap-3.5.3.orig/driver/debug.c.orig	2017-02-13 16:14:17.214217038 -0600
-+++ at91boostrap-3.5.3/driver/debug.c	2017-02-13 15:48:44.106262425 -0600
-@@ -27,7 +27,6 @@
-  */
- #include "dbgu.h"
- #include "debug.h"
--#include <stdio.h>
- #include <stdarg.h>
- 
- #define MAX_BUFFER	128
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch
new file mode 100644
index 0000000..f299d30
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch
@@ -0,0 +1,76 @@
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:20:15.036823256 -0500
++++ new/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:26:10.648812728 -0500
+@@ -44,6 +44,31 @@
+ #include "at91sam9x5ek.h"
+ #include "board_hw_info.h"
+ 
++
++static void initialize_mt_gpio(void)
++{
++ 	/* Configure DBGU pins */
++	const struct pio_desc mt_gpio_pins[] = {
++		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
++		 * B A20-A25 until bootstrap shuts them down.
++                 * This code prevents these pins from being used
++                 * during boot, since we do not
++                 * need these pins to boot the system and we
++                 * do not want resets to toggle needlessly.
++		 */
++		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++        };
++
++	pio_configure(mt_gpio_pins);
++}
++
++
+ static void at91_dbgu_hw_init(void)
+ {
+ 	/* Configure DBGU pins */
+@@ -185,6 +210,9 @@
+ 	/* Init timer */
+ 	timer_init();
+ 
++        /* Initialize MT GPIO */
++        initialize_mt_gpio();
++
+ 	/* Initialize dbgu */
+ 	initialize_dbgu();
+ 
+@@ -298,10 +326,14 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
++#ifdef NOTMTCDT
+ 	if (get_cm_rev() == 'A')
+ 		reg &= ~AT91C_EBI_NFD0_ON_D16;
+ 	else
+ 		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++#endif /* NOTMTCDT */
++        /* MTCDT */
++	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -331,11 +363,15 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
++#ifdef NOTMTCDT
+ 	if (get_cm_rev() == 'A')
+ 		pio_configure(nand_pins_lo);
+ 	else
++#endif /* NOTMTCDT */
++                /* MTCDT */
+ 		pio_configure(nand_pins_hi);
+ 
++
+ 	pmc_enable_periph_clock(AT91C_ID_PIOC_D);
+ }
+ #endif /* #ifdef CONFIG_NANDFLASH */
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch
new file mode 100644
index 0000000..2993323
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch
@@ -0,0 +1,414 @@
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:20:15.036823256 -0500
++++ new/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:42:16.920784122 -0500
+@@ -44,6 +44,31 @@
+ #include "at91sam9x5ek.h"
+ #include "board_hw_info.h"
+ 
++
++static void initialize_mt_gpio(void)
++{
++ 	/* Configure DBGU pins */
++	const struct pio_desc mt_gpio_pins[] = {
++		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
++		 * B A20-A25 until bootstrap shuts them down.
++                 * This code prevents these pins from being used
++                 * during boot, since we do not
++                 * need these pins to boot the system and we
++                 * do not want resets to toggle needlessly.
++		 */
++		{"PD15",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD16",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD17",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD18",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD19",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD20IN",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++        };
++
++	pio_configure(mt_gpio_pins);
++}
++
++
+ static void at91_dbgu_hw_init(void)
+ {
+ 	/* Configure DBGU pins */
+@@ -185,6 +210,9 @@
+ 	/* Init timer */
+ 	timer_init();
+ 
++        /* Initialize MT GPIO */
++        initialize_mt_gpio();
++
+ 	/* Initialize dbgu */
+ 	initialize_dbgu();
+ 
+@@ -298,10 +326,8 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
+-	if (get_cm_rev() == 'A')
+-		reg &= ~AT91C_EBI_NFD0_ON_D16;
+-	else
+-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++	/* MTR */
++	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -331,9 +357,7 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
+-	if (get_cm_rev() == 'A')
+-		pio_configure(nand_pins_lo);
+-	else
++	/* MTR2 */
+ 		pio_configure(nand_pins_hi);
+ 
+ 	pmc_enable_periph_clock(AT91C_ID_PIOC_D);
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c.orig new/board/at91sam9x5ek/at91sam9x5ek.c.orig
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c.orig	1969-12-31 18:00:00.000000000 -0600
++++ new/board/at91sam9x5ek/at91sam9x5ek.c.orig	2019-04-16 14:20:15.036823256 -0500
+@@ -0,0 +1,341 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2008, Atmel Corporation
++ *
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include "common.h"
++#include "hardware.h"
++#include "arch/at91_ccfg.h"
++#include "arch/at91_rstc.h"
++#include "arch/at91_pmc.h"
++#include "arch/at91_smc.h"
++#include "arch/at91_pio.h"
++#include "arch/at91_ddrsdrc.h"
++#include "gpio.h"
++#include "pmc.h"
++#include "usart.h"
++#include "debug.h"
++#include "ddramc.h"
++#include "timer.h"
++#include "watchdog.h"
++#include "string.h"
++#include "at91sam9x5ek.h"
++#include "board_hw_info.h"
++
++static void at91_dbgu_hw_init(void)
++{
++	/* Configure DBGU pins */
++	const struct pio_desc dbgu_pins[] = {
++		{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(dbgu_pins);
++}
++
++static void initialize_dbgu(void)
++{
++	at91_dbgu_hw_init();
++	usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE));
++}
++
++#ifdef CONFIG_DDR2
++/* Using the Micron MT47H64M16HR-3 */
++static void ddramc_reg_config(struct ddramc_register *ddramc_config)
++{
++	ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
++			| AT91C_DDRC2_MD_DDR2_SDRAM);
++
++	ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */
++			| AT91C_DDRC2_NR_13              /* 13 row bits (8K) */
++			| AT91C_DDRC2_CAS_3              /* CAS Latency 3 */
++			| AT91C_DDRC2_NB_BANKS_8         /* 8 banks */
++			| AT91C_DDRC2_DISABLE_RESET_DLL
++			| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
++
++	/*
++	 * Make sure to uncomment the following line if the DDR controller
++	 * shares the EBI with another memory controller (SMC, NAND,..).
++	 * For instance, AT91C_DDRC2_EBISHARE shall be set if NAND flash
++	 * data line 0 is positioned on EBI data line 0 (AT91C_EBI_NFD0_ON_D16 bit
++	 * cleared in CCFG_EBICSA register).
++	 *
++	 * For Atmel AT91SAM9x5-EK revision B onwards, this AT91C_DDRC2_EBISHARE bit
++	 * is cleared because the NAND flash data line 0 is positioned on EBI
++	 * data line number 16 (AT91C_EBI_NFD0_ON_D16 bit set in CCFG_EBICSA
++	 * register). Only the DDR controller function is thus used on lower
++	 * EBI data lines.
++	 */
++	//ddramc_config->cr |= AT91C_DDRC2_EBISHARE;       /* DQM is shared with other controller */
++
++
++	/*
++	 * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
++	 * With a 133 MHz frequency, the refresh timer count register must to be
++	 * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
++	 * or (7.81 x 133 MHz) ~ 1040 i.e. 0x410.
++	 */
++	ddramc_config->rtr = 0x411;     /* Refresh timer: 7.8125us */
++
++	/* One clock cycle @ 133 MHz = 7.5 ns */
++	ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)	/* 6 * 7.5 = 45 ns */
++			| AT91C_DDRC2_TRCD_(2)		/* 2 * 7.5 = 22.5 ns */
++			| AT91C_DDRC2_TWR_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TRC_(8)		/* 8 * 7.5 = 75   ns */
++			| AT91C_DDRC2_TRP_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TRRD_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TWTR_(2)		/* 2 clock cycles min */
++			| AT91C_DDRC2_TMRD_(2));	/* 2 clock cycles */
++
++	ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)	/*  2 clock cycles */
++			| AT91C_DDRC2_TXSRD_(200)	/* 200 clock cycles */
++			| AT91C_DDRC2_TXSNR_(19)	/* 19 * 7.5 = 142.5 ns*/
++			| AT91C_DDRC2_TRFC_(18));	/* 18 * 7.5 = 135 ns */
++
++	ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)	/* 7 * 7.5 = 52.5 ns */
++			| AT91C_DDRC2_TRTP_(2)		/* 2 clock cycles min */
++			| AT91C_DDRC2_TRPA_(3)		/* 3 * 7.5 = 22.5 ns */
++			| AT91C_DDRC2_TXARDS_(7)	/* 7 clock cycles */
++			| AT91C_DDRC2_TXARD_(2));	/* 2 clock cycles */
++}
++
++static void ddramc_init(void)
++{
++	unsigned long csa;
++	struct ddramc_register ddramc_reg;
++
++	ddramc_reg_config(&ddramc_reg);
++
++	/* ENABLE DDR2 clock */
++	pmc_enable_system_clock(AT91C_PMC_DDR);
++
++	/* Chip select 1 is for DDR2/SDRAM */
++	csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
++	csa |= AT91C_EBI_CS1A_SDRAMC;
++	csa &= ~AT91C_EBI_DBPUC;
++	csa |= AT91C_EBI_DBPDC;
++	csa |= AT91C_EBI_DRV_HD;
++
++	writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
++
++	/* DDRAM2 Controller initialize */
++	ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg);
++}
++#endif	/* #ifdef CONFIG_DDR2 */
++
++static void one_wire_hw_init(void)
++{
++	const struct pio_desc wire_pio[] = {
++		{"1-Wire", AT91C_PIN_PB(18), 1, PIO_DEFAULT, PIO_OUTPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(wire_pio);
++}
++
++#ifdef CONFIG_HW_INIT
++void hw_init(void)
++{
++	/* Disable watchdog */
++	at91_disable_wdt();
++
++	/*
++	 * At this stage the main oscillator is
++	 * supposed to be enabled PCK = MCK = MOSC
++	 */
++	pmc_init_pll(0);
++
++	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
++	pmc_cfg_plla(PLLA_SETTINGS);
++
++	/* Switch PCK/MCK on Main clock output */
++	pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
++
++	/* Switch PCK/MCK on PLLA output */
++	pmc_cfg_mck(BOARD_PRESCALER_PLLA);
++
++	/* Enable External Reset */
++	writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
++
++	/* Init timer */
++	timer_init();
++
++	/* Initialize dbgu */
++	initialize_dbgu();
++
++#ifdef CONFIG_DDR2
++	/* Initialize DDRAM Controller */
++	ddramc_init();
++#endif
++	/* one wire pin init */
++	one_wire_hw_init();
++}
++#endif /* #ifdef CONFIG_HW_INIT */
++
++#ifdef CONFIG_DATAFLASH
++void at91_spi0_hw_init(void)
++{
++	/* Configure PINs for SPI0 */
++	const struct pio_desc spi0_pins[] = {
++		{"MISO",	AT91C_PIN_PA(11),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"MOSI",	AT91C_PIN_PA(12),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"SPCK",	AT91C_PIN_PA(13),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"NPCS",	CONFIG_SYS_SPI_PCS,	1, PIO_DEFAULT, PIO_OUTPUT},
++		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(spi0_pins);
++
++	pmc_enable_periph_clock(AT91C_ID_SPI0);
++}
++#endif	/* #ifdef CONFIG_DATAFLASH */
++
++#ifdef CONFIG_SDCARD
++#ifdef CONFIG_OF_LIBFDT
++void at91_board_set_dtb_name(char *of_name)
++{
++	unsigned int cpu_board_id = get_cm_sn();
++	unsigned int disp_board_id = get_dm_sn();
++
++	if (cpu_board_id == BOARD_ID_SAM9G15_CM)
++		strcpy(of_name, "at91sam9g15ek");
++	else if (cpu_board_id == BOARD_ID_SAM9G25_CM)
++		strcpy(of_name, "at91sam9g25ek");
++	else if (cpu_board_id == BOARD_ID_SAM9G35_CM)
++		strcpy(of_name, "at91sam9g35ek");
++	else if (cpu_board_id == BOARD_ID_SAM9X25_CM)
++		strcpy(of_name, "at91sam9x25ek");
++	else if (cpu_board_id == BOARD_ID_SAM9X35_CM)
++		strcpy(of_name, "at91sam9x35ek");
++	else
++		dbg_info("WARNING: Not correct CPU board ID\n");
++
++	if (disp_board_id == BOARD_ID_PDA_DM)
++		strcat(of_name, "_pda");
++
++	strcat(of_name, ".dtb");
++}
++#endif
++
++void at91_mci0_hw_init(void)
++{
++	const struct pio_desc mci_pins[] = {
++		{"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(mci_pins);
++
++	/* Enable the clock */
++	pmc_enable_periph_clock(AT91C_ID_HSMCI0);
++}
++#endif /* #ifdef CONFIG_SDCARD */
++
++#ifdef CONFIG_NANDFLASH
++void nandflash_hw_init(void)
++{
++	unsigned int reg;
++
++	/* Configure Nand PINs */
++	const struct pio_desc nand_pins_hi[] = {
++		{"NANDOE",	CONFIG_SYS_NAND_OE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDWE",	CONFIG_SYS_NAND_WE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDALE",	CONFIG_SYS_NAND_ALE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDCLE",	CONFIG_SYS_NAND_CLE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++