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| author | John Klug <john.klug@multitech.com> | 2019-04-04 17:52:16 -0500 |
|---|---|---|
| committer | John Klug <john.klug@multitech.com> | 2019-04-04 17:55:01 -0500 |
| commit | 32780ad71b7db900c4fa42d09df79930ad24c2dd (patch) | |
| tree | 3df4b81a2ed87a1d51bc1da93f79291339beaf32 | |
| parent | 6904f40d448d26cbb21c5ad116097757d24a9050 (diff) | |
| download | meta-multitech-32780ad71b7db900c4fa42d09df79930ad24c2dd.tar.gz meta-multitech-32780ad71b7db900c4fa42d09df79930ad24c2dd.tar.bz2 meta-multitech-32780ad71b7db900c4fa42d09df79930ad24c2dd.zip | |
Pin High GPIO pins that overlap with PIOB
| -rw-r--r-- | recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch | 50 |
1 files changed, 46 insertions, 4 deletions
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch index 313bd91..0a7600d 100644 --- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch +++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch @@ -32,9 +32,51 @@ Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig +# CONFIG_DISABLE_WATCHDOG is not set Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c =================================================================== ---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-11 05:07:35.000000000 -0500 -+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-29 15:14:44.578915819 -0500 -@@ -312,10 +312,8 @@ +--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-04 15:49:54.143358228 -0500 ++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c 2019-04-04 17:31:57.691176941 -0500 +@@ -53,6 +53,31 @@ + extern void hw_init_hook(void); + #endif + ++ ++static void initialize_mt_gpio(void) ++{ ++ /* Configure DBGU pins */ ++ const struct pio_desc mt_gpio_pins[] = { ++ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH ++ * B A20-A25 until bootstrap shuts them down. ++ * This code prevents these pins from being used ++ * during boot, since we do not ++ * need these pins to boot the system and we ++ * do not want resets to toggle needlessly. ++ */ ++ {"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT}, ++ {"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT}, ++ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, ++ }; ++ ++ pio_configure(mt_gpio_pins); ++} ++ ++ + static void at91_dbgu_hw_init(void) + { + /* Configure DBGU pins */ +@@ -198,6 +223,9 @@ + slowclk_enable_osc32(); + #endif + ++ /* Initialize MT GPIO */ ++ initialize_mt_gpio(); ++ + /* Initialize dbgu */ + initialize_dbgu(); + +@@ -322,10 +350,8 @@ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); reg |= AT91C_EBI_CS3A_SM; @@ -47,7 +89,7 @@ Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c reg &= ~AT91C_EBI_DRV; writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); -@@ -345,9 +343,7 @@ +@@ -355,9 +381,7 @@ AT91C_BASE_SMC + SMC_CTRL3); /* Configure the PIO controller */ |