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Pin PIOa 7 is resetting to Periph B, SPI0_NPCS1
This might be part of the CPU design for booting
from SPI NAND. This conflicts with our usage as
an input from the USB Host port.
========================================================================================
diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
--- orig/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 16:30:43.653327254 -0500
+++ new/board/at91sam9x5ek/at91sam9x5ek.c 2020-09-10 16:16:38.597352272 -0500
@@ -56,6 +56,49 @@
writel(0xFF, RTC_SCCR + AT91C_BASE_RTC);
}
+
+static void initialize_mt_gpio(void)
+{
+ /* Configure DBGU pins */
+ const struct pio_desc mt_gpio_pins[] = {
+ /* Misc. pins -- Pins PD15-PD18 belong to PERIPH
+ * B A20-A25 until bootstrap shuts them down.
+ * This code prevents these pins from being used
+ * during boot, since we do not
+ * need these pins to boot the system and we
+ * do not want resets to toggle needlessly.
+ * GNSS-RESET is held low because the EXAR
+ * rarely will display the wrong VID/PID on the
+ * USB bus, which prevents the vizzini driver
+ * from loading. Once the VID/PID is bad, a
+ * reboot will preserve the bad VID/PID, so
+ * a power cycle is then required.
+ * PD16 and PD15 are the GPIO expander reset pins
+ * for MTCDT 0.2, and Secure Element Reset and
+ * AP2_TBD3 in MTCDT 0.1 and 0.0. No one should be using
+ * AP2_TBD3 in prior designs, and Secure Element
+ * was never used/populated.
+ * For the PCA9557, tw(rst) is listed as 6nS on page
+ * 16 of Product Data Sheet Revision 7, 10 December 2013.
+ */
+ {"WIFI_BT_RESET",AT91C_PIN_PD(14), 0, PIO_DEFAULT, PIO_OUTPUT},
+ {"N_GPIO_EXP1_RESET",AT91C_PIN_PD(16), 0, PIO_DEFAULT, PIO_OUTPUT},
+ {"N_GPIO_EXP2_RESET",AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_OUTPUT},
+ {"GNSS-RESET",AT91C_PIN_PD(15), 0, PIO_PULLUP, PIO_OUTPUT},
+ {"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
+ {"USBHUB-RESET",AT91C_PIN_PD(18), 0, PIO_PULLUP, PIO_OUTPUT},
+ {"N_USB_HOST_OC",AT91C_PIN_PA(7), 0, PIO_DEFAULT, PIO_INPUT},
+ {"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
+ {"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
+ {"N_GPIO_EXP1_RESET",AT91C_PIN_PD(16), 1, PIO_DEFAULT, PIO_OUTPUT},
+ {"N_GPIO_EXP2_RESET",AT91C_PIN_PC(26), 1, PIO_DEFAULT, PIO_OUTPUT},
+ {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+ };
+
+ pio_configure(mt_gpio_pins);
+}
+
+
static void at91_dbgu_hw_init(void)
{
/* Configure DBGU pins */
@@ -200,6 +231,9 @@
/* Init timer */
timer_init();
+ /* Initialize MT GPIO */
+ initialize_mt_gpio();
+
/* Initialize dbgu */
initialize_dbgu();
@@ -313,10 +347,14 @@
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
+#ifdef NOTMTCDT
if (get_cm_rev() == 'A')
reg &= ~AT91C_EBI_NFD0_ON_D16;
else
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+#endif /* NOTMTCDT */
+ /* MTCDT */
+ reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
@@ -346,11 +384,15 @@
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the PIO controller */
+#ifdef NOTMTCDT
if (get_cm_rev() == 'A')
pio_configure(nand_pins_lo);
else
+#endif /* NOTMTCDT */
+ /* MTCDT */
pio_configure(nand_pins_hi);
+
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}
#endif /* #ifdef CONFIG_NANDFLASH */
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