Index: linux-3.12.13/drivers/spi/spi-atmel.c
===================================================================
--- linux-3.12.13.orig/drivers/spi/spi-atmel.c	2014-04-04 15:00:11.677055454 -0500
+++ linux-3.12.13/drivers/spi/spi-atmel.c	2014-04-04 15:36:28.973123089 -0500
@@ -291,26 +291,15 @@
 	unsigned active = spi->mode & SPI_CS_HIGH;
 	u32 mr;
 
+	mr = spi_readl(as, MR);
 	if (atmel_spi_is_v2(as)) {
-		spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
-		/* For the low SPI version, there is a issue that PDC transfer
-		 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
+		/* mtcdt: always use CSR0
+		 * old 2.6.39 kernel did this and it worked for supporting more than 4 slaves
 		 */
 		spi_writel(as, CSR0, asd->csr);
-		if (as->caps.has_wdrbt) {
-			spi_writel(as, MR,
-					SPI_BF(PCS, ~(0x01 << spi->chip_select))
-					| SPI_BIT(WDRBT)
-					| SPI_BIT(MODFDIS)
-					| SPI_BIT(MSTR));
-		} else {
-			spi_writel(as, MR,
-					SPI_BF(PCS, ~(0x01 << spi->chip_select))
-					| SPI_BIT(MODFDIS)
-					| SPI_BIT(MSTR));
-		}
-
-		mr = spi_readl(as, MR);
+		mr &= (SPI_BIT(MODFDIS) | SPI_BIT(MSTR) | (as->caps.has_wdrbt ? SPI_BIT(WDRBT) : 0));
+		mr |= SPI_BF(PCS, 0x0e);
+		spi_writel(as, MR, mr);
 		gpio_set_value(asd->npcs_pin, active);
 	} else {
 		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;