diff -Naru orig/board/atmel/at91sam9x5ek/at91sam9x5ek.c new/board/atmel/at91sam9x5ek/at91sam9x5ek.c --- orig/board/atmel/at91sam9x5ek/at91sam9x5ek.c 2021-09-16 07:44:13.962787166 -0500 +++ new/board/atmel/at91sam9x5ek/at91sam9x5ek.c 2021-09-16 07:50:11.414794371 -0500 @@ -44,7 +44,8 @@ csa = readl(&matrix->ebicsa); csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; /* NAND flash on D16 */ - csa |= AT91_MATRIX_NFD0_ON_D16; + /* MTR: nand flash is set up by bootstrap, so leave it alone here */ + /* csa |= AT91_MATRIX_NFD0_ON_D16; */ /* Configure IO drive */ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; @@ -256,6 +257,9 @@ int board_init(void) { + /* Set Status LED High */ + at91_set_gpio_output(BOOT_STATUS_LED, 0); + /* arch number of AT91SAM9X5EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; @@ -362,4 +366,62 @@ /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); } + #endif + +/* on-board EEPROM */ +struct mts_id_eeprom_layout { + char vendor_id[32]; + char product_id[32]; + char device_id[32]; + char hw_version[32]; + uint8_t mac_addr[6]; + char imei[32]; + uint8_t capa[32]; + uint8_t mac_bluetooth[6]; + uint8_t mac_wifi[6]; + uint8_t reserved[302]; +}; + +int board_get_enetaddr(uchar *enetaddr) +{ + struct mts_id_eeprom_layout eeprom_buffer = {0}; + + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, &eeprom_buffer, sizeof(eeprom_buffer))) { + printf("EEPROM: read error\n"); + return 0; + } + + if (eeprom_buffer.vendor_id[0] == 0x00 || eeprom_buffer.vendor_id[0] == 0xFF) { + printf("EEPROM: uninitialized\n"); + return 0; + } + + printf("vendor-id: %s\n", eeprom_buffer.vendor_id); + printf("product-id: %s\n", eeprom_buffer.product_id); + printf("device-id: %s\n", eeprom_buffer.device_id); + printf("hw-version: %s\n", eeprom_buffer.hw_version); + printf("mac-addr: %02x:%02x:%02x:%02x:%02x:%02x\n", eeprom_buffer.mac_addr[0], + eeprom_buffer.mac_addr[1], + eeprom_buffer.mac_addr[2], + eeprom_buffer.mac_addr[3], + eeprom_buffer.mac_addr[4], + eeprom_buffer.mac_addr[5]); + + memcpy(enetaddr, eeprom_buffer.mac_addr, 6); + + return 1; +} + +int misc_init_r(void) +{ + uchar enetaddr[6]; + + /* set MAC address from EEPROM if read successful */ + if (board_get_enetaddr(enetaddr)) { + /* Use random MAC address */ + /* eth_setenv_enetaddr("ethaddr", enetaddr); */ + } + + return 0; +} diff -Naru orig/configs/at91sam9x5ek_nandflash_defconfig new/configs/at91sam9x5ek_nandflash_defconfig --- orig/configs/at91sam9x5ek_nandflash_defconfig 2022-11-18 10:42:42.778249577 -0600 +++ new/configs/at91sam9x5ek_nandflash_defconfig 2022-11-18 10:48:03.694242067 -0600 @@ -315,7 +315,8 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SF is not set # CONFIG_CMD_SPI is not set -CONFIG_CMD_I2C=y +# CONFIG_CMD_I2C is not set +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CMD_USB=y # CONFIG_CMD_DFU is not set # CONFIG_CMD_USB_MASS_STORAGE is not set diff -Naru orig/include/configs/at91sam9x5ek.h new/include/configs/at91sam9x5ek.h --- orig/include/configs/at91sam9x5ek.h 2021-09-16 07:45:26.598788630 -0500 +++ new/include/configs/at91sam9x5ek.h 2021-09-16 07:47:04.478790603 -0500 @@ -9,8 +9,10 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ +#include #include +#define USE_MTR #define CONFIG_SYS_TEXT_BASE 0x26f00000 /* ARM asynchronous clock */ @@ -26,6 +28,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_MISC_INIT_R /* enable platform-dependent misc_init_r() */ + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -36,6 +40,8 @@ #define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ +/* MTR has no LCD */ +#if !defined(MTR) #define CONFIG_LCD #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 @@ -46,7 +52,13 @@ #define CONFIG_ATMEL_HLCD #define CONFIG_ATMEL_LCD_RGB565 #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif /* !defined(MTR) */ + +/* check for keypress even if bootdelay is 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +/*STATUS LED*/ +#define BOOT_STATUS_LED AT91_PIN_PC21 /* * BOOTP options @@ -59,10 +71,7 @@ /* no NOR flash */ #define CONFIG_SYS_NO_FLASH -/* - * Command line configuration. - */ -#define CONFIG_CMD_NAND +#define CONFIG_SYS_I2C /* * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) @@ -94,13 +103,30 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +/* MTR nand ready is PC31 */ +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC31 /* PMECC & PMERRLOC */ #define CONFIG_ATMEL_NAND_HWECC 1 #define CONFIG_ATMEL_NAND_HW_PMECC 1 -#define CONFIG_PMECC_CAP 2 + +/* MTR: 4-bit PMECC */ +#define CONFIG_PMECC_CAP 4 #define CONFIG_PMECC_SECTOR_SIZE 512 +/* + * CONFIG_PMECC_INDEX_TABLE_OFFSET has been replaced by: + * ATMEL_PMECC_INDEX_OFFSET_512 and + * ATMEL_PMECC_INDEX_OFFSET_1024 + * + * Which as used depends on: + * host->pmecc_sector_size == 512 + * + * 2012.10: + * #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 + * 2016.03 (at91sam9x5.h): + * 182:#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 + */ + #define CONFIG_CMD_NAND_TRIMFFS @@ -147,6 +173,23 @@ #endif #endif +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SOFT_I2C +#define CONFIG_SOFT_I2C_GPIO_SCL AT91_PIN_PA31 +#define CONFIG_SOFT_I2C_GPIO_SDA AT91_PIN_PA30 +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED +/* Values from previous levels of Conduit U-Boot */ +#define CONFIG_SYS_I2C_SLAVE 0xfe +#define I2C_RXTX_LEN 128 + +/* I2C eeprom support */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* at24c04 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address<---><------>*/ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 + + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -156,11 +199,11 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0xc0000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_OFFSET_REDUND 0x160000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read " \ - "0x22000000 0x200000 0x300000; " \ - "bootm 0x22000000" +/* MTR: read from env variables for boot */ +#define CONFIG_BOOTCOMMAND "nboot.jffs2 ${loadaddr} 0 ${kernel_addr}; bootm ${loadaddr}" + #elif defined(CONFIG_SYS_USE_SPIFLASH) /* bootstrap + u-boot + env + linux in spi flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -197,6 +240,9 @@ "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ "root=/dev/mmcblk0p2 " \ "rw rootfstype=ext4 rootwait" +#elif defined(USE_MTR) +/* MTR uses jffs2 */ +#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 root=/dev/mtdblock8 ro rootfstype=jffs2" #else #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ @@ -274,4 +320,21 @@ #endif +/* MTR defaults */ +#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ +#define CONFIG_ETHADDR 00:08:00:87:00:02 +#define CONFIG_IPADDR 192.168.2.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.2.2 +#define CONFIG_HOSTNAME AT91SAM9G25 +#define CONFIG_LOADADDR 0x22000000 + +/* MTR - enable watchdog */ +#define CONFIG_AT91SAM9_WATCHDOG 1 +#define CONFIG_HW_WATCHDOG 1 +#define CONFIG_AT91_HW_WDT_TIMEOUT 16 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x200000\0" \ + "" + #endif