Move bootstrap to ONFI compatible 3.8.12

23 files changed, 1260 insertions, 463 deletions

diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp
deleted file mode 100644
index f31477d..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/.at91bootstrap-3.5.2-onetime-slow-clock-switch.patch.swp
+++ /dev/null
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
deleted file mode 100644
index 6f007b9..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-Index: at91bootstrap-3.5.2/Makefile
-===================================================================
---- at91bootstrap-3.5.2.orig/Makefile	2013-02-08 14:38:40.660054339 -0600
-+++ at91bootstrap-3.5.2/Makefile	2013-02-08 14:41:30.626272862 -0600
-@@ -359,4 +359,15 @@
- 
- PHONY+=tarball tarballx
- 
-+install:
-+	-install -d $(DESTDIR)
-+	install $(AT91BOOTSTRAP) $(DESTDIR)/$(IMAGE)
-+	-rm -f $(DESTDIR)/$(SYMLINK)
-+	(cd ${DESTDIR} ; \
-+	ln -sf ${IMAGE} ${SYMLINK} \
-+	)
-+
-+
-+PHONY+=install
-+
- .PHONY: $(PHONY)
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch
deleted file mode 100644
index e5dd013..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-disable-rtc-interrupts.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2015-12-21 15:42:05.498892917 -0600
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2015-12-22 14:53:59.151521592 -0600
-@@ -46,6 +46,9 @@
- 
- #include "onewire_info.h"
- 
-+#define RTC_SCCR   0x1C
-+#define RTC_IDR    0x24
-+
- #ifdef CONFIG_USER_HW_INIT
- extern void hw_init_hook(void);
- #endif
-@@ -207,6 +210,12 @@
- #ifdef CONFIG_USER_HW_INIT
- 	hw_init_hook();
- #endif
-+
-+	/* disable all RTC interrupts and clear status register.
-+	 * Prevents possible Linux lockup due to unexpected RTC interrupt
-+	 */
-+	writel(0xFF, RTC_IDR + AT91C_BASE_RTC);
-+	writel(0xFF, RTC_SCCR + AT91C_BASE_RTC);
- }
- #endif /* #ifdef CONFIG_HW_INIT */
- 
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
deleted file mode 100644
index 92a3a3b..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtcdt.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-Index: git/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
-===================================================================
---- git.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2015-01-13 13:31:45.162884794 -0600
-+++ git/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2015-01-13 13:45:17.967816395 -0600
-@@ -1,6 +1,6 @@
- #
- # Automatically generated make config: don't edit
--# Thu Apr 11 16:45:29 2013
-+# Tue Jan 13 13:09:23 2015
- #
- HAVE_DOT_CONFIG=y
- CONFIG_BOARDNAME="at91sam9x5ek"
-@@ -42,7 +42,7 @@
- ALLOW_PIO3=y
- CONFIG_HAS_PIO3=y
- CPU_HAS_PMECC=y
--CONFIG_LOAD_ONE_WIRE=y
-+# CONFIG_LOAD_ONE_WIRE is not set
- # CONFIG_MMC_SUPPORT is not set
- 
- #
-@@ -60,8 +60,8 @@
- # ALLOW_SDRAM_16BIT is not set
- # CONFIG_RAM_32MB is not set
- # CONFIG_RAM_64MB is not set
--CONFIG_RAM_128MB=y
--# CONFIG_RAM_256MB is not set
-+# CONFIG_RAM_128MB is not set
-+CONFIG_RAM_256MB=y
- # CONFIG_RAM_512MB is not set
- # CONFIG_DATAFLASH is not set
- # CONFIG_FLASH is not set
-@@ -81,8 +81,8 @@
- #
- # PMECC Configuration
- #
--CONFIG_PMECC_CORRECT_BITS_2=y
--# CONFIG_PMECC_CORRECT_BITS_4 is not set
-+# CONFIG_PMECC_CORRECT_BITS_2 is not set
-+CONFIG_PMECC_CORRECT_BITS_4=y
- # CONFIG_PMECC_CORRECT_BITS_8 is not set
- # CONFIG_PMECC_CORRECT_BITS_12 is not set
- # CONFIG_PMECC_CORRECT_BITS_24 is not set
-@@ -101,7 +101,7 @@
- # CONFIG_LOAD_64KB is not set
- CONFIG_IMG_ADDRESS="0x00040000"
- CONFIG_IMG_SIZE="0x00080000"
--CONFIG_JUMP_ADDR="0x26F00000"
-+CONFIG_JUMP_ADDR="0x2EF00000"
- 
- #
- # U-Boot Image Storage Setup
-@@ -116,4 +116,4 @@
- # CONFIG_USER_HW_INIT is not set
- CONFIG_THUMB=y
- CONFIG_SCLK=y
--CONFIG_DISABLE_WATCHDOG=y
-+# CONFIG_DISABLE_WATCHDOG is not set
-Index: git/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- git.orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 15:49:54.143358228 -0500
-+++ git/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 17:07:51.999219741 -0500
-@@ -53,6 +53,32 @@
- extern void hw_init_hook(void);
- #endif
- 
-+
-+static void initialize_mt_gpio(void)
-+{
-+ 	/* Configure DBGU pins */
-+	const struct pio_desc mt_gpio_pins[] = {
-+		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
-+		 * B A20-A25 until bootstrap shuts them down.
-+                 * This code prevents these pins from being used
-+                 * during boot, since we do not
-+                 * need these pins to boot the system and we
-+                 * do not want resets to toggle needlessly.
-+		 */
-+		{"WFBT-RESET",AT91C_PIN_PD(14), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
-+		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
-+        };
-+
-+	pio_configure(mt_gpio_pins);
-+}
-+
-+
- static void at91_dbgu_hw_init(void)
- {
- 	/* Configure DBGU pins */
-@@ -198,6 +223,9 @@
- 	slowclk_enable_osc32();
- #endif
- 
-+        /* Initialize MT GPIO */
-+        initialize_mt_gpio();
-+
- 	/* Initialize dbgu */
- 	initialize_dbgu();
- 
-@@ -322,10 +350,8 @@
- 
- 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
- 	reg |= AT91C_EBI_CS3A_SM;
--	if (get_cm_rev() == 'A')
--		reg &= ~AT91C_EBI_NFD0_ON_D16;
--	else
--		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
-+	/* MTCDT */
-+	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
- 
- 	reg &= ~AT91C_EBI_DRV;
- 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
-@@ -355,9 +381,7 @@
- 		AT91C_BASE_SMC + SMC_CTRL3);
- 
- 	/* Configure the PIO controller */
--	if (get_cm_rev() == 'A')
--		pio_configure(nand_pins_lo);
--	else
-+	/* MTCDT */
- 		pio_configure(nand_pins_hi);
- 
- 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch
deleted file mode 100644
index 0a7600d..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtr.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-11 05:07:35.000000000 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-29 15:13:01.390913836 -0500
-@@ -42,7 +42,8 @@
- ALLOW_PIO3=y
- CONFIG_HAS_PIO3=y
- CPU_HAS_PMECC=y
--CONFIG_LOAD_ONE_WIRE=y
-+# MTS: don't load one wire
-+# CONFIG_LOAD_ONE_WIRE is not set
- # CONFIG_MMC_SUPPORT is not set
- 
- #
-@@ -81,8 +82,8 @@
- #
- # PMECC Configuration
- #
--CONFIG_PMECC_CORRECT_BITS_2=y
--# CONFIG_PMECC_CORRECT_BITS_4 is not set
-+# CONFIG_PMECC_CORRECT_BITS_2 is not set
-+CONFIG_PMECC_CORRECT_BITS_4=y
- # CONFIG_PMECC_CORRECT_BITS_8 is not set
- # CONFIG_PMECC_CORRECT_BITS_12 is not set
- # CONFIG_PMECC_CORRECT_BITS_24 is not set
-@@ -116,4 +117,5 @@
- # CONFIG_USER_HW_INIT is not set
- CONFIG_THUMB=y
- CONFIG_SCLK=y
--CONFIG_DISABLE_WATCHDOG=y
-+# MTS: don't disable watchdog
-+# CONFIG_DISABLE_WATCHDOG is not set
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 15:49:54.143358228 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-04 17:31:57.691176941 -0500
-@@ -53,6 +53,31 @@
- extern void hw_init_hook(void);
- #endif
- 
-+
-+static void initialize_mt_gpio(void)
-+{
-+ 	/* Configure DBGU pins */
-+	const struct pio_desc mt_gpio_pins[] = {
-+		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
-+		 * B A20-A25 until bootstrap shuts them down.
-+                 * This code prevents these pins from being used
-+                 * during boot, since we do not
-+                 * need these pins to boot the system and we
-+                 * do not want resets to toggle needlessly.
-+		 */
-+		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
-+		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
-+		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
-+        };
-+
-+	pio_configure(mt_gpio_pins);
-+}
-+
-+
- static void at91_dbgu_hw_init(void)
- {
- 	/* Configure DBGU pins */
-@@ -198,6 +223,9 @@
- 	slowclk_enable_osc32();
- #endif
- 
-+        /* Initialize MT GPIO */
-+        initialize_mt_gpio();
-+
- 	/* Initialize dbgu */
- 	initialize_dbgu();
- 
-@@ -322,10 +350,8 @@
- 
- 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
- 	reg |= AT91C_EBI_CS3A_SM;
--	if (get_cm_rev() == 'A')
--		reg &= ~AT91C_EBI_NFD0_ON_D16;
--	else
--		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
-+	/* MTR */
-+	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
- 
- 	reg &= ~AT91C_EBI_DRV;
- 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
-@@ -355,9 +381,7 @@
- 		AT91C_BASE_SMC + SMC_CTRL3);
- 
- 	/* Configure the PIO controller */
--	if (get_cm_rev() == 'A')
--		pio_configure(nand_pins_lo);
--	else
-+	/* MTR2 */
- 		pio_configure(nand_pins_hi);
- 
- 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch
deleted file mode 100644
index 912a891..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
-===================================================================
---- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2015-09-29 09:55:07.335113881 -0500
-+++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2015-09-29 10:13:19.397489104 -0500
-@@ -81,7 +81,8 @@
- 			| AT91C_DDRC2_CAS_3              /* CAS Latency 3 */
- 			| AT91C_DDRC2_NB_BANKS_8         /* 8 banks */
- 			| AT91C_DDRC2_DLL_RESET_DISABLED /* DLL not reset */
--			| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
-+			| AT91C_DDRC2_DIC_DS		 /* Low DDR Drive Strength */
-+			| AT91C_DDRC2_DECOD_INTERLEAVED);/* Interleaved decode*/
- 
- 	/*
- 	 * Make sure to uncomment the following line if the DDR controller
-Index: at91bootstrap-3.5.3/main.c
-===================================================================
---- at91bootstrap-3.5.3.orig/main.c	2013-04-11 05:07:35.000000000 -0500
-+++ at91bootstrap-3.5.3/main.c	2015-09-29 10:10:21.354971492 -0500
-@@ -68,12 +68,15 @@
- {
- 	char *version = "AT91Bootstrap";
- 	char *ver_num = " "AT91BOOTSTRAP_VERSION" ("COMPILE_TIME")";
-+	char *feature = "DDR Drive Strength: low";
- 
- 	dbgu_print("\n\r");
- 	dbgu_print("\n\r");
- 	dbgu_print(version);
- 	dbgu_print(ver_num);
- 	dbgu_print("\n\r");
-+	dbgu_print(feature);
-+	dbgu_print("\n\r");
- 	dbgu_print("\n\r");
- }
- 
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch
deleted file mode 100644
index 01920c2..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.3-remove-std-includes.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-Index: at91bootstrap-3.5.3/driver/debug.c
-===================================================================
---- at91boostrap-3.5.3.orig/driver/debug.c.orig	2017-02-13 16:14:17.214217038 -0600
-+++ at91boostrap-3.5.3/driver/debug.c	2017-02-13 15:48:44.106262425 -0600
-@@ -27,7 +27,6 @@
-  */
- #include "dbgu.h"
- #include "debug.h"
--#include <stdio.h>
- #include <stdarg.h>
- 
- #define MAX_BUFFER	128
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch
new file mode 100644
index 0000000..f299d30
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtcdt.patch
@@ -0,0 +1,76 @@
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:20:15.036823256 -0500
++++ new/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:26:10.648812728 -0500
+@@ -44,6 +44,31 @@
+ #include "at91sam9x5ek.h"
+ #include "board_hw_info.h"
+ 
++
++static void initialize_mt_gpio(void)
++{
++ 	/* Configure DBGU pins */
++	const struct pio_desc mt_gpio_pins[] = {
++		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
++		 * B A20-A25 until bootstrap shuts them down.
++                 * This code prevents these pins from being used
++                 * during boot, since we do not
++                 * need these pins to boot the system and we
++                 * do not want resets to toggle needlessly.
++		 */
++		{"GNSS-RESET",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"SECURE-RESET",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"MTQ-RESET",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"USBHUB-RESET",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"GNSS-INT",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"WIFI-BT-LPMODE",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++        };
++
++	pio_configure(mt_gpio_pins);
++}
++
++
+ static void at91_dbgu_hw_init(void)
+ {
+ 	/* Configure DBGU pins */
+@@ -185,6 +210,9 @@
+ 	/* Init timer */
+ 	timer_init();
+ 
++        /* Initialize MT GPIO */
++        initialize_mt_gpio();
++
+ 	/* Initialize dbgu */
+ 	initialize_dbgu();
+ 
+@@ -298,10 +326,14 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
++#ifdef NOTMTCDT
+ 	if (get_cm_rev() == 'A')
+ 		reg &= ~AT91C_EBI_NFD0_ON_D16;
+ 	else
+ 		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++#endif /* NOTMTCDT */
++        /* MTCDT */
++	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -331,11 +363,15 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
++#ifdef NOTMTCDT
+ 	if (get_cm_rev() == 'A')
+ 		pio_configure(nand_pins_lo);
+ 	else
++#endif /* NOTMTCDT */
++                /* MTCDT */
+ 		pio_configure(nand_pins_hi);
+ 
++
+ 	pmc_enable_periph_clock(AT91C_ID_PIOC_D);
+ }
+ #endif /* #ifdef CONFIG_NANDFLASH */
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch
new file mode 100644
index 0000000..2993323
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91bootstrap-3.8-mtr.patch
@@ -0,0 +1,414 @@
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:20:15.036823256 -0500
++++ new/board/at91sam9x5ek/at91sam9x5ek.c	2019-04-16 14:42:16.920784122 -0500
+@@ -44,6 +44,31 @@
+ #include "at91sam9x5ek.h"
+ #include "board_hw_info.h"
+ 
++
++static void initialize_mt_gpio(void)
++{
++ 	/* Configure DBGU pins */
++	const struct pio_desc mt_gpio_pins[] = {
++		/* Misc. pins -- Pins PD15-PD18 belong to PERIPH
++		 * B A20-A25 until bootstrap shuts them down.
++                 * This code prevents these pins from being used
++                 * during boot, since we do not
++                 * need these pins to boot the system and we
++                 * do not want resets to toggle needlessly.
++		 */
++		{"PD15",AT91C_PIN_PD(15), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD16",AT91C_PIN_PD(16), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD17",AT91C_PIN_PD(17), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD18",AT91C_PIN_PD(18), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD19",AT91C_PIN_PD(19), 1, PIO_PULLUP, PIO_OUTPUT},
++		{"PD20IN",AT91C_PIN_PD(20), 0, PIO_PULLUP, PIO_INPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++        };
++
++	pio_configure(mt_gpio_pins);
++}
++
++
+ static void at91_dbgu_hw_init(void)
+ {
+ 	/* Configure DBGU pins */
+@@ -185,6 +210,9 @@
+ 	/* Init timer */
+ 	timer_init();
+ 
++        /* Initialize MT GPIO */
++        initialize_mt_gpio();
++
+ 	/* Initialize dbgu */
+ 	initialize_dbgu();
+ 
+@@ -298,10 +326,8 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
+-	if (get_cm_rev() == 'A')
+-		reg &= ~AT91C_EBI_NFD0_ON_D16;
+-	else
+-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++	/* MTR */
++	reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -331,9 +357,7 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
+-	if (get_cm_rev() == 'A')
+-		pio_configure(nand_pins_lo);
+-	else
++	/* MTR2 */
+ 		pio_configure(nand_pins_hi);
+ 
+ 	pmc_enable_periph_clock(AT91C_ID_PIOC_D);
+diff -aNru orig/board/at91sam9x5ek/at91sam9x5ek.c.orig new/board/at91sam9x5ek/at91sam9x5ek.c.orig
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c.orig	1969-12-31 18:00:00.000000000 -0600
++++ new/board/at91sam9x5ek/at91sam9x5ek.c.orig	2019-04-16 14:20:15.036823256 -0500
+@@ -0,0 +1,341 @@
++/* ----------------------------------------------------------------------------
++ *         ATMEL Microcontroller Software Support
++ * ----------------------------------------------------------------------------
++ * Copyright (c) 2008, Atmel Corporation
++ *
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * - Redistributions of source code must retain the above copyright notice,
++ * this list of conditions and the disclaimer below.
++ *
++ * Atmel's name may not be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
++ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
++ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include "common.h"
++#include "hardware.h"
++#include "arch/at91_ccfg.h"
++#include "arch/at91_rstc.h"
++#include "arch/at91_pmc.h"
++#include "arch/at91_smc.h"
++#include "arch/at91_pio.h"
++#include "arch/at91_ddrsdrc.h"
++#include "gpio.h"
++#include "pmc.h"
++#include "usart.h"
++#include "debug.h"
++#include "ddramc.h"
++#include "timer.h"
++#include "watchdog.h"
++#include "string.h"
++#include "at91sam9x5ek.h"
++#include "board_hw_info.h"
++
++static void at91_dbgu_hw_init(void)
++{
++	/* Configure DBGU pins */
++	const struct pio_desc dbgu_pins[] = {
++		{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(dbgu_pins);
++}
++
++static void initialize_dbgu(void)
++{
++	at91_dbgu_hw_init();
++	usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE));
++}
++
++#ifdef CONFIG_DDR2
++/* Using the Micron MT47H64M16HR-3 */
++static void ddramc_reg_config(struct ddramc_register *ddramc_config)
++{
++	ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
++			| AT91C_DDRC2_MD_DDR2_SDRAM);
++
++	ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */
++			| AT91C_DDRC2_NR_13              /* 13 row bits (8K) */
++			| AT91C_DDRC2_CAS_3              /* CAS Latency 3 */
++			| AT91C_DDRC2_NB_BANKS_8         /* 8 banks */
++			| AT91C_DDRC2_DISABLE_RESET_DLL
++			| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
++
++	/*
++	 * Make sure to uncomment the following line if the DDR controller
++	 * shares the EBI with another memory controller (SMC, NAND,..).
++	 * For instance, AT91C_DDRC2_EBISHARE shall be set if NAND flash
++	 * data line 0 is positioned on EBI data line 0 (AT91C_EBI_NFD0_ON_D16 bit
++	 * cleared in CCFG_EBICSA register).
++	 *
++	 * For Atmel AT91SAM9x5-EK revision B onwards, this AT91C_DDRC2_EBISHARE bit
++	 * is cleared because the NAND flash data line 0 is positioned on EBI
++	 * data line number 16 (AT91C_EBI_NFD0_ON_D16 bit set in CCFG_EBICSA
++	 * register). Only the DDR controller function is thus used on lower
++	 * EBI data lines.
++	 */
++	//ddramc_config->cr |= AT91C_DDRC2_EBISHARE;       /* DQM is shared with other controller */
++
++
++	/*
++	 * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
++	 * With a 133 MHz frequency, the refresh timer count register must to be
++	 * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
++	 * or (7.81 x 133 MHz) ~ 1040 i.e. 0x410.
++	 */
++	ddramc_config->rtr = 0x411;     /* Refresh timer: 7.8125us */
++
++	/* One clock cycle @ 133 MHz = 7.5 ns */
++	ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6)	/* 6 * 7.5 = 45 ns */
++			| AT91C_DDRC2_TRCD_(2)		/* 2 * 7.5 = 22.5 ns */
++			| AT91C_DDRC2_TWR_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TRC_(8)		/* 8 * 7.5 = 75   ns */
++			| AT91C_DDRC2_TRP_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TRRD_(2)		/* 2 * 7.5 = 15   ns */
++			| AT91C_DDRC2_TWTR_(2)		/* 2 clock cycles min */
++			| AT91C_DDRC2_TMRD_(2));	/* 2 clock cycles */
++
++	ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2)	/*  2 clock cycles */
++			| AT91C_DDRC2_TXSRD_(200)	/* 200 clock cycles */
++			| AT91C_DDRC2_TXSNR_(19)	/* 19 * 7.5 = 142.5 ns*/
++			| AT91C_DDRC2_TRFC_(18));	/* 18 * 7.5 = 135 ns */
++
++	ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7)	/* 7 * 7.5 = 52.5 ns */
++			| AT91C_DDRC2_TRTP_(2)		/* 2 clock cycles min */
++			| AT91C_DDRC2_TRPA_(3)		/* 3 * 7.5 = 22.5 ns */
++			| AT91C_DDRC2_TXARDS_(7)	/* 7 clock cycles */
++			| AT91C_DDRC2_TXARD_(2));	/* 2 clock cycles */
++}
++
++static void ddramc_init(void)
++{
++	unsigned long csa;
++	struct ddramc_register ddramc_reg;
++
++	ddramc_reg_config(&ddramc_reg);
++
++	/* ENABLE DDR2 clock */
++	pmc_enable_system_clock(AT91C_PMC_DDR);
++
++	/* Chip select 1 is for DDR2/SDRAM */
++	csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
++	csa |= AT91C_EBI_CS1A_SDRAMC;
++	csa &= ~AT91C_EBI_DBPUC;
++	csa |= AT91C_EBI_DBPDC;
++	csa |= AT91C_EBI_DRV_HD;
++
++	writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
++
++	/* DDRAM2 Controller initialize */
++	ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg);
++}
++#endif	/* #ifdef CONFIG_DDR2 */
++
++static void one_wire_hw_init(void)
++{
++	const struct pio_desc wire_pio[] = {
++		{"1-Wire", AT91C_PIN_PB(18), 1, PIO_DEFAULT, PIO_OUTPUT},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(wire_pio);
++}
++
++#ifdef CONFIG_HW_INIT
++void hw_init(void)
++{
++	/* Disable watchdog */
++	at91_disable_wdt();
++
++	/*
++	 * At this stage the main oscillator is
++	 * supposed to be enabled PCK = MCK = MOSC
++	 */
++	pmc_init_pll(0);
++
++	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
++	pmc_cfg_plla(PLLA_SETTINGS);
++
++	/* Switch PCK/MCK on Main clock output */
++	pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
++
++	/* Switch PCK/MCK on PLLA output */
++	pmc_cfg_mck(BOARD_PRESCALER_PLLA);
++
++	/* Enable External Reset */
++	writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
++
++	/* Init timer */
++	timer_init();
++
++	/* Initialize dbgu */
++	initialize_dbgu();
++
++#ifdef CONFIG_DDR2
++	/* Initialize DDRAM Controller */
++	ddramc_init();
++#endif
++	/* one wire pin init */
++	one_wire_hw_init();
++}
++#endif /* #ifdef CONFIG_HW_INIT */
++
++#ifdef CONFIG_DATAFLASH
++void at91_spi0_hw_init(void)
++{
++	/* Configure PINs for SPI0 */
++	const struct pio_desc spi0_pins[] = {
++		{"MISO",	AT91C_PIN_PA(11),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"MOSI",	AT91C_PIN_PA(12),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"SPCK",	AT91C_PIN_PA(13),	0, PIO_DEFAULT, PIO_PERIPH_A},
++		{"NPCS",	CONFIG_SYS_SPI_PCS,	1, PIO_DEFAULT, PIO_OUTPUT},
++		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(spi0_pins);
++
++	pmc_enable_periph_clock(AT91C_ID_SPI0);
++}
++#endif	/* #ifdef CONFIG_DATAFLASH */
++
++#ifdef CONFIG_SDCARD
++#ifdef CONFIG_OF_LIBFDT
++void at91_board_set_dtb_name(char *of_name)
++{
++	unsigned int cpu_board_id = get_cm_sn();
++	unsigned int disp_board_id = get_dm_sn();
++
++	if (cpu_board_id == BOARD_ID_SAM9G15_CM)
++		strcpy(of_name, "at91sam9g15ek");
++	else if (cpu_board_id == BOARD_ID_SAM9G25_CM)
++		strcpy(of_name, "at91sam9g25ek");
++	else if (cpu_board_id == BOARD_ID_SAM9G35_CM)
++		strcpy(of_name, "at91sam9g35ek");
++	else if (cpu_board_id == BOARD_ID_SAM9X25_CM)
++		strcpy(of_name, "at91sam9x25ek");
++	else if (cpu_board_id == BOARD_ID_SAM9X35_CM)
++		strcpy(of_name, "at91sam9x35ek");
++	else
++		dbg_info("WARNING: Not correct CPU board ID\n");
++
++	if (disp_board_id == BOARD_ID_PDA_DM)
++		strcat(of_name, "_pda");
++
++	strcat(of_name, ".dtb");
++}
++#endif
++
++void at91_mci0_hw_init(void)
++{
++	const struct pio_desc mci_pins[] = {
++		{"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	/* Configure the PIO controller */
++	pmc_enable_periph_clock(AT91C_ID_PIOA_B);
++	pio_configure(mci_pins);
++
++	/* Enable the clock */
++	pmc_enable_periph_clock(AT91C_ID_HSMCI0);
++}
++#endif /* #ifdef CONFIG_SDCARD */
++
++#ifdef CONFIG_NANDFLASH
++void nandflash_hw_init(void)
++{
++	unsigned int reg;
++
++	/* Configure Nand PINs */
++	const struct pio_desc nand_pins_hi[] = {
++		{"NANDOE",	CONFIG_SYS_NAND_OE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDWE",	CONFIG_SYS_NAND_WE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDALE",	CONFIG_SYS_NAND_ALE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDCLE",	CONFIG_SYS_NAND_CLE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},
++		{"D0",	AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D1",	AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D2",	AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D3",	AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D4",	AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D5",	AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D6",	AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{"D7",	AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
++		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	const struct pio_desc nand_pins_lo[] = {
++		{"NANDOE",	CONFIG_SYS_NAND_OE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDWE",	CONFIG_SYS_NAND_WE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDALE",	CONFIG_SYS_NAND_ALE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDCLE",	CONFIG_SYS_NAND_CLE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},
++		{"NANDCS", 	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},
++		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},
++	};
++
++	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
++	reg |= AT91C_EBI_CS3A_SM;
++	if (get_cm_rev() == 'A')
++		reg &= ~AT91C_EBI_NFD0_ON_D16;
++	else
++		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++
++	reg &= ~AT91C_EBI_DRV;
++	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
++
++	/* Configure SMC CS3 */
++	writel((AT91C_SMC_NWESETUP_(1)
++		| AT91C_SMC_NCS_WRSETUP_(0)
++		| AT91C_SMC_NRDSETUP_(2)
++		| AT91C_SMC_NCS_RDSETUP_(0)),
++		AT91C_BASE_SMC + SMC_SETUP3);
++
++	writel((AT91C_SMC_NWEPULSE_(3)
++		| AT91C_SMC_NCS_WRPULSE_(5)
++		| AT91C_SMC_NRDPULSE_(4)
++		| AT91C_SMC_NCS_RDPULSE_(6)),
++		AT91C_BASE_SMC + SMC_PULSE3);
++
++	writel((AT91C_SMC_NWECYCLE_(5)
++		| AT91C_SMC_NRDCYCLE_(7)),
++		AT91C_BASE_SMC + SMC_CYCLE3);
++
++	writel((AT91C_SMC_READMODE
++		| AT91C_SMC_WRITEMODE
++		| AT91C_SMC_NWAITM_NWAIT_DISABLE
++		| AT91C_SMC_DBW_WIDTH_BITS_8
++		| AT91_SMC_TDF_(1)),
++		AT91C_BASE_SMC + SMC_CTRL3);
++
++	/* Configure the PIO controller */
++	if (get_cm_rev() == 'A')
++		pio_configure(nand_pins_lo);
++	else
++		pio_configure(nand_pins_hi);
++
++	pmc_enable_periph_clock(AT91C_ID_PIOC_D);
++}
++#endif /* #ifdef CONFIG_NANDFLASH */
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91sam9x5_4bit_pmecc_header.bin
index f8d6073..f8d6073 100644
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/at91sam9x5_4bit_pmecc_header.bin
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/create_4bit_pmecc_header.rb
index 780d728..780d728 100755
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/create_4bit_pmecc_header.rb
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig
new file mode 100644
index 0000000..ba0a902
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig
@@ -0,0 +1,228 @@
+#
+# In defiance, this file was edited for
+# Multitech systems.
+# 2018 Jan 3 18:15CST
+#
+HAVE_DOT_CONFIG=y
+# CONFIG_AT91SAM9260EK is not set
+# CONFIG_AT91SAM9261EK is not set
+# CONFIG_AT91SAM9263EK is not set
+# CONFIG_AT91SAM9RLEK is not set
+# CONFIG_AT91SAM9XEEK is not set
+# CONFIG_AT91SAM9G10EK is not set
+# CONFIG_AT91SAM9G20EK is not set
+# CONFIG_AT91SAM9M10G45EK is not set
+CONFIG_AT91SAM9X5EK=y
+# CONFIG_AT91SAM9N12EK is not set
+# CONFIG_SAMA5D3XEK is not set
+# CONFIG_SAMA5D3_XPLAINED is not set
+# CONFIG_SAMA5D3X_CMP is not set
+# CONFIG_SAMA5D4EK is not set
+# CONFIG_SAMA5D4_XPLAINED is not set
+# CONFIG_SAMA5D2_PTC is not set
+# CONFIG_SAMA5D2_XPLAINED is not set
+# CONFIG_SAMA5D27_SOM1_EK is not set
+# CONFIG_VINCO is not set
+# CONFIG_AT91SAM9X5_ARIA is not set
+# CONFIG_AT91SAM9X5_ARIETTA is not set
+# CONFIG_SAMA5D3_ACQUA is not set
+# CONFIG_SAMA5D2_ROADRUNNER is not set
+# CONFIG_CORE9G25 is not set
+# CONFIG_SAMA5D3_LINEA is not set
+CONFIG_BOARDNAME="at91sam9x5ek"
+AT91SAM9X5=y
+CONFIG_MACH_TYPE="3373"
+CONFIG_LINK_ADDR="0x300000"
+CONFIG_TOP_OF_MEMORY="0x308000"
+CONFIG_CRYSTAL_12_000MHZ=y
+# CONFIG_CRYSTAL_16_000MHZ is not set
+# CONFIG_CRYSTAL_16_36766MHZ is not set
+# CONFIG_CRYSTAL_18_432MHZ is not set
+# CONFIG_CRYSTAL_24_000MHZ is not set
+ALLOW_CRYSTAL_12_000MHZ=y
+CONFIG_CRYSTAL="CRYSTAL_12_000MHZ"
+# CONFIG_CPU_CLK_166MHZ is not set
+# CONFIG_CPU_CLK_180MHZ is not set
+# CONFIG_CPU_CLK_200MHZ is not set
+# CONFIG_CPU_CLK_240MHZ is not set
+# CONFIG_CPU_CLK_266MHZ is not set
+# CONFIG_CPU_CLK_332MHZ is not set
+# CONFIG_CPU_CLK_348MHZ is not set
+# CONFIG_CPU_CLK_396MHZ is not set
+CONFIG_CPU_CLK_400MHZ=y
+# CONFIG_CPU_CLK_444MHZ is not set
+# CONFIG_CPU_CLK_492MHZ is not set
+# CONFIG_CPU_CLK_498MHZ is not set
+# CONFIG_CPU_CLK_510MHZ is not set
+# CONFIG_CPU_CLK_528MHZ is not set
+# CONFIG_CPU_CLK_594MHZ is not set
+# CONFIG_CPU_CLK_600MHZ is not set
+ALLOW_CPU_CLK_400MHZ=y
+# DISABLE_CPU_CLK_240MHZ is not set
+# CONFIG_BUS_SPEED_83MHZ is not set
+# CONFIG_BUS_SPEED_90MHZ is not set
+# CONFIG_BUS_SPEED_100MHZ is not set
+# CONFIG_BUS_SPEED_116MHZ is not set
+# CONFIG_BUS_SPEED_124MHZ is not set
+CONFIG_BUS_SPEED_133MHZ=y
+# CONFIG_BUS_SPEED_148MHZ is not set
+# CONFIG_BUS_SPEED_164MHZ is not set
+# CONFIG_BUS_SPEED_166MHZ is not set
+# CONFIG_BUS_SPEED_170MHZ is not set
+# CONFIG_BUS_SPEED_176MHZ is not set
+# CONFIG_BUS_SPEED_200MHZ is not set
+SUPPORT_BUS_SPEED_133MHZ=y
+# CPU_HAS_TRUSTZONE is not set
+# CONFIG_CPU_V7 is not set
+# CONFIG_HAS_PMIC_ACT8865 is not set
+# CONFIG_SUPPORT_PM is not set
+# CONFIG_HAS_ONE_WIRE is not set
+# CONFIG_HAS_EEPROM is not set
+# CONFIG_HAS_EHT0_PHY is not set
+# CONFIG_HAS_EHT1_PHY is not set
+# CONFIG_HAS_AUDIO_CODEC is not set
+# CONFIG_HAS_HDMI is not set
+CORE_ARM926EJS=y
+# CORE_CORTEX_A5 is not set
+CPU_HAS_SCKC=y
+# CPU_HAS_H32MXDIV is not set
+CPU_HAS_HSMCI0=y
+CPU_HAS_HSMCI1=y
+# CPU_HAS_HSMCI2 is not set
+# CPU_HAS_MCI0 is not set
+# CPU_HAS_MCI1 is not set
+# CPU_HAS_SDHC0 is not set
+# CPU_HAS_SDHC1 is not set
+CPU_HAS_SPI0=y
+CPU_HAS_SPI1=y
+# CPU_HAS_SPI0_IOSET1 is not set
+# CPU_HAS_SPI0_IOSET2 is not set
+# CPU_HAS_SPI1_IOSET1 is not set
+# CPU_HAS_SPI1_IOSET2 is not set
+# CPU_HAS_SPI1_IOSET3 is not set
+# CPU_HAS_QSPI0 is not set
+# CPU_HAS_QSPI1 is not set
+# CPU_HAS_QSPI0_IOSET1 is not set
+# CPU_HAS_QSPI0_IOSET2 is not set
+# CPU_HAS_QSPI0_IOSET3 is not set
+# CPU_HAS_QSPI1_IOSET1 is not set
+# CPU_HAS_QSPI1_IOSET2 is not set
+# CPU_HAS_QSPI1_IOSET3 is not set
+CPU_HAS_PIO3=y
+# CPU_HAS_L2CC is not set
+CPU_HAS_PMECC=y
+CONFIG_HAS_HW_INFO=y
+# CONFIG_TWI is not set
+# CONFIG_TWI0 is not set
+# CONFIG_TWI1 is not set
+# CONFIG_TWI2 is not set
+# CONFIG_TWI3 is not set
+# CONFIG_MACB is not set
+# CONFIG_AES is not set
+CONFIG_LOAD_HW_INFO=y
+CPU_HAS_TWI0=y
+CPU_HAS_TWI1=y
+CPU_HAS_TWI2=y
+# CPU_HAS_TWI3 is not set
+# CPU_HAS_AES is not set
+# CPU_HAS_PIO4 is not set
+
+#
+# Memory selection
+#
+# CONFIG_SDRAM is not set
+# CONFIG_SDDRC is not set
+CONFIG_DDRC=y
+ALLOW_DATAFLASH=y
+# ALLOW_FLASH is not set
+ALLOW_NANDFLASH=y
+ALLOW_SDCARD=y
+# ALLOW_PSRAM is not set
+# ALLOW_SDRAM_16BIT is not set
+
+#
+# RAM Configuration
+#
+# CONFIG_RAM_32MB is not set
+# CONFIG_RAM_64MB is not set
+# CONFIG_RAM_128MB is not set
+CONFIG_RAM_256MB=y
+# CONFIG_RAM_512MB is not set
+# CONFIG_LPDDR1 is not set
+# CONFIG_LPDDR2 is not set
+# CONFIG_LPDDR3 is not set
+CONFIG_DDR2=y
+# CONFIG_DDR3 is not set
+# CONFIG_SAMA5D2_LPDDR2 is not set
+# CONFIG_DATAFLASH is not set
+# CONFIG_FLASH is not set
+CONFIG_NANDFLASH=y
+# CONFIG_SDCARD is not set
+CONFIG_MEMORY="nandflash"
+ALLOW_BOOT_FROM_DATAFLASH_CS0=y
+
+#
+# NAND flash configuration
+#
+# CONFIG_ENABLE_SW_ECC is not set
+CONFIG_USE_PMECC=y
+# CONFIG_ON_DIE_ECC is not set
+
+#
+# PMECC Configuration
+#
+CONFIG_PMECC_AUTO_DETECT=y
+# CONFIG_PMECC_CORRECT_BITS_2 is not set
+# CONFIG_PMECC_CORRECT_BITS_4 is not set
+# CONFIG_PMECC_CORRECT_BITS_8 is not set
+# CONFIG_PMECC_CORRECT_BITS_12 is not set
+# CONFIG_PMECC_CORRECT_BITS_24 is not set
+CONFIG_PMECC_SECTOR_SIZE_512=y
+# CONFIG_PMECC_SECTOR_SIZE_1024 is not set
+# CONFIG_NANDFLASH_SMALL_BLOCKS is not set
+CONFIG_ONFI_DETECT_SUPPORT=y
+CONFIG_USE_ON_DIE_ECC_SUPPORT=y
+# ALLOW_NANDFLASH_RECOVERY is not set
+CONFIG_BOOTSTRAP_MAXSIZE="23000"
+CONFIG_PROJECT="nandflash"
+CONFIG_LOAD_UBOOT=y
+# CONFIG_LOAD_LINUX is not set
+# CONFIG_LOAD_ANDROID is not set
+# CONFIG_LOAD_1MB is not set
+# CONFIG_LOAD_4MB is not set
+# CONFIG_LOAD_64KB is not set
+CONFIG_IMG_ADDRESS="0x00040000"
+CONFIG_JUMP_ADDR="0x2EF00000"
+
+#
+# U-Boot Image Storage Setup
+#
+CONFIG_IMG_SIZE="0x00080000"
+CONFIG_IMAGE_NAME="u-boot.bin"
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_LOUD is not set
+CONFIG_DEBUG_VERY_LOUD=y is not set
+CONFIG_THUMB=y
+# CONFIG_DISABLE_WATCHDOG is not set
+
+#
+# Hardware Initialization Options
+#
+CONFIG_HW_DISPLAY_BANNER=y
+# Indicate ONFI Usage
+CONFIG_HW_BANNER="\"\\n\\nAT91Bootstrap \" AT91BOOTSTRAP_VERSION \" (\" COMPILE_TIME \")/MTechONFI\\n\\n\""
+CONFIG_HW_INIT=y
+# CONFIG_USER_HW_INIT is not set
+
+#
+# Slow Clock Configuration Options
+#
+CONFIG_SCLK=y
+# CONFIG_SCLK_BYPASS is not set
+# CONFIG_BACKUP_MODE is not set
+
+#
+# Board Hardware Information Options
+#
+# CONFIG_LOAD_ONE_WIRE is not set
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig.mtr b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig.mtr
new file mode 100644
index 0000000..b79a0ee
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/defconfig.mtr
@@ -0,0 +1,228 @@
+#
+# In defiance, this file was edited for
+# Multitech systems.
+# 2018 Jan 3 18:15CST
+#
+HAVE_DOT_CONFIG=y
+# CONFIG_AT91SAM9260EK is not set
+# CONFIG_AT91SAM9261EK is not set
+# CONFIG_AT91SAM9263EK is not set
+# CONFIG_AT91SAM9RLEK is not set
+# CONFIG_AT91SAM9XEEK is not set
+# CONFIG_AT91SAM9G10EK is not set
+# CONFIG_AT91SAM9G20EK is not set
+# CONFIG_AT91SAM9M10G45EK is not set
+CONFIG_AT91SAM9X5EK=y
+# CONFIG_AT91SAM9N12EK is not set
+# CONFIG_SAMA5D3XEK is not set
+# CONFIG_SAMA5D3_XPLAINED is not set
+# CONFIG_SAMA5D3X_CMP is not set
+# CONFIG_SAMA5D4EK is not set
+# CONFIG_SAMA5D4_XPLAINED is not set
+# CONFIG_SAMA5D2_PTC is not set
+# CONFIG_SAMA5D2_XPLAINED is not set
+# CONFIG_SAMA5D27_SOM1_EK is not set
+# CONFIG_VINCO is not set
+# CONFIG_AT91SAM9X5_ARIA is not set
+# CONFIG_AT91SAM9X5_ARIETTA is not set
+# CONFIG_SAMA5D3_ACQUA is not set
+# CONFIG_SAMA5D2_ROADRUNNER is not set
+# CONFIG_CORE9G25 is not set
+# CONFIG_SAMA5D3_LINEA is not set
+CONFIG_BOARDNAME="at91sam9x5ek"
+AT91SAM9X5=y
+CONFIG_MACH_TYPE="3373"
+CONFIG_LINK_ADDR="0x300000"
+CONFIG_TOP_OF_MEMORY="0x308000"
+CONFIG_CRYSTAL_12_000MHZ=y
+# CONFIG_CRYSTAL_16_000MHZ is not set
+# CONFIG_CRYSTAL_16_36766MHZ is not set
+# CONFIG_CRYSTAL_18_432MHZ is not set
+# CONFIG_CRYSTAL_24_000MHZ is not set
+ALLOW_CRYSTAL_12_000MHZ=y
+CONFIG_CRYSTAL="CRYSTAL_12_000MHZ"
+# CONFIG_CPU_CLK_166MHZ is not set
+# CONFIG_CPU_CLK_180MHZ is not set
+# CONFIG_CPU_CLK_200MHZ is not set
+# CONFIG_CPU_CLK_240MHZ is not set
+# CONFIG_CPU_CLK_266MHZ is not set
+# CONFIG_CPU_CLK_332MHZ is not set
+# CONFIG_CPU_CLK_348MHZ is not set
+# CONFIG_CPU_CLK_396MHZ is not set
+CONFIG_CPU_CLK_400MHZ=y
+# CONFIG_CPU_CLK_444MHZ is not set
+# CONFIG_CPU_CLK_492MHZ is not set
+# CONFIG_CPU_CLK_498MHZ is not set
+# CONFIG_CPU_CLK_510MHZ is not set
+# CONFIG_CPU_CLK_528MHZ is not set
+# CONFIG_CPU_CLK_594MHZ is not set
+# CONFIG_CPU_CLK_600MHZ is not set
+ALLOW_CPU_CLK_400MHZ=y
+# DISABLE_CPU_CLK_240MHZ is not set
+# CONFIG_BUS_SPEED_83MHZ is not set
+# CONFIG_BUS_SPEED_90MHZ is not set
+# CONFIG_BUS_SPEED_100MHZ is not set
+# CONFIG_BUS_SPEED_116MHZ is not set
+# CONFIG_BUS_SPEED_124MHZ is not set
+CONFIG_BUS_SPEED_133MHZ=y
+# CONFIG_BUS_SPEED_148MHZ is not set
+# CONFIG_BUS_SPEED_164MHZ is not set
+# CONFIG_BUS_SPEED_166MHZ is not set
+# CONFIG_BUS_SPEED_170MHZ is not set
+# CONFIG_BUS_SPEED_176MHZ is not set
+# CONFIG_BUS_SPEED_200MHZ is not set
+SUPPORT_BUS_SPEED_133MHZ=y
+# CPU_HAS_TRUSTZONE is not set
+# CONFIG_CPU_V7 is not set
+# CONFIG_HAS_PMIC_ACT8865 is not set
+# CONFIG_SUPPORT_PM is not set
+# CONFIG_HAS_ONE_WIRE is not set
+# CONFIG_HAS_EEPROM is not set
+# CONFIG_HAS_EHT0_PHY is not set
+# CONFIG_HAS_EHT1_PHY is not set
+# CONFIG_HAS_AUDIO_CODEC is not set
+# CONFIG_HAS_HDMI is not set
+CORE_ARM926EJS=y
+# CORE_CORTEX_A5 is not set
+CPU_HAS_SCKC=y
+# CPU_HAS_H32MXDIV is not set
+CPU_HAS_HSMCI0=y
+CPU_HAS_HSMCI1=y
+# CPU_HAS_HSMCI2 is not set
+# CPU_HAS_MCI0 is not set
+# CPU_HAS_MCI1 is not set
+# CPU_HAS_SDHC0 is not set
+# CPU_HAS_SDHC1 is not set
+CPU_HAS_SPI0=y
+CPU_HAS_SPI1=y
+# CPU_HAS_SPI0_IOSET1 is not set
+# CPU_HAS_SPI0_IOSET2 is not set
+# CPU_HAS_SPI1_IOSET1 is not set
+# CPU_HAS_SPI1_IOSET2 is not set
+# CPU_HAS_SPI1_IOSET3 is not set
+# CPU_HAS_QSPI0 is not set
+# CPU_HAS_QSPI1 is not set
+# CPU_HAS_QSPI0_IOSET1 is not set
+# CPU_HAS_QSPI0_IOSET2 is not set
+# CPU_HAS_QSPI0_IOSET3 is not set
+# CPU_HAS_QSPI1_IOSET1 is not set
+# CPU_HAS_QSPI1_IOSET2 is not set
+# CPU_HAS_QSPI1_IOSET3 is not set
+CPU_HAS_PIO3=y
+# CPU_HAS_L2CC is not set
+CPU_HAS_PMECC=y
+CONFIG_HAS_HW_INFO=y
+# CONFIG_TWI is not set
+# CONFIG_TWI0 is not set
+# CONFIG_TWI1 is not set
+# CONFIG_TWI2 is not set
+# CONFIG_TWI3 is not set
+# CONFIG_MACB is not set
+# CONFIG_AES is not set
+CONFIG_LOAD_HW_INFO=y
+CPU_HAS_TWI0=y
+CPU_HAS_TWI1=y
+CPU_HAS_TWI2=y
+# CPU_HAS_TWI3 is not set
+# CPU_HAS_AES is not set
+# CPU_HAS_PIO4 is not set
+
+#
+# Memory selection
+#
+# CONFIG_SDRAM is not set
+# CONFIG_SDDRC is not set
+CONFIG_DDRC=y
+ALLOW_DATAFLASH=y
+# ALLOW_FLASH is not set
+ALLOW_NANDFLASH=y
+ALLOW_SDCARD=y
+# ALLOW_PSRAM is not set
+# ALLOW_SDRAM_16BIT is not set
+
+#
+# RAM Configuration
+#
+# CONFIG_RAM_32MB is not set
+# CONFIG_RAM_64MB is not set
+CONFIG_RAM_128MB=y
+# CONFIG_RAM_256MB is not set
+# CONFIG_RAM_512MB is not set
+# CONFIG_LPDDR1 is not set
+# CONFIG_LPDDR2 is not set
+# CONFIG_LPDDR3 is not set
+CONFIG_DDR2=y
+# CONFIG_DDR3 is not set
+# CONFIG_SAMA5D2_LPDDR2 is not set
+# CONFIG_DATAFLASH is not set
+# CONFIG_FLASH is not set
+CONFIG_NANDFLASH=y
+# CONFIG_SDCARD is not set
+CONFIG_MEMORY="nandflash"
+ALLOW_BOOT_FROM_DATAFLASH_CS0=y
+
+#
+# NAND flash configuration
+#
+# CONFIG_ENABLE_SW_ECC is not set
+CONFIG_USE_PMECC=y
+# CONFIG_ON_DIE_ECC is not set
+
+#
+# PMECC Configuration
+#
+CONFIG_PMECC_AUTO_DETECT=y
+# CONFIG_PMECC_CORRECT_BITS_2 is not set
+# CONFIG_PMECC_CORRECT_BITS_4 is not set
+# CONFIG_PMECC_CORRECT_BITS_8 is not set
+# CONFIG_PMECC_CORRECT_BITS_12 is not set
+# CONFIG_PMECC_CORRECT_BITS_24 is not set
+CONFIG_PMECC_SECTOR_SIZE_512=y
+# CONFIG_PMECC_SECTOR_SIZE_1024 is not set
+# CONFIG_NANDFLASH_SMALL_BLOCKS is not set
+CONFIG_ONFI_DETECT_SUPPORT=y
+CONFIG_USE_ON_DIE_ECC_SUPPORT=y
+# ALLOW_NANDFLASH_RECOVERY is not set
+CONFIG_BOOTSTRAP_MAXSIZE="23000"
+CONFIG_PROJECT="nandflash"
+CONFIG_LOAD_UBOOT=y
+# CONFIG_LOAD_LINUX is not set
+# CONFIG_LOAD_ANDROID is not set
+# CONFIG_LOAD_1MB is not set
+# CONFIG_LOAD_4MB is not set
+# CONFIG_LOAD_64KB is not set
+CONFIG_IMG_ADDRESS="0x00040000"
+CONFIG_JUMP_ADDR="0x26F00000"
+
+#
+# U-Boot Image Storage Setup
+#
+CONFIG_IMG_SIZE="0x00080000"
+CONFIG_IMAGE_NAME="u-boot.bin"
+CONFIG_DEBUG=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_LOUD is not set
+CONFIG_DEBUG_VERY_LOUD=y is not set
+CONFIG_THUMB=y
+# CONFIG_DISABLE_WATCHDOG is not set
+
+#
+# Hardware Initialization Options
+#
+CONFIG_HW_DISPLAY_BANNER=y
+# Indicate ONFI Usage
+CONFIG_HW_BANNER="\"\\n\\nAT91Bootstrap \" AT91BOOTSTRAP_VERSION \" (\" COMPILE_TIME \")/MTechONFI\\n\\n\""
+CONFIG_HW_INIT=y
+# CONFIG_USER_HW_INIT is not set
+
+#
+# Slow Clock Configuration Options
+#
+CONFIG_SCLK=y
+# CONFIG_SCLK_BYPASS is not set
+# CONFIG_BACKUP_MODE is not set
+
+#
+# Board Hardware Information Options
+#
+# CONFIG_LOAD_ONE_WIRE is not set
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch
new file mode 100644
index 0000000..d262972
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/disable-rtc-interrupts.patch
@@ -0,0 +1,32 @@
+diff -Naru orig/board/at91sam9x5ek/at91sam9x5ek.c new/board/at91sam9x5ek/at91sam9x5ek.c
+--- orig/board/at91sam9x5ek/at91sam9x5ek.c	2018-01-04 18:06:52.533763774 -0600
++++ new/board/at91sam9x5ek/at91sam9x5ek.c	2018-01-04 18:32:57.905717432 -0600
+@@ -44,6 +44,18 @@
+ #include "at91sam9x5ek.h"
+ #include "board_hw_info.h"
+ 
++#define RTC_SCCR   0x1C
++#define RTC_IDR    0x24
++
++static void at91_disable_rtc(void)
++{
++	/* disable all RTC interrupts and clear status register.
++	 * Prevents possible Linux lockup due to unexpected RTC interrupt
++	 */
++	writel(0xFF, RTC_IDR + AT91C_BASE_RTC);
++	writel(0xFF, RTC_SCCR + AT91C_BASE_RTC);
++}
++
+ static void at91_dbgu_hw_init(void)
+ {
+ 	/* Configure DBGU pins */
+@@ -161,6 +173,9 @@
+ #ifdef CONFIG_HW_INIT
+ void hw_init(void)
+ {
++        /* 1st chance to disable RTC */
++        at91_disable_rtc();
++        
+ 	/* Disable watchdog */
+ 	at91_disable_wdt();
+ 
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch
new file mode 100644
index 0000000..e57ba89
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/mtrv1-DDRlowDriveStrength.patch
@@ -0,0 +1,22 @@
+diff -Naru at91bootstrap-3.8.12.orig/board/at91sam9x5ek/at91sam9x5ek.c at91bootstrap-3.8.12/board/at91sam9x5ek/at91sam9x5ek.c
+--- at91bootstrap-3.8.12.orig/board/at91sam9x5ek/at91sam9x5ek.c	2019-03-19 16:57:01.976164610 -0500
++++ at91bootstrap-3.8.12/board/at91sam9x5ek/at91sam9x5ek.c	2019-03-19 16:58:01.688162842 -0500
+@@ -75,6 +75,7 @@
+ 			| AT91C_DDRC2_CAS_3              /* CAS Latency 3 */
+ 			| AT91C_DDRC2_NB_BANKS_8         /* 8 banks */
+ 			| AT91C_DDRC2_DISABLE_RESET_DLL
++			| AT91C_DDRC2_DIC_DS		 /* Low DDR Drive Strength */
+ 			| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
+ 
+ 	/*
+diff -Naru at91bootstrap-3.8.12.orig/driver/common.c at91bootstrap-3.8.12/driver/common.c
+--- at91bootstrap-3.8.12.orig/driver/common.c	2019-03-19 16:46:52.532182652 -0500
++++ at91bootstrap-3.8.12/driver/common.c	2019-03-19 16:48:42.144179407 -0500
+@@ -143,6 +143,7 @@
+ 		usart_puts(media);
+ 
+ 	if (retval == 0) {
++                usart_puts("DDR Drive Strength: low\n");
+ #if defined(CONFIG_LOAD_NONE)
+ 		usart_puts("AT91Bootstrap completed. Can load application via JTAG and jump.\n");
+ #else
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/onetime-slow-clock-switch.patch
index 98ccd41..ebd007f 100644
--- a/recipes-bsp/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch
+++ b/recipes-bsp/at91bootstrap/at91bootstrap-3.8.12/onetime-slow-clock-switch.patch
@@ -1,20 +1,17 @@
-Index: at91bootstrap-3.5.2/driver/at91_slowclk.c
-===================================================================
---- at91bootstrap-3.5.2.orig/driver/at91_slowclk.c	2013-01-30 04:01:20.000000000 -0600
-+++ at91bootstrap-3.5.2/driver/at91_slowclk.c	2013-04-24 11:35:44.369827054 -0500
-@@ -33,12 +33,17 @@
- {
+diff -Naru orig/driver/at91_slowclk.c new/driver/at91_slowclk.c
+--- orig/driver/at91_slowclk.c	2019-03-18 16:56:37.362723190 -0500
++++ new/driver/at91_slowclk.c	2019-03-18 17:06:16.138706056 -0500
+@@ -35,12 +35,15 @@
+ #if !defined(SAMA5D4) && !defined(SAMA5D2)
  	unsigned int reg;
  
 -	/*
 -	 * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
 -	 */
-+
  	reg = readl(AT91C_BASE_SCKCR);
 -	reg |= AT91C_SLCKSEL_OSC32EN;
 -	writel(reg, AT91C_BASE_SCKCR);
-+
-+	/* Only enable 32768 Hz oscillator if needed */
++        /* Only enable 32768 Hz oscillator if needed */
 +	if ( !(reg & AT91C_SLCKSEL_OSC32EN) ) {
 +		/*
 +	 	 * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
@@ -22,44 +19,50 @@ Index: at91bootstrap-3.5.2/driver/at91_slowclk.c
 +		reg |= AT91C_SLCKSEL_OSC32EN;
 +		writel(reg, AT91C_BASE_SCKCR);
 +	}
+ #endif /* #if !defined(SAMA5D4) && !defined(SAMA5D2) */
  
  	/* start a internal timer */
- 	start_interval_timer();
-@@ -50,32 +55,40 @@
+@@ -67,12 +70,15 @@
  {
  	unsigned int reg;
  
 -	/*
--	 * Wait 32768 Hz Startup Time for clock stabilization (software loop)
--	 * wait about 1s (1000ms)
--	 */
--	wait_interval_timer(1000);
--
--	/*
--	 * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
--	 * by setting the bit OSCSEL to 1
+-	 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
 -	 */
++        /* Only disable internal RC oscillator if needed */
  	reg = readl(AT91C_BASE_SCKCR);
--	reg |= AT91C_SLCKSEL_OSCSEL;
+-	reg &= ~AT91C_SLCKSEL_RCEN;
 -	writel(reg, AT91C_BASE_SCKCR);
++	if (reg | AT91C_SLCKSEL_RCEN) {
++		/*
++		 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
++		 */
++		reg &= ~AT91C_SLCKSEL_RCEN;
++		writel(reg, AT91C_BASE_SCKCR);
++	}
+ }
+ #endif /* #if !defined(SAMA5D4) && !defined(SAMA5D2) */
+ 
+@@ -90,22 +96,32 @@
+ 	if (reg & AT91C_SLCKSEL_OSCSEL)
+ 		return 0;
  
+-	reg |= AT91C_SLCKSEL_OSCSEL;
+-	writel(reg, AT91C_BASE_SCKCR);
+-
 -	/*
 -	 * Waiting 5 slow clock cycles for internal resynchronization
 -	 * 5 slow clock cycles = ~153 us (5 / 32768)
 -	 */
 -	udelay(153);
 -
--	/*
--	 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
--	 */
-+	/* Only switch clock source if needed */
-+	if ( !(reg & AT91C_SLCKSEL_OSCSEL) ) {
-+		dbgu_print("Switching slow clock to external oscillator...\n\r");
++        if ( !(reg & AT91C_SLCKSEL_OSCSEL) ) {
++		dbg_printf("Switching slow clock to external oscillator...\n");
 +		/*
 +		 * Wait 32768 Hz Startup Time for clock stabilization (software loop)
-+		 * wait about 1s (1000ms)
++		 * wait about ~1s (1300ms)
 +		 */
-+		wait_interval_timer(1000);
++		slowclk_wait_osc32_stable();
 +
 +		/*
 +		 * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
@@ -74,18 +77,13 @@ Index: at91bootstrap-3.5.2/driver/at91_slowclk.c
 +		 */
 +		udelay(153);
 +	}
-+
-+	/* Only disable internal RC oscillator if needed */
- 	reg = readl(AT91C_BASE_SCKCR);
--	reg &= ~AT91C_SLCKSEL_RCEN;
--	writel(reg, AT91C_BASE_SCKCR);
-+	if (reg | AT91C_SLCKSEL_RCEN) {
-+		/*
-+		 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
-+		 */
-+		reg &= ~AT91C_SLCKSEL_RCEN;
-+		writel(reg, AT91C_BASE_SCKCR);
-+	}
- 
  	return 0;
  }
+ 
+ int slowclk_switch_osc32(void)
+ {
+-	slowclk_wait_osc32_stable();
+-
+ 	slowclk_select_osc32();
+ 
+ #if !defined(SAMA5D4) && !defined(SAMA5D2)
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap.inc b/recipes-bsp/at91bootstrap/at91bootstrap.inc
new file mode 100644
index 0000000..599713e
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap.inc
@@ -0,0 +1,122 @@
+SUMMARY = "Initial bootstrap for AT91 ARM MPUs"
+DESCRIPTION = " \
+		at91bootstrap is the second-level bootloader for Atmel AT91  \
+		SoCs. It provides a set of algorithms to manage the hardware \
+		initialization and to download the main application (or a    \
+		third-level bootloader) from specified boot media to         \
+		main memory and start it.                                    \
+	      "
+AUTHOR = "Atmel Corporation"
+HOMEPAGE = "http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap"
+BUGTRACKER = "https://github.com/linux4sam/at91bootstrap/issues"
+SECTION = "bootloaders"
+LICENSE = "ATMEL"
+LIC_FILES_CHKSUM = "file://main.c;endline=27;md5=42f86d2f6fd17d1221c5c651b487a07f"
+
+
+inherit cml1 deploy
+
+SRC_URI_append = " \
+	file://defconfig \
+	file://onetime-slow-clock-switch.patch \
+	file://disable-rtc-interrupts.patch \
+	file://at91sam9x5_4bit_pmecc_header.bin \
+"
+SRC_URI_append_mtrv1 = " file://mtrv1-DDRlowDriveStrength.patch \
+	file://defconfig.mtr \
+	file://at91bootstrap-3.8-mtr.patch \
+"
+SRC_URI_append_mtr = " file://defconfig.mtr \
+	file://at91bootstrap-3.8-mtr.patch \
+"
+
+SRC_URI_append_mtcdt = " file://at91bootstrap-3.8-mtcdt.patch "
+SRC_URI_append_mtcap = " file://at91bootstrap-3.8-mtcdt.patch "
+
+AT91BOOTSTRAP_MACHINE ??= "${MACHINE}"
+
+AT91BOOTSTRAP_CONFIG ??= "${AT91BOOTSTRAP_MACHINE}nf_uboot"
+AT91BOOTSTRAP_CONFIG_at91sam9x5ek-sd ??= "${AT91BOOTSTRAP_MACHINE}sd_uboot"
+AT91BOOTSTRAP_CONFIG_sama5d3-xplained-sd ??= "${AT91BOOTSTRAP_MACHINE}sd_uboot"
+AT91BOOTSTRAP_CONFIG_sama5d4ek ??= "${AT91BOOTSTRAP_MACHINE}nf_uboot_secure"
+AT91BOOTSTRAP_CONFIG_sama5d4-xplained ??= "${AT91BOOTSTRAP_MACHINE}nf_uboot_secure"
+AT91BOOTSTRAP_CONFIG_sama5d4-xplained-sd ??= "${AT91BOOTSTRAP_MACHINE}sd_uboot_secure"
+AT91BOOTSTRAP_CONFIG_sama5d2-xplained ??= "${AT91BOOTSTRAP_MACHINE}-bsrdf_uboot"
+AT91BOOTSTRAP_CONFIG_sama5d2-xplained-sd ??= "${AT91BOOTSTRAP_MACHINE}-bsrsd_uboot"
+AT91BOOTSTRAP_CONFIG_sama5d27-som1-ek ??= "${AT91BOOTSTRAP_MACHINE}qspi_uboot"
+AT91BOOTSTRAP_CONFIG_sama5d27-som1-ek-sd ??= "${AT91BOOTSTRAP_MACHINE}sd_uboot"
+
+AT91BOOTSTRAP_TARGET ??= "${AT91BOOTSTRAP_CONFIG}_defconfig"
+AT91BOOTSTRAP_LOAD ??= "nandflashboot-uboot"
+AT91BOOTSTRAP_LOAD_at91sam9x5ek-sd ??= "sdboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d2-xplained ??= "dataflashboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d2-xplained-sd ??= "sdboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d27-som1-ek ??= "qspiboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d27-som1-ek-sd ??= "sdboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d3-xplained-sd ??= "sdboot-uboot"
+AT91BOOTSTRAP_LOAD_sama5d4-xplained-sd ??= "sdboot-uboot"
+
+AT91BOOTSTRAP_SUFFIX ?= "bin"
+AT91BOOTSTRAP_IMAGE ?= "${AT91BOOTSTRAP_MACHINE}-${AT91BOOTSTRAP_LOAD}-${PV}.${PR}.${AT91BOOTSTRAP_SUFFIX}"
+AT91BOOTSTRAP_BINARY ?= "at91bootstrap.${AT91BOOTSTRAP_SUFFIX}"
+AT91BOOTSTRAP_SYMLINK ?= "at91bootstrap-${AT91BOOTSTRAP_MACHINE}.${AT91BOOTSTRAP_SUFFIX}"
+
+EXTRA_OEMAKE = 'CROSS_COMPILE=${TARGET_PREFIX} REVISION=${PR} CC="${TARGET_PREFIX}gcc ${TOOLCHAIN_OPTIONS}"'
+
+do_configure() {
+	# Copy board defconfig to .config if .config does not exist. This
+	# allows recipes to manage the .config themselves in
+	# do_configure_prepend().
+	if [ -f "${S}/board/${AT91BOOTSTRAP_MACHINE}/${AT91BOOTSTRAP_TARGET}" ] && [ ! -f "${B}/.config" ]; then
+		cp "${S}/board/${AT91BOOTSTRAP_MACHINE}/${AT91BOOTSTRAP_TARGET}" "${B}/.config"
+	fi
+
+	# Copy defconfig to .config if .config does not exist. This allows
+	# recipes to manage the .config themselves in do_configure_prepend()
+	# and to override default settings with a custom file.
+	if [[ ${MACHINE} == mtr ]] || [[ ${MACHINE} == mtrv1 ]] ; then
+            CTYPE=".mtr"
+        fi
+	
+	if [ -f "${WORKDIR}/defconfig${CTYPE}" ] && [ ! -f "${B}/.config" ]; then
+		cp "${WORKDIR}/defconfig${CTYPE}" "${B}/.config"
+	fi
+
+	if [ ! -f "${S}/.config" ]; then
+		bbfatal "No config files found"
+	fi
+
+	cml1_do_configure
+}
+
+do_compile() {
+	if [ "${@bb.utils.contains('DISTRO_FEATURES', 'ld-is-gold', 'ld-is-gold', '', d)}" = "ld-is-gold" ] ; then
+		sed -i 's/$(CROSS_COMPILE)ld$/$(CROSS_COMPILE)ld.bfd/g' ${S}/Makefile
+	fi
+
+	unset CFLAGS CPPFLAGS LDFLAGS
+	oe_runmake
+}
+
+do_deploy () {
+	install -d ${DEPLOYDIR}
+	install ${S}/binaries/${AT91BOOTSTRAP_BINARY} ${DEPLOYDIR}/${AT91BOOTSTRAP_IMAGE}
+
+	cd ${DEPLOYDIR}
+	rm -f ${AT91BOOTSTRAP_BINARY} ${AT91BOOTSTRAP_SYMLINK}
+	ln -sf ${AT91BOOTSTRAP_IMAGE} ${AT91BOOTSTRAP_SYMLINK}
+	ln -sf ${AT91BOOTSTRAP_IMAGE} ${AT91BOOTSTRAP_BINARY}
+
+	# Create a symlink ready for file copy on SD card
+	rm -f boot.bin BOOT.BIN
+	ln -sf ${AT91BOOTSTRAP_IMAGE} BOOT.BIN
+
+	# Create padded version.  Padded version is to be eliminated later.
+        cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOYDIR}/at91bootstrap_pmecc_padded.bin
+        cat ${DEPLOYDIR}/${AT91BOOTSTRAP_IMAGE} >> ${DEPLOYDIR}/at91bootstrap_pmecc_padded.bin
+}
+
+addtask deploy before do_build after do_compile
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb
deleted file mode 100644
index 04ff0db..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb
+++ /dev/null
@@ -1,34 +0,0 @@
-require at91bootstrap_3.5.inc
-
-PR = "r5"
-
-LICENSE = "custom-freely-distributable"
-LIC_FILES_CHKSUM = "file://main.c;beginline=6;endline=26;md5=6fca71334c9e8b7d033296123c91437f"
-
-SRCREV = "v${PV}"
-SRC_URI = "git://github.com/linux4sam/at91bootstrap \
-		file://at91bootstrap-3.5.2-add-install.patch \
-		file://at91bootstrap-3.5.2-onetime-slow-clock-switch.patch \
-		file://at91sam9x5_4bit_pmecc_header.bin \
-		file://at91bootstrap-3.5.3-disable-rtc-interrupts.patch"
-
-S = "${WORKDIR}/git"
-
-SRC_URI_append_mtcdt = " file://at91bootstrap-3.5.3-mtcdt.patch "
-SRC_URI_append_mtcap = " file://at91bootstrap-3.5.3-mtcdt.patch "
-SRC_URI_append_mtr = " file://at91bootstrap-3.5.3-mtr.patch"
-SRC_URI_append_mtrv1 = " file://at91bootstrap-3.5.3-mtr.patch \
-                         file://at91bootstrap-3.5.3-mtrv1-DDRlowDriveStrength.patch \
-"
-
-# generate a bootstrap file padded with the header needed for 4-bit PMECC
-# The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA
-do_pad_4bit_pmecc() {
-	cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
-	cat ${DEPLOY_DIR_IMAGE}/at91bootstrap.bin >> ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
-}
-
-do_install_append() {
-	do_pad_4bit_pmecc
-}
-
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb.orig b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb.orig
deleted file mode 100644
index c6ae7a7..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.3.bb.orig
+++ /dev/null
@@ -1,31 +0,0 @@
-require at91bootstrap_3.5.inc
-
-PR = "r2"
-
-LICENSE = "custom-freely-distributable"
-LIC_FILES_CHKSUM = "file://main.c;beginline=6;endline=26;md5=6fca71334c9e8b7d033296123c91437f"
-
-SRCREV = "v${PV}"
-SRC_URI = "git://github.com/linux4sam/at91bootstrap \
-		file://at91bootstrap-3.5.2-add-install.patch \
-		file://at91bootstrap-3.5.2-onetime-slow-clock-switch.patch \
-		file://at91sam9x5_4bit_pmecc_header.bin \
-		file://at91bootstrap-3.5.3-remove-std-includes.patch \
-		"
-
-S = "${WORKDIR}/git"
-
-SRC_URI_append_mtcdt = " file://at91bootstrap-3.5.3-mtcdt.patch "
-SRC_URI_append_mtcap = " file://at91bootstrap-3.5.3-mtcdt.patch "
-
-# generate a bootstrap file padded with the header needed for 4-bit PMECC
-# The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA
-do_pad_4bit_pmecc() {
-	cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
-	cat ${DEPLOY_DIR_IMAGE}/at91bootstrap.bin >> ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
-}
-
-do_install_append() {
-	do_pad_4bit_pmecc
-}
-
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc b/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc
deleted file mode 100644
index 4b3e957..0000000
--- a/recipes-bsp/at91bootstrap/at91bootstrap_3.5.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-DESCRIPTION = "at91bootstrap: loaded into internal SRAM by AT91 BootROM"
-SECTION = "bootloaders"
-
-PARALLEL_MAKE = ""
-
-PACKAGE_ARCH = "${MACHINE_ARCH}"
-EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOY_DIR_IMAGE} REVISION=${PR}"
-
-do_compile () {
-	unset LDFLAGS
-	unset CFLAGS
-	unset CPPFLAGS
-
-        # For Newer Yocto/Bitbake, CC does not
-        # include the staging directory
-        # by default
-        CC="${CC} --sysroot=${STAGING_DIR_HOST}"
-        LD="${LD} --sysroot=${STAGING_DIR_HOST}"
-
-	rm -Rf ${S}/binaries
-	for board in ${AT91BOOTSTRAP_BOARD} ; do
-		oe_runmake mrproper CC="${CC}" LD="${LD}"
-		filename=`find board -name ${board}_defconfig`
-		if ! [ "x$filename" == "x" ] ; then 
-			cp $filename .config
-			oe_runmake CC="${CC}" LD="${LD}"
-			oe_runmake install
-		else
-			echo "${board} could not be built"
-			exit 1
-		fi
-	done
-}
diff --git a/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb b/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb
new file mode 100644
index 0000000..99ba701
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/at91bootstrap_3.8.12.bb
@@ -0,0 +1,10 @@
+require at91bootstrap.inc
+PR = "m1"
+
+LIC_FILES_CHKSUM = "file://main.c;endline=27;md5=a2a70db58191379e2550cbed95449fbd"
+
+SRC_URI = "https://github.com/linux4sam/at91bootstrap/archive/v${PV}.tar.gz;name=tarball"
+
+SRC_URI[tarball.md5sum] = "9cdcd5b427a7998315e9a0cad4488ffd"
+SRC_URI[tarball.sha256sum] = "871140177e2cab7eeed572556025f9fdc5e82b2bb18302445d13db0f95e21694"
+
diff --git a/recipes-bsp/at91bootstrap/files/Creating-symlink-to-binary.patch b/recipes-bsp/at91bootstrap/files/Creating-symlink-to-binary.patch
new file mode 100644
index 0000000..7103d60
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/files/Creating-symlink-to-binary.patch
@@ -0,0 +1,30 @@
+From 35f4ab2ed71cd3fc13ccf14525e7de2c27348c61 Mon Sep 17 00:00:00 2001
+From: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+Date: Fri, 13 Dec 2013 10:20:03 +0100
+Subject: [PATCH 2/2] Creating symlink to binary
+
+Since the name of the flashable image is config-dependant, we create a
+symlink to this file to have a standard name to the last built flashable
+image.
+
+Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Makefile b/Makefile
+index 0b1cae6..11062f0 100644
+--- a/Makefile
++++ b/Makefile
+@@ -287,6 +287,7 @@ $(AT91BOOTSTRAP): $(OBJS)
+ 	@$(LD) $(LDFLAGS) -n -o $(BINDIR)/$(BOOT_NAME).elf $(OBJS)
+ #	@$(OBJCOPY) --strip-debug --strip-unneeded $(BINDIR)/$(BOOT_NAME).elf -O binary $(BINDIR)/$(BOOT_NAME).bin
+ 	@$(OBJCOPY) --strip-all $(BINDIR)/$(BOOT_NAME).elf -O binary $@
++	@ln -sf $(BOOT_NAME).bin ${BINDIR}/${SYMLINK}
+ 
+ %.o : %.c .config
+ 	@echo "  CC        "$<
+-- 
+1.8.2.2
+
diff --git a/recipes-bsp/at91bootstrap/files/Remove-standard-includes.patch b/recipes-bsp/at91bootstrap/files/Remove-standard-includes.patch
new file mode 100644
index 0000000..01fa9d4
--- /dev/null
+++ b/recipes-bsp/at91bootstrap/files/Remove-standard-includes.patch
@@ -0,0 +1,59 @@
+From b1e85d514d24edf45bbb8a6b647238d00194f369 Mon Sep 17 00:00:00 2001
+From: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+Date: Thu, 12 Dec 2013 11:57:27 +0100
+Subject: [PATCH 1/2] Remove standard includes
+
+These includes are not needed and fail the build when using a custom
+built toolchain from OpenEmbedded.
+
+Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+---
+ Makefile       | 4 +++-
+ driver/debug.c | 1 -
+ driver/flash.c | 2 --
+ 3 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 03dd9df..0b1cae6 100644
+--- a/Makefile
++++ b/Makefile
+@@ -211,7 +211,9 @@ OBJS:= $(SOBJS-y) $(COBJS-y)
+ INCL=board/$(BOARDNAME)
+ GC_SECTIONS=--gc-sections
+ 
+-CPPFLAGS=-ffunction-sections -g -Os -Wall \
++NOSTDINC_FLAGS=-nostdinc -isystem $(shell $(CC) -print-file-name=include)
++
++CPPFLAGS=$(NOSTDINC_FLAGS) -ffunction-sections -g -Os -Wall \
+ 	-fno-stack-protector -fno-common \
+ 	-I$(INCL) -Iinclude -Ifs/include \
+ 	-DAT91BOOTSTRAP_VERSION=\"$(VERSION)$(REV)$(SCMINFO)\" -DCOMPILE_TIME="\"$(DATE)\""
+diff --git a/driver/debug.c b/driver/debug.c
+index 9f83e4b..352c34f 100644
+--- a/driver/debug.c
++++ b/driver/debug.c
+@@ -27,7 +27,6 @@
+  */
+ #include "usart.h"
+ #include "debug.h"
+-#include <stdio.h>
+ #include <stdarg.h>
+ 
+ #define MAX_BUFFER	128
+diff --git a/driver/flash.c b/driver/flash.c
+index 11615c7..ebc5d5a 100644
+--- a/driver/flash.c
++++ b/driver/flash.c
+@@ -26,8 +26,6 @@
+ #include "../include/part.h"
+ #include "../include/main.h"
+ #include "../include/flash.h"
+-#include <stdlib.h>
+-
+ 
+ int load_norflash(unsigned int img_addr,
+ 		unsigned int img_size,
+-- 
+1.8.2.2
+