diff options
Diffstat (limited to 'recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915')
| -rw-r--r-- | recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 index 9f6031d..02d8d4c 100644 --- a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 +++ b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 @@ -17,22 +17,22 @@ "tx_freq_min": 923300000, "tx_freq_max": 927500000, "tx_lut":[ - { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 111, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 }, - { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 104, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 }, - { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 101, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 }, - { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 91, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 }, - { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 87, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 }, - { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 79, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -2, "ad9361_tcomp_coeff_b": -610 }, - { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 71, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1247 }, - { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 63, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 }, - { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 55, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 }, - { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 47, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 }, - { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 43, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, - { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 39, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, - { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 35, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, - { "rf_power": 28, "fpga_dig_gain": 5, "ad9361_atten": 30, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 }, - { "rf_power": 29, "fpga_dig_gain": 5, "ad9361_atten": 26, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 }, - { "rf_power": 30, "fpga_dig_gain": 5, "ad9361_atten": 22, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }] + { "rf_power": 2, "fpga_dig_gain": 0, "ad9361_atten": 60, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 }, + { "rf_power": 3, "fpga_dig_gain": 0, "ad9361_atten": 56, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 }, + { "rf_power": 4, "fpga_dig_gain": 0, "ad9361_atten": 52, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 }, + { "rf_power": 5, "fpga_dig_gain": 0, "ad9361_atten": 48, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 }, + { "rf_power": 6, "fpga_dig_gain": 0, "ad9361_atten": 44, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, + { "rf_power": 7, "fpga_dig_gain": 0, "ad9361_atten": 40, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, + { "rf_power": 8, "fpga_dig_gain": 0, "ad9361_atten": 36, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 }, + { "rf_power": 9, "fpga_dig_gain": 0, "ad9361_atten": 32, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 }, + { "rf_power": 10, "fpga_dig_gain": 0, "ad9361_atten": 28, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 }, + { "rf_power": 11, "fpga_dig_gain": 0, "ad9361_atten": 24, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }, + { "rf_power": 12, "fpga_dig_gain": 0, "ad9361_atten": 20, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }, + { "rf_power": 13, "fpga_dig_gain": 0, "ad9361_atten": 16, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }, + { "rf_power": 14, "fpga_dig_gain": 0, "ad9361_atten": 12, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 }, + { "rf_power": 15, "fpga_dig_gain": 0, "ad9361_atten": 8, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 }, + { "rf_power": 16, "fpga_dig_gain": 0, "ad9361_atten": 4, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 }, + { "rf_power": 17, "fpga_dig_gain": 0, "ad9361_atten": 0, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 }] }], "SX1301_conf":[ { |