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Diffstat (limited to 'recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP920')
-rw-r--r--recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP92064
1 files changed, 32 insertions, 32 deletions
diff --git a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP920 b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP920
index 2229cb9..ffaf73d 100644
--- a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP920
+++ b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_dual_antenna_8ch_full_diversity_JP920
@@ -17,22 +17,22 @@
"tx_freq_min": 920800000,
"tx_freq_max": 923400000,
"tx_lut":[
- { "rf_power": 2, "fpga_dig_gain": 5, "ad9361_atten": 135, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 5, "fpga_dig_gain": 5, "ad9361_atten": 122, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 7, "fpga_dig_gain": 5, "ad9361_atten": 115, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 108, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -18, "ad9361_tcomp_coeff_b": 573 },
- { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 100, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
- { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 96, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 264 },
- { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 93, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 179 },
- { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 87, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -15, "ad9361_tcomp_coeff_b": 0 },
- { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 78, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -14, "ad9361_tcomp_coeff_b": -141 },
- { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 69, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": -550 },
- { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 61, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": -718 },
- { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 54, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": -1195 },
- { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 44, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": -1268 },
- { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 40, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -1662 },
- { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 34, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -1865 },
- { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 30, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -7, "ad9361_tcomp_coeff_b": -2102 }]
+ { "rf_power": 2, "fpga_dig_gain": 0, "ad9361_atten": 60, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 3, "fpga_dig_gain": 0, "ad9361_atten": 56, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 4, "fpga_dig_gain": 0, "ad9361_atten": 52, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 5, "fpga_dig_gain": 0, "ad9361_atten": 48, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 6, "fpga_dig_gain": 0, "ad9361_atten": 44, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 7, "fpga_dig_gain": 0, "ad9361_atten": 40, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 8, "fpga_dig_gain": 0, "ad9361_atten": 36, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 9, "fpga_dig_gain": 0, "ad9361_atten": 32, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 10, "fpga_dig_gain": 0, "ad9361_atten": 28, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 11, "fpga_dig_gain": 0, "ad9361_atten": 24, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 12, "fpga_dig_gain": 0, "ad9361_atten": 20, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 13, "fpga_dig_gain": 0, "ad9361_atten": 16, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 14, "fpga_dig_gain": 0, "ad9361_atten": 12, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 },
+ { "rf_power": 15, "fpga_dig_gain": 0, "ad9361_atten": 8, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 },
+ { "rf_power": 16, "fpga_dig_gain": 0, "ad9361_atten": 4, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 },
+ { "rf_power": 17, "fpga_dig_gain": 0, "ad9361_atten": 0, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 }]
},{
/* RX */
"rx_enable": true,
@@ -44,22 +44,22 @@
"tx_freq_min": 920800000,
"tx_freq_max": 923400000,
"tx_lut":[
- { "rf_power": 2, "fpga_dig_gain": 5, "ad9361_atten": 135, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 5, "fpga_dig_gain": 5, "ad9361_atten": 122, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 7, "fpga_dig_gain": 5, "ad9361_atten": 115, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 752 },
- { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 108, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -18, "ad9361_tcomp_coeff_b": 573 },
- { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 100, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
- { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 96, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 264 },
- { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 93, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 179 },
- { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 87, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -15, "ad9361_tcomp_coeff_b": 0 },
- { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 78, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -14, "ad9361_tcomp_coeff_b": -141 },
- { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 69, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": -550 },
- { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 61, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": -718 },
- { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 54, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": -1195 },
- { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 44, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": -1268 },
- { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 40, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -1662 },
- { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 34, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -1865 },
- { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 30, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -7, "ad9361_tcomp_coeff_b": -2102 }]
+ { "rf_power": 2, "fpga_dig_gain": 0, "ad9361_atten": 60, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 3, "fpga_dig_gain": 0, "ad9361_atten": 56, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 4, "fpga_dig_gain": 0, "ad9361_atten": 52, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 5, "fpga_dig_gain": 0, "ad9361_atten": 48, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 6, "fpga_dig_gain": 0, "ad9361_atten": 44, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 7, "fpga_dig_gain": 0, "ad9361_atten": 40, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 8, "fpga_dig_gain": 0, "ad9361_atten": 36, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 9, "fpga_dig_gain": 0, "ad9361_atten": 32, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 10, "fpga_dig_gain": 0, "ad9361_atten": 28, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 11, "fpga_dig_gain": 0, "ad9361_atten": 24, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 12, "fpga_dig_gain": 0, "ad9361_atten": 20, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 13, "fpga_dig_gain": 0, "ad9361_atten": 16, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 },
+ { "rf_power": 14, "fpga_dig_gain": 0, "ad9361_atten": 12, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 },
+ { "rf_power": 15, "fpga_dig_gain": 0, "ad9361_atten": 8, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -10, "ad9361_tcomp_coeff_b": 696 },
+ { "rf_power": 16, "fpga_dig_gain": 0, "ad9361_atten": 4, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 },
+ { "rf_power": 17, "fpga_dig_gain": 0, "ad9361_atten": 0, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -907 }]
}],
"SX1301_conf":[
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 12:26:31 +0000