From ce9350c7aaa927a00c3676436cfec331dc507e9e Mon Sep 17 00:00:00 2001
From: Harsh Sharma <92harshsharma@gmail.com>
Date: Wed, 13 Jun 2018 13:55:51 -0500
Subject: Added FPGA registers for full card

---
 libloragw/inc/loragw_fpga.h | 50 ++++++++++++++++++++++++---------------------
 libloragw/src/loragw_fpga.c |  2 ++
 2 files changed, 29 insertions(+), 23 deletions(-)

(limited to 'libloragw')

diff --git a/libloragw/inc/loragw_fpga.h b/libloragw/inc/loragw_fpga.h
index f599f73..852f378 100644
--- a/libloragw/inc/loragw_fpga.h
+++ b/libloragw/inc/loragw_fpga.h
@@ -35,6 +35,8 @@ Maintainer: Michael Coracin
 #define LGW_MAX_NOTCH_FREQ      250000U /* 250 KHz */
 #define LGW_DEFAULT_NOTCH_FREQ  129000U /* 129 KHz */
 
+#define LGW_RF_ATTN_CONV_CONST  4.0f	/* RF Attenuation conversion factor */
+
 /*
 auto generated register mapping for C code
 this file contains autogenerated C struct used to access the FPGA registers
@@ -57,29 +59,31 @@ this file is autogenerated from registers description
 #define LGW_FPGA_HISTO_RAM_ADDR 13
 #define LGW_FPGA_HISTO_RAM_DATA 14
 #define LGW_FPGA_HISTO_NB_READ 15
-#define LGW_FPGA_LBT_TIMESTAMP_CH 16
-#define LGW_FPGA_LBT_TIMESTAMP_SELECT_CH 17
-#define LGW_FPGA_LBT_CH0_FREQ_OFFSET 18
-#define LGW_FPGA_LBT_CH1_FREQ_OFFSET 19
-#define LGW_FPGA_LBT_CH2_FREQ_OFFSET 20
-#define LGW_FPGA_LBT_CH3_FREQ_OFFSET 21
-#define LGW_FPGA_LBT_CH4_FREQ_OFFSET 22
-#define LGW_FPGA_LBT_CH5_FREQ_OFFSET 23
-#define LGW_FPGA_LBT_CH6_FREQ_OFFSET 24
-#define LGW_FPGA_LBT_CH7_FREQ_OFFSET 25
-#define LGW_FPGA_SCAN_FREQ_OFFSET 26
-#define LGW_FPGA_LBT_SCAN_TIME_CH0 27
-#define LGW_FPGA_LBT_SCAN_TIME_CH1 28
-#define LGW_FPGA_LBT_SCAN_TIME_CH2 29
-#define LGW_FPGA_LBT_SCAN_TIME_CH3 30
-#define LGW_FPGA_LBT_SCAN_TIME_CH4 31
-#define LGW_FPGA_LBT_SCAN_TIME_CH5 32
-#define LGW_FPGA_LBT_SCAN_TIME_CH6 33
-#define LGW_FPGA_LBT_SCAN_TIME_CH7 34
-#define LGW_FPGA_RSSI_TARGET 35
-#define LGW_FPGA_HISTO_SCAN_FREQ 36
-#define LGW_FPGA_NOTCH_FREQ_OFFSET 37
-#define LGW_FPGA_TOTALREGS 38
+#define LGW_FPGA_RF_ATTN_VALUE 16
+#define LGW_FPGA_RF_ATTN_MODE 17
+#define LGW_FPGA_LBT_TIMESTAMP_CH 18
+#define LGW_FPGA_LBT_TIMESTAMP_SELECT_CH 19
+#define LGW_FPGA_LBT_CH0_FREQ_OFFSET 20
+#define LGW_FPGA_LBT_CH1_FREQ_OFFSET 21
+#define LGW_FPGA_LBT_CH2_FREQ_OFFSET 22
+#define LGW_FPGA_LBT_CH3_FREQ_OFFSET 23
+#define LGW_FPGA_LBT_CH4_FREQ_OFFSET 24
+#define LGW_FPGA_LBT_CH5_FREQ_OFFSET 25
+#define LGW_FPGA_LBT_CH6_FREQ_OFFSET 26
+#define LGW_FPGA_LBT_CH7_FREQ_OFFSET 27
+#define LGW_FPGA_SCAN_FREQ_OFFSET 28
+#define LGW_FPGA_LBT_SCAN_TIME_CH0 29
+#define LGW_FPGA_LBT_SCAN_TIME_CH1 30
+#define LGW_FPGA_LBT_SCAN_TIME_CH2 31
+#define LGW_FPGA_LBT_SCAN_TIME_CH3 32
+#define LGW_FPGA_LBT_SCAN_TIME_CH4 33
+#define LGW_FPGA_LBT_SCAN_TIME_CH5 34
+#define LGW_FPGA_LBT_SCAN_TIME_CH6 35
+#define LGW_FPGA_LBT_SCAN_TIME_CH7 36
+#define LGW_FPGA_RSSI_TARGET 37
+#define LGW_FPGA_HISTO_SCAN_FREQ 38
+#define LGW_FPGA_NOTCH_FREQ_OFFSET 39
+#define LGW_FPGA_TOTALREGS 40
 
 /* -------------------------------------------------------------------------- */
 /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */
diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c
index 40b0b2e..90fb9b7 100644
--- a/libloragw/src/loragw_fpga.c
+++ b/libloragw/src/loragw_fpga.c
@@ -69,6 +69,8 @@ const struct lgw_reg_s fpga_regs[LGW_FPGA_TOTALREGS] = {
     {-1,4,0,0,8,0,0}, /* HISTO_RAM_ADDR */
     {-1,5,0,0,8,1,0}, /* HISTO_RAM_DATA */
     {-1,8,0,0,16,0,1000}, /* HISTO_NB_READ */
+    {-1,10,0,0,7,0,127}, /* RF_ATTN_VALUE */
+    {-1,10,7,0,1,0,1}, /* RF_ATTN_MODE */
     {-1,14,0,0,16,1,0}, /* LBT_TIMESTAMP_CH */
     {-1,17,0,0,4,0,0}, /* LBT_TIMESTAMP_SELECT_CH */
     {-1,18,0,0,8,0,0}, /* LBT_CH0_FREQ_OFFSET */
-- 
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