From ce9350c7aaa927a00c3676436cfec331dc507e9e Mon Sep 17 00:00:00 2001
From: Harsh Sharma <92harshsharma@gmail.com>
Date: Wed, 13 Jun 2018 13:55:51 -0500
Subject: Added FPGA registers for full card

---
 libloragw/src/loragw_fpga.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'libloragw/src')

diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c
index 40b0b2e..90fb9b7 100644
--- a/libloragw/src/loragw_fpga.c
+++ b/libloragw/src/loragw_fpga.c
@@ -69,6 +69,8 @@ const struct lgw_reg_s fpga_regs[LGW_FPGA_TOTALREGS] = {
     {-1,4,0,0,8,0,0}, /* HISTO_RAM_ADDR */
     {-1,5,0,0,8,1,0}, /* HISTO_RAM_DATA */
     {-1,8,0,0,16,0,1000}, /* HISTO_NB_READ */
+    {-1,10,0,0,7,0,127}, /* RF_ATTN_VALUE */
+    {-1,10,7,0,1,0,1}, /* RF_ATTN_MODE */
     {-1,14,0,0,16,1,0}, /* LBT_TIMESTAMP_CH */
     {-1,17,0,0,4,0,0}, /* LBT_TIMESTAMP_SELECT_CH */
     {-1,18,0,0,8,0,0}, /* LBT_CH0_FREQ_OFFSET */
-- 
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