From 8b99bdc47b08796e79fd450b5601a8dfaffbc5d8 Mon Sep 17 00:00:00 2001
From: Harsh Sharma <92harshsharma@gmail.com>
Date: Wed, 13 Jun 2018 13:40:20 -0500
Subject: Applied patch: lora-gateway-add-fpga-version-28-31-33

---
 libloragw/src/loragw_reg.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/libloragw/src/loragw_reg.c b/libloragw/src/loragw_reg.c
index 14e23cd..3fc3f32 100644
--- a/libloragw/src/loragw_reg.c
+++ b/libloragw/src/loragw_reg.c
@@ -48,7 +48,7 @@ Maintainer: Sylvain Miermont
 #define PAGE_ADDR        0x00
 #define PAGE_MASK        0x03
 
-const uint8_t FPGA_VERSION[] = { 31, 33 }; /* several versions could be supported */
+const uint8_t FPGA_VERSION[] = { 28, 31, 33 }; /* several versions could be supported */
 
 /*
 auto generated register mapping for C code : 11-Jul-2013 13:20:40
@@ -419,6 +419,16 @@ bool check_fpga_version(uint8_t version) {
     return false;
 }
 
+uint8_t read_fpga_version() {
+       uint8_t u = 0;
+       uint8_t spi_stat = lgw_spi_r(lgw_spi_target, LGW_SPI_MUX_MODE1, LGW_SPI_MUX_TARGET_FPGA, loregs[LGW_VERSION].addr, &u);
+        if (spi_stat != LGW_SPI_SUCCESS) {
+            DEBUG_MSG("ERROR READING VERSION REGISTER\n");
+            return LGW_REG_ERROR;
+        }
+       return u;
+}
+
 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
 
 int reg_w_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t reg_value) {
-- 
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