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author | Harsh Sharma <harsh.sharma@multitech.com> | 2018-08-09 15:10:43 -0500 |
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committer | Harsh Sharma <harsh.sharma@multitech.com> | 2018-08-09 15:10:43 -0500 |
commit | 1e66084295f37f0d7f5f0a3518e43ae0cc613898 (patch) | |
tree | 3b6fcae715309aeec4f39c2b59f5945a18542c18 /libloragw/src/loragw_fpga.c | |
parent | 4a262a7c7e76e118cefb0cc7569a9597f230c888 (diff) | |
download | lora_gateway_mtac_full-1e66084295f37f0d7f5f0a3518e43ae0cc613898.tar.gz lora_gateway_mtac_full-1e66084295f37f0d7f5f0a3518e43ae0cc613898.tar.bz2 lora_gateway_mtac_full-1e66084295f37f0d7f5f0a3518e43ae0cc613898.zip |
Changed attenuation setup to be the difference between the LUT power and the tx packet power and make it automatically set
Diffstat (limited to 'libloragw/src/loragw_fpga.c')
-rw-r--r-- | libloragw/src/loragw_fpga.c | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c index 1379679..ce1c9c6 100644 --- a/libloragw/src/loragw_fpga.c +++ b/libloragw/src/loragw_fpga.c @@ -130,7 +130,7 @@ float lgw_fpga_get_tx_notch_delay(void) { /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ -int lgw_fpga_configure(uint32_t tx_notch_freq, bool fpga_attn_used) { +int lgw_fpga_configure(uint32_t tx_notch_freq) { int x; int32_t val; bool spectral_scan_support, lbt_support; @@ -175,17 +175,9 @@ int lgw_fpga_configure(uint32_t tx_notch_freq, bool fpga_attn_used) { DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n"); return LGW_REG_ERROR; } - /* Set Attenuator mode to be used or not depending on if a full card with valid conf settings are given*/ + /* Set Attenuator mode to be used for the full card*/ if (fpga_version == 32) { - if (fpga_attn_used == true) { - lgw_reg_w(LGW_FPGA_RF_ATTN_MODE, 0); - printf("INFO: Valid attenuation settings detected. Using Attenuator mode\n"); - } else { - printf("INFO: Valid attenuation settings not detected. Using Legacy mode\n"); - lgw_reg_w(LGW_FPGA_RF_ATTN_MODE, 1); - } - } else { - lgw_reg_w(LGW_FPGA_RF_ATTN_MODE, 1); + lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_MODE, 0); } } @@ -367,4 +359,23 @@ int lgw_fpga_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size) { } } +/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ + +int lgw_set_attenuation(float attenuation) { + int i; + int32_t val; + if (attenuation > 31.75 || attenuation < 0) { + return LGW_HAL_ERROR; + } + i = lgw_fpga_reg_w(LGW_FPGA_RF_ATTN_VALUE, (uint8_t)(attenuation * LGW_RF_ATTN_CONV_CONST)); + + i = lgw_fpga_reg_r(LGW_FPGA_RF_ATTN_VALUE, &val); + if (i == LGW_REG_SUCCESS) { + DEBUG_PRINTF("INFO: Attenuator set to %u \n", (uint8_t)val); + return LGW_HAL_SUCCESS; + } else { + return LGW_HAL_ERROR; + } +} + /* --- EOF ------------------------------------------------------------------ */ |