diff options
| author | Sylvain Miermont <smiermont@semtech.com> | 2013-09-19 15:46:06 +0200 |
|---|---|---|
| committer | Sylvain Miermont <smiermont@semtech.com> | 2013-10-23 14:03:05 +0200 |
| commit | b922932d1c9869d82042b600db2382d8c15f63dc (patch) | |
| tree | b97b83a74f5b3faadb674867f6cc004b8426a8a9 /loragw_hal/src | |
| parent | 68b8b7a70d9104888997174506fbbaa0abb12a4c (diff) | |
| download | lora_gateway-b922932d1c9869d82042b600db2382d8c15f63dc.tar.gz lora_gateway-b922932d1c9869d82042b600db2382d8c15f63dc.tar.bz2 lora_gateway-b922932d1c9869d82042b600db2382d8c15f63dc.zip | |
Beta 7 (beta6 skipped)v1.b7
- API: change memory allocation for payload, they are now part of the struct for TX/RX, no need to malloc/free
- reduced number of SPI transactions to fetch a packet (improved number a packets par second that can be downloaded from gateway)
- streamlined build process, main target is now a static library: libloragw.a
- All RX chains can use any of the two radios now
- FSK is available and working in TX and RX (variable length mode)
- Calibrated RSSI for FSK
- lgw_connect now check the CHIP_ID
- Added a license file and a changelog
- Added a function returning a version string to allow identification of the version/options once compiled
Diffstat (limited to 'loragw_hal/src')
| -rw-r--r-- | loragw_hal/src/agc_fw.var | 526 | ||||
| -rw-r--r-- | loragw_hal/src/arb_fw.var | 526 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_aux.c | 51 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_hal.c | 1033 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_reg.c | 756 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_spi.ftdi.c | 285 | ||||
| -rw-r--r-- | loragw_hal/src/loragw_spi.native.c | 346 |
7 files changed, 0 insertions, 3523 deletions
diff --git a/loragw_hal/src/agc_fw.var b/loragw_hal/src/agc_fw.var deleted file mode 100644 index 7d30fb9..0000000 --- a/loragw_hal/src/agc_fw.var +++ /dev/null @@ -1,526 +0,0 @@ -/* - / _____) _ | | -( (____ _____ ____ _| |_ _____ ____| |__ - \____ \| ___ | (_ _) ___ |/ ___) _ \ - _____) ) ____| | | || |_| ____( (___| | | | -(______/|_____)_|_|_| \__)_____)\____)_| |_| - ©2013 Semtech-Cycleo - -Description: - AGC firmware -*/ - -static uint8_t agc_firmware[MCU_AGC_FW_BYTE] = { -0x8A, 0x51, 0x11, 0x28, 0xFF, 0xBF, 0xFF, 0xBF, 0x80, 0x40, 0x03, 0x4E, 0x83, 0x52, 0x03, 0x53, -0xA8, 0xC0, 0x04, 0x88, 0xA9, 0x00, 0x0A, 0xC8, 0xAA, 0x00, 0x01, 0x88, 0xAB, 0x40, 0x8A, 0x51, -0x79, 0x6E, 0x8A, 0x51, 0x3A, 0x2E, 0xA2, 0x70, 0x84, 0x80, 0x37, 0xF0, 0x83, 0x52, 0x03, 0x53, -0xB3, 0x40, 0x04, 0x88, 0xB4, 0x00, 0x08, 0xF0, 0xB5, 0x40, 0x33, 0x48, 0x84, 0x80, 0x83, 0x93, -0x00, 0x48, 0xB6, 0x40, 0xB3, 0xCA, 0x34, 0x08, 0x84, 0x80, 0x36, 0x48, 0x80, 0x40, 0xB4, 0x8A, -0xB5, 0x0B, 0x1D, 0xA8, 0x2B, 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-------------------------------------------------------------------------- */ -/* --- PRIVATE MACROS ------------------------------------------------------- */ - -#if DEBUG_AUX == 1 - #define DEBUG_MSG(str) fprintf(stderr, str) - #define DEBUG_PRINTF(fmt, args...) fprintf(stderr,"%s:%d: "fmt, __FUNCTION__, __LINE__, args) -#else - #define DEBUG_MSG(str) - #define DEBUG_PRINTF(fmt, args...) -#endif - -/* -------------------------------------------------------------------------- */ -/* --- PUBLIC FUNCTIONS DEFINITION ------------------------------------------ */ - -/* This implementation is POSIX-pecific and require a fix to be compatible with C99 */ -void wait_ms(unsigned long a) { - struct timespec dly; - struct timespec rem; - - dly.tv_sec = a / 1000; - dly.tv_nsec = ((long)a % 1000) * 1000000; - - DEBUG_PRINTF("NOTE dly: %ld sec %ld ns\n", dly.tv_sec, dly.tv_nsec); - - if((dly.tv_sec > 0) || ((dly.tv_sec == 0) && (dly.tv_nsec > 100000))) { - clock_nanosleep(CLOCK_MONOTONIC, 0, &dly, &rem); - DEBUG_PRINTF("NOTE remain: %ld sec %ld ns\n", rem.tv_sec, rem.tv_nsec); - } - return; -} - -/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/src/loragw_hal.c b/loragw_hal/src/loragw_hal.c deleted file mode 100644 index 5b261f2..0000000 --- a/loragw_hal/src/loragw_hal.c +++ /dev/null @@ -1,1033 +0,0 @@ -/* - / _____) _ | | -( (____ _____ ____ _| |_ _____ ____| |__ - \____ \| ___ | (_ _) ___ |/ ___) _ \ - _____) ) ____| | | || |_| ____( (___| | | | -(______/|_____)_|_|_| \__)_____)\____)_| |_| - ©2013 Semtech-Cycleo - -Description: - Lora gateway Hardware Abstraction Layer -*/ - - -/* -------------------------------------------------------------------------- */ -/* --- DEPENDANCIES --------------------------------------------------------- */ - -#include <stdint.h> /* C99 types */ -#include <stdlib.h> /* malloc & free */ -#include <stdbool.h> /* bool type */ -#include <stdio.h> /* printf fprintf */ -#include <math.h> /* NaN */ -#include <string.h> /* memcpy */ - -#include "loragw_reg.h" -#include "loragw_hal.h" -#include "loragw_aux.h" - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE MACROS ------------------------------------------------------- */ - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#if DEBUG_HAL == 1 - #define DEBUG_MSG(str) fprintf(stderr, str) - #define DEBUG_PRINTF(fmt, args...) fprintf(stderr,"%s:%d: "fmt, __FUNCTION__, __LINE__, args) - #define DEBUG_ARRAY(a,b,c) for(a=0;a<b;++a) fprintf(stderr,"%x.",c[a]);fprintf(stderr,"end\n") - #define CHECK_NULL(a) if(a==NULL){fprintf(stderr,"%s:%d: ERROR: NULL POINTER AS ARGUMENT\n", __FUNCTION__, __LINE__);return LGW_HAL_ERROR;} -#else - #define DEBUG_MSG(str) - #define DEBUG_PRINTF(fmt, args...) - #define DEBUG_ARRAY(a,b,c) - #define CHECK_NULL(a) if(a==NULL){return LGW_HAL_ERROR;} -#endif - -#define IF_HZ_TO_REG(f) (f << 5)/15625 -#define SET_PPM_ON(bw,dr) (((bw == BW_125KHZ) && ((dr == DR_LORA_SF11) || (dr == DR_LORA_SF12))) || ((bw == BW_250KHZ) && (dr == DR_LORA_SF12))) - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE CONSTANTS ---------------------------------------------------- */ - -#define MCU_ARB 0 -#define MCU_AGC 1 - -const uint8_t ifmod_config[LGW_IF_CHAIN_NB] = LGW_IFMODEM_CONFIG; /* define hardware capability */ - -const uint32_t rf_rx_lowfreq[LGW_RF_CHAIN_NB] = LGW_RF_RX_LOWFREQ; -const uint32_t rf_rx_upfreq[LGW_RF_CHAIN_NB] = LGW_RF_RX_UPFREQ; -const uint32_t rf_rx_bandwidth[LGW_RF_CHAIN_NB] = LGW_RF_RX_BANDWIDTH; -const uint32_t rf_tx_lowfreq[LGW_RF_CHAIN_NB] = LGW_RF_TX_LOWFREQ; -const uint32_t rf_tx_upfreq[LGW_RF_CHAIN_NB] = LGW_RF_TX_UPFREQ; - -#define MCU_ARB_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ -#define MCU_AGC_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ - -#define SX1257_CLK_OUT 1 -#define SX1257_TX_DAC_CLK_SEL 1 /* 0:int, 1:ext */ -#define SX1257_TX_DAC_GAIN 2 /* 3:0, 2:-3, 1:-6, 0:-9 dBFS (default 2) */ -#define SX1257_TX_MIX_GAIN 14 /* -38 + 2*TxMixGain dB (default 14) */ -#define SX1257_TX_PLL_BW 3 /* 0:75, 1:150, 2:225, 3:300 kHz (default 3) */ -#define SX1257_TX_ANA_BW 0 /* 17.5 / 2*(41-TxAnaBw) MHz (default 0) */ -#define SX1257_TX_DAC_BW 7 /* 24 + 8*TxDacBw Nb FIR taps (default 2) */ -#define SX1257_RX_LNA_GAIN 1 /* 1 to 6, 1 highest gain */ -#define SX1257_RX_BB_GAIN 12 /* 0 to 15 , 15 highest gain */ -#define SX1257_RX_ADC_BW 7 /* 0 to 7, 2:100<BW<200, 5:200<BW<400,7:400<BW (kHz) */ -#define SX1257_RX_ADC_TRIM 6 /* 0 to 7, 6 for 32MHz ref, 5 for 36MHz ref */ -#define SX1257_RXBB_BW 2 - -#define RSSI_OFFSET_LORA_MULTI -130.0 /* calibrated value */ -#define RSSI_OFFSET_LORA_STD -168.0 /* calibrated for all bandwidth */ -#define RSSI_OFFSET_FSK 0.0 /* TODO */ - -#define TX_METADATA_NB 16 -#define RX_METADATA_NB 16 - -#define MIN_LORA_PREAMBLE 4 -#define PLL_LOCK_MAX_ATTEMPTS 6 - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE VARIABLES ---------------------------------------------------- */ - -#include "arb_fw.var" /* external definition of the variable */ -#include "agc_fw.var" /* external definition of the variable */ - -/* -The following static variables are the configuration set that the user can -modify using rxrf_setconf and rxif_setconf functions. -The function _start then use that set to configure the hardware. - -Parameters validity and coherency is verified by the _setconf functions and -the _start function assumes -*/ - -static bool lgw_is_started = false; - -static bool rf_enable[LGW_RF_CHAIN_NB] = {0, 0}; -static uint32_t rf_rx_freq[LGW_IF_CHAIN_NB] = {0, 0}; /* absolute, in Hz */ - -static uint8_t if_rf_switch = 0x00; /* each IF from 0 to 7 has 1 bit associated to it, 0 -> radio A, 1 -> radio B */ -/* IF 8 and 9 are on radio A */ - -static bool if_enable[LGW_IF_CHAIN_NB] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -static int32_t if_freq[LGW_IF_CHAIN_NB] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; /* relative to radio frequency, +/- in Hz */ - -static uint8_t lora_multi_sfmask[LGW_MULTI_NB] = {0, 0, 0, 0}; /* enables SF for Lora 'multi' modems */ -static uint8_t lora_rx_bw = 0; /* for the Lora standalone modem(s) */ -static uint16_t lora_rx_sf = 0; /* for the Lora standalone modem(s) */ -static uint8_t lora_rx_ppm_offset = 0; /* for the Lora standalone modem(s) */ - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE FUNCTIONS DECLARATION ---------------------------------------- */ - -int load_firmware(uint8_t target, uint8_t *firmware, uint16_t size); - -void sx125x_write(uint8_t rf_chain, uint8_t addr, uint8_t data); - -uint8_t sx125x_read(uint8_t rf_chain, uint8_t addr); - -int setup_sx1257(uint8_t rf_chain, uint32_t freq_hz); - -void lgw_constant_adjust(void); - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE FUNCTIONS DEFINITION ----------------------------------------- */ - -/* size is the firmware size in bytes (not 14b words) */ -int load_firmware(uint8_t target, uint8_t *firmware, uint16_t size) { - int32_t read_value; - int reg_rst; - int reg_sel; - - /* check parameters */ - CHECK_NULL(firmware); - if (target == MCU_ARB) { - if (size != MCU_ARB_FW_BYTE) { - DEBUG_MSG("ERROR: NOT A VALID SIZE FOR MCU ARG FIRMWARE\n"); - return -1; - } - reg_rst = LGW_MCU_RST_0; - reg_sel = LGW_MCU_SELECT_MUX_0; - }else if (target == MCU_AGC) { - if (size != MCU_AGC_FW_BYTE) { - DEBUG_MSG("ERROR: NOT A VALID SIZE FOR MCU AGC FIRMWARE\n"); - return -1; - } - reg_rst = LGW_MCU_RST_1; - reg_sel = LGW_MCU_SELECT_MUX_1; - } else { - DEBUG_MSG("ERROR: NOT A VALID TARGET FOR LOADING FIRMWARE\n"); - return -1; - } - - /* reset the targeted MCU */ - lgw_reg_w(reg_rst, 1); - - /* set mux to access MCU program RAM and set address to 0 */ - lgw_reg_w(reg_sel, 0); - lgw_reg_w(LGW_MCU_PROM_ADDR, 0); - - /* write the program in one burst */ - lgw_reg_wb(LGW_MCU_PROM_DATA, firmware, size); - - /* give back control of the MCU program ram to the MCU */ - lgw_reg_w(reg_sel, 1); - - return 0; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -void sx125x_write(uint8_t channel, uint8_t addr, uint8_t data) { - int reg_add, reg_dat, reg_cs; - - /* checking input parameters */ - if (channel >= LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: INVALID RF_CHAIN\n"); - return; - } - if (addr >= 0x7F) { - DEBUG_MSG("ERROR: ADDRESS OUT OF RANGE\n"); - return; - } - - /* selecting the target radio */ - switch (channel) { - case 0: - reg_add = LGW_SPI_RADIO_A__ADDR; - reg_dat = LGW_SPI_RADIO_A__DATA; - reg_cs = LGW_SPI_RADIO_A__CS; - break; - - case 1: - reg_add = LGW_SPI_RADIO_B__ADDR; - reg_dat = LGW_SPI_RADIO_B__DATA; - reg_cs = LGW_SPI_RADIO_B__CS; - break; - - default: - DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", channel); - return; - } - - /* SPI master data write procedure */ - lgw_reg_w(reg_cs, 0); - lgw_reg_w(reg_add, 0x80 | addr); /* MSB at 1 for write operation */ - lgw_reg_w(reg_dat, data); - lgw_reg_w(reg_cs, 1); - lgw_reg_w(reg_cs, 0); - - return; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -uint8_t sx125x_read(uint8_t channel, uint8_t addr) { - int reg_add, reg_dat, reg_cs, reg_rb; - int32_t read_value; - - /* checking input parameters */ - if (channel >= LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: INVALID RF_CHAIN\n"); - return 0; - } - if (addr >= 0x7F) { - DEBUG_MSG("ERROR: ADDRESS OUT OF RANGE\n"); - return 0; - } - - /* selecting the target radio */ - switch (channel) { - case 0: - reg_add = LGW_SPI_RADIO_A__ADDR; - reg_dat = LGW_SPI_RADIO_A__DATA; - reg_cs = LGW_SPI_RADIO_A__CS; - reg_rb = LGW_SPI_RADIO_A__DATA_READBACK; - break; - - case 1: - reg_add = LGW_SPI_RADIO_B__ADDR; - reg_dat = LGW_SPI_RADIO_B__DATA; - reg_cs = LGW_SPI_RADIO_B__CS; - reg_rb = LGW_SPI_RADIO_B__DATA_READBACK; - break; - - default: - DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", channel); - return 0; - } - - /* SPI master data read procedure */ - lgw_reg_w(reg_cs, 0); - lgw_reg_w(reg_add, addr); /* MSB at 0 for read operation */ - lgw_reg_w(reg_dat, 0); - lgw_reg_w(reg_cs, 1); - lgw_reg_w(reg_cs, 0); - lgw_reg_r(reg_rb, &read_value); - - return (uint8_t)read_value; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int setup_sx1257(uint8_t rf_chain, uint32_t freq_hz) { - uint32_t part_int; - uint32_t part_frac; - int cpt_attempts = 0; - - if (rf_chain >= LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: INVALID RF_CHAIN\n"); - return -1; - } - - /* misc */ - sx125x_write(rf_chain, 0x10, SX1257_TX_DAC_CLK_SEL + SX1257_CLK_OUT*2); - - /* Tx gain and trim */ - sx125x_write(rf_chain, 0x08, SX1257_TX_MIX_GAIN + SX1257_TX_DAC_GAIN*16); - sx125x_write(rf_chain, 0x0A, SX1257_TX_ANA_BW + SX1257_TX_PLL_BW*32); - sx125x_write(rf_chain, 0x0B, SX1257_TX_DAC_BW); - - /* Rx gain and trim */ - sx125x_write(rf_chain, 0x0C, 0 + SX1257_RX_BB_GAIN*2 + SX1257_RX_LNA_GAIN*32); - sx125x_write(rf_chain, 0x0D, SX1257_RXBB_BW + SX1257_RX_ADC_TRIM*4 + SX1257_RX_ADC_BW*32); - - /* set RX PLL frequency */ - part_int = freq_hz / LGW_SX1257_DENOMINATOR; /* integer part, gives the MSB and the middle byte */ - part_frac = ((freq_hz % LGW_SX1257_DENOMINATOR) << 8) / LGW_SX1257_DENOMINATOR; /* fractional part, gives LSB */ - sx125x_write(rf_chain, 0x01,0xFF & (part_int >> 8)); /* Most Significant Byte */ - sx125x_write(rf_chain, 0x02,0xFF & part_int); /* middle byte */ - sx125x_write(rf_chain, 0x03,0xFF & part_frac); /* Least Significant Byte */ - - /* start and PLL lock */ - do { - if (cpt_attempts >= PLL_LOCK_MAX_ATTEMPTS) { - DEBUG_MSG("ERROR: FAIL TO LOCK PLL\n"); - return -1; - } - sx125x_write(rf_chain, 0x00, 1); /* enable Xtal oscillator */ - sx125x_write(rf_chain, 0x00, 3); /* Enable RX (PLL+FE) */ - ++cpt_attempts; - DEBUG_PRINTF("Note: SX1257 #%d PLL start (attempt %d)\n", rf_chain, cpt_attempts); - wait_ms(1); - } while(sx125x_read(rf_chain, 0x11) & 0x02 == 0); - - return 0; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -void lgw_constant_adjust(void) { - - /* I/Q path setup */ - // lgw_reg_w(LGW_RX_INVERT_IQ,0); /* default 0 */ - // lgw_reg_w(LGW_MODEM_INVERT_IQ,1); /* default 1 */ - // lgw_reg_w(LGW_CHIRP_INVERT_RX,1); /* default 1 */ - // lgw_reg_w(LGW_RX_EDGE_SELECT,0); /* default 0 */ - // lgw_reg_w(LGW_MBWSSF_MODEM_INVERT_IQ,0); /* default 0 */ - // lgw_reg_w(LGW_DC_NOTCH_EN,1); /* default 1 */ - lgw_reg_w(LGW_RSSI_BB_FILTER_ALPHA,9); /* default 7 */ - lgw_reg_w(LGW_RSSI_DEC_FILTER_ALPHA,7); /* default 5 */ - lgw_reg_w(LGW_RSSI_CHANN_FILTER_ALPHA,7); /* default 8 */ - // lgw_reg_w(LGW_RSSI_BB_DEFAULT_VALUE,32); /* default 32 */ - lgw_reg_w(LGW_RSSI_CHANN_DEFAULT_VALUE,90); /* default 100 */ - lgw_reg_w(LGW_RSSI_DEC_DEFAULT_VALUE,90); /* default 100 */ - // lgw_reg_w(LGW_DEC_GAIN_OFFSET, 8); /* default 8 */ - // lgw_reg_w(LGW_CHAN_GAIN_OFFSET, 7); /* default 7 */ - - /* Correlator setup */ - // lgw_reg_w(LGW_CORR_DETECT_EN,126); /* default 126 */ - // lgw_reg_w(LGW_CORR_NUM_SAME_PEAK,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_MAC_GAIN,5); /* default 5 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF6,0); /* default 0 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF7,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF8,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF9,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF10,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF11,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SAME_PEAKS_OPTION_SF12,1); /* default 1 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF6,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF7,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF8,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF9,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF10,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF11,4); /* default 4 */ - // lgw_reg_w(LGW_CORR_SIG_NOISE_RATIO_SF12,4); /* default 4 */ - - /* Lora 'multi' modems setup */ - lgw_reg_w(LGW_PREAMBLE_SYMB1_NB,4); /* default 10 */ - // lgw_reg_w(LGW_FREQ_TO_TIME_DRIFT,9); /* default 9 */ - // lgw_reg_w(LGW_FREQ_TO_TIME_INVERT,29); /* default 29 */ - // lgw_reg_w(LGW_FRAME_SYNCH_GAIN,1); /* default 1 */ - // lgw_reg_w(LGW_SYNCH_DETECT_TH,1); /* default 1 */ - // lgw_reg_w(LGW_ZERO_PAD,0); /* default 0 */ - lgw_reg_w(LGW_SNR_AVG_CST,3); /* default 2 */ - // lgw_reg_w(LGW_FRAME_SYNCH_PEAK1_POS,1); /* default 1 */ - // lgw_reg_w(LGW_FRAME_SYNCH_PEAK2_POS,2); /* default 2 */ - // lgw_reg_w(LGW_PREAMBLE_FINE_TIMING_GAIN,1); /* default 1 */ - // lgw_reg_w(LGW_ONLY_CRC_EN,1); /* default 1 */ - // lgw_reg_w(LGW_PAYLOAD_FINE_TIMING_GAIN,2); /* default 2 */ - // lgw_reg_w(LGW_TRACKING_INTEGRAL,0); /* default 0 */ - // lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_RDX8,0); /* default 0 */ - // lgw_reg_w(LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4,4092); /* default 4092 */ - // lgw_reg_w(LGW_MAX_PAYLOAD_LEN,255); /* default 255 */ - - /* MBWSSF Modem */ - // lgw_reg_w(LGW_MBWSSF_MODEM_ENABLE,1); /* default 0 */ - // lgw_reg_w(LGW_MBWSSF_PREAMBLE_SYMB1_NB,10); /* default 10 */ - // lgw_reg_w(LGW_MBWSSF_FREQ_TO_TIME_DRIFT,36); /* default 36 */ - // lgw_reg_w(LGW_MBWSSF_FREQ_TO_TIME_INVERT,29); /* default 29 */ - // lgw_reg_w(LGW_MBWSSF_FRAME_SYNCH_GAIN,1); /* default 1 */ - // lgw_reg_w(LGW_MBWSSF_SYNCH_DETECT_TH,1); /* default 1 */ - // lgw_reg_w(LGW_MBWSSF_ZERO_PAD,0); /* default 0 */ - // lgw_reg_w(LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS,1); /* default 1 */ - // lgw_reg_w(LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS,2); /* default 2 */ - // lgw_reg_w(LGW_MBWSSF_ONLY_CRC_EN,1); /* default 1 */ - // lgw_reg_w(LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN,2); /* default 2 */ - // lgw_reg_w(LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN,1); /* default 1 */ - // lgw_reg_w(LGW_MBWSSF_TRACKING_INTEGRAL,0); /* default 0 */ - // lgw_reg_w(LGW_MBWSSF_AGC_FREEZE_ON_DETECT,1); /* default 1 */ - - /* FSK datapath */ - lgw_reg_w(LGW_FSK_RX_INVERT,1); /* default 0 */ - lgw_reg_w(LGW_FSK_MODEM_INVERT_IQ,1); /* default 0 */ - - /* FSK demod */ - // lgw_reg_w(LGW_FSK_AUTO_AFC_ON,0); /* default 0 */ - // lgw_reg_w(LGW_FSK_BROADCAST,0); /* default 0 */ - lgw_reg_w(LGW_FSK_CRC_EN,1); /* default 0 */ - // lgw_reg_w(LGW_FSK_CRC_IBM,0); /* default 0 */ - // lgw_reg_w(LGW_FSK_DCFREE_ENC,0); /* default 0 */ - lgw_reg_w(LGW_FSK_ERROR_OSR_TOL,10); /* default 0 */ - lgw_reg_w(LGW_FSK_MODEM_INVERT_IQ,1); /* default 0 */ - // lgw_reg_w(LGW_FSK_NODE_ADRS,0); /* default 0 */ - lgw_reg_w(LGW_FSK_PATTERN_TIMEOUT_CFG,64); /* default 0 */ - lgw_reg_w(LGW_FSK_PKT_LENGTH,64); /* default 0 */ - lgw_reg_w(LGW_FSK_PKT_MODE,1); /* default 0 */ - lgw_reg_w(LGW_FSK_PSIZE,3); /* default 0 */ - lgw_reg_w(LGW_FSK_REF_PATTERN_LSB,0x55); /* default 0 */ - lgw_reg_w(LGW_FSK_REF_PATTERN_MSB,0x55); /* default 0 */ - lgw_reg_w(LGW_FSK_RSSI_LENGTH,4); /* default 0 */ - lgw_reg_w(LGW_FSK_CH_BW_EXPO,2); /* 125kHz (default 0, 500kHz) */ - - /* FSK mod */ - lgw_reg_w(LGW_FSK_TX_PSIZE,3); /* default 0 */ - lgw_reg_w(LGW_FSK_TX_GAUSSIAN_SELECT_BT,1); /* default 0 */ - - /* TX */ - // lgw_reg_w(LGW_TX_MODE,0); /* default 0 */ - lgw_reg_w(LGW_TX_START_DELAY,1000); /* default 0 */ - lgw_reg_w(LGW_TX_SWAP_IQ,1); /* "normal" polarity; default 0 */ - - return; -} - -/* -------------------------------------------------------------------------- */ -/* --- PUBLIC FUNCTIONS DEFINITION ------------------------------------------ */ - -int lgw_rxrf_setconf(uint8_t rf_chain, struct lgw_conf_rxrf_s conf) { - - /* check if the gateway is running */ - if (lgw_is_started == true) { - DEBUG_MSG("ERROR: GATEWAY IS RUNNING, STOP IT BEFORE TOUCHING CONFIGURATION\n"); - return LGW_HAL_ERROR; - } - - /* check input parameters */ - if (rf_chain > LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: NOT A VALID RF_CHAIN NUMBER\n"); - return LGW_HAL_ERROR; - } - if (conf.freq_hz > rf_rx_upfreq[rf_chain]) { - DEBUG_MSG("ERROR: FREQUENCY TOO HIGH FOR THAT RF_CHAIN\n"); - return LGW_HAL_ERROR; - } else if (conf.freq_hz < rf_rx_lowfreq[rf_chain]) { - DEBUG_MSG("ERROR: FREQUENCY TOO LOW FOR THAT RF_CHAIN\n"); - return LGW_HAL_ERROR; - } - - /* set internal config according to parameters */ - rf_enable[rf_chain] = conf.enable; - rf_rx_freq[rf_chain] = conf.freq_hz; - - return LGW_HAL_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_rxif_setconf(uint8_t if_chain, struct lgw_conf_rxif_s conf) { - /* check if the gateway is running */ - if (lgw_is_started == true) { - DEBUG_MSG("ERROR: GATEWAY IS RUNNING, STOP IT BEFORE TOUCHING CONFIGURATION\n"); - return LGW_HAL_ERROR; - } - - /* if chain is disabled, don't care about most parameters */ - if (conf.enable == false) { - if_enable[if_chain] = false; - if_freq[if_chain] = 0; - DEBUG_PRINTF("Note: if_chain %d disabled\n", if_chain); - return LGW_HAL_SUCCESS; - } - - /* check 'general' parameters */ - if (if_chain > LGW_IF_CHAIN_NB) { - DEBUG_PRINTF("ERROR: %d NOT A VALID IF_CHAIN NUMBER\n", if_chain); - return LGW_HAL_ERROR; - } - if (ifmod_config[if_chain] == IF_UNDEFINED) { - DEBUG_PRINTF("ERROR: IF CHAIN %d NOT CONFIGURABLE\n", if_chain); - } - if (conf.rf_chain >= LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: INVALID RF_CHAIN TO ASSOCIATE WITH A LORA_STD IF CHAIN\n"); - return LGW_HAL_ERROR; - } - if ((conf.freq_hz + LGW_REF_BW/2) > ((int32_t)rf_rx_bandwidth[conf.rf_chain] / 2)) { - DEBUG_PRINTF("ERROR: IF FREQUENCY %d TOO HIGH\n", conf.freq_hz); - return LGW_HAL_ERROR; - } else if ((conf.freq_hz - LGW_REF_BW/2) < -((int32_t)rf_rx_bandwidth[conf.rf_chain] / 2)) { - DEBUG_PRINTF("ERROR: IF FREQUENCY %d TOO LOW\n", conf.freq_hz); - return LGW_HAL_ERROR; - } - /* WARNING: if the channel is 250 or 500kHz wide, that check is insufficient */ - - /* check parameters according to the type of IF chain + modem, - fill default if necessary, and commit configuration if everything is OK */ - switch (ifmod_config[if_chain]) { - case IF_LORA_STD: - /* fill default parameters if needed */ - if (conf.bandwidth == 0) { - conf.bandwidth = BW_250KHZ; - } - if (conf.datarate == 0) { - conf.datarate = DR_LORA_SF9; - } - /* check BW & DR */ - if (!IS_LORA_BW(conf.bandwidth)) { - DEBUG_MSG("ERROR: BANDWIDTH NOT SUPPORTED BY LORA_STD IF CHAIN\n"); - return LGW_HAL_ERROR; - } - if (!IS_LORA_STD_DR(conf.datarate)) { - DEBUG_MSG("ERROR: DATARATE NOT SUPPORTED BY LORA_STD IF CHAIN\n"); - return LGW_HAL_ERROR; - } - /* set internal configuration */ - if_enable[if_chain] = conf.enable; - if_freq[if_chain] = conf.freq_hz; - lora_rx_bw = conf.bandwidth; - lora_rx_sf = conf.datarate; - if (SET_PPM_ON(conf.bandwidth, conf.datarate)) { - lora_rx_ppm_offset = 1; - } else { - lora_rx_ppm_offset = 0; - } - - DEBUG_PRINTF("Note: Lora 'std' if_chain %d configured; en:%d freq:%d bw:%d dr:%d\n", if_chain, if_enable[if_chain], if_freq[if_chain], lora_rx_bw, lora_rx_sf); - break; - - case IF_LORA_MULTI: - /* fill default parameters if needed */ - if (conf.datarate == 0) { - conf.datarate = DR_LORA_MULTI; - } - /* check BW & DR */ - if ((conf.bandwidth != BW_125KHZ) && (conf.bandwidth != 0)) { /* 0 is for default */ - DEBUG_MSG("ERROR: BANDWIDTH NOT SUPPORTED BY LORA_MULTI IF CHAIN\n"); - return LGW_HAL_ERROR; - } - if (!IS_LORA_MULTI_DR(conf.datarate)) { - DEBUG_MSG("ERROR: DATARATE(S) NOT SUPPORTED BY LORA_MULTI IF CHAIN\n"); - return LGW_HAL_ERROR; - } - /* set internal configuration */ - if_enable[if_chain] = conf.enable; - switch (conf.rf_chain) { - case 0: if_rf_switch &= ~((uint8_t)1 << if_chain); break; /* force a 0 at the if_chain-th position */ - case 1: if_rf_switch |= ((uint8_t)1 << if_chain); break; /* force a 1 at the if_chain-th position */ - default: DEBUG_MSG("ERROR: IMPROPRER IF_CHAIN/RF_CHAIN ASSOCIATION\n"); - } - if_freq[if_chain] = conf.freq_hz; - lora_multi_sfmask[if_chain] = (uint8_t)(0x007F & conf.datarate); - DEBUG_PRINTF("Note: Lora 'multi' if_chain %d configured; en:%d freq:%d SF_mask:0x%02x\n", if_chain, if_enable[if_chain], if_freq[if_chain], lora_multi_sfmask[if_chain]); - DEBUG_PRINTF("Note: rf/if switch state 0x%02x\n", if_rf_switch); - break; - - // case IF_FSK_STD: - // TODO: fill the correct metadata for a FSK packet to be sent - - default: - DEBUG_PRINTF("ERROR: IF CHAIN %d TYPE NOT SUPPORTED\n", if_chain); - return LGW_HAL_ERROR; - } - - return LGW_HAL_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_start(void) { - int reg_stat; - int32_t read_value; - - if (lgw_is_started == true) { - DEBUG_MSG("Note: Lora Gateway already started, restarting it now\n"); - } - - reg_stat = lgw_connect(); - if (reg_stat == LGW_REG_ERROR) { - DEBUG_MSG("ERROR: FAIL TO CONNECT BOARD\n"); - return LGW_HAL_ERROR; - } - - /* reset the registers (also shuts the radios down) */ - lgw_soft_reset(); - - /* Ungate clocks (gated by default) */ - lgw_reg_w(LGW_GLOBAL_EN, 1); - // lgw_reg_w(LGW_CLK32M_EN, 1); - // lgw_reg_w(LGW_CLKHS_EN, 1); - - /* switch on and reset the radios (also starts the 32 MHz XTAL) */ - lgw_reg_w(LGW_RADIO_A_EN,1); /* radio A *must* be started to get 32 MHz clk */ - lgw_reg_w(LGW_RADIO_B_EN,1); /* radio B *must* be started because they share the same XTAL I/O is clamped to ground when off */ - wait_ms(500); - lgw_reg_w(LGW_RADIO_RST,1); - wait_ms(5); - lgw_reg_w(LGW_RADIO_RST,0); - - /* setup the radios */ - if (rf_enable[0] == 1) { - setup_sx1257(0, rf_rx_freq[0]); - } - if (rf_enable[1] == 1) { - setup_sx1257(1, rf_rx_freq[1]); - } - - /* gives the AGC MCU control over radio, RF front-end and filter gain */ - lgw_reg_w(LGW_FORCE_HOST_RADIO_CTRL,0); - lgw_reg_w(LGW_FORCE_HOST_FE_CTRL,0); - lgw_reg_w(LGW_FORCE_DEC_FILTER_GAIN,0); - - /* TODO load the calibration firmware and wait for calibration to end */ - - /* in the absence of calibration firmware, do a "manual" calibration */ - lgw_reg_w(LGW_TX_OFFSET_I,10); - lgw_reg_w(LGW_TX_OFFSET_Q,5); - lgw_reg_w(LGW_IQ_MISMATCH_A_AMP_COEFF,63); - lgw_reg_w(LGW_IQ_MISMATCH_A_PHI_COEFF,9); - lgw_reg_w(LGW_IQ_MISMATCH_B_AMP_COEFF,0); - lgw_reg_w(LGW_IQ_MISMATCH_B_PHI_COEFF,0); - - /* load adjusted parameters */ - lgw_constant_adjust(); - - /* configure Lora 'multi' (aka. Lora 'sensor' channels */ - lgw_reg_w(LGW_RADIO_SELECT, if_rf_switch); /* IF mapping to radio A/B (per bit, 0=A, 1=B) */ - - lgw_reg_w(LGW_IF_FREQ_0, IF_HZ_TO_REG(if_freq[0])); /* default -384 */ - lgw_reg_w(LGW_IF_FREQ_1, IF_HZ_TO_REG(if_freq[1])); /* default -128 */ - lgw_reg_w(LGW_IF_FREQ_2, IF_HZ_TO_REG(if_freq[2])); /* default 128 */ - lgw_reg_w(LGW_IF_FREQ_3, IF_HZ_TO_REG(if_freq[3])); /* default 384 */ - - lgw_reg_w(LGW_CORR0_DETECT_EN, (if_enable[0] == true) ? lora_multi_sfmask[0] : 0); /* default 0 */ - lgw_reg_w(LGW_CORR1_DETECT_EN, (if_enable[1] == true) ? lora_multi_sfmask[1] : 0); /* default 0 */ - lgw_reg_w(LGW_CORR2_DETECT_EN, (if_enable[2] == true) ? lora_multi_sfmask[2] : 0); /* default 0 */ - lgw_reg_w(LGW_CORR3_DETECT_EN, (if_enable[3] == true) ? lora_multi_sfmask[3] : 0); /* default 0 */ - - lgw_reg_w(LGW_PPM_OFFSET, 0x60); /* as the threshold is 16ms, use 0x60 to enable ppm_offset for SF12 and SF11 @125kHz*/ - - lgw_reg_w(LGW_CONCENTRATOR_MODEM_ENABLE,1); /* default 0 */ - - /* configure Lora 'stand-alone' modem */ - lgw_reg_w(LGW_IF_FREQ_8, IF_HZ_TO_REG(if_freq[8])); /* MBWSSF modem (default 0) */ - if (if_enable[8] == true) { - switch(lora_rx_bw) { - case BW_125KHZ: lgw_reg_w(LGW_MBWSSF_MODEM_BW,0); break; - case BW_250KHZ: lgw_reg_w(LGW_MBWSSF_MODEM_BW,1); break; - case BW_500KHZ: lgw_reg_w(LGW_MBWSSF_MODEM_BW,2); break; - default: DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", lora_rx_bw); return LGW_HAL_ERROR; - } - switch(lora_rx_sf) { - case DR_LORA_SF7: lgw_reg_w(LGW_MBWSSF_RATE_SF,7); break; - case DR_LORA_SF8: lgw_reg_w(LGW_MBWSSF_RATE_SF,8); break; - case DR_LORA_SF9: lgw_reg_w(LGW_MBWSSF_RATE_SF,9); break; - case DR_LORA_SF10: lgw_reg_w(LGW_MBWSSF_RATE_SF,10); break; - case DR_LORA_SF11: lgw_reg_w(LGW_MBWSSF_RATE_SF,11); break; - case DR_LORA_SF12: lgw_reg_w(LGW_MBWSSF_RATE_SF,12); break; - default: DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", lora_rx_sf); return LGW_HAL_ERROR; - } - lgw_reg_w(LGW_MBWSSF_PPM_OFFSET, lora_rx_ppm_offset); /* default 0 */ - lgw_reg_w(LGW_MBWSSF_MODEM_ENABLE, 1); /* default 0 */ - } else { - lgw_reg_w(LGW_MBWSSF_MODEM_ENABLE, 0); - } - - /* configure FSK modem */ - //lgw_reg_w(LGW_IF_FREQ_9, IF_HZ_TO_REG(if_freq[9])); /* FSK modem (default 0) */ - - /* Load firmware */ - load_firmware(MCU_ARB, arb_firmware, MCU_ARB_FW_BYTE); - load_firmware(MCU_AGC, agc_firmware, MCU_AGC_FW_BYTE); - - /* Get MCUs out of reset */ - lgw_reg_w(LGW_MCU_RST_0, 0); - lgw_reg_w(LGW_MCU_RST_1, 0); - - lgw_is_started = true; - return LGW_HAL_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_stop(void) { - lgw_soft_reset(); - lgw_disconnect(); - - lgw_is_started = false; - return LGW_HAL_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_receive(uint8_t max_pkt, struct lgw_pkt_rx_s *pkt_data) { - int nb_pkt_fetch; /* loop variable and return value */ - struct lgw_pkt_rx_s *p; /* pointer to the current structure in the struct array */ - uint8_t buff[255+RX_METADATA_NB]; /* buffer to store the result of SPI read bursts */ - uint16_t data_addr; /* address read from the FIFO and programmed before the data buffer read operation */ - int s; /* size of the payload, uses to address metadata */ - int ifmod; /* type of if_chain/modem a packet was received by */ - int stat_fifo; /* the packet status as indicated in the FIFO */ - - /* check if the gateway is running */ - if (lgw_is_started == false) { - DEBUG_MSG("ERROR: GATEWAY IS NOT RUNNING, START IT BEFORE RECEIVING\n"); - return LGW_HAL_ERROR; - } - - /* check input variables */ - if (max_pkt <= 0) { - DEBUG_PRINTF("ERROR: %d = INVALID MAX NUMBER OF PACKETS TO FETCH\n", max_pkt); - return LGW_HAL_ERROR; - } - CHECK_NULL(pkt_data); - - /* iterate max_pkt times at most */ - for (nb_pkt_fetch = 0; nb_pkt_fetch < max_pkt; ++nb_pkt_fetch) { - - /* point to the proper struct in the struct array */ - p = &pkt_data[nb_pkt_fetch]; - - /* fetch all the RX FIFO data */ - lgw_reg_rb(LGW_RX_PACKET_DATA_FIFO_NUM_STORED, buff, 5); - - /* how many packets are in the RX buffer ? Break if zero */ - if (buff[0] == 0) { - DEBUG_MSG("Note: RX packet buffer empty, receive function returning nothing\n"); - break; /* no more packets to fetch, exit out of FOR loop */ - } - - DEBUG_PRINTF("FIFO content: %x %x %x %x %x\n",buff[0],buff[1],buff[2],buff[3],buff[4]); - - p->size = buff[4]; - s = p->size; - stat_fifo = buff[3]; /* will be used later, need to save it before overwriting buff */ - - /* STILL required */ - data_addr = (uint16_t)buff[1] + ((uint16_t)buff[2] << 8); - lgw_reg_w(LGW_RX_DATA_BUF_ADDR, data_addr); - - /* dynamically allocate memory to store payload */ - p->payload = (uint8_t *)malloc(s); - if (p->payload == NULL) { - /* not enough memory to allocate for payload, abort with error */ - DEBUG_MSG("ERROR: IMPOSSIBLE TO ALLOCATE MEMORY TO FETCH PAYLOAD\n"); - return LGW_HAL_ERROR; - } - - /* get payload + metadata */ - lgw_reg_rb(LGW_RX_DATA_BUF_DATA, buff, s+RX_METADATA_NB); - - /* copy payload */ - memcpy(p->payload, buff, s); - - /* process metadata */ - p->if_chain = buff[s+0]; - ifmod = ifmod_config[p->if_chain]; - DEBUG_PRINTF("[%d %d]\n", p->if_chain, ifmod); - - if ((ifmod == IF_LORA_MULTI) || (ifmod == IF_LORA_STD)) { - DEBUG_MSG("Note: Lora packet\n"); - switch(stat_fifo & 0x07) { - case 5: p->status = STAT_CRC_OK; break; - case 7: p->status = STAT_CRC_BAD; break; - case 1: p->status = STAT_NO_CRC; break; - default: p->status = STAT_UNDEFINED; - } - p->modulation = MOD_LORA; - p->snr = ((float)((int8_t)buff[s+2]))/4; - p->snr_min = ((float)((int8_t)buff[s+3]))/4; - p->snr_max = ((float)((int8_t)buff[s+4]))/4; - if (ifmod == IF_LORA_MULTI) { - p->rssi = RSSI_OFFSET_LORA_MULTI + (float)buff[s+5]; - p->bandwidth = BW_125KHZ; /* fixed in hardware */ - } else { - p->rssi = RSSI_OFFSET_LORA_STD + (float)buff[s+5]; - p->bandwidth = lora_rx_bw; /* get the parameter from the config variable */ - } - switch ((buff[s+1] >> 4) & 0x0F) { - case 7: p->datarate = DR_LORA_SF7; break; - case 8: p->datarate = DR_LORA_SF8; break; - case 9: p->datarate = DR_LORA_SF9; break; - case 10: p->datarate = DR_LORA_SF10; break; - case 11: p->datarate = DR_LORA_SF11; break; - case 12: p->datarate = DR_LORA_SF12; break; - default: p->datarate = DR_UNDEFINED; - } - switch ((buff[s+1] >> 1) & 0x07) { - case 1: p->coderate = CR_LORA_4_5; break; - case 2: p->coderate = CR_LORA_4_6; break; - case 3: p->coderate = CR_LORA_4_7; break; - case 4: p->coderate = CR_LORA_4_8; break; - default: p->coderate = CR_UNDEFINED; - } - } else if (ifmod == IF_FSK_STD) { - // TODO: process received FSK packets - DEBUG_MSG("Note: FSK packet\n"); - p->status = STAT_UNDEFINED; - p->modulation = MOD_FSK; - p->rssi = NAN; - p->snr = NAN; - p->snr_min = NAN; - p->snr_max = NAN; - p->bandwidth = BW_UNDEFINED; - p->datarate = DR_UNDEFINED; - p->coderate = CR_UNDEFINED; - } else { - DEBUG_MSG("ERROR: UNEXPECTED PACKET ORIGIN\n"); - p->status = STAT_UNDEFINED; - p->modulation = MOD_UNDEFINED; - p->rssi = NAN; - p->snr = NAN; - p->snr_min = NAN; - p->snr_max = NAN; - p->bandwidth = BW_UNDEFINED; - p->datarate = DR_UNDEFINED; - p->coderate = CR_UNDEFINED; - } - - p->count_us = (uint32_t)buff[s+6] + ((uint32_t)buff[s+7] << 8) + ((uint32_t)buff[s+8] << 16) + ((uint32_t)buff[s+9] << 24); - p->crc = (uint16_t)buff[s+10] + ((uint16_t)buff[s+11] << 8); - - /* advance packet FIFO */ - lgw_reg_w(LGW_RX_PACKET_DATA_FIFO_NUM_STORED, 0); - } - - return nb_pkt_fetch; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_send(struct lgw_pkt_tx_s pkt_data) { - uint8_t buff[255+TX_METADATA_NB]; /* buffer to prepare the packet to send + metadata before SPI write burst */ - uint32_t part_int; /* integer part for PLL register value calculation */ - uint32_t part_frac; /* fractional part for PLL register value calculation */ - int i; - - /* check if the gateway is running */ - if (lgw_is_started == false) { - DEBUG_MSG("ERROR: GATEWAY IS NOT RUNNING, START IT BEFORE SENDING\n"); - return LGW_HAL_ERROR; - } - - /* check input variables */ - CHECK_NULL(pkt_data.payload); - if (pkt_data.rf_chain >= LGW_RF_CHAIN_NB) { - DEBUG_MSG("ERROR: INVALID RF_CHAIN TO SEND PACKETS\n"); - return LGW_HAL_ERROR; - } - if (rf_enable[pkt_data.rf_chain] == false) { - DEBUG_MSG("ERROR: SELECTED RF_CHAIN IS DISABLED\n"); - return LGW_HAL_ERROR; - } - if (pkt_data.freq_hz > rf_tx_upfreq[pkt_data.rf_chain]) { - DEBUG_PRINTF("ERROR: FREQUENCY %d HIGHER THAN UPPER LIMIT %d OF RF_CHAIN %d\n", pkt_data.freq_hz, rf_tx_upfreq[pkt_data.rf_chain], pkt_data.rf_chain); - return LGW_HAL_ERROR; - } else if (pkt_data.freq_hz < rf_tx_lowfreq[pkt_data.rf_chain]) { - DEBUG_PRINTF("ERROR: FREQUENCY %d LOWER THAN LOWER LIMIT %d OF RF_CHAIN %d\n", pkt_data.freq_hz, rf_tx_lowfreq[pkt_data.rf_chain], pkt_data.rf_chain); - return LGW_HAL_ERROR; - } - if (!IS_TX_MODE(pkt_data.tx_mode)) { - DEBUG_MSG("ERROR: TX_MODE NOT SUPPORTED\n"); - return LGW_HAL_ERROR; - } - if (pkt_data.modulation == MOD_LORA) { - if (!IS_LORA_BW(pkt_data.bandwidth)) { - DEBUG_MSG("ERROR: BANDWIDTH NOT SUPPORTED BY LORA TX\n"); - return LGW_HAL_ERROR; - } - if (!IS_LORA_STD_DR(pkt_data.datarate)) { - DEBUG_MSG("ERROR: DATARATE NOT SUPPORTED BY LORA TX\n"); - return LGW_HAL_ERROR; - } - if (!IS_LORA_CR(pkt_data.coderate)) { - DEBUG_MSG("ERROR: CODERATE NOT SUPPORTED BY LORA TX\n"); - return LGW_HAL_ERROR; - } - if (pkt_data.size > 255) { - DEBUG_MSG("ERROR: PAYLOAD LENGTH TOO BIG FOR LORA TX\n"); - return LGW_HAL_ERROR; - } - }else if ((pkt_data.modulation == MOD_FSK) || (pkt_data.modulation == MOD_GFSK)) { - DEBUG_MSG("ERROR: (G)FSK TX MODULATION NOT SUPPORTED YET\n"); - return LGW_HAL_ERROR; - } else { - DEBUG_MSG("ERROR: INVALID TX MODULATION\n"); - return LGW_HAL_ERROR; - } - - /* reset TX command flags */ - lgw_reg_w(LGW_TX_TRIG_IMMEDIATE, 0); - lgw_reg_w(LGW_TX_TRIG_DELAYED, 0); - lgw_reg_w(LGW_TX_TRIG_GPS, 0); - - /* metadata 0 to 2, TX PLL frequency */ - part_int = pkt_data.freq_hz / LGW_SX1257_DENOMINATOR; /* integer part, gives the MSB and the middle byte */ - part_frac = ((pkt_data.freq_hz % LGW_SX1257_DENOMINATOR) << 8) / LGW_SX1257_DENOMINATOR; /* fractional part, gives LSB */ - buff[0] = 0xFF & (part_int >> 8); /* Most Significant Byte */ - buff[1] = 0xFF & part_int; /* middle byte */ - buff[2] = 0xFF & part_frac; /* Least Significant Byte */ - - /* metadata 3 to 6, timestamp trigger value */ - buff[3] = 0xFF & (pkt_data.count_us >> 24); - buff[4] = 0xFF & (pkt_data.count_us >> 16); - buff[5] = 0xFF & (pkt_data.count_us >> 8); - buff[6] = 0xFF & pkt_data.count_us; - - /* parameters depending on modulation */ - if (pkt_data.modulation == MOD_LORA) { - /* metadata 7, modulation type, radio chain selection and TX power */ - buff[7] = (0x20 & (pkt_data.rf_chain << 5)) | (0x0F & pkt_data.rf_power); /* bit 4 is 0 -> Lora modulation */ - /* fine control over TX power not supported yet, any value other than 8 is 14 dBm */ - - buff[8] = 0; /* metadata 8, not used */ - - /* metadata 9, CRC, Lora CR & SF */ - switch (pkt_data.datarate) { - case DR_LORA_SF7: buff[9] = 7; break; - case DR_LORA_SF8: buff[9] = 8; break; - case DR_LORA_SF9: buff[9] = 9; break; - case DR_LORA_SF10: buff[9] = 10; break; - case DR_LORA_SF11: buff[9] = 11; break; - case DR_LORA_SF12: buff[9] = 12; break; - default: DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", pkt_data.datarate); - } - switch (pkt_data.coderate) { - case CR_LORA_4_5: buff[9] |= 1 << 4; break; - case CR_LORA_4_6: buff[9] |= 2 << 4; break; - case CR_LORA_4_7: buff[9] |= 3 << 4; break; - case CR_LORA_4_8: buff[9] |= 4 << 4; break; - default: DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", pkt_data.coderate); - } - if (pkt_data.no_crc == false) { - buff[9] |= 0x80; /* set 'CRC enable' bit */ - } - - /* metadata 10, payload size */ - buff[10] = pkt_data.size; - - /* metadata 11, implicit header, modulation bandwidth, PPM offset & polarity */ - switch (pkt_data.bandwidth) { - case BW_125KHZ: buff[11] = 0; break; - case BW_250KHZ: buff[11] = 1; break; - case BW_500KHZ: buff[11] = 2; break; - default: DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", pkt_data.bandwidth); - } - if (pkt_data.no_header == true) { - buff[11] |= 0x04; /* set 'implicit header' bit */ - } - if (SET_PPM_ON(pkt_data.bandwidth,pkt_data.datarate)) { - buff[11] |= 0x08; /* set 'PPM offset' bit at 1 */ - } - if (pkt_data.invert_pol == true) { - buff[11] |= 0x10; /* set 'TX polarity' bit at 1 */ - } - - /* metadata 12 & 13, Lora preamble size */ - if (pkt_data.preamble < MIN_LORA_PREAMBLE) { /* enforce minimum preamble size */ - pkt_data.preamble = MIN_LORA_PREAMBLE; - DEBUG_MSG("Note: preamble length adjusted to respect minimum Lora preamble size\n"); - } - buff[12] = 0xFF & (pkt_data.preamble >> 8); - buff[13] = 0xFF & pkt_data.preamble; - - /* metadata 14 & 15, not used */ - buff[14] = 0; - buff[15] = 0; - - } else { - DEBUG_MSG("ERROR: ONLY LORA TX SUPPORTED FOR NOW\n"); - return LGW_HAL_ERROR; - } - - /* copy payload */ - memcpy((void *)(buff + TX_METADATA_NB), pkt_data.payload, pkt_data.size); - - /* put metadata + payload in the TX data buffer */ - lgw_reg_w(LGW_TX_DATA_BUF_ADDR, 0); - lgw_reg_wb(LGW_TX_DATA_BUF_DATA, buff, (pkt_data.size + TX_METADATA_NB)); - DEBUG_ARRAY(i, pkt_data.size+TX_METADATA_NB, buff); - - /* send data */ - switch(pkt_data.tx_mode) { - case IMMEDIATE: - lgw_reg_w(LGW_TX_TRIG_IMMEDIATE, 1); - break; - - case TIMESTAMPED: - lgw_reg_w(LGW_TX_TRIG_DELAYED, 1); - break; - - case ON_GPS: - lgw_reg_w(LGW_TX_TRIG_GPS, 1); - break; - - default: - DEBUG_PRINTF("ERROR: UNEXPECTED VALUE %d IN SWITCH STATEMENT\n", pkt_data.tx_mode); - return LGW_HAL_ERROR; - } - - return LGW_HAL_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -int lgw_status(uint8_t select, uint8_t *code) { - int32_t read_value; - - /* check input variables */ - CHECK_NULL(code); - - if (select == TX_STATUS) { - lgw_reg_r(LGW_TX_STATUS, &read_value); - if (lgw_is_started == false) { - *code = TX_OFF; - } else if ((read_value & 0x10) == 0) { /* bit 4 @1: TX programmed */ - *code = TX_FREE; - } else if ((read_value & 0x60) != 0) { /* bit 5 or 6 @1: TX sequence */ - *code = TX_EMITTING; - } else { - *code = TX_SCHEDULED; - } - return LGW_HAL_SUCCESS; - - } else if (select == RX_STATUS) { - *code = RX_STATUS_UNKNOWN; /* todo */ - return LGW_HAL_SUCCESS; - - } else { - DEBUG_MSG("ERROR: SELECTION INVALID, NO STATUS TO RETURN\n"); - return LGW_HAL_ERROR; - } - -} - - -/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/src/loragw_reg.c b/loragw_hal/src/loragw_reg.c deleted file mode 100644 index a9122d2..0000000 --- a/loragw_hal/src/loragw_reg.c +++ /dev/null @@ -1,756 +0,0 @@ -/* - / _____) _ | | -( (____ _____ ____ _| |_ _____ ____| |__ - \____ \| ___ | (_ _) ___ |/ ___) _ \ - _____) ) ____| | | || |_| ____( (___| | | | -(______/|_____)_|_|_| \__)_____)\____)_| |_| - ©2013 Semtech-Cycleo - -Description: - Functions used to handle a single Lora gateway. - Registers are addressed by name. - Multi-bytes registers are handled automatically. - Read-modify-write is handled automatically. -*/ - - -/* -------------------------------------------------------------------------- */ -/* --- DEPENDANCIES --------------------------------------------------------- */ - -#include <stdint.h> /* C99 types */ -#include <stdbool.h> /* bool type */ -#include <stdio.h> /* printf fprintf */ - -#include "loragw_spi.h" -#include "loragw_reg.h" - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE MACROS ------------------------------------------------------- */ - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#if DEBUG_REG == 1 - #define DEBUG_MSG(str) fprintf(stderr, str) - #define DEBUG_PRINTF(fmt, args...) fprintf(stderr,"%s:%d: "fmt, __FUNCTION__, __LINE__, args) - #define CHECK_NULL(a) if(a==NULL){fprintf(stderr,"%s:%d: ERROR: NULL POINTER AS ARGUMENT\n", __FUNCTION__, __LINE__);return LGW_REG_ERROR;} -#else - #define DEBUG_MSG(str) - #define DEBUG_PRINTF(fmt, args...) - #define CHECK_NULL(a) if(a==NULL){return LGW_REG_ERROR;} -#endif - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE TYPES -------------------------------------------------------- */ - -struct lgw_reg_s { - int8_t page; /*!< page containing the register (-1 for all pages) */ - uint8_t addr; /*!< base address of the register (7 bit) */ - uint8_t offs; /*!< position of the register LSB (between 0 to 7) */ - bool sign; /*!< 1 indicates the register is signed (2 complem.) */ - uint8_t leng; /*!< number of bits in the register */ - bool rdon; /*!< 1 indicates a read-only register */ - int32_t dflt; /*!< register default value */ -}; - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE CONSTANTS ---------------------------------------------------- */ - -#define PAGE_ADDR 0x00 -#define PAGE_MASK 0x03 - -/* -auto generated register mapping for C code : 11-Jul-2013 13:20:40 -this file contains autogenerated C struct used to access the Lora register from the Primer firmware -this file is autogenerated from registers description -293 registers are defined -*/ -const struct lgw_reg_s loregs[LGW_TOTALREGS] = { - {-1,0,0,0,2,0,0}, /* PAGE_REG */ - {-1,0,7,0,1,0,0}, /* SOFT_RESET */ - {-1,1,0,0,8,1,103}, /* VERSION */ - {-1,2,0,0,16,0,0}, /* RX_DATA_BUF_ADDR */ - {-1,4,0,0,8,0,0}, /* RX_DATA_BUF_DATA */ - {-1,5,0,0,8,0,0}, /* TX_DATA_BUF_ADDR */ - {-1,6,0,0,8,0,0}, /* TX_DATA_BUF_DATA */ - {-1,7,0,0,8,0,0}, /* CAPTURE_RAM_ADDR */ - {-1,8,0,0,8,1,0}, /* CAPTURE_RAM_DATA */ - {-1,9,0,0,8,0,0}, /* MCU_PROM_ADDR */ - {-1,10,0,0,8,0,0}, /* MCU_PROM_DATA */ - {-1,11,0,0,8,0,0}, /* RX_PACKET_DATA_FIFO_NUM_STORED */ - {-1,12,0,0,16,1,0}, /* RX_PACKET_DATA_FIFO_ADDR_POINTER */ - {-1,14,0,0,8,1,0}, /* RX_PACKET_DATA_FIFO_STATUS */ - {-1,15,0,0,8,1,0}, /* RX_PACKET_DATA_FIFO_PAYLOAD_SIZE */ - {-1,16,0,0,1,0,0}, /* MBWSSF_MODEM_ENABLE */ - {-1,16,1,0,1,0,0}, /* CONCENTRATOR_MODEM_ENABLE */ - {-1,16,2,0,1,0,0}, /* FSK_MODEM_ENABLE */ - {-1,16,3,0,1,0,0}, /* GLOBAL_EN */ - {-1,17,0,0,1,0,1}, /* CLK32M_EN */ - {-1,17,1,0,1,0,1}, /* CLKHS_EN */ - {-1,18,0,0,1,0,0}, /* START_BIST0 */ - {-1,18,1,0,1,0,0}, /* START_BIST1 */ - {-1,18,2,0,1,0,0}, /* CLEAR_BIST0 */ - {-1,18,3,0,1,0,0}, /* CLEAR_BIST1 */ - {-1,19,0,0,1,1,0}, /* BIST0_FINISHED */ - {-1,19,1,0,1,1,0}, /* BIST1_FINISHED */ - {-1,20,0,0,1,1,0}, /* MCU_AGC_PROG_RAM_BIST_STATUS */ - {-1,20,1,0,1,1,0}, /* MCU_ARB_PROG_RAM_BIST_STATUS */ - {-1,20,2,0,1,1,0}, /* CAPTURE_RAM_BIST_STATUS */ - {-1,20,3,0,1,1,0}, /* CHAN_FIR_RAM0_BIST_STATUS */ - {-1,20,4,0,1,1,0}, /* CHAN_FIR_RAM1_BIST_STATUS */ - {-1,21,0,0,1,1,0}, /* CORR0_RAM_BIST_STATUS */ - {-1,21,1,0,1,1,0}, /* CORR1_RAM_BIST_STATUS */ - {-1,21,2,0,1,1,0}, /* CORR2_RAM_BIST_STATUS */ - {-1,21,3,0,1,1,0}, /* CORR3_RAM_BIST_STATUS */ - {-1,21,4,0,1,1,0}, /* CORR4_RAM_BIST_STATUS */ - {-1,21,5,0,1,1,0}, /* CORR5_RAM_BIST_STATUS */ - {-1,21,6,0,1,1,0}, /* CORR6_RAM_BIST_STATUS */ - {-1,21,7,0,1,1,0}, /* CORR7_RAM_BIST_STATUS */ - {-1,22,0,0,1,1,0}, /* MODEM0_RAM0_BIST_STATUS */ - {-1,22,1,0,1,1,0}, /* MODEM1_RAM0_BIST_STATUS */ - {-1,22,2,0,1,1,0}, /* MODEM2_RAM0_BIST_STATUS */ - {-1,22,3,0,1,1,0}, /* MODEM3_RAM0_BIST_STATUS */ - {-1,22,4,0,1,1,0}, /* MODEM4_RAM0_BIST_STATUS */ - {-1,22,5,0,1,1,0}, /* MODEM5_RAM0_BIST_STATUS */ - {-1,22,6,0,1,1,0}, /* MODEM6_RAM0_BIST_STATUS */ - {-1,22,7,0,1,1,0}, /* MODEM7_RAM0_BIST_STATUS */ - {-1,23,0,0,1,1,0}, /* MODEM0_RAM1_BIST_STATUS */ - {-1,23,1,0,1,1,0}, /* MODEM1_RAM1_BIST_STATUS */ - {-1,23,2,0,1,1,0}, /* MODEM2_RAM1_BIST_STATUS */ - {-1,23,3,0,1,1,0}, /* MODEM3_RAM1_BIST_STATUS */ - {-1,23,4,0,1,1,0}, /* MODEM4_RAM1_BIST_STATUS */ - {-1,23,5,0,1,1,0}, /* MODEM5_RAM1_BIST_STATUS */ - {-1,23,6,0,1,1,0}, /* MODEM6_RAM1_BIST_STATUS */ - {-1,23,7,0,1,1,0}, /* MODEM7_RAM1_BIST_STATUS */ - {-1,24,0,0,1,1,0}, /* MODEM0_RAM2_BIST_STATUS */ - {-1,24,1,0,1,1,0}, /* MODEM1_RAM2_BIST_STATUS */ - {-1,24,2,0,1,1,0}, /* MODEM2_RAM2_BIST_STATUS */ - {-1,24,3,0,1,1,0}, /* MODEM3_RAM2_BIST_STATUS */ - {-1,24,4,0,1,1,0}, /* MODEM4_RAM2_BIST_STATUS */ - {-1,24,5,0,1,1,0}, /* MODEM5_RAM2_BIST_STATUS */ - {-1,24,6,0,1,1,0}, /* MODEM6_RAM2_BIST_STATUS */ - {-1,24,7,0,1,1,0}, /* MODEM7_RAM2_BIST_STATUS */ - {-1,25,0,0,1,1,0}, /* MODEM_MBWSSF_RAM0_BIST_STATUS */ - {-1,25,1,0,1,1,0}, /* MODEM_MBWSSF_RAM1_BIST_STATUS */ - {-1,25,2,0,1,1,0}, /* MODEM_MBWSSF_RAM2_BIST_STATUS */ - {-1,26,0,0,1,1,0}, /* MCU_AGC_DATA_RAM_BIST0_STATUS */ - {-1,26,1,0,1,1,0}, /* MCU_AGC_DATA_RAM_BIST1_STATUS */ - {-1,26,2,0,1,1,0}, /* MCU_ARB_DATA_RAM_BIST0_STATUS */ - {-1,26,3,0,1,1,0}, /* MCU_ARB_DATA_RAM_BIST1_STATUS */ - {-1,26,4,0,1,1,0}, /* TX_TOP_RAM_BIST0_STATUS */ - {-1,26,5,0,1,1,0}, /* TX_TOP_RAM_BIST1_STATUS */ - {-1,26,6,0,1,1,0}, /* DATA_MNGT_RAM_BIST0_STATUS */ - {-1,26,7,0,1,1,0}, /* DATA_MNGT_RAM_BIST1_STATUS */ - {-1,27,0,0,4,0,0}, /* GPIO_SELECT_INPUT */ - {-1,28,0,0,4,0,0}, /* GPIO_SELECT_OUTPUT */ - {-1,29,0,0,5,0,0}, /* GPIO_MODE */ - {-1,30,0,0,5,1,0}, /* GPIO_PIN_REG_IN */ - {-1,31,0,0,5,0,0}, /* GPIO_PIN_REG_OUT */ - {-1,32,0,0,8,1,0}, /* MCU_AGC_STATUS */ - {-1,125,0,0,8,1,0}, /* MCU_ARB_STATUS */ - {-1,126,0,0,8,1,1}, /* CHIP_ID */ - {-1,127,0,0,1,0,1}, /* EMERGENCY_FORCE_HOST_CTRL */ - {0,33,0,0,1,0,0}, /* RX_INVERT_IQ */ - {0,33,1,0,1,0,1}, /* MODEM_INVERT_IQ */ - {0,33,2,0,1,0,0}, /* MBWSSF_MODEM_INVERT_IQ */ - {0,33,3,0,1,0,0}, /* RX_EDGE_SELECT */ - {0,33,4,0,1,0,0}, /* MISC_RADIO_EN */ - {0,33,5,0,1,0,0}, /* FSK_MODEM_INVERT_IQ */ - {0,34,0,0,4,0,7}, /* FILTER_GAIN */ - {0,35,0,0,8,0,240}, /* RADIO_SELECT */ - {0,36,0,1,13,0,-384}, /* IF_FREQ_0 */ - {0,38,0,1,13,0,-128}, /* IF_FREQ_1 */ - {0,40,0,1,13,0,128}, /* IF_FREQ_2 */ - {0,42,0,1,13,0,384}, /* IF_FREQ_3 */ - {0,44,0,1,13,0,-384}, /* IF_FREQ_4 */ - {0,46,0,1,13,0,-128}, /* IF_FREQ_5 */ - {0,48,0,1,13,0,128}, /* IF_FREQ_6 */ - {0,50,0,1,13,0,384}, /* IF_FREQ_7 */ - {0,52,0,1,13,0,0}, /* IF_FREQ_8 */ - {0,54,0,1,13,0,0}, /* IF_FREQ_9 */ - {0,64,0,0,1,0,0}, /* CHANN_OVERRIDE_AGC_GAIN */ - {0,64,1,0,4,0,7}, /* CHANN_AGC_GAIN */ - {0,65,0,0,7,0,0}, /* CORR0_DETECT_EN */ - {0,66,0,0,7,0,0}, /* CORR1_DETECT_EN */ - {0,67,0,0,7,0,0}, /* CORR2_DETECT_EN */ - {0,68,0,0,7,0,0}, /* CORR3_DETECT_EN */ - {0,69,0,0,7,0,0}, /* CORR4_DETECT_EN */ - {0,70,0,0,7,0,0}, /* CORR5_DETECT_EN */ - {0,71,0,0,7,0,0}, /* CORR6_DETECT_EN */ - {0,72,0,0,7,0,0}, /* CORR7_DETECT_EN */ - {0,73,0,0,1,0,0}, /* CORR_SAME_PEAKS_OPTION_SF6 */ - {0,73,1,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF7 */ - {0,73,2,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF8 */ - {0,73,3,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF9 */ - {0,73,4,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF10 */ - {0,73,5,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF11 */ - {0,73,6,0,1,0,1}, /* CORR_SAME_PEAKS_OPTION_SF12 */ - {0,74,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF6 */ - {0,74,4,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF7 */ - {0,75,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF8 */ - {0,75,4,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF9 */ - {0,76,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF10 */ - {0,76,4,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF11 */ - {0,77,0,0,4,0,4}, /* CORR_SIG_NOISE_RATIO_SF12 */ - {0,78,0,0,4,0,4}, /* CORR_NUM_SAME_PEAK */ - {0,78,4,0,3,0,5}, /* CORR_MAC_GAIN */ - {0,81,0,0,12,0,0}, /* ADJUST_MODEM_START_OFFSET_RDX4 */ - {0,83,0,0,12,0,4092}, /* ADJUST_MODEM_START_OFFSET_SF12_RDX4 */ - {0,85,0,0,8,0,7}, /* DBG_CORR_SELECT_SF */ - {0,86,0,0,8,0,0}, /* DBG_CORR_SELECT_CHANNEL */ - {0,87,0,0,8,1,0}, /* DBG_DETECT_CPT */ - {0,88,0,0,8,1,0}, /* DBG_SYMB_CPT */ - {0,89,0,0,1,0,1}, /* CHIRP_INVERT_RX */ - {0,89,1,0,1,0,1}, /* DC_NOTCH_EN */ - {0,90,0,0,1,0,0}, /* IMPLICIT_CRC_EN */ - {0,90,1,0,3,0,0}, /* IMPLICIT_CODING_RATE */ - {0,91,0,0,8,0,0}, /* IMPLICIT_PAYLOAD_LENGHT */ - {0,92,0,0,8,0,29}, /* FREQ_TO_TIME_INVERT */ - {0,93,0,0,6,0,9}, /* FREQ_TO_TIME_DRIFT */ - {0,94,0,0,2,0,2}, /* PAYLOAD_FINE_TIMING_GAIN */ - {0,94,2,0,2,0,1}, /* PREAMBLE_FINE_TIMING_GAIN */ - {0,94,4,0,2,0,0}, /* TRACKING_INTEGRAL */ - {0,95,0,0,4,0,1}, /* FRAME_SYNCH_PEAK1_POS */ - {0,95,4,0,4,0,2}, /* FRAME_SYNCH_PEAK2_POS */ - {0,96,0,0,16,0,10}, /* PREAMBLE_SYMB1_NB */ - {0,98,0,0,1,0,1}, /* FRAME_SYNCH_GAIN */ - {0,98,1,0,1,0,1}, /* SYNCH_DETECT_TH */ - {0,99,0,0,4,0,8}, /* LLR_SCALE */ - {0,99,4,0,2,0,2}, /* SNR_AVG_CST */ - {0,100,0,0,7,0,0}, /* PPM_OFFSET */ - {0,101,0,0,8,0,255}, /* MAX_PAYLOAD_LEN */ - {0,102,0,0,1,0,1}, /* ONLY_CRC_EN */ - {0,103,0,0,8,0,0}, /* ZERO_PAD */ - {0,104,0,0,4,0,8}, /* DEC_GAIN_OFFSET */ - {0,104,4,0,4,0,7}, /* CHAN_GAIN_OFFSET */ - {0,105,1,0,1,0,1}, /* FORCE_HOST_RADIO_CTRL */ - {0,105,2,0,1,0,1}, /* FORCE_HOST_FE_CTRL */ - {0,105,3,0,1,0,1}, /* FORCE_DEC_FILTER_GAIN */ - {0,106,0,0,1,0,1}, /* MCU_RST_0 */ - {0,106,1,0,1,0,1}, /* MCU_RST_1 */ - {0,106,2,0,1,0,0}, /* MCU_SELECT_MUX_0 */ - {0,106,3,0,1,0,0}, /* MCU_SELECT_MUX_1 */ - {0,106,4,0,1,1,0}, /* MCU_CORRUPTION_DETECTED_0 */ - {0,106,5,0,1,1,0}, /* MCU_CORRUPTION_DETECTED_1 */ - {0,106,6,0,1,0,0}, /* MCU_SELECT_EDGE_0 */ - {0,106,7,0,1,0,0}, /* MCU_SELECT_EDGE_1 */ - {0,107,0,0,8,0,1}, /* CHANN_SELECT_RSSI */ - {0,108,0,0,8,0,32}, /* RSSI_BB_DEFAULT_VALUE */ - {0,109,0,0,8,0,100}, /* RSSI_DEC_DEFAULT_VALUE */ - {0,110,0,0,8,0,100}, /* RSSI_CHANN_DEFAULT_VALUE */ - {0,111,0,0,5,0,7}, /* RSSI_BB_FILTER_ALPHA */ - {0,112,0,0,5,0,5}, /* RSSI_DEC_FILTER_ALPHA */ - {0,113,0,0,5,0,8}, /* RSSI_CHANN_FILTER_ALPHA */ - {0,114,0,0,6,0,0}, /* IQ_MISMATCH_A_AMP_COEFF */ - {0,115,0,0,6,0,0}, /* IQ_MISMATCH_A_PHI_COEFF */ - {0,116,0,0,6,0,0}, /* IQ_MISMATCH_B_AMP_COEFF */ - {0,116,6,0,1,0,0}, /* IQ_MISMATCH_B_SEL_I */ - {0,117,0,0,6,0,0}, /* IQ_MISMATCH_B_PHI_COEFF */ - {1,33,0,0,1,0,0}, /* TX_TRIG_IMMEDIATE */ - {1,33,1,0,1,0,0}, /* TX_TRIG_DELAYED */ - {1,33,2,0,1,0,0}, /* TX_TRIG_GPS */ - {1,34,0,0,16,0,0}, /* TX_START_DELAY */ - {1,36,0,0,4,0,1}, /* TX_FRAME_SYNCH_PEAK1_POS */ - {1,36,4,0,4,0,2}, /* TX_FRAME_SYNCH_PEAK2_POS */ - {1,37,0,0,3,0,0}, /* TX_RAMP_DURATION */ - {1,39,0,1,8,0,0}, /* TX_OFFSET_I */ - {1,40,0,1,8,0,0}, /* TX_OFFSET_Q */ - {1,41,0,0,1,0,0}, /* TX_MODE */ - {1,41,1,0,4,0,0}, /* TX_ZERO_PAD */ - {1,41,5,0,1,0,0}, /* TX_EDGE_SELECT */ - {1,41,6,0,1,0,0}, /* TX_EDGE_SELECT_TOP */ - {1,42,0,0,2,0,0}, /* TX_GAIN */ - {1,42,2,0,3,0,5}, /* TX_CHIRP_LOW_PASS */ - {1,42,5,0,2,0,0}, /* TX_FCC_WIDEBAND */ - {1,42,7,0,1,0,1}, /* TX_SWAP_IQ */ - {1,43,0,0,1,0,0}, /* MBWSSF_IMPLICIT_HEADER */ - {1,43,1,0,1,0,0}, /* MBWSSF_IMPLICIT_CRC_EN */ - {1,43,2,0,3,0,0}, /* MBWSSF_IMPLICIT_CODING_RATE */ - {1,44,0,0,8,0,0}, /* MBWSSF_IMPLICIT_PAYLOAD_LENGHT */ - {1,45,0,0,1,0,1}, /* MBWSSF_AGC_FREEZE_ON_DETECT */ - {1,46,0,0,4,0,1}, /* MBWSSF_FRAME_SYNCH_PEAK1_POS */ - {1,46,4,0,4,0,2}, /* MBWSSF_FRAME_SYNCH_PEAK2_POS */ - {1,47,0,0,16,0,10}, /* MBWSSF_PREAMBLE_SYMB1_NB */ - {1,49,0,0,1,0,1}, /* MBWSSF_FRAME_SYNCH_GAIN */ - {1,49,1,0,1,0,1}, /* MBWSSF_SYNCH_DETECT_TH */ - {1,50,0,0,8,0,10}, /* MBWSSF_DETECT_MIN_SINGLE_PEAK */ - {1,51,0,0,3,0,3}, /* MBWSSF_DETECT_TRIG_SAME_PEAK_NB */ - {1,52,0,0,8,0,29}, /* MBWSSF_FREQ_TO_TIME_INVERT */ - {1,53,0,0,6,0,36}, /* MBWSSF_FREQ_TO_TIME_DRIFT */ - {1,54,0,0,12,0,0}, /* MBWSSF_PPM_CORRECTION */ - {1,56,0,0,2,0,2}, /* MBWSSF_PAYLOAD_FINE_TIMING_GAIN */ - {1,56,2,0,2,0,1}, /* MBWSSF_PREAMBLE_FINE_TIMING_GAIN */ - {1,56,4,0,2,0,0}, /* MBWSSF_TRACKING_INTEGRAL */ - {1,57,0,0,8,0,0}, /* MBWSSF_ZERO_PAD */ - {1,58,0,0,2,0,0}, /* MBWSSF_MODEM_BW */ - {1,58,2,0,1,0,0}, /* MBWSSF_RADIO_SELECT */ - {1,58,3,0,1,0,1}, /* MBWSSF_RX_CHIRP_INVERT */ - {1,59,0,0,4,0,8}, /* MBWSSF_LLR_SCALE */ - {1,59,4,0,2,0,3}, /* MBWSSF_SNR_AVG_CST */ - {1,59,6,0,1,0,0}, /* MBWSSF_PPM_OFFSET */ - {1,60,0,0,4,0,7}, /* MBWSSF_RATE_SF */ - {1,60,4,0,1,0,1}, /* MBWSSF_ONLY_CRC_EN */ - {1,61,0,0,8,0,255}, /* MBWSSF_MAX_PAYLOAD_LEN */ - {1,62,0,0,8,1,128}, /* TX_STATUS */ - {1,63,0,0,3,0,0}, /* FSK_CH_BW_EXPO */ - {1,63,3,0,3,0,0}, /* FSK_RSSI_LENGTH */ - {1,63,6,0,1,0,0}, /* FSK_RX_INVERT */ - {1,63,7,0,1,0,0}, /* FSK_PKT_MODE */ - {1,64,0,0,3,0,0}, /* FSK_PSIZE */ - {1,64,3,0,1,0,0}, /* FSK_CRC_EN */ - {1,64,4,0,2,0,0}, /* FSK_DCFREE_ENC */ - {1,64,6,0,1,0,0}, /* FSK_CRC_IBM */ - {1,65,0,0,5,0,0}, /* FSK_ERROR_OSR_TOL */ - {1,65,7,0,1,0,0}, /* FSK_RADIO_SELECT */ - {1,66,0,0,16,0,0}, /* FSK_BR_RATIO */ - {1,68,0,0,32,0,0}, /* FSK_REF_PATTERN_LSB */ - {1,72,0,0,32,0,0}, /* FSK_REF_PATTERN_MSB */ - {1,76,0,0,8,0,0}, /* FSK_PKT_LENGTH */ - {1,77,0,0,1,0,1}, /* FSK_TX_GAUSSIAN_EN */ - {1,77,1,0,2,0,0}, /* FSK_TX_GAUSSIAN_SELECT_BT */ - {1,77,3,0,1,0,1}, /* FSK_TX_PATTERN_EN */ - {1,77,4,0,1,0,0}, /* FSK_TX_PREAMBLE_SEQ */ - {1,77,5,0,3,0,0}, /* FSK_TX_PSIZE */ - {1,80,0,0,8,0,0}, /* FSK_NODE_ADRS */ - {1,81,0,0,8,0,0}, /* FSK_BROADCAST */ - {1,82,0,0,1,0,1}, /* FSK_AUTO_AFC_ON */ - {1,83,0,0,10,0,0}, /* FSK_PATTERN_TIMEOUT_CFG */ - {2,33,0,0,8,0,0}, /* SPI_RADIO_A__DATA */ - {2,34,0,0,8,1,0}, /* SPI_RADIO_A__DATA_READBACK */ - {2,35,0,0,8,0,0}, /* SPI_RADIO_A__ADDR */ - {2,37,0,0,1,0,0}, /* SPI_RADIO_A__CS */ - {2,38,0,0,8,0,0}, /* SPI_RADIO_B__DATA */ - {2,39,0,0,8,1,0}, /* SPI_RADIO_B__DATA_READBACK */ - {2,40,0,0,8,0,0}, /* SPI_RADIO_B__ADDR */ - {2,42,0,0,1,0,0}, /* SPI_RADIO_B__CS */ - {2,43,0,0,1,0,0}, /* RADIO_A_EN */ - {2,43,1,0,1,0,0}, /* RADIO_B_EN */ - {2,43,2,0,1,0,1}, /* RADIO_RST */ - {2,43,3,0,1,0,0}, /* LNA_A_EN */ - {2,43,4,0,1,0,0}, /* PA_A_EN */ - {2,43,5,0,1,0,0}, /* LNA_B_EN */ - {2,43,6,0,1,0,0}, /* PA_B_EN */ - {2,44,0,0,2,0,0}, /* PA_GAIN */ - {2,45,0,0,4,0,2}, /* LNA_A_CTRL_LUT */ - {2,45,4,0,4,0,4}, /* PA_A_CTRL_LUT */ - {2,46,0,0,4,0,2}, /* LNA_B_CTRL_LUT */ - {2,46,4,0,4,0,4}, /* PA_B_CTRL_LUT */ - {2,47,0,0,5,0,0}, /* CAPTURE_SOURCE */ - {2,47,5,0,1,0,0}, /* CAPTURE_START */ - {2,47,6,0,1,0,0}, /* CAPTURE_FORCE_TRIGGER */ - {2,47,7,0,1,0,0}, /* CAPTURE_WRAP */ - {2,48,0,0,16,0,0}, /* CAPTURE_PERIOD */ - {2,51,0,0,8,1,0}, /* MODEM_STATUS */ - {2,52,0,0,8,1,0}, /* VALID_HEADER_COUNTER_0 */ - {2,54,0,0,8,1,0}, /* VALID_PACKET_COUNTER_0 */ - {2,56,0,0,8,1,0}, /* VALID_HEADER_COUNTER_MBWSSF */ - {2,57,0,0,8,1,0}, /* VALID_HEADER_COUNTER_FSK */ - {2,58,0,0,8,1,0}, /* VALID_PACKET_COUNTER_MBWSSF */ - {2,59,0,0,8,1,0}, /* VALID_PACKET_COUNTER_FSK */ - {2,60,0,0,8,1,0}, /* CHANN_RSSI */ - {2,61,0,0,8,1,0}, /* BB_RSSI */ - {2,62,0,0,8,1,0}, /* DEC_RSSI */ - {2,63,0,0,8,1,0}, /* DBG_MCU_DATA */ - {2,64,0,0,8,1,0}, /* DBG_ARB_MCU_RAM_DATA */ - {2,65,0,0,8,1,0}, /* DBG_AGC_MCU_RAM_DATA */ - {2,66,0,0,16,1,0}, /* NEXT_PACKET_CNT */ - {2,68,0,0,16,1,0}, /* ADDR_CAPTURE_COUNT */ - {2,70,0,0,32,1,0}, /* TIMESTAMP */ - {2,74,0,0,4,1,0}, /* DBG_CHANN0_GAIN */ - {2,74,4,0,4,1,0}, /* DBG_CHANN1_GAIN */ - {2,75,0,0,4,1,0}, /* DBG_CHANN2_GAIN */ - {2,75,4,0,4,1,0}, /* DBG_CHANN3_GAIN */ - {2,76,0,0,4,1,0}, /* DBG_CHANN4_GAIN */ - {2,76,4,0,4,1,0}, /* DBG_CHANN5_GAIN */ - {2,77,0,0,4,1,0}, /* DBG_CHANN6_GAIN */ - {2,77,4,0,4,1,0}, /* DBG_CHANN7_GAIN */ - {2,78,0,0,4,1,0}, /* DBG_DEC_FILT_GAIN */ - {2,79,0,0,3,1,0}, /* SPI_DATA_FIFO_PTR */ - {2,79,3,0,3,1,0}, /* PACKET_DATA_FIFO_PTR */ - {2,80,0,0,8,0,0}, /* DBG_ARB_MCU_RAM_ADDR */ - {2,81,0,0,8,0,0}, /* DBG_AGC_MCU_RAM_ADDR */ - {2,82,0,0,1,0,0}, /* SPI_MASTER_CHIP_SELECT_POLARITY */ - {2,82,1,0,1,0,0}, /* SPI_MASTER_CPOL */ - {2,82,2,0,1,0,0}, /* SPI_MASTER_CPHA */ - {2,83,0,0,1,0,0}, /* SIG_GEN_ANALYSER_MUX_SEL */ - {2,84,0,0,1,0,0}, /* SIG_GEN_EN */ - {2,84,1,0,1,0,0}, /* SIG_ANALYSER_EN */ - {2,84,2,0,2,0,0}, /* SIG_ANALYSER_AVG_LEN */ - {2,84,4,0,3,0,0}, /* SIG_ANALYSER_PRECISION */ - {2,84,7,0,1,1,0}, /* SIG_ANALYSER_VALID_OUT */ - {2,85,0,0,8,0,0}, /* SIG_GEN_FREQ */ - {2,86,0,0,8,0,0}, /* SIG_ANALYSER_FREQ */ - {2,87,0,0,8,1,0}, /* SIG_ANALYSER_I_OUT */ - {2,88,0,0,8,1,0}, /* SIG_ANALYSER_Q_OUT */ - {2,89,0,0,1,0,0}, /* GPS_EN */ - {2,89,1,0,1,0,1}, /* GPS_POL */ - {2,90,0,1,8,0,0}, /* SW_TEST_REG1 */ - {2,91,2,1,6,0,0}, /* SW_TEST_REG2 */ - {2,92,0,1,16,0,0}, /* SW_TEST_REG3 */ - {2,94,0,0,4,1,0}, /* DATA_MNGT_STATUS */ - {2,95,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_ALLOCATED */ - {2,96,0,0,5,1,0}, /* DATA_MNGT_CPT_FRAME_FINISHED */ - {2,97,0,0,5,1,0} /* DATA_MNGT_CPT_FRAME_READEN */ -}; - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE VARIABLES ---------------------------------------------------- */ - -void *lgw_spi_target = NULL; /*! generic pointer to the SPI device */ -static int lgw_regpage = -1; /*! keep the value of the register page selected */ - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE FUNCTIONS ---------------------------------------------------- */ - -int page_switch(uint8_t target) { - lgw_regpage = PAGE_MASK & target; - lgw_spi_w(lgw_spi_target, PAGE_ADDR, (uint8_t)lgw_regpage); - return LGW_REG_SUCCESS; -} - -/* -------------------------------------------------------------------------- */ -/* --- PUBLIC FUNCTIONS DEFINITION ------------------------------------------ */ - -/* Gateway connect */ -int lgw_connect(void) { - int spi_stat = LGW_SPI_SUCCESS; - uint8_t u = 0; - - if (lgw_spi_target != NULL) { - DEBUG_MSG("WARNING: gateway was already connected\n"); - lgw_spi_close(lgw_spi_target); - } - /* open the SPI link */ - spi_stat = lgw_spi_open(&lgw_spi_target); - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR CONNECTING GATEWAY\n"); - return LGW_REG_ERROR; - } - /* write 0 to the page/reset register */ - spi_stat = lgw_spi_w(lgw_spi_target, loregs[LGW_PAGE_REG].addr, 0); - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR WRITING PAGE REGISTER\n"); - return LGW_REG_ERROR; - } else { - lgw_regpage = 0; - } - /* checking the version register */ - spi_stat = lgw_spi_r(lgw_spi_target, loregs[LGW_VERSION].addr, &u); - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR READING VERSION REGISTER\n"); - return LGW_REG_ERROR; - } else if (u == 0) { - DEBUG_MSG("ERROR: GATEWAY SEEMS DISCONNECTED\n"); - return LGW_REG_ERROR; - } else if (u != loregs[LGW_VERSION].dflt) { - DEBUG_MSG("ERROR: MISMATCH BETWEEN EXPECTED REG VERSION AND READ REG VERSION\n"); - return LGW_REG_ERROR; - } - DEBUG_MSG("Note: success connecting the gateway\n"); - return LGW_REG_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Gateway disconnect */ -int lgw_disconnect(void) { - if (lgw_spi_target != NULL) { - lgw_spi_close(lgw_spi_target); - lgw_spi_target = NULL; - DEBUG_MSG("Note: success disconnecting the gateway\n"); - return LGW_REG_SUCCESS; - } else { - DEBUG_MSG("WARNING: gateway was already disconnected\n"); - return LGW_REG_ERROR; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* soft-reset function */ -int lgw_soft_reset(void) { - int32_t read_value; - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - lgw_spi_w(lgw_spi_target, 0, 0x80); /* 1 -> SOFT_RESET bit */ - lgw_regpage = 0; /* reset the paging static variable */ - return LGW_REG_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* register verification */ -int lgw_reg_check(FILE *f) { - struct lgw_reg_s r; - int32_t read_value; - char ok_msg[] = "+++MATCH+++"; - char notok_msg[] = "###MISMATCH###"; - char *ptr; - int i; - - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - fprintf(f, "ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - - fprintf(f, "Start of register verification\n"); - for (i=0; i<LGW_TOTALREGS; ++i) { - r = loregs[i]; - lgw_reg_r(i, &read_value); - ptr = (read_value == r.dflt) ? ok_msg : notok_msg; - if (r.sign == true) - fprintf(f, "%s reg number %d read: %d (%x) default: %d (%x)\n", ptr, i, read_value, read_value, r.dflt, r.dflt); - else - fprintf(f, "%s reg number %d read: %u (%x) default: %u (%x)\n", ptr, i, read_value, read_value, r.dflt, r.dflt); - } - fprintf(f, "End of register verification\n"); - - return LGW_REG_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Write to a register addressed by name */ -int lgw_reg_w(uint16_t register_id, int32_t reg_value) { - int spi_stat = LGW_SPI_SUCCESS; - struct lgw_reg_s r; - uint8_t buf[4] = "\x00\x00\x00\x00"; - int i, size_byte; - - /* check input parameters */ - if (register_id >= LGW_TOTALREGS) { - DEBUG_MSG("ERROR: REGISTER NUMBER OUT OF DEFINED RANGE\n"); - return LGW_REG_ERROR; - } - - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - - /* intercept direct access to PAGE_REG & SOFT_RESET */ - if (register_id == LGW_PAGE_REG) { - page_switch(reg_value); - return LGW_REG_SUCCESS; - } else if (register_id == LGW_SOFT_RESET) { - /* only reset if lsb is 1 */ - if ((reg_value & 0x01) != 0) - lgw_soft_reset(); - return LGW_REG_SUCCESS; - } - - /* get register struct from the struct array */ - r = loregs[register_id]; - - /* reject write to read-only registers */ - if (r.rdon == 1){ - DEBUG_MSG("ERROR: TRYING TO WRITE A READ-ONLY REGISTER\n"); - return LGW_REG_ERROR; - } - - /* select proper register page if needed */ - if ((r.page != -1) && (r.page != lgw_regpage)) { - spi_stat += page_switch(r.page); - } - - if ((r.leng == 8) && (r.offs == 0)) { - /* direct write */ - spi_stat += lgw_spi_w(lgw_spi_target, r.addr, (uint8_t)reg_value); - } else if ((r.offs + r.leng) <= 8) { - /* single-byte read-modify-write, offs:[0-7], leng:[1-7] */ - spi_stat += lgw_spi_r(lgw_spi_target, r.addr, &buf[0]); - buf[1] = ((1 << r.leng) - 1) << r.offs; /* bit mask */ - buf[2] = ((uint8_t)reg_value) << r.offs; /* new data offsetted */ - buf[3] = (~buf[1] & buf[0]) | (buf[1] & buf[2]); /* mixing old & new data */ - spi_stat += lgw_spi_w(lgw_spi_target, r.addr, buf[3]); - } else if ((r.offs == 0) && (r.leng > 0) && (r.leng <= 32)) { - /* multi-byte direct write routine */ - size_byte = (r.leng + 7) / 8; /* add a byte if it's not an exact multiple of 8 */ - for (i=0; i<size_byte; ++i) { - /* big endian register file for a file on N bytes - Least significant byte is stored in buf[0], most one in buf[N-1] */ - buf[i] = (uint8_t)(0x000000FF & reg_value); - reg_value = (reg_value >> 8); - } - spi_stat += lgw_spi_wb(lgw_spi_target, r.addr, buf, size_byte); /* write the register in one burst */ - } else { - /* register spanning multiple memory bytes but with an offset */ - DEBUG_MSG("ERROR: REGISTER SIZE AND OFFSET ARE NOT SUPPORTED\n"); - return LGW_REG_ERROR; - } - - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER WRITE\n"); - return LGW_REG_ERROR; - } else { - return LGW_REG_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Read to a register addressed by name */ -int lgw_reg_r(uint16_t register_id, int32_t *reg_value) { - int spi_stat = LGW_SPI_SUCCESS; - struct lgw_reg_s r; - uint8_t bufu[4] = "\x00\x00\x00\x00"; - int8_t *bufs = bufu; - int i, size_byte; - uint32_t u = 0; - - /* check input parameters */ - CHECK_NULL(reg_value); - if (register_id >= LGW_TOTALREGS) { - DEBUG_MSG("ERROR: REGISTER NUMBER OUT OF DEFINED RANGE\n"); - return LGW_REG_ERROR; - } - - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - - /* get register struct from the struct array */ - r = loregs[register_id]; - - /* select proper register page if needed */ - if ((r.page != -1) && (r.page != lgw_regpage)) { - spi_stat += page_switch(r.page); - } - - if ((r.offs + r.leng) <= 8) { - /* read one byte, then shift and mask bits to get reg value with sign extension if needed */ - spi_stat += lgw_spi_r(lgw_spi_target, r.addr, &bufu[0]); - bufu[1] = bufu[0] << (8 - r.leng - r.offs); /* left-align the data */ - if (r.sign == true) { - bufs[2] = bufs[1] >> (8 - r.leng); /* right align the data with sign extension (ARITHMETIC right shift) */ - *reg_value = (int32_t)bufs[2]; /* signed pointer -> 32b sign extension */ - } else { - bufu[2] = bufu[1] >> (8 - r.leng); /* right align the data, no sign extension */ - *reg_value = (int32_t)bufu[2]; /* unsigned pointer -> no sign extension */ - } - } else if ((r.offs == 0) && (r.leng > 0) && (r.leng <= 32)) { - size_byte = (r.leng + 7) / 8; /* add a byte if it's not an exact multiple of 8 */ - spi_stat += lgw_spi_rb(lgw_spi_target, r.addr, bufu, size_byte); - u = 0; - for (i=(size_byte-1); i>=0; --i) { - u = (uint32_t)bufu[i] + (u << 8); /* transform a 4-byte array into a 32 bit word */ - } - if (r.sign == true) { - u = u << (32 - r.leng); /* left-align the data */ - *reg_value = (int32_t)u >> (32 - r.leng); /* right-align the data with sign extension (ARITHMETIC right shift) */ - } else { - *reg_value = (int32_t)u; /* unsigned value -> return 'as is' */ - } - } else { - /* register spanning multiple memory bytes but with an offset */ - DEBUG_MSG("ERROR: REGISTER SIZE AND OFFSET ARE NOT SUPPORTED\n"); - return LGW_REG_ERROR; - } - - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER WRITE\n"); - return LGW_REG_ERROR; - } else { - return LGW_REG_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Point to a register by name and do a burst write */ -int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size) { - int spi_stat; - struct lgw_reg_s r; - - /* check input parameters */ - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_REG_ERROR; - } - if (register_id >= LGW_TOTALREGS) { - DEBUG_MSG("ERROR: REGISTER NUMBER OUT OF DEFINED RANGE\n"); - return LGW_REG_ERROR; - } - - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - - /* get register struct from the struct array */ - r = loregs[register_id]; - - /* reject write to read-only registers */ - if (r.rdon == 1){ - DEBUG_MSG("ERROR: TRYING TO BURST WRITE A READ-ONLY REGISTER\n"); - return LGW_REG_ERROR; - } - - /* select proper register page if needed */ - if ((r.page != -1) && (r.page != lgw_regpage)) { - spi_stat += page_switch(r.page); - } - - /* do the burst write */ - spi_stat = lgw_spi_wb(lgw_spi_target, r.addr, data, size); - - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER BURST WRITE\n"); - return LGW_REG_ERROR; - } else { - return LGW_REG_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Point to a register by name and do a burst read */ -int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size) { - int spi_stat; - struct lgw_reg_s r; - - /* check input parameters */ - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_REG_ERROR; - } - if (register_id >= LGW_TOTALREGS) { - DEBUG_MSG("ERROR: REGISTER NUMBER OUT OF DEFINED RANGE\n"); - return LGW_REG_ERROR; - } - - /* check if SPI is initialised */ - if ((lgw_spi_target == NULL) || (lgw_regpage < 0)) { - DEBUG_MSG("ERROR: GATEWAY UNCONNECTED\n"); - return LGW_REG_ERROR; - } - - /* get register struct from the struct array */ - r = loregs[register_id]; - - /* select proper register page if needed */ - if ((r.page != -1) && (r.page != lgw_regpage)) { - spi_stat += page_switch(r.page); - } - - /* do the burst read */ - spi_stat = lgw_spi_rb(lgw_spi_target, r.addr, data, size); - - if (spi_stat != LGW_SPI_SUCCESS) { - DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER BURST READ\n"); - return LGW_REG_ERROR; - } else { - return LGW_REG_SUCCESS; - } -} - -/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/src/loragw_spi.ftdi.c b/loragw_hal/src/loragw_spi.ftdi.c deleted file mode 100644 index 7b71901..0000000 --- a/loragw_hal/src/loragw_spi.ftdi.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - / _____) _ | | -( (____ _____ ____ _| |_ _____ ____| |__ - \____ \| ___ | (_ _) ___ |/ ___) _ \ - _____) ) ____| | | || |_| ____( (___| | | | -(______/|_____)_|_|_| \__)_____)\____)_| |_| - ©2013 Semtech-Cycleo - -Description: - Host specific functions to address the LoRa™ gateway registers through a - SPI interface. - Single-byte read/write and burst read/write. - Does not handle pagination. - Could be used with multiple SPI ports in parallel (explicit file descriptor) -*/ - - -/* -------------------------------------------------------------------------- */ -/* --- DEPENDANCIES --------------------------------------------------------- */ - -#include <stdint.h> /* C99 types */ -#include <stdio.h> /* printf fprintf */ -#include <stdlib.h> /* malloc free */ -#include <string.h> /* memcpy */ - -#include <mpsse.h> - -#include "loragw_spi.h" - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE MACROS ------------------------------------------------------- */ - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#if DEBUG_SPI == 1 - #define DEBUG_MSG(str) fprintf(stderr, str) - #define DEBUG_PRINTF(fmt, args...) fprintf(stderr,"%s:%d: "fmt, __FUNCTION__, __LINE__, args) - #define CHECK_NULL(a) if(a==NULL){fprintf(stderr,"%s:%d: ERROR: NULL POINTER AS ARGUMENT\n", __FUNCTION__, __LINE__);return LGW_SPI_ERROR;} -#else - #define DEBUG_MSG(str) - #define DEBUG_PRINTF(fmt, args...) - #define CHECK_NULL(a) if(a==NULL){return LGW_SPI_ERROR;} -#endif - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE CONSTANTS ---------------------------------------------------- */ - -#define READ_ACCESS 0x00 -#define WRITE_ACCESS 0x80 - -/* parameters for a FT2232H */ -#define VID 0x0403 -#define PID 0x6010 - -/* -------------------------------------------------------------------------- */ -/* --- PUBLIC FUNCTIONS DEFINITION ------------------------------------------ */ - -/* SPI initialization and configuration */ -int lgw_spi_open(void **spi_target_ptr) { - struct mpsse_context *mpsse = NULL; - - /* check input variables */ - CHECK_NULL(spi_target_ptr); /* cannot be null, must point on a void pointer (*spi_target_ptr can be null) */ - - /* try to open the first available FTDI device matching VID/PID parameters */ - mpsse = OpenIndex(VID,PID,SPI0, SIX_MHZ, MSB, IFACE_A, NULL, NULL, 0); - if (mpsse == NULL) { - DEBUG_MSG("ERROR: MPSSE OPEN FUNCTION RETURNED NULL\n"); - return LGW_SPI_ERROR; - } - if (mpsse->open != 1) { - DEBUG_MSG("ERROR: MPSSE OPEN FUNCTION FAILED\n"); - return LGW_SPI_ERROR; - } - - DEBUG_PRINTF("SPI port opened and configured ok\ndesc: %s\nPID: 0x%04X\nVID: 0x%04X\nclock: %d\nLibmpsse version: 0x%02X\n", GetDescription(mpsse), GetPid(mpsse), GetVid(mpsse), GetClock(mpsse), Version()); - *spi_target_ptr = (void *)mpsse; - return LGW_SPI_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* SPI release */ -int lgw_spi_close(void *spi_target) { - struct mpsse_context *mpsse = spi_target; - - /* check input variables */ - CHECK_NULL(spi_target); - - Close(mpsse); - - /* close return no status, assume success (0_o) */ - return LGW_SPI_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Simple write */ -/* transaction time: .6 to 1 ms typically */ -int lgw_spi_w(void *spi_target, uint8_t address, uint8_t data) { - struct mpsse_context *mpsse = spi_target; - uint8_t out_buf[2]; - int a, b, c; - - /* check input variables */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - - /* prepare frame to be sent */ - out_buf[0] = WRITE_ACCESS | (address & 0x7F); - out_buf[1] = data; - - /* MPSSE transaction */ - a = Start(mpsse); - b = FastWrite(mpsse, (char *)out_buf, 2); - c = Stop(mpsse); - - /* determine return code */ - if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK)) { - DEBUG_MSG("ERROR: SPI WRITE FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI write success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Simple read (using Transfer function) */ -/* transaction time: 1.1 to 2 ms typically */ -int lgw_spi_r(void *spi_target, uint8_t address, uint8_t *data) { - struct mpsse_context *mpsse = spi_target; - uint8_t out_buf[2]; - uint8_t *in_buf = NULL; - int a, b; - - /* check input variables */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - - /* prepare frame to be sent */ - out_buf[0] = READ_ACCESS | (address & 0x7F); - out_buf[1] = 0x00; - - /* MPSSE transaction */ - a = Start(mpsse); - in_buf = (uint8_t *)Transfer(mpsse, (char *)out_buf, 2); - b = Stop(mpsse); - - /* determine return code */ - if ((in_buf == NULL) || (a != MPSSE_OK) || (b != MPSSE_OK)) { - DEBUG_MSG("ERROR: SPI READ FAILURE\n"); - if (in_buf != NULL) { - free(in_buf); - } - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI read success\n"); - *data = in_buf[1]; - free(in_buf); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Burst (multiple-byte) write */ -/* transaction time: 3.7ms for 2500 data bytes @6MHz, 1kB chunks */ -/* transaction time: 0.5ms for 16 data bytes @6MHz, 1kB chunks */ -int lgw_spi_wb(void *spi_target, uint8_t address, uint8_t *data, uint16_t size) { - struct mpsse_context *mpsse = spi_target; - uint8_t command; - uint8_t *out_buf = NULL; - int size_to_do, buf_size, chunk_size, offset; - int a, b, c; - int i; - - /* check input parameters */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_SPI_ERROR; - } - - /* prepare command byte */ - command = WRITE_ACCESS | (address & 0x7F); - size_to_do = size + 1; /* add a byte for the address */ - - /* allocate data buffer */ - buf_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK; - out_buf = malloc(buf_size); - if (out_buf == NULL) { - DEBUG_MSG("ERROR: MALLOC FAIL\n"); - return LGW_SPI_ERROR; - } - - /* start MPSSE transaction */ - a = Start(mpsse); - for (i=0; size_to_do > 0; ++i) { - chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK; - if (i == 0) { - /* first chunk, need to append the address */ - out_buf[0] = command; - memcpy(out_buf+1, data, chunk_size-1); - } else { - /* following chunks, just copy the data */ - offset = (i * LGW_BURST_CHUNK) - 1; - memcpy(out_buf, data + offset, chunk_size); - } - b = FastWrite(mpsse, (char *)out_buf, chunk_size); - size_to_do -= chunk_size; /* subtract the quantity of data already transferred */ - } - c = Stop(mpsse); - - /* deallocate data buffer */ - free(out_buf); - - /* determine return code (only the last FastWrite is checked) */ - if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK)) { - DEBUG_MSG("ERROR: SPI BURST WRITE FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI burst write success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Burst (multiple-byte) read (using FastWrite & FastRead functions) */ -/* transaction time: 7-12ms for 2500 data bytes @6MHz, 1kB chunks */ -/* transaction time: 2ms for 16 data bytes @6MHz, 1kB chunks */ -int lgw_spi_rb(void *spi_target, uint8_t address, uint8_t *data, uint16_t size) { - struct mpsse_context *mpsse = spi_target; - uint8_t command; - int size_to_do, chunk_size, offset; - int a, b, c, d; - int i; - - /* check input parameters */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_SPI_ERROR; - } - - /* prepare command byte */ - command = READ_ACCESS | (address & 0x7F); - size_to_do = size; - - /* start MPSSE transaction */ - a = Start(mpsse); - b = FastWrite(mpsse, (char *)&command, 1); - for (i=0; size_to_do > 0; ++i) { - chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK; - offset = i * LGW_BURST_CHUNK; - c = FastRead(mpsse, (char *)(data + offset), chunk_size); - size_to_do -= chunk_size; /* subtract the quantity of data already transferred */ - } - d = Stop(mpsse); - - /* determine return code (only the last FastRead is checked) */ - if ((a != MPSSE_OK) || (b != MPSSE_OK) || (c != MPSSE_OK) || (d != MPSSE_OK)) { - DEBUG_MSG("ERROR: SPI BURST READ FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI burst read success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* --- EOF ------------------------------------------------------------------ */ diff --git a/loragw_hal/src/loragw_spi.native.c b/loragw_hal/src/loragw_spi.native.c deleted file mode 100644 index f5f0701..0000000 --- a/loragw_hal/src/loragw_spi.native.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - / _____) _ | | -( (____ _____ ____ _| |_ _____ ____| |__ - \____ \| ___ | (_ _) ___ |/ ___) _ \ - _____) ) ____| | | || |_| ____( (___| | | | -(______/|_____)_|_|_| \__)_____)\____)_| |_| - ©2013 Semtech-Cycleo - -Description: - Host specific functions to address the LoRa™ gateway registers through a - SPI interface. - Single-byte read/write and burst read/write. - Does not handle pagination. - Could be used with multiple SPI ports in parallel (explicit file descriptor) -*/ - - -/* -------------------------------------------------------------------------- */ -/* --- DEPENDANCIES --------------------------------------------------------- */ - -#include <stdint.h> /* C99 types */ -#include <stdio.h> /* printf fprintf */ -#include <stdlib.h> /* malloc free */ -#include <unistd.h> /* lseek, close */ -#include <fcntl.h> /* open */ -#include <string.h> /* memset */ - -#include <sys/ioctl.h> -#include <linux/spi/spidev.h> - -#include "loragw_spi.h" - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE MACROS ------------------------------------------------------- */ - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#if DEBUG_SPI == 1 - #define DEBUG_MSG(str) fprintf(stderr, str) - #define DEBUG_PRINTF(fmt, args...) fprintf(stderr,"%s:%d: "fmt, __FUNCTION__, __LINE__, args) - #define CHECK_NULL(a) if(a==NULL){fprintf(stderr,"%s:%d: ERROR: NULL POINTER AS ARGUMENT\n", __FUNCTION__, __LINE__);return LGW_SPI_ERROR;} -#else - #define DEBUG_MSG(str) - #define DEBUG_PRINTF(fmt, args...) - #define CHECK_NULL(a) if(a==NULL){return LGW_SPI_ERROR;} -#endif - -/* -------------------------------------------------------------------------- */ -/* --- PRIVATE CONSTANTS ---------------------------------------------------- */ - -#define READ_ACCESS 0x00 -#define WRITE_ACCESS 0x80 -#define SPI_SPEED 8000000 -#define SPI_DEV_PATH "/dev/spidev0.0" - -/* -------------------------------------------------------------------------- */ -/* --- PUBLIC FUNCTIONS DEFINITION ------------------------------------------ */ - -/* SPI initialization and configuration */ -int lgw_spi_open(void **spi_target_ptr) { - int *spi_device = NULL; - int dev; - int a,b,c; - int i; - - /* check input variables */ - CHECK_NULL(spi_target_ptr); /* cannot be null, must point on a void pointer (*spi_target_ptr can be null) */ - - /* allocate memory for the device descriptor */ - spi_device = malloc(sizeof(int)); - if (spi_device == NULL) { - DEBUG_MSG("ERROR: MALLOC FAIL\n"); - return LGW_SPI_ERROR; - } - - /* open SPI device */ - dev = open(SPI_DEV_PATH, O_RDWR); - if (dev < 0) { - DEBUG_MSG("SPI port fail to open\n"); - return LGW_SPI_ERROR; - } - - /* setting SPI mode to 'mode 0' */ - i = SPI_MODE_0; - a = ioctl(dev, SPI_IOC_WR_MODE, &i); - b = ioctl(dev, SPI_IOC_RD_MODE, &i); - if ((a < 0) || (b < 0)) { - DEBUG_MSG("ERROR: SPI PORT FAIL TO SET IN MODE 0\n"); - close(dev); - free(spi_device); - return LGW_SPI_ERROR; - } - - /* setting SPI max clk (in Hz) */ - i = SPI_SPEED; - a = ioctl(dev, SPI_IOC_WR_MAX_SPEED_HZ, &i); - b = ioctl(dev, SPI_IOC_RD_MAX_SPEED_HZ, &i); - if ((a < 0) || (b < 0)) { - DEBUG_MSG("ERROR: SPI PORT FAIL TO SET MAX SPEED\n"); - close(dev); - free(spi_device); - return LGW_SPI_ERROR; - } - - /* setting SPI to MSB first */ - i = 0; - a = ioctl(dev, SPI_IOC_WR_LSB_FIRST, &i); - b = ioctl(dev, SPI_IOC_RD_LSB_FIRST, &i); - if ((a < 0) || (b < 0)) { - DEBUG_MSG("ERROR: SPI PORT FAIL TO SET MSB FIRST\n"); - close(dev); - free(spi_device); - return LGW_SPI_ERROR; - } - - /* setting SPI to 8 bits per word */ - i = 0; - a = ioctl(dev, SPI_IOC_WR_BITS_PER_WORD, &i); - b = ioctl(dev, SPI_IOC_RD_BITS_PER_WORD, &i); - if ((a < 0) || (b < 0)) { - DEBUG_MSG("ERROR: SPI PORT FAIL TO SET 8 BITS-PER-WORD\n"); - close(dev); - return LGW_SPI_ERROR; - } - - *spi_device = dev; - *spi_target_ptr = (void *)spi_device; - DEBUG_MSG("Note: SPI port opened and configured ok\n"); - return LGW_SPI_SUCCESS; -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* SPI release */ -int lgw_spi_close(void *spi_target) { - int spi_device; - int a; - - /* check input variables */ - CHECK_NULL(spi_target); - - /* close file & deallocate file descriptor */ - spi_device = *(int *)spi_target; /* must check that spi_target is not null beforehand */ - a = close(spi_device); - free(spi_target); - - /* determine return code */ - if (a < 0) { - DEBUG_MSG("ERROR: SPI PORT FAILED TO CLOSE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI port closed\n"); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Simple write */ -int lgw_spi_w(void *spi_target, uint8_t address, uint8_t data) { - int spi_device; - uint8_t out_buf[2]; - struct spi_ioc_transfer k; - int a; - - /* check input variables */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - - spi_device = *(int *)spi_target; /* must check that spi_target is not null beforehand */ - - /* prepare frame to be sent */ - out_buf[0] = WRITE_ACCESS | (address & 0x7F); - out_buf[1] = data; - - /* I/O transaction */ - memset(&k, 0, sizeof(k)); /* clear k */ - k.tx_buf = (unsigned long) out_buf; - k.len = ARRAY_SIZE(out_buf); - k.speed_hz = SPI_SPEED; - k.cs_change = 1; - k.bits_per_word = 8; - a = ioctl(spi_device, SPI_IOC_MESSAGE(1), &k); - - /* determine return code */ - if (a != 2) { - DEBUG_MSG("ERROR: SPI WRITE FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI write success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Simple read */ -int lgw_spi_r(void *spi_target, uint8_t address, uint8_t *data) { - int spi_device; - uint8_t out_buf[2]; - uint8_t in_buf[ARRAY_SIZE(out_buf)]; - struct spi_ioc_transfer k; - int a; - - /* check input variables */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - - spi_device = *(int *)spi_target; /* must check that spi_target is not null beforehand */ - - /* prepare frame to be sent */ - out_buf[0] = READ_ACCESS | (address & 0x7F); - out_buf[1] = 0x00; - - /* I/O transaction */ - memset(&k, 0, sizeof(k)); /* clear k */ - k.tx_buf = (unsigned long) out_buf; - k.rx_buf = (unsigned long) in_buf; - k.len = ARRAY_SIZE(out_buf); - k.cs_change = 1; - a = ioctl(spi_device, SPI_IOC_MESSAGE(1), &k); - - /* determine return code */ - if (a != 2) { - DEBUG_MSG("ERROR: SPI READ FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI read success\n"); - *data = in_buf[1]; - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Burst (multiple-byte) write */ -int lgw_spi_wb(void *spi_target, uint8_t address, uint8_t *data, uint16_t size) { - int spi_device; - uint8_t command; - struct spi_ioc_transfer k[2]; - int size_to_do, chunk_size, offset; - int byte_transfered = 0; - int i; - - /* check input parameters */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_SPI_ERROR; - } - - spi_device = *(int *)spi_target; /* must check that spi_target is not null beforehand */ - - /* prepare command byte */ - command = WRITE_ACCESS | (address & 0x7F); - size_to_do = size; - - /* I/O transaction */ - memset(&k, 0, sizeof(k)); /* clear k */ - k[0].tx_buf = (unsigned long) &command; - k[0].len = 1; - k[0].cs_change = 0; - k[1].cs_change = 1; - for (i=0; size_to_do > 0; ++i) { - chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK; - offset = i * LGW_BURST_CHUNK; - k[1].tx_buf = (unsigned long)(data + offset); - k[1].len = chunk_size; - byte_transfered += (ioctl(spi_device, SPI_IOC_MESSAGE(2), &k) - 1 ); - DEBUG_PRINTF("BURST WRITE: to trans %d # chunk %d # transferred %d \n", size_to_do, chunk_size, byte_transfered); - size_to_do -= chunk_size; /* subtract the quantity of data already transferred */ - } - - /* determine return code */ - if (byte_transfered != size) { - DEBUG_MSG("ERROR: SPI BURST WRITE FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI burst write success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ - -/* Burst (multiple-byte) read */ -int lgw_spi_rb(void *spi_target, uint8_t address, uint8_t *data, uint16_t size) { - int spi_device; - uint8_t command; - struct spi_ioc_transfer k[2]; - int size_to_do, chunk_size, offset; - int byte_transfered = 0; - int i; - - /* check input parameters */ - CHECK_NULL(spi_target); - if ((address & 0x80) != 0) { - DEBUG_MSG("WARNING: SPI address > 127\n"); - } - CHECK_NULL(data); - if (size == 0) { - DEBUG_MSG("ERROR: BURST OF NULL LENGTH\n"); - return LGW_SPI_ERROR; - } - - spi_device = *(int *)spi_target; /* must check that spi_target is not null beforehand */ - - /* prepare command byte */ - command = READ_ACCESS | (address & 0x7F); - size_to_do = size; - - /* I/O transaction */ - memset(&k, 0, sizeof(k)); /* clear k */ - k[0].tx_buf = (unsigned long) &command; - k[0].len = 1; - k[0].cs_change = 0; - k[1].cs_change = 1; - for (i=0; size_to_do > 0; ++i) { - chunk_size = (size_to_do < LGW_BURST_CHUNK) ? size_to_do : LGW_BURST_CHUNK; - offset = i * LGW_BURST_CHUNK; - k[1].rx_buf = (unsigned long)(data + offset); - k[1].len = chunk_size; - byte_transfered += (ioctl(spi_device, SPI_IOC_MESSAGE(2), &k) - 1 ); - DEBUG_PRINTF("BURST READ: to trans %d # chunk %d # transferred %d \n", size_to_do, chunk_size, byte_transfered); - size_to_do -= chunk_size; /* subtract the quantity of data already transferred */ - } - - /* determine return code */ - if (byte_transfered != size) { - DEBUG_MSG("ERROR: SPI BURST READ FAILURE\n"); - return LGW_SPI_ERROR; - } else { - DEBUG_MSG("Note: SPI burst read success\n"); - return LGW_SPI_SUCCESS; - } -} - -/* --- EOF ------------------------------------------------------------------ */ |