ORCA
6
15
2
2
5
Timeout
5000
Time in msec to wait for the event
Number HCI commands
any
Number of additional HCI Command Packets to be sent to the Host Controller from the host
Command Opcode
Layer
0x04
Event Opcode
0xFF
Length
Opcode
Ignore
Opcode
Payload
F4 Payload
FTD Ignore
FTD Header
Payload
Opcode2
Payload
Layer
0x04
Event Opcode
Length
Payload
Layer
0x01
Event Opcode
Length
Payload
Layer
0x02
Handle
Length
Payload
Layer
Layer
Layer
0xF0
DOT Debug Opcode
Length
Payload
Layer
0xF0
DOT Debug Opcode
Length
Payload
Layer
0xF1
DOT Status Opcode
Length
Payload
Layer
0x06
Length
Payload
Layer
0x07
Length
Payload
Layer
0x08
Length
Status
0x00
Status
Num_FM_HCI_Commands
any
FM Opcode
0x00
Command Type
0x00
Data Length
0x02
Data Parameters
0x00
Layer
0x09
opcode
Length
Payload
Layer
0x52
opcode
ConnectionId
Data
Success
Unknown HCI Command
Unknown Connection Identifier
Hardware Failure
Page Timeout
Authentication Failure
PIN Missing
Memory Capacity Exceeded
Connection Timeout
Connection Limit Exceeded
Synchronous Connection Limit To A Device Exceeded
ACL Connection Already Exists
Command Disallowed
Connection Rejected due to Limited Resources
Connection Rejected Due To Security Reasons
Connection Rejected due to Unacceptable BD_ADDR
Connection Accept Timeout Exceeded
Unsupported Feature or Parameter Value
Invalid HCI Command Parameters
Remote User Terminated Connection
Remote Device Terminated Connection due to Low Resources
Remote Device Terminated Connection due to Power Off
Connection Terminated By Local Host
Repeated Attempts
Pairing Not Allowed
Unknown LMP PDU
Unsupported Remote Feature
SCO Offset Rejected
SCO Interval Rejected
SCO Air Mode Rejected
Invalid LMP Parameters
Unspecified Error
Unsupported LMP Parameter Value
Role Change Not Allowed
LMP Response Timeout
LMP Error Transaction Collision
LMP PDU Not Allowed
Encryption Mode Not Acceptable
Link Key Can Not be Changed
Requested QoS Not Supported
Instant Passed
Pairing With Unit Key Not Supported
Different Transaction Collision
Reserved
QoS Unacceptable Parameter
QoS Rejected
Channel Classification Not Supported
Insufficient Security
Parameter Out Of Mandatory Range
Reserved
Role Switch Pending
Reserved
Reserved Slot Violation
Role Switch Failed
Controller Busy
Unacceptable Connection Interval
Directed Advertisement Timeout
Connection Terminated Due To MIC Failure
Connection Failed To Be Established
Test Mux 1
Test Mux 2
Test Mux 3
Test Mux 4
Test Mux 5
DBG 1
DBG 2
DBG 3
DBG 4
DBG 5
DBG 6
DBG 7
DBG 8
DBG 9
DBG 10
DRP - Run also DRP_MUX
WIBREE - Run also Wibree_MUX
Resereved
DMA
OCP_IC
UART
I2C - Not Supported
BT
Don't Change
vra1_write_txd_cmd
vra21_tx_fifo_rd_req
vra21_rx_fifo_wr_req
vra1_read_rxd_cmd
vra1_irq_source(0)
qra20_halt
qra20_rx_flow_ctrl_state
vre0_byte_en
vra1_tx_rxn
vra1_espi_int_pending
ca21_baud_clk --> dbg (10)
vre0_bit_count(18:10) --> dbg (9:1)
vre0_bit_count(9:0) --> dbg (10:1)
vre0_tx_state(3:0)--> dbg (4:1)
vre0_rx_state(3:0)--> dbg (8:5)
qra1_rx_data_reg(7:0) --> dbg (8:1)
qra1_tx_state(2:0) --> dbg (3:1)
qra1_rx_state(2:0) --> dbg (6:4)
vra1_dfc_api_req
vra1_dfc_l3_req
vra1_bt_gocpu_drp_req
vra1_bt_gocpu_l3_req
vra1_pcmi_l3_req
vra1_pcmi_api_req
vra1_dma1_drp_req
vra1_dma1_api_req
vra1_dma1_sdio_req
vra1_dma1_uart_req
vra1_dma1_l3_req
vra1_dma0_drp_req
vra1_dma0_api_req
vra1_dma0_sdio_req
vra1_dma0_uart_req
vra1_dma0_l3_req
vra1_arm_drp_req
vra1_arm_api_req
vra1_arm_sdio_req
vra1_arm_uart_req
vra1_arm_l3_req
vra1_wibree_api_req
vra1_wibree_l3_req
vra1_api_mcmd(0)
vra1_drp_mcmd(0)
vra1_l3_bridge_mcmd(0)
vra1_sdio_mcmd_i(0)
vra1_uart_mcmd_i(0)
vra1_wibree_mcmd_i(0)
vra1_drp_scmdaccept(0)
vra1_l3_bridge_scmdaccept
vra1_sdio_scmdaccept_i
vra1_uart_scmdaccept_i
vra1_wibree_scmdaccept_i
vra1_arm_serror_i
vra1_pcmi_serror_i
vra1_bt_gocpu_serror_i
bt_dfc_serror
vra1_dma1_serror
vra1_dma0_serror
vra1_wibree_serror
vra1_sinterrupts(0)
vra1_sinterrupts(1)
vra1_sinterrupts(2)
vra1_sinterrupts(3)
vra1_sinterrupts(4)
vra1_sinterrupts(5)
vra1_sinterrupts(6)
vra1_sinterrupts(7)
vra1_sinterrupts(8)
vra1_sinterrupts(9)
vra1_sinterrupts(10)
vra1_sinterrupts(11)
vra1_sinterrupts(12)
vra1_sinterrupts(13)
vra1_sinterrupts(14)
vra1_sinterrupts(15)
vra1_l3_cs(0)--> dbg 0
vra1_l3_cs(1)--> dbg 1
vra1_l3_cs(2)--> dbg 2
vra1_l3_cs(3)--> dbg 3
vra1_l3_cs(0)--> dbg 4
vra1_l3_cs(1)--> dbg 5
vra1_l3_cs(2)--> dbg 6
vra1_l3_cs(3)--> dbg 7
SCE1 state (bit 0/1) *
SCE2 state (bit 0/1) *
Ch1 arbiter state (bit 0/1) *
Ch2 arbiter state (bit 0/1) *
SDMARequest ch1(0)
SDMARequest ch1(1)
SDMARequest ch2(0)
SDMARequest ch2(1)
SCE1 FIFO empty
SCE2 FIFO empty
end-of-transfer ch1
end-of-transfer ch2
end-of-script ch1
end-of-script ch2
bt_sdio_phy_direction--> dbg 1
bt_sdio_block_start--> dbg 2
bt_sdio_phy_direction--> dbg 3
bt_sdio_phy_block_crc_err--> dbg 4
vra1_dma_flow_rd--> dbg 5
vra1_l2_rxfifo_rd_en--> dbg 6
vra2_phy_rxfifo_wr_en--> dbg 7
qra2_start_tx_sync--> dbg 8
bt_sdio_phy_direction--> dbg 9
bt_sdio_phy_direction--> dbg 10
vra2_ack--> dbg 1
vra2_nack--> dbg 2
vra2_write_retry--> dbg 3
bt_sdio_phy_card_reset--> dbg 4
bt_sdio_phy_interrupt--> dbg 5
vra2_phy_txfifo_rd_en--> dbg 6
vra1_l2_txfifo_wr_en--> dbg 7
vra1_dma_flow_wr--> dbg 8
vra2_ack--> dbg 9
vra2_ack--> dbg 10
bt_sdio_phy_set_busy--> dbg 1
bt_sdio_block_crc_err--> dbg 1
qra_txfifo_busy--> dbg 1
qra2_txfifo_busy_sync--> dbg 1
qra2_crc_busy--> dbg 1
bt_sdio_phy_direction--> dbg 1
vra2_phy_txfifo_rd_en--> dbg 1
vra1_l2_txfifo_wr_en--> dbg 1
bt_sdio_phy_set_busy--> dbg 1
bt_sdio_phy_set_busy--> dbg 1
qra2_txfifo_busy--> dbg 1
qra2_rxfifo_busy_sync--> dbg 2
bt_sdio_phy_set_busy--> dbg 3
vra2_ack--> dbg 4
vra2_nack--> dbg 5
vra2_write_retry--> dbg 6
bt_sdio_phy_block_start--> dbg 7
bt_sdio_phy_block_crc_err--> dbg 8
qra2_txfifo_busy--> dbg 9
qra2_txfifo_busy--> dbg 10
ca1_ocp_gated_clk--> dbg 1
vra1_dma_flow_wr--> dbg 2
vra1_dma_flow_rd--> dbg 3
vra1_l2_rxfifo_rd_en--> dbg 4
vra2_phy_rxfifo_wr_en--> dbg 5
qra2_start_tx_sync--> dbg 6
qra2_start_tx_clr--> dbg 7
vra2_phy_if_error--> dbg 8
ca1_ocp_gated_clk--> dbg 9
ca1_ocp_gated_clk--> dbg 10
bt_sdio_phy_mcmd[0]--> dbg 1
bt_sdio_phy_mcmd[1]--> dbg 2
bt_sdio_phy_mcmd[0]--> dbg 3
bt_sdio_phy_mcmd[0]--> dbg 4
bt_sdio_phy_sresp[0]--> dbg 5
bt_sdio_phy_sresp[1]--> dbg 6
bt_sdio_phy_sdata[0]--> dbg 7
bt_sdio_phy_sdata[1]--> dbg 8
bt_sdio_phy_mcmd[0]--> dbg 9
bt_sdio_phy_mcmd[0]--> dbg 10
vra1_wr_ptr_bin_ocp[0]--> dbg 1
vra1_wr_ptr_bin_ocp[1]--> dbg 2
vra1_wr_ptr_bin_ocp[2]--> dbg 3
vra1_wr_ptr_bin_ocp[3]--> dbg 4
qra1_wr_ptr_wrap--> dbg 5
qra1_rd_ptr_bin[0]--> dbg 6
qra1_rd_ptr_bin[1]--> dbg 7
qra1_rd_ptr_bin[2]--> dbg 8
qra1_rd_ptr_bin[3]--> dbg 9
qra1_rd_ptr_wrap--> dbg 10
qra1_wr_ptr_bin_ocp[0]--> dbg 1
qra1_wr_ptr_bin_ocp[1]--> dbg 2
qra1_wr_ptr_bin_ocp[2]--> dbg 3
qra1_wr_ptr_bin_ocp[3]--> dbg 4
qra1_wr_ptr_bin_ocp[9]--> dbg 5
vra1_rd_ptr_bin_ocp[0]--> dbg 6
vra1_rd_ptr_bin_ocp[1]--> dbg 7
vra1_rd_ptr_bin_ocp[2]--> dbg 8
vra1_rd_ptr_bin_ocp[3]--> dbg 9
vra1_rd_ptr_bin_ocp[9]--> dbg 10
pll clock signal to design
pll input clock signal from GCM
pll lock signal
pll sync signal
pll power down command (active low)
fast frequency input
system slow clock
system root clock after retiming in DRP
ocp clock
arm clock
uart clock
1MHz bt clock
4MHz bt clock
8MHz bt clock
external memory interface clock
codec clock
sdio clock
spi clock
powerup reset
watchdog timer reset
watch timer interrupt
fast clock enable indication from fcgen to fdc
slow wakeup event from wakeup unit
fast wakeup event from wakeup unit
usec timer event
slow domain control state machine (bus only 0:3), fast domain control state machine (bus only 4:7)
slow domain scripter control bus (bus only 0:3 or 4:7)
codec_get [0]
codec_get [1]
codec_take [0]
codec_take [1]
codec_fsync [0]
codec_fsync [1]
buffer_full [0]
buffer_full [1]
wrap_around_cond [0]
wrap_around_cond [1]
go_packet_loss [0]
go_packet_loss [1]
codec_get_toggle [0]
codec_get_toggle [1]
tx_ch_sel
motorola_mode_duplication [0]
motorola_mode_duplication [1]
motorola_mode_noise [0]
motorola_mode_noise [1]
chx_rx_api_almost_full [0]
chx_rx_api_almost_full [1]
chx_rx_api_full [0]
chx_rx_api_full [1]
codec_take_toggle [0]
codec_take_toggle [1]
rx_ch_sel
motorola_state_ch0 (0..1;2..3; 4..5; 6..7; 8..9)
motorola_state_ch1 (0..1;2..3; 4..5; 6..7; 8..9)
eplc_n_cnt_ch0 (0..4; 5..9)
eplc_r_cnt_ch0 (0..4; 5..9)
eplc_n_cnt_ch1 (0..4; 5..9)
eplc_r_cnt_ch1 (0..4; 5..9)
tx_state (0..3; 4..7)
tx_mn_state (0..3; 4..7)
a_tx_state_ch0 (0..2; 3..5; 6..8)
a_tx_state_ch1 (0..2; 3..5; 6..8)
tx_a_fifo_len_ch0 (0..3; 4..7)
tx_a_fifo_len_ch1 (0..3; 4..7)
rx_state (0..3; 4..7)
rx_mn_state (0..3; 4..7)
a_rx_state_ch0 (0..2; 3..5; 6..8)
a_rx_state_ch1 (0..2; 3..5; 6..8)
rx_a_fifo_len_ch0 (0..3; 4..7)
rx_a_fifo_len_ch1 (0..3; 4..7)
state (0..2; 3..5; 6..8)
dout_state (0..1;2..3; 4..5; 6..7; 8..9)
dout_state1_ch0 (0..1;2..3; 4..5; 6..7; 8..9)
dout_state1_ch1 (0..1;2..3; 4..5; 6..7; 8..9)
din_state (0..1;2..3; 4..5; 6..7; 8..9)
din_mux_sel_ch0 (0..4; 5..9)
din_mux_sel_ch1 (0..4; 5..9)
dout_mux_sel_ch0 (0..4; 5..9)
dout_mux_sel_ch1 (0..4; 5..9)
frame_timer (9..0)
frame_timer(15..10)
Vf1_LBT[2]
Vf1_LBT[3]
Vf1_NBT1[2]
Vf1_NBT1[3]
Vf1_NBT2[2]
Vf1_NBT2[3]
C51_network1_clk_cts
C52_network2_clk_cts
C6_local_clk_cts
Vf1_switched_BTC[2]
Vf1_switched_BTC[3]
Vf1_switched_scheduler_BTC[2]
Sr1_lcl_packet_timer[10]
Sr1_net1_packet_timer[10]
Sr1_net2_packet_timer[10]
Sr1_switched_packet_timer[10]
Scheduler_switched_packet_timer[10]
Vr1_SCO_ch1_window
Vr1_SCO_ch2_window
Vr1_SCO_ch1_instant
Vr1_SCO_ch2_instant
Vr1_SCO_ch_select
Vr1_SCO_ch1_active
Vr1_SCO_ch2_active
Vr1_SCO_req
Vr1_SCO_go
Vr1_SCO_block
Vr1_scheduler_req
Vr1_scheduler_go
Vr1_scheduler_block
Vr1_periodic_req
Vr1_periodic_go
Vr1_periodic_block
Vr1_sco_tx_enable
Vr1_ACL_tx_enable
NIRQ1
NIRQ2
NIRQ3
NIRQ4
Vr1_scheduler_empty
Vr1_scheduler_stalled
Vr1_scheduler_almost_empty
Vr1_mode_reg_jump
Vr10_scheduler_flush_command
scheduler_continue_program
scheduler_program_started
Vr1_correlation_win
Vr1_sync_event
OCP clk
ca11_bt_ctl_clk
ca12_bt_dt_clk
cs1_bt_slow_clk
L_Status
N1_Status
N2_Status
Main_clk_Status
Vr1_Slave_nMaster
Vr1_N2_Select
L_Load_event
N1_Load_ event
N2_Load_ event
AFH_selector[0]
AFH_selector[1]
AFH_enabled
AFH_recovery
Vr1_HEC_event
Vr1_HEC_ok
Vr1_CRC_event
Vr1_CRC_ok
Vr1_length_event
Vr1_bad_length
Vr1_rx_stop
Vr1_tx_strech
Vr1_rx_strech
Vr1_rx_time_out
BB_TX_Data @ 3M
BB_RX_Data @ 3M
BB_TX_RX_Data @ 3M
RX_nTX_wire (MU1_control)
Tx_payload_br[0]
Tx_payload_br[1]
Rx_payload_br[0]
Rx_payload_br[1]
EDR_sync
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
Per Debug
vra11_sco_chid(ESCO1_WINDOW) - Orca
vra11_sco_chid(ESCO2_WINDOW) - Orca
vra11_sco_chid(INSTANT1) - Orca
vra11_sco_chid(INSTANT2) - Orca
vra11_sco_chid(CH_SELECT) - Orca
vra11_sco_chid(CH1_ACTIVE) - Orca
vra11_sco_chid(CH2_ACTIVE) - Orca
vra11_sco_req - Orca
vra11_sco_go - Orca
vra11_sco_block - Orca
vra11_scheduler_req - Orca
vra11_scheduler_go - Orca
vra11_scheduler_block - Orca
vra11_sco_tx_en - Orca
vra11_acl_tx_en - Orca
qra11_dc2dc_mode - Orca
vra11_nirq1 - Orca
vra11_nirq3 - Orca
vra11_nirq4 - Orca
vra11_scheduler_empty - Orca
vra11_scheduler_stalled - Orca
vra11_scheduler_almost_empty - Orca
vra11_mode_register_jump_event - Orca
vra11_scheduler_flush_cmd - Orca
vra11_scheduler_continue_pgm - Orca
vra11_program_started_dbg - Orca
vra11_scheduler_fetch_done - Orca
qra11_correlation_window - Orca
ca1_ocp_clk - Orca
ca11_bt_ctl_clk - Orca
ca12_bt_dt_clk - Orca
vra11_static_control(SLAVE_NMASTER) - Orca
vra11_static_control(N2_SELECT) - Orca
vra11_decoded_afh_sel[0] - Orca
vra11_decoded_afh_sel[1] - Orca
vra11_decoded_afh_en - Orca
vra11_decoded_recovery_en - Orca
vra11_HEC_event - Orca
vra11_HEC_ok - Orca
vra11_CRC_event - Orca
vra11_CRC_ok - Orca
vra11_length_event - Orca
vra11_bad_length - Orca
vra11_rx_stop - Orca
vra11_tx_strech - Orca
vra11_rx_strech - Orca
vra1_rx_acl_almost_empty_intr - Orca
OR Fifo hflush - Orca
OR Fifo sflush - Orca
vra12_bb_txd_dbg - Orca
qra11_rx_ntx_wire - Orca
qra11_packet_br[0] (TX) - Orca
qra11_packet_br[1] (TX) - Orca
vra11_packet_br[0] (RX) - Orca
vra11_packet_br[1] (RX) - Orca
vra11_gfsk_sync - Orca
vra11_edr_sync - Orca
vra12_bb_rxd_dbg - Orca
tx_rx_data_post_sync - Orca
tx_data_toggle - Orca
phy_data_toggle (RX data) - Orca
BGA
WSP
All
Master
Slave
Rising Edge
Falling Edge
STEREO_GET
RSSI_LVL_GET
IF_COUNT_GET
FLAG_GET
RDS_SYNC_GET
RDS_DATA_GET
LOCK_GET
FREQ_SET_GET
AF_FREQ_SET_GET
MOST_MODE_SET_GET
MOST_BLEND_SET_GET
DEMPH_MODE_SET_GET
SEARCH_LVL_SET_GET
BAND_SET_GET
MUTE_STATUS_SET_GET
RDS_PAUSE_LVL_SET_GET
RDS_PAUSE_DUR_SET_GET
RDS_MEM_SET_GET
RDS_BLK_B_SET_GET
RDS_MSK_B_SET_GET
RDS_PI_MASK_SET_GET
RDS_PI_SET_GET
RDS_SYSTEM_SET_GET
INT_MASK_SET_GET
SEARCH_DIR_SET_GET
VOLUME_SET_GET
AUDIO_ENABLE_SET_GET
I2S_CLOCK_CONFIG_SET_GET
I2S_MODE_CONFIG_SET_GET
POWER_SET_GET
INTX_CONFIG_SET_GET
PULL_EN_SET_GET
HILO_SET_GET
SWITCH2FREF
FREQ_DRIFT_REPORT
PCE_GET
FIRM_VER_GET
ASIC_VER_GET
ASIC_ID_GET
MAN_ID_GET
TUNER_MODE_SET
STOP_SEARCH
CHANL_SET
CHANL_BW_SET
REF_SET
POWER_ATT_SET
POWER_LEV_SET
AUDIO_DEV_SET
PILOT_DEV_SET
RDS_DEV_SET
AUDIO_IO_SET
PREMPH_SET
BAND_SET
MONO_SET
MPX_LMT_SET
PI_SET
TYPE_SET
PTY
AF
DISPLAY_SIZE
RDS_MODE
DISPLAY_MODE
LENGTH
TOGGLE_AB
RDS_REP_SET
TA_SET
TP_SET
DI_SET
MS_SET
PS_SCROLL_SPEED
POWER_ENB_SET
PUPD_SET
MUTE
REF_ERR_SET
RDS_DATA_ENB
RDS_DATA_SET !!! Experimental !!!
HW_REGISTER_SET
CODE_DOWNLOAD
RESET
FM_POWER_MODE (Relevant only on Channel 8)
HCILL
PALAU
PALAU Six Wire
BORNEO Six Wite Active High
BORNEO Six Wite Active Low
H5 (you can either choose 0xFF for H5 deep sleep)
SPI (Both eSPI and BT_SPI)
Reserved
Reserved
UART Break Indication protocol
SBIS (SlimBus In-band Sleep protocol)
SLIMbus Out Of Band
Don't Change
BT_FUNC1
BT_FUNC2
BT_FUNC3
BT_FUNC4
BT_FUNC5
BT_FUNC6
BT_FUNC7
0xFF - Dont Change
BT_FUNC1
BT_FUNC2
BT_FUNC3
BT_FUNC1
BT_FUNC2
BT_FUNC3
BT_FUNC4
BT_FUNC5
BT_FUNC7
Disable Pull
Enable Pull
Pull Down
Pull up
Output is Tri-state
Output enabled
Wired OR (Clk_Req=L, output is Z;Clk_Req=H, output is enabled)
Disable
Enable
No change
Disable pull
Enable pull
Default pull
No change
Network 1
Network 2
Auto Recovery Stopped because of SLOW TO expiration
Auto Recovery Succeeded
Auto Recovery is in the Fast Recovery State
Auto Recovery is in the Slow Recovery State
Recovery Page is being scheduled
Recovery Scan is being scheduled
always override rwin with acl
use the poll override theshold to override rwin
Power Level 0
Power Level 1
Power Level 2
Power Level 3
Power Level 4
Power Level 5
Power Level 6
Power Level 7
Power Level 8
Power Level 9
Power Level 10
Power Level 11
Power Level 12
Power Level 13
Power Level 14
Power Level 15
DM1
DH1
DM3
DH3
DM5
DH5
2-DH1
2-DH3
2-DH5
3-DH1
3-DH3
3-DH5
All 0
All 1
ZOZO
F0F0
Ordered
PRBS9 Random
Off
DAC
PWM
Digital
Don't change
Only if temp changes
Override temp changes
GFSK
EDR 2MB
EDR 3MB
CW
GFSK
2-EDR
3-EDR
BLE
PN9
PN15
ZOZO
All 1
All 0
F0F0
FF00
User Defined
Hopping
Single freq
Enable
Disable
Enable
Disable
Don't Force
Force
0
1
2
3
4
5
6
7
Dont Change
2 mAmp
4 mAmp
6 mAmp
8 mAmp
DM1
DH1
DM3
DH3
DM5
DH5
2-DH1
2-DH3
2-DH5
3-DH1
3-DH3
3-DH5
R0
R1
R2
Authentication Failure
Remote User Terminated Connection
Remote Device Terminated Connection due to Power Off
Unsupported Remote Feature
Pairing With Unit Key Not Supported
Connection Rejected due to Limited Resources
Connection Rejected Due To Security Reasons
Connection Rejected due to Unacceptable BD_ADDR
Off
On
On
Off
Use semi-permanent Link Keys
Use Temporary Link Key
No retransmissions
At least one retransmission, optimize for power consumption
At least one retransmission, optimize for link quality
Don't care
Display only
DisplayYesNo
KeyboardOnly
NoInputNoOutput
OOB authentication data not present
OOB authentication data from remote device present
MITM Protection Not Required – Single Profile. Numeric comparison with automatic accept allowed
MITM Protection Required – Single Profile. Use IO Capabilities to determine authentication procedure
MITM Protection Not Required – All Profiles. Numeric comparison with automatic accept allowed
MITM Protection Required – All Profiles. Use IO Capabilities to determine authentication procedure
Passkey entry started
Passkey digit entered
Passkey digit erased
Passkey cleared
Passkey entry completed
No Traffic
Best Effort
Guaranteed
Outgoing Flow
Incoming Flow
Clear All Filters
Inquiry Result
Connection Setup
All Devices
Specific Class Of Device
Specific BD Address
Do NOT auto accept
Accept with role switch disabled
Accept with role switch enabled
Variable
Fixed
Link Key specified by BD_ADDR
All stored Link Keys
No Scans
Inquiry Scan
Page Scan
Page and Inquiry Scan
Disable
Enable
Maintain current Power State
Suspend Page Scan
Suspend Inquiry Scan
Suspend Periodic Inquiries
Read Current Transmit Power Level
Read Maximum Transmit Power Level
Flow Control Off
Flow Control On for ACL
Flow Control On for SCO
Flow Control On for both ACL and SCO
P0
P1
P2
Mandatory
Optional 1
Optional 2
Optional 3
Mandatory: Standard Scan
Optional: Interlaced Scan
Standard
With RSSI
Inquiry Result with RSSI or Extended Inquiry Result Format
Not Aware of Alphanumeric PIN codes support
Cannot support Alphanumeric PIN codes
Support Alphanumeric PIN codes
Undefined
Simple Pairing enabled
The Packet_Status_Flag shall be set to 0 for new (e)SCO connections (Default)
For new (e)SCO connections, the Packet_Status_Flag will be set
Bluetooth HCI Specification 1.0B
Bluetooth HCI Specification 1.1
Bluetooth HCI Specification 1.2
Bluetooth HCI Specification 2.0
Bluetooth HCI Specification 2.1
Bluetooth HCI Specification 3.0
Bluetooth HCI Specification 4.0
Bluetooth Core Specification 1.0B
Bluetooth Core Specification 1.1
Bluetooth Core Specification 1.2
Bluetooth Core Specification 2.0
Bluetooth Core Specification 2.1
Bluetooth Core Specification 3.0
Bluetooth Core Specification 4.0
Ericsson Technology Licensing
Nokia Mobile Phones
Intel Corp.
IBM Corp.
Toshiba Corp.
3Com
Microsoft
Lucent
Motorola
Infineon Technologies AG
Cambridge Silicon Radio
Silicon Wave
Digianswer A/S
Texas Instruments Inc.
Parthus Technologies Inc.
Broadcom Corporation
Mitel Semiconductor
Widcomm, Inc.
Zeevo, Inc.
Atmel Corporation
Mitsubishi Electric Corporation
RTX Telecom A/S
KC Technology Inc.
Newlogic
Transilica, Inc.
Rohde & Schwarz GmbH & Co. KG
TTPCom Limited
Signia Technologies, Inc.
Conexant Systems Inc.
Qualcomm
Inventel
AVM Berlin
BandSpeed, Inc.
Mansella Ltd
NEC Corporation
WavePlus Technology Co., Ltd.
Alcatel
Philips Semiconductors
C Technologies
Open Interface
R F Micro Devices
Hitachi Ltd
Symbol Technologies, Inc.
Tenovis
Macronix International Co. Ltd.
GCT Semiconductor
Norwood Systems
MewTel Technology Inc.
ST Microelectronics
Synopsys
Red-M (Communications) Ltd
Commil Ltd
Computer Access Technology Corporation (CATC)
Eclipse (HQ Espana) S.L.
Renesas Technology Corp.
Mobilian Corporation
Terax
Integrated System Solution Corp.
Matsushita Electric Industrial Co., Ltd.
Gennum Corporation
Research In Motion
Local Clock
Piconet Clock
Start Flushable
Continuation
Start Non-Flushable
No Loopback mode enabled
Enable Local Loopback
Enable Remote Loopback
None
Active
All
Start
Continuation
Send File
Send Text
UPF
HCI Commander
L2CAP
FTD_NUM_MASTER_CON
FTD_NUM_SLAVE_INSTANCE
FTD_ACTIVE_SLEEP_RATIO
FTD_HW_VERSION_NUM
FTD_SW_VERSION_NUM
FTD_CLASS_OF_DEVICE
FTD_BT_COUNTRY_CODE
FTD_BD_ADDR
FTD_FRIENDLY_NAME
FTD_PMD_RESET_REASON
FTD_CON_0_CON_STATE
FTD_CON_1_HANDLE
FTD_CON_1_BD_ADDR
FTD_CON_1_CON_STATE
FTD_CON_1_LOC_DEV_STATE
FTD_CON_1_QUALITY
FTD_CON_2_HANDLE
FTD_CON_2_BD_ADDR
FTD_CON_2_CON_STATE
FTD_CON_2_LOC_DEV_STATE
FTD_CON_2_QUALITY
FTD_CON_3_HANDLE
FTD_CON_3_BD_ADDR
FTD_CON_3_CON_STATE
FTD_CON_3_LOC_DEV_STATE
FTD_CON_3_QUALITY
FTD_CON_4_HANDLE
FTD_CON_4_BD_ADDR
FTD_CON_4_CON_STATE
FTD_CON_4_LOC_DEV_STATE
FTD_CON_4_QUALITY
FTD_CON_5_HANDLE
FTD_CON_5_BD_ADDR
FTD_CON_5_CON_STATE
FTD_CON_5_LOC_DEV_STATE
FTD_CON_5_QUALITY
FTD_CON_6_HANDLE
FTD_CON_6_BD_ADDR
FTD_CON_6_CON_STATE
FTD_CON_6_LOC_DEV_STATE
FTD_CON_6_QUALITY
FTD_CON_7_HANDLE
FTD_CON_7_BD_ADDR
FTD_CON_7_CON_STATE
FTD_CON_7_LOC_DEV_STATE
FTD_CON_7_QUALITY
FTD_CON_8_HANDLE
FTD_CON_8_BD_ADDR
FTD_CON_8_CON_STATE
FTD_CON_8_LOC_DEV_STATE
FTD_CON_8_QUALITY
Write
Read
COMM_FTD_DATA_FAIL
FTD_NUM_MASTER_CON
FTD_NUM_SLAVE_INSTANCE
FTD_ACTIVE_SLEEP_RATIO
FTD_HW_VERSION_NUM
FTD_SW_VERSION_NUM
FTD_CLASS_OF_DEVICE
FTD_BT_COUNTRY_CODE
FTD_BD_ADDR
FTD_FRIENDLY_NAME
FTD_PMD_RESET_REASON
FTD_CON_0_CON_STATE
FTD_CON_1_HANDLE
FTD_CON_1_BD_ADDR
FTD_CON_1_CON_STATE
FTD_CON_1_LOC_DEV_STATE
FTD_CON_1_QUALITY
FTD_CON_2_HANDLE
FTD_CON_2_BD_ADDR
FTD_CON_2_CON_STATE
FTD_CON_2_LOC_DEV_STATE
FTD_CON_2_QUALITY
FTD_CON_3_HANDLE
FTD_CON_3_BD_ADDR
FTD_CON_3_CON_STATE
FTD_CON_3_LOC_DEV_STATE
FTD_CON_3_QUALITY
FTD_CON_4_HANDLE
FTD_CON_4_BD_ADDR
FTD_CON_4_CON_STATE
FTD_CON_4_LOC_DEV_STATE
FTD_CON_4_QUALITY
FTD_CON_5_HANDLE
FTD_CON_5_BD_ADDR
FTD_CON_5_CON_STATE
FTD_CON_5_LOC_DEV_STATE
FTD_CON_5_QUALITY
FTD_CON_6_HANDLE
FTD_CON_6_BD_ADDR
FTD_CON_6_CON_STATE
FTD_CON_6_LOC_DEV_STATE
FTD_CON_6_QUALITY
FTD_CON_7_HANDLE
FTD_CON_7_BD_ADDR
FTD_CON_7_CON_STATE
FTD_CON_7_LOC_DEV_STATE
FTD_CON_7_QUALITY
FTD_CON_8_HANDLE
FTD_CON_8_BD_ADDR
FTD_CON_8_CON_STATE
FTD_CON_8_LOC_DEV_STATE
TD_CON_8_QUALITY
Not Activated
Not Supported
Not Available
Off
Loopback
Codec
Pattern Sine
Pattern Byte Saw Tooth
Pattern Packet Saw Tooth
Legacy mode
Shared SDIO, BT
Shared SDIO, WLAN
Legacy mode
Shared SDIO, BT
Shared SDIO, WLAN
CMD0
CMD3
CMD5
CMD7
CMD15
Advertise
Scan
Connect
Connection
FREF
TCXO (5500 Only)
DRX_BUS[31:0]
DTX_BUS[15:0]
DRPb_BUS[31:0]
SCR_BUS[15:0]
OCP_IC_BUS[15:0]
DRX_CKVD48
DRX_CKVD96
DRX_CKVD240
DRX_5M_CLK
DRX_CKVD96_TDM
DRX_CKVD240_TDM
DRX_5M_CLK_TDM
DTX_CKVD96_192
DTX_CKVD96_192_TDM
DLO_DEBUG_CKR
SCR_DEBUG_CLK
OCP_CLK
NO_CLOCK
No_shift
shift_by_1
shift_by_2
shift_by_3
shift_by_4
shift_by_4
shift_by_5
shift_by_6
shift_by_7
shift_by_8
shift_by_9
shift_by_10
shift_by_11
shift_by_12
shift_by_13
shift_by_14
shift_by_15
IO_pins
External_Memory_pins
Disable_DTST
Enable_DTST
mirror_Disable
mirror_Enable
DTST_clk_Selected
APLL_clk_Selected
PhyDebugBus
UserOverridePattern
ToggelPattern_FFFF_0000
Recording
Random_Access
Continuous_Access
Disable_Mem
Enable_Mem
Disable_Dtst
Enable_Dtst
1_KByte
2_KByte
3_KByte
4_KByte
2_Byte
4_Byte
16_LSB
16_MSB
Disable_Mem_Wrap
Enable_Mem_Wrap
Disable_Mem
Enable_Mem
None
HCILL
PALAU
TCP Client
TCP Server
UDP
Create
Append
Port 0x0378
Port 0x0379
Port 0x037a
-->
OK button
OK and Cancel buttons
Abort, Retry and Ignore buttons
Yes, No and Cancel buttons
Yes and No buttons
Retry and Cancel buttons
SCO
ACL
eSCO
No Buffers Command
No Buffers ACL Data
No Buffers SCO Data
Bad Type
Bad Len
Overrun
Parity
Framing
Break
Radio Event
Palau Error: Ram Area Full
Palau Error: H4 Corrupt Data
Palau Error: About To Reset
Active
Hold
Sniff
Park
Combination Key
Local Unit Key
Remote Unit Key
Debug combination key
Unauthenticated key
Authenticated key
Changed combination key
1
3
5
µ-law log
A-law log
CVSD
Transparent Data
De-assert
Show real value
Set l2cap positive length in the payload header
Set l2cap zero length in the payload header
40MHz output (Europe)
48MHz output (Japan)
Don't change
BT_FUNC4
Don't change
BT_FUNC1
BT_FUNC7
BT_FUNC2
BT_FUNC5
BT_FUNC3
BT_FUNC6
Disable
Immediate shutdown
Shutdown next packet
Do not change
AUD_IN
AUD_OUT
AUD_CLK
AUD_FSYNC
TX_HCI
RX_HCI
CTS_HCI
RTS_HCI
BT_FUNC_1
BT_FUNC_2
BT_FUNC_3
BT_FUNC_4
BT_FUNC_5
BT_FUNC_6
BT_FUNC_7
BT_FUNC_8
BT_FUNC_9
BT_FUNC_10
tx_hci
armio_out12
tx_hci
espi_do
rx_hci(input)/espi_di(input)
armio_out13
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
rx_hci(input)/espi_di(input)
cts_hci(unput)/espi_cs(input)
armio_out14
debug_2
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
debug_8
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
cts_hci(input)/espi_cs(input)
rts_hci
armio_out15
debug_3
rts_hci
espi_irq
drp_tst_clk
aud_in
armio_out(0)
debug_12
aud_out
armio_out(1)
debug_11
aud_clk
armio_out(16)
debug_10
aud_fsync
armio_out(17)
debug_9
armio_out1 -as host wkup
wlan1
exp_pa_cmd2
spi_clk
tx_bypass
debug_6
armio_out2 -as BT wkup
wlan0
ext_pa_en
tx_dbg
tx_wire_3
debug_5
armio_out(3)
next_pa_en
wlan1
tx_dbg
tx_wire_2
rx_bypass(input)
debug_4
armio_out4
wibree_gpio5
tx_dbg
exp_pa_cmd1
tx_bypass
rx_bypass(input)
wlan0
debug_3
armio_out5 -as sys_sync
wlan1
wlan0
ext_pa_en
rts_bypass
wlan2
wibree_gpio_2
debug_2
armio_out(6)
tx_dbg
wlan1
next_pa_en
cts_bypass(input)
tx_wire_1
sda
debug_1
armio_out(7)
wibree_gpio(9)(input)
wlan3(input)
exp_pa_cmd2
rx_bypass(input)
tx_wire_4
scl
debug_0
armio_out8
wibree_gpio8
wlan2
wlan0
scl
tx_dbg
debug_7
armio_out9
wibree_gpio7
tx_dbg
wlan3(input)
debug_13
armio_out10
tx_dbg
wlan2
debug_14
TX_HCI
RX_HCI
CTS_HCI
RTS_HCI
AUD_IN
AUD_OUT
AUD_CLK
AUD_FSYNC
BT_FUNC_1
BT_FUNC_2
TX_DBG
BT_FUNC_4
BT_FUNC_6
BT_FUNC_7
CLK_REQ_OUT
FM_IRQ
FM_SCL
FM_SDA
FM_I2S_DI
FM_I2S_DO
FM_I2S_CLK
FM_I2S_WS
tx_hci
fm_dtst_clk
top_dbg7
fm_dtst0
bt_dbg7
rx_hci (input)
fm_dtst4
top_dbg8
fm_dtst1
bt_dbg9
cts_hci (input)
bt_func6
fm_dtst9
bt_func1
fm_dtst_13
top_dbg15
fm_dtst2
bt_dbg_clk
rts_hci
bt_func3
top_dbg10
fm_dtst4
bt_dbg10
aud_in
fm_i2s_di (input)
arm_mclk
fm_dtst4
fm_dtst_clk
top_dbg4
fm_dtst12
bt_dbg4
aud_out
fm_i2s_do
arm_mas(1)
NU
fm_dtst_clk
top_dbg6
fm_dtst9
bt_dbg6
aud_clk
fm_i2s_clk
arm_mas(0)
NU
NU
top_dbg0
fm_dtst10
bt_dbg0
aud_fsync
fm_i2s_ws
arm_nmreq
NU
fm_dtst4
top_dbg9
fm_dtst11
bt_dbg9
hci_clk (input)
bt_func1
fm_i2s_do
NU
NU
top_dbg1
fm_dtst5
bt_dbg1
bt_func2
arm_nwait
fm_i2s_do
NU
NU
top_dbg2
fm_dtst6
bt_dbg2
bt_func3 tx_dbg
arm_nexec
fm_i2s_do
fm_dtst_clk
tx_dbg
top_dbg3
fm_dtst7
bt_dbg3
bt_func4
NU
ext_be_0
fm_i2s_do
NU (Default)
top_dbg4
fm_dtst12
bt_dbg4
bt_func6
tx_dbg
ext_be_1
NU (Default)
NU
top_dbg6
fm_dtst14
bt_dbg6
bt_func7
NU
fm_i2s_do
NU (Default)
NU
top_dbg7
fm_dtst15
bt_dbg7
clk_req_out
tx_dbg
arm_nwait
bt_func5
fm_dtst3
top_dbg5
fm_dtst8
bt_dbg5
fm_irq
arm_nemu1
bt_func3
bt_func10
bt_func4
top_dbg13
fm_dtst2
bt_dbg13
fm_scl
arm_nopc
bt_func1
bt_func8
bt_func7
top_dbg11
fm_dtst0
bt_dbg11
fm_sda
arm_nemu0
bt_func2
bt_func9
bt_func6
top_dbg12
fm_dtst1
bt_dbg12
fm_i2s_di (input)
fm_i2s_do
bt_func4
bt_func8
tdo
top_dbg14
fm_dtst_clk
bt_dbg14
fm_i2s_do
NU
bt_func7
fm_dtst4
tck (input)
top_dbg7
fm_dtst13
bt_dbg7
fm_i2s_clk
fm_dtst4
bt_func5
bt_func9
tms (input)
top_dbg15
fm_dtst15
bt_dbg15
fm_i2s_ws
NU
bt_func6
bt_func10
tdi (input)
top_dbg8
fm_dtst14
bt_dbg8
TX_HCI
RX_HCI
CTS_HCI
RTS_HCI
AUD_IN
AUD_OUT
AUD_CLK
AUD_FSYNC
BT_FUNC_1
BT_FUNC_2
BT_FUNC_5
BT_FUNC_3
BT_FUNC_6
BT_FUNC_7
SB_DATA
SB_CLK
WL_TX
WL_RX
FREF_CLK_REQ
FM_I2S_DI
FM_I2S_DO
FM_I2S_CLK
FM_I2S_WS
SPI_CSX
WLAN_IRQ
WL_UART_DBG
WL_PAEN_A
WL_PAEN_B
WL_BTH_SW
WL_EXT_LNA_EN
WL_RS232_RX
WL_RS232_TX
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
GPS_UART_TX
GPS_UART_RX
GPS_SENS_I2C_SCL
GPS_SENS_I2C_SDA
TESTMODE
TCXO_CLK_REQ
GPS_IRQ
GPS_TIMESTAMP
GPS_PPS_OUT
GPS_I2C_UART_SELECT
GPS_EXT_LNA_EN
GPS_PA_EN
DC2DC_MODE
TCXO_SLI_OUT
WL_SPI_DIN
WL_SPI_DOUT
WL_SDIO_D1
WL_SDIO_D2
bt_tx_hci
shared[2]
bt_rx_hci
shared[2]
bt_cts_hci
gps_fm_debug_clk_o
wlan_drpw_clk
bt_debug_clk
shared[4]
bt_rts_hci
shared[14]
ext_pcm_di
gps_fm_debug[15]
wlan_drpw[6]
prcm_sdio[5]
fm_dtst_o[2]
sb[18]
ext_pcm_do_o
gps_fm_debug[12]
bt_func5
wlan_drpw[14]
prcm_sdio[6]
fm_dtst_o[3]
sb[19]
ext_pcm_clk
gps_fm_debug[13]
gps_gpio_o[7]
wlan_drpw[0]
prcm_sdio[4]
fm_dtst_o[0]
shared[13]
ext_pcm_fsync
gps_fm_debug[10]
bt_ic_o[1]
wlan_drpw[1]
prcm_sdio[15]
fm_dtst_o[1]
sb[17]
bt_func1
fm_dtst_o[15]
wlan_drpw[8]
sb[10]
bt_ic[2]
shared[0]
bt_func2
fm_dtst_o[8]
wlan_drpw[9]
shared[1]
bt_func5
wlan_drpw[12]
prcm_sdio[8]
prcm_sdio[22]
shared[3]
bt_func3
wlan_drpw[11]
prcm_sdio[23]
fm_dtst_o[6]
shared[3]
bt_func6
fm_dtst_o[4]
gps_ext_addr[13]
wlan_drpw[7]
bt_debug_clk
gps_gpio_o[4]
shared[3]
bt_func7
gps_ext_addr[12]
wlan_drpw[10]
bt_ic[11]
shared[3]
sb_data
wlan_drpw[17]
bt_func7_o
shared[6]
sb_clk
gps_fm_gpio[0]
wlan_drpw[18]
bt_ic[13]
shared[4]
wl_tx_sw_final
gps_fm_debug[0]
gps_gpio_o[4]
wl_rx_sw_final
gps_fm_debug[6]
gps_gpio_o[5]
fref_clk_req_o
fm_dtst_o[5]
jtag_rtck
sb[10]
bt_ic[3]
shared[12]
ext_i2s_di
gps_fm_gpio[6]
ext_addr_0
wlan_drpw[2]
prcm_sdio[0]
bt_func1_o
shared[8]
ext_i2s_do_o
gps_fm_gpio[7]
ext_addr_1
wlan_drpw[3]
prcm_sdio[1]
bt_func2_o
shared[9]
ext_i2s_clk
ext_addr_2
wlan_drpw[4]
prcm_sdio[2]
bt_func3_o
shared[10]
ext_i2s_fsync
jtag_rtck
ext_addr_3
wlan_drpw[5]
prcm_sdio[3]
bt_func4_o
shared[11]
spi_csx_o
gps_fm_debug[3]
gps_ext_addr[6]
fm_dtst_o[11]
sb[2]
bt_ic[12]
shared[0]
sdio_wl_irq
gps_fm_debug[1]
gps_ext_be[1]
sb[5]
bt_ic[0]
wl_uart_dbg_o
gps_fm_gpio[2]
gps_irq_o
sb[9]
jtag_rtck
shared[2]
wl_paen_a_final
gps_ext_be[0]
sb[6]
bt_ic[12]
shared[0]
wl_paen_b_final
gps_fm_debug[9]
gps_gpio_o[3]
bt_ic[1]
wl_bth_sw_final
gps_fm_debug[7]
gps_gpio_o[6]
shared[7]
wl_gpio_o[7]
gps_fm_debug[11]
ext_addr_5
wl_rs232_rx_i
gps_fm_debug[14]
gps_ext_we
sb[8]
bt_ic[10]
shared[2]
wl_rs232_tx_o
gps_fm_gpio[5]
ext_addr_14
gps_gpio_o[6]
sb[7]
bt_ic[9]
shared[1]
JTAG_TCK
jtag_tms
gps_ext_addr[4]
gps_gpio_o[5]
prcm_sdio[13]
bt_ic[13]
shared[6]
jtag_tdi
gps_fm_gpio[4]
gps_ext_be[1]
gps_gpio_o[3]
sb[12]
bt_ic[15]
shared[8]
jtag_tdo_test_out
gps_fm_gpio[3]
gps_ext_addr[8]
wlan_drpw[15]
prcm_sdio[14]
bt_ic[14]
shared[7]
gps_uart_tx_o
wimax_info_1
bt_ext_addr[6]
wlan_drpw[13]
sb[0]
bt_ic[3]
fm_dtst_o[9]
gps_uart_rx_i
fm_irq
bt_ext_addr[8]
wlan_drpw[19]
sb[1]
fm_dtst_o[10]
gps_sens_i2c_scl
ext_fm_scl
bt_ext_addr[4]
gfm_dtst_o[7]
sb[14]
bt_func5_o
shared[10]
gps_sens_i2c_sda
ext_fm_sda
bt_ext_we
wlan_drpw[23]
sb[15]
bt_ic[2]
fm_dtst_o[8]
/*TESTMODE_in*/
fm_dtst_o[6]
gps_ext_addr[6]
wlan_drpw[16]
sb[13]
jtag_rtck
shared[15]
tcxo_clk_req_o
bt_ic_o[15]
gps_irq_o
sb[11]
bt_func6_o
shared[5]
gps_irq_o
fm_dtst_o[13]
wimax_tx_0
wlan_drpw[21]
sb[16]
bt_ic[6]
shared[14]
gpsip_time_stamp_i
gps_fm_debug_o[10]
bt_ext_addr[12]
wlan_drpw[22]
prcm_sdio[9]
bt_ic[4]
shared[13]
gps_pps_out
gps_fm_gpio[1]
wimax_tx_1
prcm_sdio[11]
sb[7]
jtag_rtck
fm_dtst_o[14]
wl_rs232_tx_o
gps_fm_gpio[5]
ext_addr_14
gps_gpio_o[6]
sb[7]
bt_ic[9]
shared[1]
gps_ext_lna_en
fm_dtst_o[12]
bt_ext_addr[13]
prcm_sdio[12]
bt_ic[7]
shared[9]
gps_pa_en
gps_fm_debug_o[15]
ext_addr_11
fm_dtst_o[11]
prcm_sdio[10]
bt_ic[5]
shared[5]
dc2dc_active_mode
ext_addr_14
prcm_sdio[7]
bt_ic[8]
shared[4]
tcxo_sli_out_o
fm_dtst_o[5]
ext_addr_7
gps_gpio_o[7]
sb[11]
bt_func7_o
shared[5]
spi_din
gps_fm_debug[5]
gps_ext_addr[4]
sb[7]
jtag_rtck
spi_dout
gps_fm_debug[4]
gps_ext_addr[8]
sb[1]
bt_ic[1]
sdio_d1
gps_fm_debug[2]
gps_ext_addr[11]
fm_dtst_o[7]
sb[]
bt_ic[11]
bt_ic[7]
sdio_d2
gps_fm_debug[8]
ggps_gpio_o[2]
sb[4]
bt_ic[8]
fm_dtst_o[6]
Don't Change
Don't Change
pll clock signal to design
fref after division
pll lock signal
pll sync signal
fast frequency input
pll power down command (active low)
system slow clock
system root clock after retiming in DRP
ocp clock
arm clock
uart clock
1MHz bt clock
4MHz bt clock
usec timer0 event
usec timer1 event
codec clock
sdio clock
spi clock
powerup reset
watchdog timer reset
watch timer event
fast clock enable indication from fcgen to fdc
slow wakeup event from wakeup unit
fast wakeup event from wakeup unit
usec timer event
BT_SLOW_CLK
Status of local clock load in fast domain (0–no load/load completed,1–load in progress)
Status of network1 clock load in fast domain (0–no load/load completed, 1–load in progress)
Status of network2 clock load in fast domain (0–no load/load completed,1–load in progress)
Local Bluetooth clock, bit 2
Local Bluetooth clock, bit 3
Network1 Bluetooth clock, bit 2
Network1 Bluetooth clock, bit 3
Network2 Bluetooth clock, bit 2
Network2 Bluetooth clock, bit 3
Network2 domain status
Status of local clock load in fast domain (0–no load/load completed,1–load in progress)
Status of network1 clock load in fast domain (0–no load/load completed,1–load in progress)
Local domain 1MHz clock
Network2 domain 1MHz clock
Network1 domain 1MHz clock
Switched Bluetooth clock, bit 2
Switched Bluetooth clock, bit 3
Scheduler Bluetooth clock, bit 2
Local Packet Timer, bit 10
Network2 Packet Timer, bit 10
Network1 Packet Timer, bit 10
Switched Packet Timer, bit 10
Scheduler Packet Timer, bit 10
NIRQ 2 (timer interrupts)
slow domain control state machine - dbg3:0 only
fast domain control state machine - dbg7:4 only
DMA clock (check dynamic DMA clock gating) - dbg9:8 only
slow domain scripter control bus - dbg5:0 only
Wibree root clock - dbg7:6 only
Wibree gated cortex clock - dbg8 only
Wibree free cortex clock - dbg9 only
slow domain scripter control bus - dbg5:0 only
Wibree AES clock - dbg6 only
Wibree OCP gated clock - dbg7 only
Wibree free OCP clock - dbg8 only
Wibree dma clock - dbg9 only
BT dma clock - dbg0 only
BT PCMI clock - dbg1 only
BT I2C clock - dbg2 only
BT Debug clock - dbg3 only
Network1 Bluetooth clock, bit 4 - dbg6 or dbg8 only
Network2 Bluetooth clock, bit 5 - dbg4 or dbg9 only
Network1 Bluetooth clock, bit 5 - dbg5 or dbg7 only
Fast clock status (on / off) - dbg0 or dbg4 only
qra11_n1_cdc_adjust_event_i - dbg1 or dbg5 only
qra11_n2_cdc_adjust_event_i - dbg2 or dbg9 only
Local Bluetooth clock, bit 5 - dbg3 or dbg7 only
Network2 Bluetooth clock, bit 4 - dbg6 or dbg8 only
Local Bluetooth clock, bit 4 - dbg7 or dbg8 only
Switched Packet Timer, bit 9 - dbg4 only
Switched Bluetooth clock, bit 4 - dbg6 or dbg9 only
Switche4 Bluetooth clock, bit 5 - dbg0 or dbg5 only
Local Packet Timer, bit 9 - dbg1 only
Network1 Packet Timer, bit 9 - dbg2 only
Network2 Packet Timer, bit 9 - dbg3 only
Priority disabled
SCO/eSCO
Priority during eSCO window
Priority during FHS/ID
Sniff
Hold
Inq Scan
Inquiry
Page Scan
Page
Park
TDD
First successfull sniff attempt only
Park beacon
eSCO window only in master
Tpoll
AFH scans
Pre RF init
Clock Dependant Calc
Temperature recognition
DC
LDO
DCO Current Optimization
DCO Coarse Open Loop
KDCO Nominal Current
PPA LDO Current
TPC
IFA Pole Location
LPS
Wide Band RSSI TH
IQ MM
Don't Change
Pre RF init
None
None
Clock Dependant Calc
Temperature recognition
DC
LDO
DCO Current Optimization
DCO Coarse Open Loop
KDCO Nominal Current
PPA LDO Current
TPC
IFA Pole Location
LPS
Wide Band RSSI TH
IQ MM
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
PowerLevel 0
PowerLevel 1
PowerLevel 2
PowerLevel 3
PowerLevel 4
PowerLevel 5
PowerLevel 6
PowerLevel 7
PowerLevel 8
PowerLevel 9
PowerLevel 10
PowerLevel 11
PowerLevel 12
PowerLevel 13
PowerLevel 14
PowerLevel 15
DM1
DH1
DM3
DH3
DM5
DH5
No 2DH1
No 3DH1
No 2DH3
No 3DH3
No 2DH5
No 3DH5
HV1
HV2
HV3
DM1
DH1
DM3
DH3
DM5
DH5
HV1
HV2
HV3
No 2DH1
No 3DH1
No 2DH3
No 3DH3
No 2DH5
No 3DH5
HV1
HV2
HV3
EV3
EV4
EV5
No2EV3
No3EV3
No2EV5
No3EV5
Role Switch
Hold Mode
Sniff Mode
Park Mode
Inquiry Complete Event
Inquiry Result Event
Connection Complete Event
Connection Request Event
Disconnection Complete Event
Authentication Complete Event
Remote Name Request Complete Event
Encryption Change Event
Change Connection Link Key Complete Event
Master Link Key Complete Event
Read Remote Supported Features Complete Event
Read Remote Version Information Complete Event
QoS Setup Complete Event
Hardware Error Event
Flush Occurred Event
Role Change Event
Mode Change Event
Return Link Keys Event
PIN Code Request Event
Link Key Request Event
Link Key Notification Event
Loopback Command Event
Data Buffer Overflow Event
Max Slots Change Event
Read Clock Offset Complete Event
Connection Packet Type Changed Event
QoS Violation Event
Page Scan Mode Change Event [deprecated]
Page Scan Repetition Mode Change Event
Flow Specification Complete Event
Inquiry Result with RSSI Event
Read Remote Extended Features Complete Event
Fixed Address Event
Alias Address Event
Generate Alias Request Event
Active Address Event
Allow Private Pairing Event
Alias Address Request Event
Alias Not Recognized Event
Fixed Address Attempt Event
Synchronous Connection Complete Event
Synchronous Connection Changed Event
Sniff Subrate Changed Event
Extended Inquiry Result Event
Encryption Key Refresh Event
Io Capabilities Request Event
Io Capabilities Response Event
Io User Conf Req Event
User Passkey Request Event
Io User Oob Data Req Event
Simple Pairing Complete Event
Reserved
Link Supervision Timeout Change Event
Enhanced Flush Complete Event
Sniff_Request Event
User Passkey Notification Event
Keypress Notification Event
Remote Host Supported Features Notification Event
LE Meta Event
Disabled
Enabled
Data driven LSB-first
Swap bytes within the sample
Shift sample by (24|16-dout_size) bits
No bits output
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Patch #1
Patch #2
Patch #3
Patch #4
Patch #5
Patch #6
Patch #7
Patch #8
Patch #9
Patch #10
Patch #11
Patch #12
Patch #13
Patch #14
Patch #15
Patch #16
Patch #17
Patch #18
Patch #19
Patch #20
Patch #21
Patch #22
Patch #23
Patch #24
Patch #25
Patch #26
Patch #27
Patch #28
Patch #29
Patch #30
Patch #31
Patch #32
FM Off
FM On
FM Off with retention
Host's PCM bus
Internal Controller's FM.
Source
Sink
8000 Hz
11025 Hz
12000 Hz
16000 Hz
22050 Hz
24000 Hz
32000 Hz
44100 Hz
48000 Hz
1 channel
2 channels
16000 Hz
32000 Hz
44100 Hz
48000 Hz
Mono
Dual Stereo
Stereo
Joint Stereo
Loudness
SNR
Disable
Enable
Transmit internal buffers before flush (soft flush)
Immediate flush of buffers (hard flush)
No
Yes
a3dp_generate_event
HCI GPS Inbound Data Event
HCI GPS Outbound Data Event
HCI GPS Number of Completed Packets Event
Power Off
Power On
Public Device Address
Random Device Address
White_List Not In Use
White List Is Used
LE Connection Complete Event
Advertising Report Event
LE Connection Update Complete Event
LE Read Remote Used Features Complete Event
LE Long Term Key Request Event
unmask bit 0
unmask bit 1
unmask bit 2
unmask bit 3
unmask bit 4
unmask bit 5
unmask bit 6
unmask bit 7
unmask bit 8
unmask bit 9
unmask bit 10
unmask bit 11
unmask bit 12
unmask bit 13
unmask bit 14
unmask bit 15
WB_CONNECTION_UPDATE
WB_CHANNEL_MAP_UPDATE
WB_TERMINATE_IND
WB_ENC_REQ
WB_ENC_RSP
WB_START_ENC_REQ
WB_START_ENC_RSP
WB_UNKNOWN_RSP
WB_FEATURES_REQ
WB_FEATURES_RES
WB_PAUSE_ENC_REQ
WB_PAUSE_ENC_RSP
WB_VERSION_IND
WB_REJECT_IND
WB_ADV_IND
WB_ADV_DIRECT_IND
WB_NON_CONN_ADV_IND
WB_SCAN_REQ
WB_SCAN_RSP
WB_CONNECT_REQ
WB_ADV_DISCOVER_IND
WB_ON_CONNECT_REQ_SENT
WB_ON_CONNECTION_ESTABLISHED
WB_ON_BAD_MIC_TERMINATION
WB_ON_LE_FLUSH_FINISHED
Start
Stop
Duplicate filtering is disabled
Duplicate filtering is enabled
Connectable Undirect Event
Connectable Direct Event
Discoverable Event
Non-Connectable Undirect Event
Scan Response
Connectable Undirect Event
Connectable Direct Event
Discoverable Non-direct Event
Non-Connectable Undirect Event
Allow Scan Request from Any, Allow Connect Request from Any
Allow Scan Request from White List, Allow Connect Request from Any
Allow Scan Request From Any, Connect from White List
Allow Scan Request From White List, Connect from White List
Allow ADV From Any
Allow ADV White List
LE Connection Created Event
LE Advertising Report Event
LE Connection Update Complete Event
LE Read Remote Used Features Event
LE Long Term Key Requested Event
No Other Profiles Supported
Other Profiles Supported
Passive
Active
Apply to HCI_LE_Encrypt
Apply to Data Packets
LL Connection Requested by Peer Device
Advertising Stopped by the Host
Termination Requested by the Local Device
Termination Requested by the Peer Device
Link Supervision Timeout
Termination Due To MIC failure
Termination Due To Peer Device Transaction Too Late
PLL Sharing Scheme Disabled
PLL Sharing Scheme Enabled
Force COEX PLL
Force HP PLL
Force LP PLL
Force LP Bypass PLL
SHARED_PLL_NOT_ENABLED
COEX_PLL
MCS HP PLL
MCS LP PLL
MCS LP Power Save
MCS LP Bypass PLL
disabled
enabled
According to detection
don't change
FM OCP
TCXO
HP
LP
Don't change
SPI_DIN
WL_UART_DBG
FM_I2S_FSYNC
FREF_CLK_REQ
TESTMODE
GPS_PPS_OUT
PRBS 9
FOFO
ZOZO
PRBS 15
ALL 1
ALL 0
OFOFO
OZOZO
Normal Mode
Wide Window
Continious RX
Wide window and power saving
In Range Alert
Low Alert
High Alert
Sync valid check from phy
Sync valid check misc
Sync valid check in connection setup
Sync valid check in test mode
Print syncs check to logger
Wave io pin for syncs check
Force sending events to host upon disconnect
Prevent sending events to host upon disconnect
Set specific window and offset
Send reject on start enc
Generate transaction in past
Generate specific packet counter in transaction
Ignore start enc req
Slave generate incorrect crc on conn setup
Generate clock drift
Skip verison ind at establishement
Stay in latency
Enc master use forced skdm ivm
Enc slave use forced skds ivs
Enc generate bad mic on invalid header received
Enc use header rfu bits in b1
Send lmp timeout on disconnect with lmp to
Automatic Detection
Manual Detection
RFMD
TRIQ
SKW
TRIQ HP
Overrite
Single Band
Dual Band
Spec 1.1
LAP
"9E8B33"
The LAP from which the inquiry access code should be derived
Inquiry Length
0x04
Maximum amount of time in 1.28 sec before the Inquiry is halted
Number of Responses
0x00
Maximum number of responses before the Inquiry is halted. 0 - Unlimited
HCI_Command_Status_Event
Spec 1.1
HCI_Command_Complete_Event
Spec 1.1
Max Period Length
0x0008
Maximum amount of time in 1.28s specified between consecutive inquiries
Min Period Length
0x0007
Minimum amount of time in 1.28s specified between consecutive inquiries
LAP
"9E8B33"
LAP from which the inquiry access code should be derived when the inquiry procedure is made
Inquiry Length
0x04
Maximum amount of time in 1.28s before the Inquiry is halted (0x00 - 0x30)
Number of Responses
0x00
Maximum number of responses from the Inquiry before the Inquiry is halted. 0 - Unlimited
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Spec 1.1
BD Address of the Remote
BD_ADDR
Packet Types Allowed
0x0018
0x018 - DM1 and DH1
Page Scan Repetition Mode
0x01
R0=0, R1=1, R2=2
Reserved
0x00
Must be set to 0x00 (from spec 1.2)
Clock Offset
0x0000
Role Switch allowed
0x00
M/S switch not allowed=0, Allow M/S switch=1
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
Reason
0x13
Reason for disconnection
HCI_Command_Status_Event
HCI_Disconnect
Spec 1.1
Connection Handle
Handle
Packet Types Allowed
0x0080
HV3 packet only
HCI_Command_Status_Event
HCI_Add_SCO_Connection
Spec 1.2
BD Address of the Remote
BD_ADDR
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
BD Address of the Remote
BD_ADDR
Role
0x01
0 - Become the Master for this connection; 1 - Remain the Slave for this connection
HCI_Command_Status_Event
Spec 1.1
BD Address of the Remote
Bd_Addr
Reason
0x0D
Host Reject Error Code
HCI_Command_Status_Event
Spec 1.1
BD Address of the Remote
BD_ADDR
Link Key
"00000000000000000000000000000000"
Link Key for the associated BD_ADDR
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
BD Address of the Remote
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
BD Address of the Remote
Bd_Addr
Pin Code Length
0x01
The length, in bytes, of the PIN code to be used
Pin Code
"ACBDEFGHIJKLMNOP"
PIN code for the device that is to be connected
"00"
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
BD Address of the Remote
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
Connection Handle
Handle
Packet Types Allowed
0x0C18
ACL or SCO packet types
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
Encryption Enable
0x00
0 - Turn Link Level Encryption OFF, 1 - Turn Link Level Encryption ON
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.1
Key Flag
0x00
0 - Use Semi-permanent Link Keys, 1 - Use Temporary Link Key
HCI_Command_Status_Event
Spec 1.1
BD Address of the Remote
BD_ADDR
Page Scan Repetition Mode
0x01
0 - R0(contineus scan), 1 - R1(Tpage scan <= 1.28s); 2 - R2(T page scan <= 2.56s)
Reserved
0x00
Must be set to 0x00 (from spec 1.2)
Clock Offset
0x0000
Bit 16.2 of CLKslave-CLKmaster. If bit 15 is 0, Clock Offset invalid
HCI_Command_Status_Event
Spec 1.2
BD Address of the Remote
BD_ADDR
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.2
Connection Handle
Handle
Page Number
0x00
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.2
Connection Handle
Handle
Should be a voice connection handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
LMP_Handle
"0x00"
Reserved
0x00000000
Spec 1.2
Connection Handle
Handle
Transmit_Bandwidth
0x1f40
Transmit bandwidth in octets per second
Receive_Bandwidth
0x1f40
Receive bandwidth in octets per second
Max_Latency
0xFFFF
an upper limit (in ms) of the size of: (e)SCO instant + retransmission window + reserved slots, or don't care (0xFFFF).
Voice_Setting
0x0060
voice settings
Retransmission_Effort
0xFF
0x00 - no retr. 0x01 - optimize for power consumption, 0x02 - optimize for link quality, 0xFF - don't care
Packet_Type
0x3F
0x01-HV1, 0x02-HV2, 0x04-HV3, 0x08-EV3, 0x10-EV4, 0x20-EV5, 0x004-No2EV3, 0x008-No3EV3, 0x01-No2EV5, 0x02-No3EV5, 0x3F - All
HCI_Command_Status_Event
Spec 1.2
BD Address
Get_Bd_Addr
Transmit_Bandwidth
0xFFFFFFFF
Maximum possible transmit bandwidth in octets per second, or don't care (0xFFFFFFFF)
Receive_Bandwidth
0xFFFFFFFF
Maximum possible receive bandwidth in octets per second, or don't care (0xFFFFFFFF)
Max_Latency
0xFFFF
an upper limit (in ms) of the size of: (e)SCO instant + retransmission window + reserved slots, or don't care (0xFFFF).
Content_Format
0x60
voice settings
Retransmission_Effort
0xFF
0x00 - no retr. 0x01 - optimize for power consumption, 0x02 - optimize for link quality, 0xFF - don't care
Packet_Type
0xFFFF
0x01-HV1, 0x02-HV2, 0x04-HV3, 0x08-EV3, 0x10-EV4, 0x20-EV5
HCI_Command_Status_Event
Spec 1.2
BD Address of the Remote
Bd_Addr
Reason
0x0D
Host Reject Error Code
HCI_Command_Status_Event
HCI_Reject_Synchronous_Connection_Request
Lisbon
BD Address of the Remote involved in simple pairing process
Bd_Addr
Io Capability
0x00
0x00 - DisplayOnly, 0x01 - DisplayYesNo, 0x02 - KeyboardOnly, 0x03 - NoInputNoOutput, 0x04 - 0xFF Reserved for future use
OOB data present
0x00
OOB capability with remote
Authentication Required
0x00
0 - MITM Protection Not Required – Single Profile. Numeric comparison with automatic accept allowed. 1 - MITM Protection Required – Single Profile. Use IO Capabilities to determine authentication procedure. 2 - MITM Protection Not Required – All Profiles. Numeric comparison with automatic accept allowed. 3 - MITM Protection Required – All Profiles. Use IO Capabilities to determine authentication procedure
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address of the Remote involved in simple pairing process
Bd_Addr
Reason
0x1F
0x1F Unspecified Error , reason 0x37 (Secure Simple Pairing Not Supported By Host) is invalid
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address of the Remote involved in simple pairing process
Bd_Addr
Numeric value Number of Responses
0x0000
Numeric value (Passkey) entered by user. Valid values are decimal 000000-999999
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote
Lisbon
BD Address
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address
Bd_Addr
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address
Bd_Addr
Notification Type
0x00
0 - Passkey entry started ,1 - Passkey digit entered ,2 - Passkey digit erased ,3 - Passkey cleared ,4 - Passkey entry completed
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Lisbon
BD Address
Bd_Addr
Notification_Type
0x00
0 - Passkey entry started ,1 - Passkey digit entered ,2 - Passkey digit erased ,3 - Passkey cleared ,4 - Passkey entry completed
Lisbon
BD Address
Bd_Addr
Passkey
0x00
Passkey to be displayed. Valid values are decimal 000000 – 999999
Lisbon
BD Address
Bd_Addr
Host Features
"0000000000000000"
Lisbon
BD Address
Bd_Addr
C
"00000000000000000000000000000002"
Simple pairing hash C
R
"00000000000000000000000000000001"
Simple pairing Randomizer R
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the Remote involved in simple pairing process
Spec 1.1
Connection Handle
Handle
Hold Mode Max Interval
0x1000
Maximum acceptable number of Baseband slots to wait in Hold Mode
Hold Mode Min interval
0x0800
Minimum acceptable number of Baseband slots to wait in Hold Mode
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
Sniff Max Interval
0x0800
Maximum acceptable number of Baseband slots between each sniff period (1 - 0xFFFF)
Sniff Min interval
0x0700
Minimum acceptable number of Baseband slots between each sniff period (1 - 0xFFFF)
Sniff Attempt
0x0008
Number of Baseband slots for sniff attempt (0 - 0xFFFF)
Sniff Timeout
0x0002
Number of Baseband slots for sniff timeout (0 - 0xFFFF)
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
Beacon Max Interval
0x0100
Maximum acceptable number of Baseband slots between consecutive beacons (0 - 0xFFFF)
Beacon Min interval
0x0100
Minimum acceptable number of Baseband slots between consecutive beacons (0 - 0xFFFF)
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
Flags
0x00
Reserved for Future Use
Service Type
0x01
0 - No Traffic; 1 - Best Effort; 2 - Guaranteed
Token Rate
0xFFFFFFFF
Token Rate in bytes per second
Peak Bandwidth
0x00000000
Peak Bandwidth in bytes per second
Latency
0xFFFFFFFF
Latency in microseconds, 0xFFFFFFFF - do not care
Delay Variation
0xFFFFFFFF
Delay Variation in microseconds, 0xFFFFFFFF - do not care
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Role
0x00
Current role for this connection handle
Spec 1.1
BD Address of the Remote
BD_ADDR
Role
0x00
For this Connection Handle change own Role to 0 - Master; 1 - Slave
HCI_Command_Status_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Link Policy Settings
0x0000
0 - Disable all LM modes
Spec 1.1
Connection Handle
Handle
Link Policy Settings
0x0003
switch, hold, no sniff, no park
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Spec 1.2
HCI_Command_Complete_Event
HCI_Read_Default_Link_Policy_Settings
Status
0x00
Status
Default Link Policy Settings
"0x0000"
Spec 1.2
Default Link Policy Settings
0x0003
0 - Disable All LM Modes
HCI_Command_Complete_Event
Spec 1.2
Connection Handle
Handle
Flags
0x00
Reserved for Future Use
Flow Direction
0x00
0 - Outgoing; 1 - Incoming
Service Type
0x01
0 - No Traffic; 1 - Best Effort; 2 - Guaranteed
Token Rate
0x00000000
Token Rate in bytes per seconds, 0x00000000 - not specified; 0xFFFFFFFF - maximum available
Token Bucket Size
0x00000000
Token Bucket Size in bytes, 0x00000000 - not needed; 0xFFFFFFFF - maximum available
Peak Bandwidth
0x00000000
Peak Bandwidth in bytes per second, 0x00000000 - do not care
Access Latency
0xFFFFFFFF
Latency in microseconds, 0xFFFFFFFF - do not care
HCI_Command_Status_Event
Spec 1.2
Connection Handle
Handle
Maximum Latency
0x0000
Maximum latency in slots that the remote device with a link in sniff sub-rate can use[0x0000 - 0xFFFE]
Min Remote Timeout
0x0000
Maximum sniff sub-rate zero timeout that the remote device should use in slots[0x0000 - 0xFFFE]
Min Local Timeout
0x0000
Minimum sniff sub-rate zero timeout that the local device should use in slots[0x0000 - 0xFFFE]
HCI_Command_Complete_Event
HCI_Sniff_Subrate
Status
0x00
Status
Connection Handle
Handle
Spec 1.1
Event Mask
0x000000000003FFFF
Mask events to be generated
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Spec 1.1
Filter type
0x00
0-Clear all, 1-Inq result, 2-Connection Setup
Result Filter Type
0x00
Class of Device
0x000000
Class of Device for the device
Class of Device Mask
0x000000
Class of Device Mask
BD Address of the device
BD_ADDR
Auto Accept Flag
0x01
HCI_Command_Complete_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Spec 1.1
Persistent Sniff Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Persistent Sniff Interval
0
Spec 1.1
Sniff Interval
0x0800
Maximum acceptable number of Baseband slots between each sniff period (2 - 0xFFFE)
HCI_Command_Complete_Event
Status
0x00
Status
Persistent Sniff Handle
0
Spec 1.1
Sniff Reservation Handle
0
Persistent sniff reservation handle
HCI_Command_Complete_Event
Status
0x00
Status
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Pin Type
0x00
Spec 1.1
PIN Type
0x00
0 - Variable PIN, 1 - Fixed PIN
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Spec 1.1
BD Address of the Remote
BD_ADDR
Read All Flag
0x00
0 - Return Link Key for specified BD_ADDR, 1 - Return all stored Link Keys
HCI_Command_Complete_Event
Status
0x00
Status
Max Num Keys
Any
Num Keys Read
Any
Spec 1.1
Num Keys To Write
0x01
Number of Link Keys to Write
BD Address of the Remote
BD_ADDR
Link Key
"0102030405060708090a0b0c0d0e0f00"
Link Key for the associated BD_ADDR
HCI_Command_Complete_Event
Status
0x00
Status
Max Num Keys
Any
Spec 1.1
BD Address of the Remote
Bd_Addr
Delete All Flag
0x00
0 - Delete only the Link Key for specified BD_ADDR; 1 - Delete all stored Link Keys
HCI_Command_Complete_Event
Status
0x00
Status
Num Keys Deleted
Any
Spec 1.1
New name
"Bluetooth By Texas Instruments"
User Friendly Descriptive Name for the device
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Local Name
User Friendly Descriptive Name for the device
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Conn Accept Timeout
Any
Spec 1.1
Conn Accept Timeout
0x1FA0
Connection Accept Timeout measured in Number of Baseband slots (0 - 0xFFFF)
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Page Timeout
Any
Spec 1.1
Page Timeout
0x2000
Page Timeout measured in Number of Baseband slots (0 - 0xFFFF)
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Scan Enable
0x03
Spec 1.1
Scan Enable
0x00
0 - No Scans enabled, 1 - Inquiry scan enabled, 2 - Page scan enabled, 3 - both enabled
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Page Scan Interval
Any
Page Scan Window
Any
Spec 1.1
PageScan Interval
0x0800
Interval between 2 consecutive Page Scans, (0x0012 - 0x1000)
PageScan Window
0x0012
Duration of each Page Scan (0x0012 - 0x1000)
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Inquiry Scan Interval
0x0800
Inquiry Scan Window
0x0012
Duration of each Page Scan (0x0012 - 0x1000)
Spec 1.1
InquiryScan Interval
0x1000
Interval between 2 consecutive Inquiry Scans (0x0012 - 0x1000 time slots)
InquiryScan Window
0x0012
Duration of each Inquiry Scan Window (0x0012 - 0x1000 time slots)
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Authentication Enable
0x01
Spec 1.1
Authentication Enable
0x00
0 - Authentication disabled, 1 - Authentication enabled for all connections
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Class Of Device
"000000"
Spec 1.1
Class of Device
"000000"
Class of Device for the device
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Voice Settings
Any
Spec 1.1
Voice settings bitmap
0x0060
HCI_Command_Complete_Event
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Handle of connection
Handle
Flash timeout
0
Spec 1.1
Connection Handle
Handle
Flush Timeout
0x0000
0 - No Automatic Flush, otherwise flush timeout in slots (0 - 0x07FF)
HCI_Command_Complete_Event
Status
0x00
Status
Handle of connection
Handle
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Num Broadcast Retran
0x01
Number of Broadcast Retransmissions
Spec 1.1
Num Broadcast Retran
0x01
Number of Broadcast Retransmissions
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Hold Mode Activity
0x00
Spec 1.1
Hold Mode Activity
0x00
HCI_Command_Complete_Event
Spec 1.1
Connection Handle
Handle
Type
0x00
0 - Read Current Transmit Power Level, 1 - Read Maximum Transmit Power Level
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Transmit Power Level
0
dBm
Spec 3.0
Connection Handle
Handle
Type
0x00
0 - Read Current Transmit Power Level, 1 - Read Maximum Transmit Power Level
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Transmit Power Level GFSK
0
dBm
Transmit Power Level DQPSK
0
dBm
Transmit Power Level 8DPSK
0
dBm
Tokyo
HCI_Command_Complete_Event
Status
0x00
Status
LE Host Support
0
Support Of the Host of LE
Simultaneous LE Host Support
0
Support Of the Host of LE in Parallel to BT
Tokyo
LE Host Support
0x00
Support of LE by Host
Simultaneous LE Host Support
0x00
Support of LE by Host in Parallel to BTH
HCI_Command_Complete_Event
Status
0x00
Status
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
SCO Flow Control Enable
0x00
Spec 1.1
SCO Flow Control Enable
0x00
0 - no flow control, 1 - Num Packets Completed event should include SCO information
HCI_Command_Complete_Event
Spec 1.1
Flow Control Enable
0x00
Flow control in direction from Host Controller to Host 0 - OFF, 1 - ON
HCI_Command_Complete_Event
Spec 1.1
Host ACl Data Packet Length
0x0000
Maximum length of the data portion of each HCI ACL Data Packet that the Host is able to accept
Host SCO Data Packet Length
0x00
Maximum length of the data portion of each HCI SCO Data Packet that the Host is able to accept
Host Total Num ACL Data Packets
0x0000
Total number of HCI ACL Data Packets that can be stored in the data buffers of the Host
Host Total Num SCO Data Packets
0x0000
Total number of HCI SCO Data Packets that can be stored in the data buffers of the Host
HCI_Command_Complete_Event
Spec 1.1
Number Of Handles
0x01
The number of Handles and parameters pairs contained in this command
Connection Handle
Handle
Host Num Of Completed Packets
0x0001
The number of HCI Data Packets completed since the previous time the event was returned
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Link Supervision Timeout
0x7D00
0 - No Link_Supervision_Timeout, otherwise - timeout Measured in Number of Baseband slots (0 - 0xFFFF)
Spec 1.1
Connection Handle
Handle
Link Supervision Timeout
0x7D00
0 - No Link_Supervision_Timeout, otherwise - timeout Measured in Number of Baseband slots (0 - 0xFFFF)
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Num Support IAC
0x05
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Num Current IAC
0x01
IAC LAP
"9E8B33"
Spec 1.1
NumCurrentIAC
0x01
Number of IAC which are currently in use to listen for during an Inquiry Scan
IAC LAP
"9E8B00"
HCI_Command_Complete_Event
Spec 1.2
Channel Map
"FFFFFFFFFFFFFFFFFF7F"
0-79 bits
HCI_Command_Complete_Event
Spec 1.2
HCI_Command_Complete_Event
Status
0x00
Status
Inquiry Scan Type
0x00
0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan
Spec 1.2
Inquiry Scan Type
0x00
0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan
HCI_Command_Complete_Event
Spec 1.2
HCI_Command_Complete_Event
Status
0x00
Status
Inquiry Mode
0x00
0 - Standard Inquiry Result event format; 1 - Inquiry Result format with RSSI
Spec 1.2
Inquiry Mode
0x00
0 - Standard Inquiry Result event format; 1 - Inquiry Result format with RSSI
HCI_Command_Complete_Event
Spec 1.2
HCI_Command_Complete_Event
Status
0x00
Status
Page Scan Type
0x00
0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan
Spec 1.2
Page Scan Type
0x00
0 - Mandatory: Standard Scan (default); 1 - Optional: Interlaced Scan
HCI_Command_Complete_Event
Spec 1.2
HCI_Command_Complete_Event
Status
0x00
Status
AFH Channel Assessment Mode
0x00
0x00 = local channel assessment disabled, 0x01 = local channel assessment enabled
Spec 1.2
AFH Channel Assessment Mode
0x00
0x00 = local channel assessment disabled 0x01 = local channel assessment enabled
HCI_Command_Complete_Event
Spec 3.0
FEC Required
0x00
0x00 o FEC is not required (DH packet might be sent) 0x01 - only DM packet will be sent
Inquiry Response Data
Will be paddad with zero to 240 bytes
HCI_Command_Complete_Event
Spec 3.0
HCI_Command_Complete_Event
Status
0x00
0 - Success
FEC Required
Inquiry Response Data
Lisbon
Simple_Pairing_Mode
0x00
Simple pairing mode
HCI_Command_Complete_Event
Lisbon
HCI_Command_Complete_Event
Status
0x00
Status
Simple Pairing Mode
0
Simple pairing mode: 0 - Uninitialized, 1- Enabled
Spec 1.1
Connection Handle
Handle
Packet Type
0x0
HCI_Command_Status_Event
Lisbon
Connection Handle
Handle
Persistent Sniff Handle
0
Persistent Sniff Handle.0 - no assosiation with persistent sniff
HCI_Command_Complete_Event
Status
0x00
Status
Lisbon
Handle
Handle
Connection Handle
HCI_Command_Complete_Event
Status
0x00
Status
Lisbon
HCI_Command_Complete_Event
Status
0x00
Status
C
"00000000000000000000000000000000"
Simple pairing hash C
R
"00000000000000000000000000000000"
Simple pairing Randomizer R
Lisbon
HCI_Command_Complete_Event
This command will read the inquiry response Transmit Power level used to transmit the FHS and EIR data packets. This can be used directly in the Tx Power Level EIR data type, -70dBm to +20dBm
Status
0x00
Status
Tx Power
dBm
Lisbon
Tx_Power
10
This command is used to write the transmit power level used to transmit the inquiry (ID) packets. The Controller should use the supported TX power level closest to the Tx_Power parameter
HCI_Command_Complete_Event
Status
0x00
Status
Spec 3.0
HCI_Command_Complete_Event
Status
0x00
Status
Erroneous Data Reporting
0x00
Erroneous data reporting methoid is currently used
Spec 3.0
Erroneous Data Reporting
0x00
Erroneous data reporting methoid that will be used for new connections
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
0 - Success
HCI Version
0x00
HCI Revision
0x0000
Revision of the Current HCI in the Bluetooth device
LMP Version
0x00
Version of the Current LMP in the Bluetooth device
Manufacturer Name
0x0000
Manufacturer name of the bluetooth device
LMP Subversion
0x0000
Subversion of the Current LMP in the Bluetooth device
Spec 1.2
HCI_Command_Complete_Event
Status
0x00
Status
Supported Commands
"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
Supported commands bitmask
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Supported Commands
"0000000000000000"
Supported features bitmask
Spec 1.2
Page Number
0x00
0 - the only available page
HCI_Command_Complete_Event
Status
0x00
Status
Page Number
0x00
0 - the only available page
Maximum Page Number
0x00
0 - the only available maximum page
Extended LMP Features
"0000000000000000"
Supported extended features bitmask
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
0 - Success
ACL Data Packet Length
0x0000
Expecting parameter value
SCO Data Packet Length
0x00
Expecting parameter value
Total Num ACL Data Packets
0x0000
Expecting parameter value
Total Num SCO Data Packets
0x0000
Expecting parameter value
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
BD Address
BD_ADDR
BD Address of the device
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Failed contact Counter
Any
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Link Quality
0xFF
Spec 1.1
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
RSSI
0
Spec 1.2
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
AFH Mode
0x00
0x00 = AFH disable, 0x01 = AFH enable
AFH Channel Map
"00000000000000000000"
last AFH channel map to be broadcasted
Spec 1.2
Connection Handle
Handle
Which Clock
0x00
0x00 = Local Clock, 0x01 = Piconet Clock
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
Clock
0x00000000
BT clock
Accuracy
0x0000
Spec 3.0
Connection Handle
Handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
KEY_SIZE
0
Spec 1.1
HCI_Command_Complete_Event
Status
0x00
Status
Loopback Mode
0x00
Spec 1.1
Loopback Mode
0x00
0 - No Loopback mode enabled, 1 - Enable Local Loopback, 2 - Enable Remote Loopback
HCI_Command_Complete_Event
Spec 1.1
HCI_Command_Complete_Event
Spec 1.1
Simple_Pairing_Debug_Mode
0x00
0 - Simple Pairing debug mode disabled (default), 1 - Simple pairing debug mode enabled, 0x02 - 0xFF - Reserved for future use
HCI_Command_Complete_Event
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Inquiry command completed successfully, otherwise Inquiry command failed
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Number of Responses
0x01
Number of responses from the Inquiry
BD_ADDR responded
Get_Bd_Addr
Page Scan Repetition Mode
0x00
0 - R0, 1 - R1, 2 - R2
Page Scan Period Mode
0x00
0 - P0, 1 - P1, 2 - P2
Page Scan Mode
0x00
0 - Mandatory Page Scan Mode, 1 - Optional Page Scan Mode I
Class of Device
"000000"
Class of Device for the device
Clock Offset
any
Bit 16-2 of CLKslave-CLKmaster
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Connection successfully completed, otherwise Connection failed to Complete
Connection Handle
Get_Handle
BD Address of the Remote
BD_ADDR
Link Type
0x01
0 - SCO connection, 1 - ACL connection
Encryption_Status
0x00
0 - Link level encryption disabled, 1 - Link level encryption enabled
Spec 1.1
Timeout
5000
Time in msec to wait for the event
BD Address of the Remote
Get_Bd_Addr
Class of Device
"001F00"
Class of Device for the device, which request the connection
Link Type
0x01
0 - SCO connection requested, 1 - ACL connection requested
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Disconnection has occurred, otherwise Disconnection failed to Complete
Connection Handle
Handle
Reason
0x08
Other End Terminated Connection (0x13-0x15), Terminated by Local Host (0x16), Timeout (0x08)
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Authentication Request successfully completed, otherwise Request failed
Connection Handle
Handle
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Remote Name Request command succeeded
BD Address of the Remote
Bd_Addr
Remote Name
Any
User Friendly Descriptive Name for the remote device
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Encryption Change has occurred, otherwise Encryption Change failed
Connection Handle
Handle
Encryption Enable
0x00
0 - Turn Link Level Encryption OFF, 1 - Turn Link Level Encryption ON
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Change_Connection_Link_Key command succeeded, otherwise Request failed
Connection Handle
Handle
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Master Link Key Link Key command succeeded, otherwise request failed
Connection Handle
Handle
Key Flag
0x00
0 - Using Semi-permanent Link Keys, 1 - Using Temporary Link Key
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Read Remote Supported Features command succeeded
Connection Handle
Handle
LMP Features
"0000000000000000"
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Read Remote Version Information command succeeded
Connection Handle
Handle
LMP Version
0x00
Version of the Current LMP in the remote Bluetooth Hardware
Manufacturer Name
13
Manufacturer Name of the Remote Bluetooth Hardware
LMP Subversion
0x0000
Subversion of the Current LMP in the remote Bluetooth Hardware
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - QoS Setup command succeeded, otherwise Request failed
Connection Handle
Handle
Flags
0x00
Reserved for Future Use
Service Type
0x01
0 - No Traffic Available; 1 - Best Effort Available; 2 - Guaranteed Available
Token Rate
0x00000000
Available Token Rate in bytes per second
Peak Bandwidth
0x00000000
Available Peak Bandwidth in bytes per second
Latency
0x00000000
Available Latency in microseconds
Delay Variation
0x00000000
Available Delay Variation in microseconds
Spec 1.1
Status
0x00
0 - Success
Spec 1.1
Timeout
2000
Time in msec
Status
0x00
Number HCI commands
Any
Command Opcode
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Hardware Code
0x00
Error code to indicate various Hardware problems
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Role change has occurred, 1 - Role change failed
BD Address of the Remote
Bd_Addr
New Role
0x00
0 - Currently the Master for specified Connection Handle, 1 - Currently the Slave
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Number of Handles
0x01
The number of Handles and Data_Packets parameters pairs contained in this event
Connection Handle
Handle
Num Completed Packets
0x0000
number of packets that have been completed (transmitted or flushed) since the previous time the event was returned
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - A Mode change has occurred, otherwise request failed
Connection Handle
Handle
Current Mode
0x00
0 - Active Mode, 1 - Hold Mode, 2 - Sniff Mode, 3 - Park Mode
Interval
0x0000
Hold interval, or Sniff interval, or Beacon interval
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Num Keys
0x00
Number of Link Keys contained in this event
BD Address of the Remote
BD_ADDR
Link Key
"00000000000000000000000000000000"
Link Key for the associated BD_ADDR
Spec 1.1
Timeout
5000
Time in msec to wait for the event
BD Address of the Remote
BD_ADDR
Spec 1.1
Timeout
5000
Time in msec to wait for the event
BD Address of the Remote
BD_ADDR
Spec 1.1
Timeout
5000
Time in msec to wait for the event
BD Address of the Remote
BD_ADDR
Link Key
"00000000000000000000000000000000"
Link Key for the associated BD_ADDR
Key Type
any
0 - Combination, 1 - Local Unit, 2 - Remote Unit Key
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Opcode
any
Opcode of the HCI Command Packet
Length
any
Length of the HCI Command Packet
HCI Command Packet Data
Any
HCI command packet data segment
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Link Type
0x01
0 - SCO Buffer Overflow, 1 - ACL Buffer Overflow
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
LMP Max Slots
0x01
Maximum number of slots allowed to use for baseband packets
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
LMP Link Supervision Timeout
any
Measured in number of baseband slots. For actual timeout multiply this parm by 0.625msec. Range is 0x001-0xFFFF (0.625ms-40.9s).
Spec 1.1
Status
0x00
Connection Handle
Handle
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Read Clock Offset command succeeded, otherwise request failed
Connection Handle
Handle
Clock Offset
any
Bit 16.2 of CLKslave-CLKmaster
Spec 1.1
Timeout
5000
Time in msec
Status
0x00
0 - Success
Connection Handle
Handle
Packet Type
0x0018
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
Spec 1.1
Timeout
5000
Time in msec to wait for the event
BD Address of the Remote
BD_ADDR
Page Scan Repetition Mode
0x00
0 - R0,1 - R1, 2 - R2
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - QoS Flow Specification succeeded; 0x2c - QoS Unacceptable Parameters; 0x2d - QoS Rejected
Connection Handle
Handle
Flags
0x00
Reserved for Future Use
Flow Direction
0x00
0 - Outgoing; 1 - Incoming
Service Type
0x01
0 - No Traffic Available; 1 - Best Effort Available; 2 - Guaranteed Available
Token Rate
0x00000000
Token Rate in bytes per seconds, 0x00000000 - not specified; 0xFFFFFFFF - maximum available
Token Bucket Size
0x00000000
Token Bucket Size in bytes, 0x00000000 - not needed; 0xFFFFFFFF - maximum available
Peak Bandwidth
0x00000000
Peak Bandwidth in bytes per second, 0x00000000 - do not care
Access Latency
0xFFFFFFFF
Latency in microseconds, 0xFFFFFFFF - do not care
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Number of Responses
0x01
Number of responses from the Inquiry
BD_ADDR for each device which responded
Get_Bd_Addr
Page Scan Repetition Mode
0x00
0 - R0, 1 - R1, 2 - R2
Page Scan Period Mode
0x00
0 - P0, 1 - P1, 2 - P2
Class of Device
"000000"
Class of Device for the device
Clock Offset
any
Bit 16.2 of CLKslave-CLKmaster
RSSI
0x00
Range: -127 to +20 Units: dBm
Spec Lisbon
Timeout
5000
Time in msec to wait for the event
Number of Responses
0x01
Number of responses from the Inquiry
BD_ADDR for each device which responded
Get_Bd_Addr
Page Scan Repetition Mode
0x00
0 - R0, 1 - R1, 2 - R2
Page Scan Period Mode
0x00
0 - P0, 1 - P1, 2 - P2
Class of Device
"000000"
Class of Device for the device
Clock Offset
any
Bit 16.2 of CLKslave-CLKmaster
RSSI
0x00
Range: -127 to +20 Units: dBm
Inquiry Response Data
Will be paddad with zero to 240 bytes
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Read Remote Supported Features command succeeded
Connection Handle
Handle
Page Number
0x00
0 - the only available page
Maximum Page Number
0x00
0 - the only available maximum page
LMP_Features
"0000000000000000"
Expecting parameter value
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Connection successfully completed, otherwise Connection failed to Complete
Connection Handle
Handle
BD Address of the Remote
Bd_Addr
Link Type
0x02
0x00 - SCO, 0x02 - eSCO
Transmission Interval
0x06
Time (in slots) between two consecutive eSCO instants. Must be 0 for SCO
Retransmission Window
0x00
The size (in slots) of the retransmission window. Must be 0 for SCO
Rx Packet Length
30
Length in bytes of the eSCO payload in the receive direction. Must be 0 for SCO
Tx Packet Length
30
Length in bytes of the eSCO payload in the transmit direction. Must be 0 for SCO
Air Mode
0x00
0x00: µ-law; 0x01: A-law; 0x02: CVSD; 0x03: Transparent Data
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Connection successfully completed, otherwise Connection failed to Complete
Connection Handle
Handle
Transmission Interval
0x06
Time (in slots) between two consecutive SCO/eSCO instants
Retransmission Window
0x00
The size (in slots) of the retransmission window. Must be 0 for SCO
Rx Packet Length
30
Length in bytes of the SCO/eSCO payload in the receive direction
Tx Packet Length
30
Length in bytes of the SCO/eSCO payload in the transmit direction
Spec 1.2
Timeout
5000
Time in msec to wait for the event
Status
0x00
0 - Connection successfully completed, otherwise Connection failed to Complete
Connection Handle
Handle
Max Transmit Latency
0x00000
Maximum latency for data being transmitted from the local device to the remote device in ms[0x0000 - 0x9FFF]
Max Received Latency
0x00000
Maximum latency for data being received by the local device from the remote device in ms[0x0000 - 0x9FFF]
Min Remote Timeout
0x00000
The sub-rate zero timeout in baseband slots that the remote device can use in slots[0x0000 - 0x8000]
Min Local Timeout
0x00000
The sub-rate zero timeout in baseband slots that the local device will use in slots[0x0000 - 0x8000]
Lisbon
Timeout
5000
Time in msec to wait for the event
BD_ADDR
BD_ADDR
BD Addr of remote device involved in simple pairing process
Lisbon
Timeout
5000
Time in msec to wait for the event
BD_ADDR
BD Addr of remote device involved in simple pairing process
IO capability
0x00
IO capability of peer
OOB data present
0x00
OOB capability with remote
Authentication Required
0x00
0 - MITM Protection Not Required – Single Profile. Numeric comparison with automatic accept allowed. 1 - MITM Protection Required – Single Profile. Use IO Capabilities to determine authentication procedure. 2 - MITM Protection Not Required – All Profiles. Numeric comparison with automatic accept allowed. 3 - MITM Protection Required – All Profiles. Use IO Capabilities to determine authentication procedure
Lisbon
Timeout
5000
Time in msec to wait for the event
BD_ADDR
BD_ADDR
BD Addr of remote device involved in simple pairing process
Numeric Value
0000
Numeric value to be displayed. Valid values are decimal 0000 - 9999.
Lisbon
Timeout
5000
Time in msec to wait for the event
BD_ADDR
BD Addr of remote device involved in simple pairing process
Lisbon
Timeout
5000
Time in msec to wait for the event
BD_ADDR
BD_ADDR
BD Addr of remote device involved in simple pairing process
Timeout
5000
Time in msec to wait for the event
Status
0x00
BD_ADDR
BD_ADDR
BD Addr of remote device involved in simple pairing process
Lisbon
BD_ADDR
BD Addr of remote device involved in simple pairing process
Timeout
5000
Time in msec to wait for the event
Status
0x00
Lisbon
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
Lisbon
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
Sniff Interval
0
Sniff Attempt
0
Sniff timeout
0
Lisbon
Timeout
5000
Time in msec to wait for the event
Number of Dropped Messages
any
number of dropped messages
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Number HCI commands
any
Number of additional HCI Command Packets to be sent to the Host Controller from the Host
Command Opcode
Status
0x00
0 - Success
Parameter(1 Byte)
0x00
Expecting parameter value
Opcode
0xFF2B
set encryption key parameters.
PIN Length
16
Pin Code Length.
Pin Code Bytes
00000000000000000000000000000000
LSB to MSB in HEX
HCI_Command_Complete_Event
Opcode
0xFE46
control l2cap payload header and length for testing l2cap flow using zero l2cap payload length in the payload header.
L2cap flow
0
Sets the l2cap flow.
L2cap length flag
0
Sets the l2cap length in the header (Zero or positive).
HCI_Command_Complete_Event
Opcode
0xFD0D
Select the mode which defines how the packet type field of the Change Packet Type Event is set in regard to the EDR bits
EDR Mode
0
Show or diregard the real value of the EDR packet bit.
HCI_Command_Complete_Event
Opcode
0xFD2F
HCIPP Set Udi connection
udi_enable
0
0=Disabled 1=Enabled. When set to 1, indicates enabling pcm synchronization for udi.
synch channel
0
voice channel that the pcm should synchronize to.0 - channel one, 1- channel two
HCI_Command_Complete_Event
Opcode
0xFD08
HCIPP Write EPLC (Enhanced packet loss concealment)
EPLC enable
0x00
Enhanced packet loss control feature: 0 - diabled, 1 - enabled. Enable only when there is no active voice connection.
EPLC R value
0x00
[0-15] R parameter used in EPLC (previous packet transmissions count), recommended max of 3. Updated only when enabling.
EPLC N value
0x00
[0-15] N parameter used in EPLC (noise packet transmissions count). Updated only when enabling.
Reserved
0x00
This field is reserved for future use
HCI_Command_Complete_Event
Opcode
0xFD1F
Config pcm synch params
T_Check
2400
Monitoring time of pcm buffer [frames]
T_Hold
4000
Stabilizing time of pcm clock [frames]
Interrupt Threshold
12
Min Threshold in percentage of the sco buffer size
Complement interrupt Threshold
37
Max Threshold in percentage of the sco buffer size
PPM fix
2
delta of ppm fix in pcm synchronization
HCI_Command_Complete_Event
Opcode
0xFD05
Set Power Consumption Configuration part 1
ACTIVE current (multiplied by 8)
45
RF Standby current (multiplied by 8)
10
RX current (multiplied by 8)
295
Current consumed in rx activity (i.e. scan) per frame
Low Power Scan current (multiplied by 8)
334
Current consumed in one LPS
Page/Inquiry current (multiplied by 8)
222
Current consumed in page/inquiry activity per frame (multiplied by 8)
Big Sleep current
25
Current consumed in big sleep per frame (multiplied by 8)
Deep Sleep current
1
Current consumed in deep sleep per frame (multiplied by 32)
HV1 current
230
Current consumed in HV1 connection per frame (multiplied by 8)
HV2 current
115
Current consumed in HV1 connection per frame (multiplied by 8)
HV3 current
77
Current consumed in HV1 connection per frame (multiplied by 8)
EV3 rx current
108
Current consumed for one packet (multiplied by 8)
EV3 tx current
129
Current consumed for one packet (multiplied by 8)
2EV3 rx current
217
Current consumed for one packet (multiplied by 8)
2EV3 tx current
186
Current consumed for one packe (multiplied by 8)t
3EV3 rx current
293
Current consumed for one packet (multiplied by 8)
3EV3 tx current
243
Current consumed for one packet (multiplied by 8)
EV4 rx current
383
Current consumed for one packet (multiplied by 8)
EV4 tx current
415
Current consumed for one packet (multiplied by 8)
EV5 rx current
381
Current consumed for one packet (multiplied by 8)
EV5 tx current
413
Current consumed for one packet (multiplied by 8)
2EV5 rx current
976
Current consumed for one packet (multiplied by 8)
2EV5 tx current
753
Current consumed for one packet (multiplied by 8)
3EV5 rx current
1431
Current consumed for one packet (multiplied by 8)
3EV5 tx current
1092
Current consumed for one packet (multiplied by 8)
DM1 rx current
104
Current consumed for one packet (multiplied by 8)
DM1 tx current
126
Current consumed for one packet (multiplied by 8)
DH1 rx current
104
Current consumed for one packet (multiplied by 8)
DH1 tx current
126
Current consumed for one packet (multiplied by 8)
2DH1 rx current
207
Current consumed for one packet (multiplied by 8)
2DH1 tx current
179
Current consumed for one packet (multiplied by 8)
3DH1 rx current
280
Current consumed for one packet (multiplied by 8)
3DH1 tx current
233
Current consumed for one packet (multiplied by 8)
DM3 rx current
391
Current consumed for one packet (multiplied by 8)
DM3 tx current
423
Current consumed for one packet (multiplied by 8)
DH3 rx current
390
Current consumed for one packet (multiplied by 8)
DH3 tx current
422
Current consumed for one packet (multiplied by 8)
DM5 rx current
675
Current consumed for one packet (multiplied by 8)
DM5 tx current
717
Current consumed for one packet (multiplied by 8)
DH5 rx current
675
Current consumed for one packet (multiplied by 8)
DH5 tx current
717
Current consumed for one packet (multiplied by 8)
2DH3 rx current
998
Current consumed for one packet (multiplied by 8)
2DH3 tx current
770
Current consumed for one packet (multiplied by 8)
3DH3 rx current
1466
Current consumed for one packet (multiplied by 8)
3DH3 tx current
1119
Current consumed for one packet (multiplied by 8)
2DH5 rx current
1787
Current consumed for one packet (multiplied by 8)
2DH5 tx current
1359
Current consumed for one packet (multiplied by 8)
3DH5 rx current
2652
Current consumed for one packet (multiplied by 8)
3DH5 tx current
2004
Current consumed for one packet (multiplied by 8)
POLL rx current
49
Current consumed for one packet (multiplied by 8)
POLL tx current
69
Current consumed for one packet (multiplied by 8)
NULL rx current
49
Current consumed for one packet (multiplied by 8)
NULL tx current
69
Current consumed for one packet (multiplied by 8)
Slave RX Window current
62
Current consumed for slave window opened every frame (assuming no RX) (multiplied by 8)
TX Power Level 0 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 0 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 1 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 1 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 2 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 2 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 3 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 3 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 4 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 4 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 5 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 5 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 6 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 6 Factor for SCO
1
factor for multipling SCO current acording to power level
TX Power Level 7 Factor Per Packet
1
factor for multipling TX packets acording to power level
TX Power Level 7 Factor for SCO
1
factor for multipling SCO current acording to power level
FM current
180
currrent consumed by FM radio per frame (multiplied by 8)
HCI_Command_Complete_Event
Opcode
0xFD01
Change UART Debug Buffer Params. This command actually MOVES & RESIZES the buffer. Be carefull when using it!
Buffer Start Address
0x85400
The base address in RAM of the new UART Debug Buffer (Nominal values: 0x80000-0x853FF).
Buffer Size
512
The size (in bytes) of the new UART Debug Buffer (Nominal values: 128-3000).
HCI_Command_Complete_Event
Opcode
0xFDC5
Enable or Disable the UART Debug HW output (does not affect debug-over-HCI)
action
1
0 - Enable, 1 - Disable (as soon as the SW FIFO gets empty), 2 - Disable immediately (may casue logger corruption)
HCI_Command_Complete_Event
Opcode
0xFF76
HCIPP Set RF Link Timer
Interval
0x14
20 frames - 25 mili
HCI_Command_Complete_Event
Opcode
0xFD11
HCIPP Host Report Fref Drift Over Temperature
1st Range drift in ppm
0xFFFF
0xFFFF - don't change
1st Range High Limit
0xFF
0xFF - don't change
2nd Range drift in ppm
0xFFFF
0xFFFF - don't change
2nd Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
3rd Range drift in ppm
0xFFFF
0xFFFF - don't change
3rd Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
4th Range drift in ppm
0xFFFF
0xFFFF - don't change
4th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
5th Range drift in ppm
0xFFFF
0xFFFF - don't change
5th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
6th Range drift in ppm
0xFFFF
0xFFFF - don't change
6th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
7th Range drift in ppm
0xFFFF
0xFFFF - don't change
7th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
8th Range drift in ppm
0xFFFF
0xFFFF - don't change
8th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
9th Range drift in ppm
0xFFFF
0xFFFF - don't change
9th Range High Limit
0xFF
(do not fill this field for highest range) 0xFF - don't change
10th Range drift in ppm
0xFFFF
0xFFFF - don't change
HCI_Command_Complete_Event
Module Name
0xFF
PIN ID
1
Pin nuber (from table)
Test Mux value - Enter Value
0x00
Register Value
Test Mux number of bits - Don't Touch
0x7
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001A0F00
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A0F00
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
7
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A0F02
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A0F02
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
7
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A0F04
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A0F04
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
7
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A0F06
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A0F06
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
7
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
7
Register Value (3 bits)
Test Mux value - Enter Value
0x00
Register Value
Test Mux number of bits - Don't Touch
0x3
number of bits each pin requires
Test Mux 0 Address
0x001A2018
Test Mux 0 Address
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 0 Address
0x001A2018
Test Mux 0 Address
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A2018
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A2018
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A201A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A201A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A201A
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A201A
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A201C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A201C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
2
Register Value (3 bits)
Test Mux value - Enter Value
0x00
Register Value
(*) - bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8
bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 3 Address - Don't Touch
0x001AF12A
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001AF12A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001AF12A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001AF12A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 2 Address - Don't Touch
0x001AF12C
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 2 Address - Don't Touch
0x001AF12C
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 2 Address - Don't Touch
0x001AF12C
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 2 Address - Don't Touch
0x001AF12C
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 3 Address - Don't Touch
0x001AF12E
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux number of bits - Don't Touch
0x4
number of bits each pin requires
Test Mux 3 Address - Don't Touch
0x001AF12E
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
3
Register Value (3 bits)
Test Mux value - Enter Value
0x00
Register Value
(*) - bit 0 of this signal will appear on test_bus bits: 0,2,4,6,8
bit 1 of this signal will appear on test_bus bits: 1,3,5,7,9
Test Mux number of bits - Don't Touch
6
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001AF416
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001AF416
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001AF418
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001AF418
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001AF41A
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001AF41A
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001AF41C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001AF41C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 5 Address - Don't Touch
0x001AF41E
Test Mux 5 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux 5 Address - Don't Touch
0x001AF41E
Test Mux 5 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
4
Register Value (3 bits)
Test Mux value - Enter Value
0x00
Register Value
Test Mux number of bits - Don't Touch
4
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001A1020
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A1020
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A1020
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A1020
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A1022
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A1022
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A1022
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
8
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A1022
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A1024
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A1024
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
4
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
5
Register Value (3 bits)
Test Mux value - don't touch
0x00
Register Value
Test Mux number of bits - Don't Touch
0x3
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
3
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
6
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A300A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
9
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A300A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A300C
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A300C
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
3
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
6
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
9
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
0
Register Value (3 bits)
Test Mux value - Don't touch1
0x01
Register Value
Test Mux number of bits - Don't Touch
0x3
number of bits each pin requires
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
3
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 1 Address - Don't Touch
0x001A300A
Test Mux 1 Address - Don't Touch
Test Mux Offset - Don't Touch
6
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A300A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
9
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 2 Address - Don't Touch
0x001A300A
Test Mux 2 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300A
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A300C
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
0
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
0
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 3 Address - Don't Touch
0x001A300C
Test Mux 3 Address - Don't Touch
Test Mux Offset - Don't Touch
3
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
3
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
6
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
6
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
9
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
9
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
Test Mux 4 Address - Don't Touch
0x001A300C
Test Mux 4 Address - Don't Touch
Test Mux Offset - Don't Touch
12
offset inside test_mux register
Debug Module register - Don't Touch
0x001A300C
Register Address
Debug Module offset - Don't Touch
12
Offset within the register
Debug Module value - Don't Touch
1
Register Value (3 bits)
HCI_Command_Complete_Event
Opcode
0xFE39
HCIPP HW Reset
HCI_Command_Complete_Event
Opcode
0xFE32
HCIPP Run Long Seflf Test
HCI_Command_Complete_Event
Opcode
0xFE1E
HCIPP Get Rf Meters
HCI_Command_Complete_Event
Opcode
0xFF84
HCIPP Read Stream from EEPROM
Address
0x00000000
Size
01
1-200
HCI_Command_Complete_Param1_Event
Opcode
0xFF85
HCIPP Write Stream to EEPROM
Address
0x00000000
Size
04
1-200
Values
"0000"
stream in hex, from left to right
HCI_Command_Complete_Event
Opcode
0xFF93
HCIPP_READ_ERROR_STATISTICS
Request
3
1 - BER, 2 - PER, 3 - Both
Handle
0
HCI_Command_Complete_Event
Status
0x00
Status
Data
Any
Opcode
0xFE05
HCIPP TestMode Override PowerControl
Power_Control_Override
1
If TRUE, power control commands will never be ignored in Test Mode. 1=TRUE, 0=FALSE
HCI_Command_Complete_Event
Opcode
0xFF71
HCIPP CDC Enable
Enable CDC
0x0
1- Enable, 0- Disable
HCI_Command_Complete_Event
Opcode
0xFF3A
HCIPP Set AFH Classification Req Parameters
Classification Req Mode
1
0-Disable, 1-Enable
Classification Req Min Interval
0x1F40
slots (0-30 sec)
Classification Req Max Interval
0x3E80
slots (0-30 sec)
HCI_Command_Complete_Event
Opcode
0xFF63
HCIPP Scan All Stacks
Choice
0x01
0-scan all stacks, 1-scan registered stacks, 2- get data, 3-check program memory area
HCI_Command_Complete_Event
Opcode
0xFF64
HCIPP Scan All Buffers
HCI_Command_Complete_Event
Opcode
0xFF65
HCIPP Write Inquiry Scan Mode
Scanning Mode
0x10
0x00 - Chain Mode, 0x01 - Distributed Mode, 0x10 - Default Mode
HCI_Command_Complete_Event
Opcode
0xFF67
HCIPP Measure CPU Idle Time
Time
80
0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" BT Frames
HCI_Command_Complete_Event
Opcode
0xFF37
HCIPP Self Test Result
HCI_Command_Complete_Event
Opcode
0xFF16
HCIPP Send LMP Frame
Connection Handle
0x0001
Length
1
Number of bytes for the inserted parameters (excluding the opcode)
LMP Opcode
31
Trans started by slave
0
0- Master initiate, 1- Slave initiate
Parameters
"00"
If a parameter is longer than 1 byte, the bytes order should be reverse for that param.
HCI_Command_Complete_Event
Opcode
0xFE00
HCIPP Send LMP Frame Extended
Connection Handle
0x0001
Length
0x00
number of bytes for the inserted parameters, including lmp ext opcode
lmp opcode
0x7F
must enter a value between 124-127
lmp ext opcode
0x00
lmp opcode must be between 124-127 for usage of this field
trans started by slave
0x0
0- master initiate, 1- slave initiate
params
"0000"
if parameter is longer than 1 byte, the bytes order should be revrse for that param.
HCI_Command_Complete_Event
Opcode
0xFF18
HCIPP Set LM Bypass
new value
01
0- normal, 1-bypass LM when receiving LMPs
HCI_Command_Complete_Event
Opcode
0xFF0F
HCIPP Set LBT
Clock Value
0x3FF447F
0-min, 0x3FFFFFF -max
HCI_Command_Complete_Event
Opcode
0xFF0A
HCIPP Set Whitening Mode
Whitening Mode
01
0-enable, 1-disable
HCI_Command_Complete_Event
Opcode
0xFF92
HCIPP_CONFIGURE_ERROR_STATISTICS
Error_Statistics_Mode
0
0 - Disable, 1 - Enable
BER_Min_Resolution
1
0 - 5 possible resolution
PER_Min_Resolution
1
0 - 5 possible resolution
Auto_Reset
20
0 - 20 possible auto reset
HCI_Command_Complete_Event
Opcode
0xFF00
HCIPP Read Hardware Register
Address
0x001A0000
HW register address (32 bit)
HCI_Command_Complete_Event
Status
0x00
Status
Value
Any
The value to be read
Opcode
0xFF01
HCIPP Write Hardware Register
Address
0x001A0000
HW register address (32 bit)
Value
0x0000
The value to be written
HCI_Command_Complete_Event
Opcode
0xFD09
HCIPP Read Modify Write Hardware Register
Address
0x001A0000
HW register address (32 bit)
Value
0x0000
The value to be written. Bits that equal 0 in the mask will be ignored.
Mask
0x0000
The bit mask of the bits that will be over-written. In every bit: 0=No change 1=Change.
HCI_Command_Complete_Event
Opcode
0xFF0D
HCIPP Read Modify Write Hardware Register
Address
0x001A0000
HW register address (32 bit)
Value
0x00000000
The value to be written. Bits that equal 0 in the mask will be ignored.
Mask
0x00000000
The bit mask of the bits that will be over-written. In every bit: 0=No change 1=Change.
HCI_Command_Complete_Event
Opcode
0xFF02
HCIPP Read Memory
Address
0x00000000
Type
01
1 - UINT8, 2 - UINT16, 4 - UINT32
HCI_Command_Complete_Event
Status
0x00
Status
Data
Any
Opcode
0xFF03
HCIPP Write Memory
Address
0x00000000
Type
01
1 - UINT8, 2 - UINT16, 4 - UINT32
Value
0x00000000
Types 1,2 - MSBytes don't care
HCI_Command_Complete_Event
Opcode
0xFF04
HCIPP Read Memory Block
Address
0x00000000
Size
01
1-200
HCI_Command_Complete_Event
Status
0x00
Status
Data
any
Data
any
Opcode
0xFF05
HCIPP Write Memory Block
Address
0x00000000
Size
04
1-200
Values
"00000000"
Addresses increase from left to right
HCI_Command_Complete_Event
Opcode
0xFD97
HCIPP Write Memory Block To DTST Mem
Address
0x00190200
Size
04
1-200
Values
"00000000"
Data starts from left to right
HCI_Command_Complete_Event
Opcode
0xFD7F
HCIPP Read Memory Block From DTST Mem
Address
0x00190200
Size
04
1-200
HCI_Command_Complete_Event
Status
0x00
Status
Data
any
Opcode
0xFC06
HCIPP Write BD Address
New BD Addr
BD_ADDR
HCI_Command_Complete_Event
Opcode
0xFF06
HCIPP Set Frequency Mode
Frequency Mode
00
0-79 Freqs, 1-23 (Spain), 2-23 (France), 3-Single Freq. Mode
Single Frequency Index
00
(0-22) / (0-78) in 23 / 79 Freq. Modes
HCI_Command_Complete_Event
Opcode
0xFF07
HCIPP Get Frequency Mode
HCI_Command_Complete_Event
Status
0x00
Status
Frequency
Any
Opcode
0xFF1A
HCIPP_CONFIGURE_ARM_IO
Port number
0x0
0-min, 0x12 -max
port direction
0x0
1-Input, 0 -output
HCI_Command_Complete_Event
Opcode
0xFF1B
HCIPP Write ARMIO Port
ARMIO Port Number
00
Range 0-18, except 0 & 9
ARMIO Port Level
0
0=False, 1=True
HCI_Command_Complete_Event
Opcode
0xFF1C
HCIPP Read ARMIO Port
ARMIO Port Number
0
Range 0-18, except 0 & 9
HCI_Command_Complete_Event
Status
0x00
Status
Value
0x00
The value to be read
Opcode
0xFF26
HCIPP Set Supported Features
Byte
0xFF
0 - Byte #0 , 1 - Byte #1 , 2 - Byte #2
Bit
0xFF
0..7 - single bit , 0xXX - WHOLE Byte value
Support
0xFF
0 - not supported , 1 - supported , FF - change WHOLE Byte
HCI_Command_Complete_Event
Opcode
0xFF22
HCI_Command_Complete_Event
Status
0x00
Status
Enabled Mask
0x00
Bit mask of active patch traps
ReleaseMajor
0x00
Main Release Major Number – The upper byte of the base SW version that the patch package is referred to.
ReleaseMinor
0x00
Main Release Minor Number – The lower byte of the base SW version that the patch package is referred to.
PackageID
0x00
Patch Trap Package ID – A unique number for patch package. A patch package contains up to 32 different patch traps.
Build Number
0x00
Patch Trap Package Build Number – A unique number for the patch package build number. This is a serial number within the patch package.
Opcode
0xFF24
HCIPP Get Encryption Key Params
HCI_Command_Complete_Event
Status
0x00
0 - success, 1 - illegal command
Prefered Key Size
0x00
Max Key Size
0x00
Min Key Size
0x00
Opcode
0xFF25
HCIPP Set Encryption Key Params
Preferred Key
0x10
Default 16
Max Key
0x10
Default 16
Min Key
0x05
Default 5
HCI_Command_Complete_Event
Opcode
0xFF32
HCIPP Set DBG Pins
DBG1 Value
0xFF
The value to set to the DBG1 pin (0xFF=Don't change)
DBG2 Value
0xFF
The value to set to the DBG2 pin (0xFF=Don't change)
DBG3 Value
0xFF
The value to set to the DBG3 pin (0xFF=Don't change)
DBG4 Value
0xFF
The value to set to the DBG4 pin (0xFF=Don't change)
DBG5 Value
0xFF
The value to set to the DBG5 pin (0xFF=Don't change)
DBG6 Value
0xFF
The value to set to the DBG6 pin (0xFF=Don't change)
DBG7 Value
0xFF
The value to set to the DBG7 pin (0xFF=Don't change)
DBG8 Value
0xFF
The value to set to the DBG8 pin (0xFF=Don't change)
HCI_Command_Complete_Event
Opcode
0xFF33
HCIPP Set QOS Interval
Connection Handle
0x0001
QOS Interval
19
Poll period (a poll will be sent every poll period frames) Range: 1 - 255.
HCI_Command_Complete_Event
Opcode
0xFF39
HCIPP Set AFH Mode
Connection Handle
0x0001
0x00FF - Set AFH mode for all connections, otherwise - choose connection Handle
AFH Mode
1
0-Disable, 1-Enable
HCI_Command_Complete_Event
Opcode
0xFF68
HCIPP Enable Protocol Viewer
Enable
1
0-Disable, 1-Enable
HCI_Command_Complete_Event
Opcode
0xFF83
HCIPP Goto Address
Address
0x00028151
Param 1
0x00000000
Param 2
0x00000000
Param 3
0x00000000
Param 4
0x00000000
HCI_Command_Complete_Event
Opcode
0xFE0E
HCIPP Write I2C Register
Slave ID
0x71
Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50
PVT CLK
0
Working Frequency
0x190
Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)
Sub Address
0x00
0-255. I2C Slave device internal register address.
Data Length
0x01
1-16. Data Length (in bytes).
Data
"00"
Data stream in hex, from left to right
HCI_Command_Complete_Event
Opcode
0xFD36
HCIPP Write I2C Register
Slave ID
0x71
Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50
PVT CLK
0
Working Frequency
0x190
Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)
Address Access Size
0x01
1-2 bytes of address (Max of 64Kbyte address space).
Sub Address
0x0000
I2C Slave device internal register address. 1-2 bytes, according to address access size field.
Data Length
0x01
1-16. Data Length (in bytes).
Data
"00"
Data stream in hex, from left to right
HCI_Command_Complete_Event
Opcode
0xFE0F
HCIPP Write I2C Register
Slave ID
0x71
Codec 1: 0x71, Codec 2: 0x1A, E2PROM: 0x50
PVT CLK
0
Working Frequency
0x190
Codec = 0x190 (400 KHz), E2PROM = 0x64 (100 KHz)
Sub Address
0x00
0-255. I2C Slave device internal register address.
HCI_Command_Complete_Param1_Event
HCIPP_READ_I2C_REGISTER
Opcode
0xFE10
HCIPP Write SCO Configuration
Connection Type
0x01
0 - Codec , 1 - HCI , 0xFF - don't change
TX buffer size (for host)
120
30-255 bytes, 0x0 - don't change
TX buffer max latency
511
1-720 bytes, 0 - don't change
Accept packet with bad CRC
0xFF
0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change
HCI_Command_Complete_Event
Status
0x00
Status
TX Buffer size
100
0x1-0xFF TX buffer size for next channel to be activated
Num of buffers
0x0
0x0-0xFF - number of SCO TX buffers for next channel to be activated
Opcode
0xFE11
HCIPP Read SCO Configuration
HCI_Command_Complete_Event
Status
0x00
Status
CH#1 Connection type
0x1
0 - Codec , 1 - HCI
CH#1 TX buffer size (for host)
100
[0x1-0xFF] bytes
CH#1 Num of buffers
3
[0x0-0xFF] - number of SCO TX buffers
CH#1 TX buffer max latency
511
[1-511] bytes
CH#1 Accept packet with bad CRC
0xFF
0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change
CH#2 Connection type
0x1
0 - Codec , 1 - HCI
CH#2 TX buffer size (for host)
100
[0x1-0xFF] bytes
CH#2 Num of buffers
3
[0x0-0xFF] - number of SCO TX buffers
CH#2 TX buffer max latency
511
[1-511] bytes
CH#2 Accept packet with bad CRC
0xFF
0x0/0x1 - Reject/Accept packet with bad CRC, 0xFF - Don't change
Opcode
0xFE1F
HCIPP Get System Status
HCI_Command_Complete_Event
Status
0
0 - Success, 1 - Illegal command
SW Version ("Major")
0
X
SW Version ("Internal")
0
Z
Chip Revision
0
HW Revision
Chip mode
0
0 - Palau, 1 - TI, 2-3 - Reserved, 4 - Borneo, 5 - Cayman
ROOT Clock
0
in KHz
Slow Clock used
0
0 - Internal, 1 - External
Process Type
1
0 - Nominal, 1 - Weak, 2 - Strong
Deep Sleep Mode
0
0 - Disabled, 1 - Palau, 2 - HCILL
Whitening Mode
0
0 - Enabled, 1 - Disabled
CDC Mode
0
0 - Disabled, 1 - Enabled
Self Test Result
0
0 - Failed, 1 - Passed
Hopping Mode
0
0 - Freq Hopping, 1 - Single Freq Tx & Rx, 2 - Only Tx Single Freq, 3 - Only Rx Single Freq
HCI UART Baud Rate
0
in bps
Temperature Index
1
0 - Hot. 1 - Room. 2 - Cold. 3 - Warm. 4 - Cool
Detected Temperature
0
in Degrees (C), 0x00-0x7F Positive Value, 0xFF-0x80 Negative Value
I2C Status
0x00
bit 0 - is I2C enabled, bit 1 - is E2PROM connected, bit 2 - is Codec connected
FREF/TCXO Clock
0
in KHz
PLL Sharing Running Mode
0x00
Relevant for Wilink 7 Only.
Opcode
0xFE28
HCI_VS_Set_Pcm_Loopback_Configuration
PCM loopback enable
0x01
0 - Stop PCM loopback operation, 1 - Start PCM loopback operation
HCI_Command_Complete_Event
Opcode
0xFE2C
HCIPP Set Minimum Deep Sleep Time
Minimum Deep Sleep Time [ms]
4
Minimum Deep Sleep Time [in frames], will not go to deep sleep for less than that time.
HCI_Command_Complete_Event
Opcode
0xFE2F
HCIPP Set Max Voice Connections. Affects also Local Loopback
Max Voice Connections
2
0-2 Number of Voice Connections
HCI_Command_Complete_Event
Opcode
0xFE34
HCIPP Set Max ACL Connections. Affects also Local Loopback
Max ACL Connections
7
0-7 Number of ACL Connections
HCI_Command_Complete_Event
Opcode
0xFE37
Start VS Commands Lock (start of protected part of script)
Major Version Number
0
The Major number of the SW Version (X)
Minor Version Number
0
The Minor number of the SW Version (Z)
HCI_Command_Complete_Event
Opcode
0xFE38
Stop VS Commands Lock (end of protected part of the script)
HCI_Command_Complete_Event
Opcode
0xFE3A
HCIPP Calculate ROM Checksum
HCI_Command_Complete_Event
Status
0x00
Status
Checksum
0x00000000
The ROM Checksum
Timeout
5000
Timeout in msec
Checksum
0x00000000
The ROM Checksum
Opcode
0xFE3b
Start VS Commands Lock according package (start of protected part of script)
Package type
0
chips with this package type should accept VS commands
HCI_Command_Complete_Event
Opcode
0xFD0F
HCIPP enables/disables the BRF6300 BB PLL
PLL Enable
0
0 - Disable, 1 - Enable
HCI_Command_Complete_Event
Opcode
0xFD10
HCIPP Host Report Fref Drift
Initial FREF drift
20
Initial FREF drift in ppm
Number of temperature ranges
0
Number of temperature ranges that infuance the FREF clock
HCI_Command_Complete_Event
Opcode
0xFD02
HCIPP Long Buffers Mode
Mode
0
0-Disable (default), 1-Enable (1021 bytes)
HCI_Command_Complete_Event
Opcode
0xFD03
ontrol the number of command buffers reported to the host
Cmd control
1
Number of maximum command buffers to report to the host. (1-4)
HCI_Command_Complete_Event
Opcode
0xFD04
HCI_VS_Set_Pcm_Loopback_Configuration
PCM loopback delay
64
delay in sample units [0-1348]
HCI_Command_Complete_Event
Opcode
0xFD06
HCIPP Write CODEC Configuration
PCM clock rate
2048
[64-16000] The PCM clock rate is between 64k to 4096k (Master mode) or 64K to 16M (Slave mode), it influence other params like: wait cycles, freq rate calcs and therefore shall be configured even if external clock is used
PCM direction/role
0x00
PCM clock and fsync direction: 0x00 - output (Master on PCM bus) sampled on rising edge. 0x01 - input (Slave on PCM bus).
Frame sync frequency
8000
[100Hz-173KHz] Actual frame sync frequency in Hz.
Frame sync duty cycle
0x0001
0x0000 - 50 % of Fsync period, [0x0001-0xFFFF] - Number of PCM clock cycles
Frame sync edge
0x00
0x00 - Driven/sampled at rising edge, 0x01 - Driven/sampled at falling edge
Frame sync polarity
0x00
0x00 - Active-high, 0x01 - Active-low
Reserved
0x00
This field is reserved for future use - Must be set to 0.
CH1 data out size
0x0010
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
CH1 data out offset
0x0001
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
CH1 out_edge
0x00
Data driven: 0x00 - rising edge, 0x01 - falling edge
CH1 data in size
0x0010
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
CH1 data in offset
0x0001
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
CH1 in_edge
0x01
Data sampled: 0x00- rising edge, 0x01 - falling edge
Reserved
0x00
This field is reserved for future use - Must be set to 0.
CH2 data out size
0x0010
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
CH2 data out offset
0x0011
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
CH2 out_edge
0x00
Data driven: 0x00 - rising edge, 0x01 - falling edge
CH2 data in size
0x0010
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
CH2 data in offset
0x0011
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
CH2 in_edge
0x01
Data sampled: 0x00- rising edge, 0x01 - falling edge
Reserved
0x00
This field is reserved for future use - Must be set to 0.
HCI_Command_Complete_Event
Opcode
0xFD07
HCIPP Write CODEC Configuration
PCM clock shutdown
0x00
PCM clock shutdown feature: 0x00 - disabled. 0x01 - enabled. Time of start stop is defined in the following 2 fields.
PCM clock start
0x0000
[0x0000-0xFFFF] Number of PCM clock cycles relative to the PCM frame sync to start PCM clock (for example - start 2 clocks before frame sync).
PCM clock stop
0x0000
[0x0000-0xFFFF] Number of PCM clock cycles relative to the PCM frame sync to stop PCM clock (for example - stop 20 clocks after frame sync).
Reserved
0x00
This field is reserved for future use - Must be set to 0.
CH1 data in order
0x04
bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits
CH1 data out order
0x04
bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits
CH1 data out mode
0x02
0 - Always 3-state (input), 1 - Always output, 2 - Switch to 3-state (input) when idle
CH1 data out dup
0x00
0 - Retransmit last sample when no data available, 1 - Transmit DUP_VALUE when no data available
CH1 tx_dup_value
0x000000
Replacement value to transmit when no data is available. ONLY 24-bits
CH1 data quant
0x00
1 - Byte-wise mode, 0 - Bit-wise mode
Reserved
0x00
This field is reserved for future use - Must be set to 0.
CH2 data in order
0x04
bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits
CH2 data out order
0x04
bit 0: 0-Data driven MSB-first; bit 1: 1-swap bytes within the sample in bit-wise mode; bit 2: 1-Shift sample by (24|16-dout_size) bits
CH2 data out mode
0x02
0 - Always 3-state (input), 1 - Always output, 2 - Switch to 3-state (input) when idle
CH2 data out dup
0x00
0 - Retransmit last sample when no data available, 1 - Transmit DUP_VALUE when no data available
CH2 tx_dup_value
0x000000
Replacement value to transmit when no data is available. ONLY 24-bits
CH2 data quant
0x00
1 - Byte-wise mode, 0 - Bit-wise mode
Reserved
0x00
This field is reserved for future use - Must be set to 0.
HCI_Command_Complete_Event
Opcode
0xFD2B
hcill_parameters
inactivity_timeout
80
Time from UART inactivity to sending SLEEP_IND. 0=BT never sends sleep_ind. Unit=Frames, 80 =100msec
RESERVED (retransmit_timeout)
0xFFFF
0xFFFF=ignore this field. Timeout for resending WAKEUP_IND. 0=no retransmission. Unit=Frames
RESERVED (rts_minimum_pulse_width)
0xFF
0xFF=ignore this field. RTS pulse may accompany WAKEUP_IND packet. 0=disable pulse. Unit=Micro seconds
HCI_Command_Complete_Event
Opcode
0xFF36
HCIPP Update Uart HCI Baudrate
Uart Baudrate
115200
Baud Rate - in bit/sec units.
HCI_Command_Complete_Event
Opcode
0xFF35
HCIPP Set Uart HCI Baudrate
Divider
0
Baudrate Uart Divider
Oversampling
0
Baudrate Uart Oversampling
Swallow Period
0
Baudrate Uart Swallow Period
HCI_Command_Complete_Event
Opcode
0xFD4B
HCIPP enable loopback at UART
HCI_Command_Complete_Event
Opcode
0xFD41
configures TI SPI Interface
Bits Direction
0
0 - MSb First, LSb First
Clock Polarity
1
0 - Output changed on falling edge, Sampling on rising edge, 1 - Output changed on rising edge, Sampling on falling edge
clock_frequency
0
Clock Frequency
miso_tri_state_enable
0
0 - BTSPI MISO is output always , 1 - BTSPI MISO is in tri-state mode when the CS is de-asserted
fast_wakeup_enable
0
0 - Disable, 1 - Enable
BT SPI Mode
0
0 - eSPI (H4), 1 - TI SPI (H4 Packet wise)
BTSPI MISO Pull Enable
0
0 - Disable, 1 - Enable
BTSPI MOSI Pull Enable
0
0 - Disable, 1 - Enable
BTSPI Clock Pull Enable
0
0 - Disable, 1 - Enable
BTSPI IRQ Pull Enable
0
0 - Disable, 1 - Enable
BTSPI CS Pull Enable
0
0 - Disable, 1 - Enable
BTSPI Swap mode
0
0 disable swap mode; 1 enable swap mode
BTSPI Block SPI IRQ
0
0 - Disable (SW Control); 1 - Enable (HW Control); 2 - Dynamic Control
DO IO Strength
0
5500 Only: 0x00 - Don't change; 0x2 - 2mAmp; 0x4 - 4mAmp; 0x6 - 6mAmp; 0x8 - 8mAmp
Reserved
0
Reserved for future use
Reserved
0
Reserved for future use
HCI_Command_Complete_Event
Opcode
0xFD35
HCI_VS_I2C_Write_to_FM
Fm_Opcode
0
opcode of FM module [8 bits]
Length
0x02
Data
0x0000
Data to write
Length
0x06
Address
0x00000000
Address to write
Data
0x0000
Data to write
Length
2
Data Length 0-1024 [16 bits]
Data
"0000"
start Address in hex (16 bit), and new code
Length
04
0-200 ???
Data
"00:00:00:00"
Bytes are sent from left to right
HCI_Command_Complete_Event
Opcode
0xFD33
HCI_VS_I2C_Read_FM
FM_Opcode
0
opcode of FM module [8 bits]
Length
0x02
Length
0x0003
Data Length [16 bits], should be multiple of 3, Max Length 250
HCI_Command_Complete_Event
Status
0x00
Status
Value
0x0000
Fm Read Value
RDS data
RDS data
Opcode
0xFD45
HCI_VS_I2C_Read_FM_HW_Register_32_bit_address
Address
0x00000000
Fm register address [32 bits]
HCI_Command_Complete_Event
Status
0x00
Status
Value
"0x0000"
Fm HW Register Value
Opcode
0xFD37
HCI_VS_I2C_FM_POWER_MODE
Enable Type
0
Enable type for FM via I2C
HCI_Command_Complete_Event
Opcode
0xFD3A
HCI_VS_I2C_FM_CHANGE_I2C_ADDRESS
Dev_Addr
0
7 bits I2C Device Address
Change_FM_I2C
0
0 - change only awake device address.1 - change device address on both awake and FM I2C modules
HCI_Command_Complete_Event
Opcode
0xFDB1
HCI_VS_SLIMBUS_CONFIGURATION
slimbus_on
0
1: turn SLIMbus on, 0: turn slimbus off, 0xFF: don't change
audio_enabled
1
SLIMbus Audio: 1: enable, otherwise: don't change. Valid only if slimbus_on = 1
hci_enabled
1
SLIMbus HCI: 1: enable, otherwise: don't change. Valid only if slimbus_on = 1
SLIMbus_core_off_during_pause
0
Should SLIMbus core be turned off while the SLIMbus clock is paused: 1: enable, 0: disable, 0xFF: don't change.
SLIMbus_core_off_during_OutOfBand_sleep
0
Should SLIMbus core be turned off while in Deep-Sleep using OutOfBand protocol, regardless of clock pause: 1: enable, 0: disable, 0xFF: don't change.
Use_KALDO_when_BT_is_in_deep_sleep
0
Should KALDO be used for driving the SLIMbus when the BT is in Deep-Sleep (rather than staying with DIGLDO): 1: enable, 0: disable, 0xFF: don't change.
debug_traces_level1_enabled
1
SLIMbus Debug Level1 Traces (to Logger): 1: enable, 0: disable, 0xFF: don't change.
debug_traces_level2_enabled
1
SLIMbus Debug Level2 Traces (to Logger): 1: enable, 0: disable, 0xFF: don't change.
Reserved_1
0
For future use
Reserved_2
0
For future use
Reserved_3
0
For future use
Reserved_4
0
For future use
Reserved_5
0
For future use
Reserved_6
0
For future use
Reserved_7
0
For future use
Reserved_8
0
For future use
Reserved_9
0
For future use
Reserved_10
0
For future use
Reserved_11
0
For future use
Reserved_12
0
For future use
HCI_Command_Complete_Event
Opcode
0xFDB2
sbis_parameters
inactivity_timeout
80
Time from SLIMbus HCI inactivity to sending TX_SUSPENDED. 0=BT never sends TX_SUSPENDED. Unit=Frames, 80=100msec
rx_should_reset_inactivity_timer
0
Values: 0xFF=Don't change, 0=RX activity does not influence TX suspending mechanism, 1=RX activity resets inactivity timer and sends TX_ENABLE request if TX is suspended
auto_tx_enable_upon_rx_enable
1
Values: 0xFF=Don't change, 0=RX_ENABLE does not influence TX suspending mechanism, 1=Receiving RX_ENABLE from host will force sending TX_ENABLE request if TX is suspended, and will also reset the inactivity timer
HCI_Command_Complete_Event
Opcode
0xFD0C
HCIPP Sleep Mode Configurations. Use output io BT_FUNC 5 for TRIO alone!
Big Sleep Enable
1
0-disable, 1-enable
Deep Sleep Enable
0
0-disable, 1-enable
Deep Sleep Mode
0xFF
Deep Sleep Protocol Mode
Output IO Select
0xFF
Output IO Select
Output Pull Enable
0xFF
0-disable, 1-enable, 0xFF Don't Change
Input Pull Enable
0xFF
0-disable, 1-enable, 0xFF Don't Change
Input io Select
0xFF
IO on which BT_wakeup will be assereted by host
BORNEO Deassertion Timout
100
Deassertion timout in milisecond (BORNEO mode only)
HCI_Command_Complete_Event
Opcode
0xFD23
sets which band the baseband PLL should work with and enables forcing the dividers.
PLL_band
0
40MHz output (Europe) / 48MHz output (Japan) / 0xFF don't change
M Value
0
Value For M divider. 0xFFFF for don't change
N Value
0
Value For N divider. 0xFFFF for don't change
HCI_Command_Complete_Event
Opcode
0xFD59
Configure the ACL data statistics parameters. Once called, data throughput statistics will be printed to the logger
ACL Statistics Enable
0x1
Enable/Disable Statistics printings to the logger
Printings Interval
5000
Time in milisec between one logger printing to another not including sleep time
Get Static from Handle
0xFF
0xFF- Don't print,0x00-0x06 print static from the current handle.
HCI_Command_Complete_Event
Status
0
0 - Success
RX Result
0
TX Result
0
NACK Ratio
0
Opcode
0xFD2E
HCIPP Set Low Power Scan Params
Enable
0x1
0 - Disable, 1 - Enable
Disable sweeps length
600
Number of scans after LPS exit to return back to LPS
Positive sweeps Threshold
5
Number of consequent positive scans to exit LPS
Enable LPS in active connection
0
1 - run LPS scan in active connection. 0 - run LPS only in Idle mode
minimum time between scan
30
The minimum time betweet to LPS scan in frame (1.25 msec)
scans history max length
7
The number of lps scan results to remember for positive scans counting (max: 32)
Reserved
0
Reserved
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD66
HCIPP Setup Gemini interface in BTIP
Enable Mode
0xFF
0x4-Soft Gemini Palau; 0x5-Soft Gemini Borneo; All others - Reserved;
PA Configuration
0xFF
0xFF - Don't change; bit0 - PA off polarity (0 = Active Low)
TX_mode
0xFF
Configures the TX mode
RX_mode
0xFF
Configures the RX mode
Priority select
0xFFFF
Connection handle select
0xFF
0x0-0xEFF - select the connection handle; 0xF000 - Disable priority on all handles; 0xFFFF - Don't change
Connection handle enable
0xFF
0 - Disable; 1- Enable
Freq_mask_enable
0xFF
0xFF - Do not change; 0x0 - No Freq mask; 0x1 - Enable freq mask on WLAN 0; 0x2 - Enable freq mask on WLAN 1; 0x3 - Enable freq mask on WLAN0 and WLAN1
Freq mask
"FFFFFFFFFFFFFFFFFFFF"
Frequency mask
WLAN013_BT_IP_selected_pin
0xFF
ORCA Only
0: Mux WLAN0, WLAN1 and WLAN3 on the FM_I2S i/f ports, WLAN0 on FM_I2S_DI, WLAN1 on FM_I2S_WS, WLAN3 on FM_I2S_DO
1: Mux WLAN0, WLAN1 and WLAN3 on the FM I2C i/f ports, WLAN0 on FM_IRQ, WLAN1 on FM_SDA, WLAN3 on FM_SCL
2: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_FUNC2, WLAN1 on BT_FUNC1, WLAN3 on FM_I2S_DO
NL5500+1270
3: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on FM_SDA/BT_FUNC4, WLAN1 on FM_IRQ/BT_FUNC5, WLAN3 on BT_GPIO5/BT_FUNC7
NL5500
4: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_GPIO2/BT_FUNC4, WLAN1 on BT_GPIO4/BT_FUNC6, WLAN3 on BT_GPIO5/BT_FUNC7
5: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on FM_SDA/BT_FUNC4, WLAN1 on FM_I2S_CLK/BT_FUNC6, WLAN3 on FM_I2S_FSYNC/BT_FUNC7
Quattro
6: Mux WLAN0, WLAN1 and WLAN3 as seen below, WLAN0 on BT_FUNC5, WLAN1 on BT_FUNC6, WLAN3 on BT_FUNC7
WLAN2_BT_IP_selected_pin
0xFF
0: Mux WLAN2 on the FM_I2S_CLK port, 1: Mux WLAN2 on the CLK_REQ_OUT
Not Used For NL5500 and Quattro
Wlan0 pull enable
0xFF
0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled.
For Quattro:
00 => IP pull control (default).
01 => Pull Up.
10 => Pull down.
11 => Pull disabled.
Wlan1 pull enable
0xFF
0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled.
For Quattro:
00 => IP pull control (default).
01 => Pull Up.
10 => Pull down.
11 => Pull disabled.
Wlan2 pull enable
0xFF
0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled. Not supported for QUATTRO
Wlan3 pull enable
0xFF
0xFF - Don't change; 0 - Pull set by IP, 1 - Input pull (on selected input IO) is disabled; 2 - Input pull (on selected input IO) is enabled
For Quattro:
00 => IP pull control (default).
01 => Pull Up.
10 => Pull down.
11 => Pull disabled.
Disable WLAN
0x0
0x0 - Don't do anything; 0x1 - Disable WLAN;; 0x2 - Enable BT mechanism for NL5500 +1270
HCI_Command_Complete_Event
Opcode
0xFD68
HCIPP Setup sync scans to GSM wakeup
Enable Mode
0xFF
0x0 - Enable; 0x1-Enable on BT_FUNC1; 0x2-Enable on BT_FUNC2; 0x3-Enable on BT_FUNC3; 0x4-Enable on BT_FUNC4;0x5-Enable on BT_FUNC5; 0x7-Enable on BT_FUNC7; 0xFF-Disable
Clock active pull enable
0xFF
0xFF - Don't change; 0x0 - Input pull disabled; 0x1 Input pull enabled
min page scan interval
0x0800
Minimal interval in baseband slots between page scans. Range 0x0012 - 0x1000
min inquiry scan interval
0x0800
Minimal interval in baseband slots between inquiry scans. Range 0x0012 - 0x1000
IRQ wakeup type
0xFF
The type of the wakeup: 0x0 - Slow, 0x1 - Fast; 0xFF do not change
HCI_Command_Complete_Event
Opcode
0xFD58
HCIPP Config Power Mng Params
Enable flag
1
When set to 1, indicates enabling of power management algorithm
rssi_thl_acl (dBm)
-60
rssi_thl_sco (dBm)
-60
rssi_thl_edr3 (dBm)
-60
rssi_thh_acl (dBm)
-40
rssi_thh_sco (dBm)
-40
rssi_thh_edr3 (dBm)
-40
rssi_vhth (dBm)
-20
rssi_vhth_edr3 (dBm)
-15
rssi_th_sensitivity
-80
snr_thl
0
0 - disable SNR condition.
snr_edr3_thl
0
0 - disable SNR condition.
snr_thh
0
0 - disable SNR condition.
snr_edr3_thh
0
0 - disable SNR condition.
bad_sync_count_th_sco
3
fec_ration_thl_sco
20
fec_ration_thh_sco
10
fec_min_bits_acl
144
fec_min_bits_sco
144
crc_ratio_thl_acl
60
crc_ratio_thh_acl
2
min_pkts_acl
50
Minimum number of packets to calculate CRC statistics
power_decision_time
2
The interval, in which a decision is made whether to increase/decrease or not to change peer tx power (decision interval = power_decision_time x100ms)
power_acl_response_time
1
On ACL channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)
power_sco_response_time
1
On E/SCO channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)
power_edr3_response_time
1
On EDR3 channel the minimal delay between the last command requested to increase power or decrease to the command request to increase power (delay interval = power_decision_time x power_response_time x 100ms)
power_delay_time
3
The minimal delay between the last command requested to increase power or decrease to the command request to decrease power (delay interval = power_delay_time x power_decision_time x 100ms)
deep_fade_rssi_delta1 (dBm)
-10
rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1])
deep_fade_rssi_delta2 (dBm)
-20
rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])
deep_fade_edr3_rssi_delta1 (dBm)
-10
rssi threshold between current measure and the previews measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-1]
deep_fade_edr3_rssi_delta2 (dBm)
-20
rssi threshold between current measure and the one before the preview measure to make decision if we in deep fade.(delta2 = rssi[N] - rssi[N-2])
HCI_Command_Complete_Event
Opcode
0xFD64
HCIPP Config CQDDR Params
Enable flag
1
0=Disabled 1=Enabled. When set to 1, indicates enabling of the CQDDR algorithm.
reserved
0
rssi_on_max_slot_1_thr
-69
-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 1.
rssi_off_max_slot_1_thr
-69
-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 1.
rssi_on_max_slot_3_thr
-67
-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 3.
rssi_off_max_slot_3_thr
-67
-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 3.
rssi_on_max_slot_5_thr
-67
-100..100. The RSSI threshold for changing the CQDDR state to EDR2 when max slot is 5.
rssi_off_max_slot_5_thr
-67
-100..100. The RSSI threshold for changing the CQDDR state to EDR3 when max slot is 5.
rssi_thr_offset
0
-100..100. The RSSI threshold offset.
ber_fec_on_thr
1
0..65535. The BER threshold for changing the CQDDR state to FEC_ON.
ber_fec_off_thr
6000
0..65535. The BER threshold for changing the CQDDR state to FEC_OFF.
ber_fec_off_esco_thr
0
0..65535. The BER threshold for changing the CQDDR state to FEC_OFF at eSCO connection. ***RESERVED***
per_fec_on_max_slot_1_thr
10
0..255. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 1. ***RESERVED***
per_fec_off_max_slot_1_thr
0
0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 1. ***RESERVED***
per_fec_on_max_slot_3_thr
30
0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 3.
per_fec_off_max_slot_3_thr
0
0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 3. ***RESERVED***
per_fec_on_max_slot_5_thr
30
0..100 The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR2 when max slot is 5.
per_fec_off_max_slot_5_thr
0
0..100. The PER percentage threshold (1unit = 10%) for changing the CQDDR state to EDR3 when max slot is 5. ***RESERVED***
enable in basic rate
0
0 - Disable, 1-Enable Cqddr in basic rate
timer_thr
3
0..100. The minimum time (1 unit = 400ms) before returning to EDR3 due to good hec & crc. ***RESERVED***
Debug handle
0xFFFF
Connection handle.0xFFFF - debug not valid
Enable/Disable Cqddr in Tx/Rx
0x11
0x00:tx disable,rx disable;0x10:tx enable,rx disable;0x01:tx disable,rx enable;0x11;tx enable,rx enable
HCI_Command_Complete_Event
Opcode
0xFD1C
HCIPP configures the BTIP fast clock configuration
XTAL Enable
0xFF
0 - Disable, 1 - Enable, 0xFF - Don't Change
Normal Wakeup Settling Time
5000
Normal WakeUp settling time (in uS)
Fast Wakeup Settling Time
2000
Fast WakeUp settling time (in uS)
Fast wakeup enable
0xFF
0x00 - disabled For BT and FM. 0x01 - enabled For BT, disabled for FM. 0x10 - enabled For FM, disabled for BT. 0x11 - enabled For BT and FM. 0xFF - Dont Change.
XTAL Boost Gain
0xFF
This parameter determines the initial gain of the OSC cell
XTAL Normal Gain
0xFF
This parameter determines the steady state gain of the OSC cell
BT TX Slicer Trim
0xFF
This parameter determines the Slicer gain when BT is during TX/RX
BT idle Slicer Trim
0xFF
This parameter determines the Slicer gain when BT is during TX/RX
Fast Clock AC/DC Coupling
0xFF
0 - DC Coupling, 1 - AC Coupling
Slow Clock Accuracy
250
Slow clock drift (PPM)
Clock Source
0
0 for FREF, 1 for TCXO (5500 only)
GCM extra settling time
0
Extra settling time to add to default settling time
Reserved
0
Reserved
HCI_Command_Complete_Event
Status
0x00
0 - Success, Else - Error
Opcode
0xFD6A
HCIPP Configure Clock Sharing
Polarity
1
0- Active Low Polarity, 1- Active High Polarity
Clock Sharing Output Mode
0
Clock Sharing Outout Mode
Output pull Enable
0
0-disable; 1-enable;
Pull configuration
0
Only relevant for 5500: 0-disable pull; 1-enable pull;
HCI_Command_Complete_Event
Opcode
0xfd63
HCI_VS_Configure_channel_classification_params
Pattern length in ACTIVE
15
number of scans in an AFH pattern, value must be less than 16
Pattern length in SHORT_SNIFF (only)
7
number of scans in an AFH pattern, value must be less than 16
Pattern length in LONG_SNIFF (only)
4
number of scans in an AFH pattern, value must be less than 16
SHORT to LONG SNIFF transition threshold
100
Threshold Tsniff period which will be considered as short / longsniff [in slots ] comparison is minimal_T_sniff to threshold , minimal_T_sniff includes subrating
Active pattern timing array
0x89abcdef89abcdef
array holding the number of idle frames between scans (in a pattern)
each nibble (value 1 to 15) represents the time between two scans
nibble 0,(byte[0] bits[3:0] is the number of frames between the first and second scan
nibble 1,(byte[0] bits[7:4] is the number of frames between the second and third scan
Const interferer sequence count
3
the number of scans where a narrow band interferer must be seen in order to be classified as bad (and removed)
Clear channel sequence count
6
the number of patterns where a channel must be clean in order to be classified as good (and returned)
Increase priority rejection threshold
10
the number of times an AFH scan can be "bumped" by other activities before raising its priority
Number of slots between scan patterns
800
the number of slots from the end of a pattern to the activation of another
C_to_I threshold 0 2
75
threshold between grade 0 to 2, 17dB = 7.07 >> times 10 is 71
C_to_I threshold 2 3
56
threshold between grade 2 to 3, 15dB = 5.6 >> times 10 is 56
C_to_I threshold 3 4
31
threshold between grade 3 to 4, 10dB = 3.1 >> times 10 is 31
RSSI level 1 for threshold shift
-65
RSSI level 1 in which the C/I to GRADE thresholds are updated
RSSI level 2 for threshold shift
-75
RSSI level 2 in which the C/I to GRADE thresholds are updated
Min RSSI level for grading
-80
min RSSI level for which channels are graded based on GEORTZEL result
Wideband detection enabled
1
1 - enable checking for wideband interferer on a single scan result, 0- disable
Wideband detection half window size
5
How many channels to look forward / backward from current channel for wideband interferer detection
Wideband detection half window threshold
4
How many channels in side window need to be bad inorder for channel to be classified as having a wideband interferer
Wideband detection full window threshold
8
How many channels in entire window need to be bad inorder for channel to be classified as having a wideband interferer
HCI_Command_Complete_Event
Opcode
0xFE47
HCI_VS_Config_AFH_IN_HV1
Pattern Detection Enable
1
0 - disable, 1 - enable
Pattern Detection Window size
11
length of the pattern window
Pattern Detection Errors within window
2
number of error that will be fixed
Pattern Detection Margin
1
Good channels that will be removed from each margin
CCM sample period
1
How many times CCM is update before reading CCM results (unit of 25mS)
Accumulate threshold
40
How many times CCM results are read before processing data (units of "CCM sample period")
Min hits th 1
2
When minimal RSSI is above "TH switch RSSI": Minimal number of HEC events for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests)
Good HEC percent TH 1
70
When minimal RSSI is above "TH switch RSSI":Percentage of good HEC for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests)
Min SNR th 1
0
When minimal RSSI is above "TH switch RSSI":Minimal PHY SNR for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in dB
Min hits th 2
2
When minimal RSSI is below "TH switch RSSI": Minimal number of HEC events for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests)
Good HEC percent TH 2
70
When minimal RSSI is below "TH switch RSSI":Percentage of good HEC for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in percent
Min SNR th 2
0
When minimal RSSI is below "TH switch RSSI":Minimal PHY SNR for channel not to be considered as bad (if less than TH it is bad, otherwise check other tests), in dB
TH switch RSSI
-72
RSSI level at which other thresholds are switched, in dBm
HV1 return channel threshold
50
minimal munber of good channels allowed in HV1, when reaching this number all channels are returned
HV1 return timer
60
time in seconds for channel return in HV1 (stand alone timer, not restared at channel drop)
HCI_Command_Complete_Event
Opcode
0xFE48
HCI_VS_switch_from_tcxo_to_fref
HCI_Command_Complete_Event
Opcode
0xFE4A
HCI_VS_Set_Clk_Req_Mode_For_TCXO
Clock Sharing Output Mode
1
0 - disable, 1 - enable
Output pull enable
1
0 - disable, 1 - enable, 2 - default pull, 0xFF - No change
Pull configuration
0
0-pull down; 1-pull up;
HCI_Command_Complete_Event
Opcode
0xFE4B
HCI_VS_Write_TCXO_LDO_Enable
TCXO LDO state
0
0-disable; 1-enable;
HCI_Command_Complete_Event
Opcode
0xFD62
HCI_VS_Configure_AFH_debug
bit mask
0
Table select
0xFF
0 - print debug map 0
1 - print debug map 1
2 - print debug map 2
3 - print debug map 3
Channel to print
0xFF
Channel for which grade and C2I will be printed (if bit in mask is high)
Power 1
0
power 1 != 0 for loop to work [if(power1) {....}]
make sure bit 11 of debug mask is high (0x00000400) - to print logs of dBm_to_geortzel calc */
Power 2
0
power 1 must be larger than power 2, loop while (p1>=p2){... p1-=power step}
Power step
0
power step must be possitive , (step >0) uints in [db]
PHY store enable
1
When low, PHY does not store its results, they can be written through HCI script
ref Power
-80
ref power for geortzel conversion (on Island 3 only)
ref Goertzel
100
ref geortzel for geortzel conversion (on Island 3 only)
HCI_Command_Complete_Event
Opcode
0xFD5D
HCI_VS_FM_BT_coex_configuration
Coex enable bitmap
0x0000
Bit 0: report spur channels as bad in FM_RX
Bit 1: report spur channels as bad in FM_TX
Bit 2: AFH will be activated only in EDR
Bit 3: switch PLL mode (band)
Bit 4: switch OCP dividers
Bit 5: disable FM synt offset (ignore offset)
Bit 6: when in long sniff only, force basic data rate packets
Bit 8: enable/disable top/drp clock divison mechanism due to fm interference - disabled by default
Bit 15: enable debug messages for logger
OCP - FREF frequency gaurdband
60
frequency gaurdband from FM station to OCP spur (in KHz)
BT CKVD frequency gaurdband
200
frequency gaurdband from FM station to CKVD spur (in KHz)
Lock to AFH wait timer
1600
time in slots to wait from FM station lock to removing channels by AFH
HCI_Command_Complete_Event
Opcode
0xFD59
Changes Sniff FBF Scheduling Parameters
Sniff Instance Limit
10
Number of frames to limit a sniff instance
Sniff Voice Override Threshold
80
Number of frames sniff could not schedule before overriding voice
Sniff Timeout Limit
2
Number of frames to limit a sniff timeout
HCI_Command_Complete_Event
Opcode
0xFD65
Controls the audio output pin mux and override pull registers
PCMI override
0
The value of the PCMI_TOP_CTRL_REG. Zero indicated no change.
I2S override
0
The value of the I2S_TOP_CTRL_REG. Zero indicated no change.
Operation Mode
0
FM audio path operation mode
PCMI mux
0
PCMI mux
PCMI Enable
0
Enable disable the external PCM interface.
I2S Enable
0
Enable disable the external I2S interface.
Reserved
0
Reserved
0
Reserved
0
Reserved
0
HCI_Command_Complete_Event
Opcode
0xFD54
HCI VS Configure Bad Voice Scenario Params
No voice override (by slave)period in bad voice scenario
400
Number of Frames that there will be no override of voice in bad voice scenario
Disable Voice Override Period
0x05
The number of frames the slave will override voice for sending ACL data
Multislot configuration in Bad Voice Scenario
0x02
The length of slave data packets used to override voice: 0x0 - single slot, 0x1 - 3-slot packets, 0x2 - 5 slot packets
Reserved
0xFF
Reserved
Reserved
0xFF
Reserved
Reserved
0xFF
Reserved
HCI_Command_Complete_Event
Opcode
0xFD55
Set Data During Inquiry Page Parameters
BE access percentage
20
0-100: Percentage of Page or Inq to sucrifice for BE ACL
Guaranteed access percentage
70
0-100: Percentage of Page or Inq to sucrifice for guaranteed ACL
Poll period
2
Poll period to be requested by slave ACL during DDIP (0x02 - 0xFF)
Slave Wait After Tx Boundry
0x7
A number of frames for ACK reception after the slave transmitted packet (0x02 - 0xFF)
Slave Master Search Boundry
0x2
The maximal number of frames in which the slave is searching for the master during DDIP (0x02 - 0xFF)
Master Burst After Rx Enable
1
Allows a following the Rx frame to be allocated to the same connection
Master Burst After Rx Limit
1
Limits a number of frames after Rx
Reserved
0xFF
Reserved
Reserved
0xFF
Reserved
HCI_Command_Complete_Event
Opcode
0xFD56
Configure conection frame by frame scheduling
Poll Override Threshold
5
The Minimum number of poll intervals needed before overriding voice
Nulls Allocated for RX Data
1
The number of NULL packets sent to peer after a data packet is received: 0-255.
Slave Search Timeout
40
The maximum number of frames slave will wait for Poll/Null from master before giving up
Slave Ack Timeout
7
The maximum number of frames slave will wait for ACK after data transmission
Master Burst After Rx Enable
1
Master Burst After Rx Enable
Master Burst After Rx Limit
1
Master Burst After Rx Limit
Best Effort Percantage
15
Best Effort Percantage that shall be provided to Connection
RWIN Override
1
HCI_Command_Complete_Event
Opcode
0xFD70
Configure voice override for inquiry incase of HV connections
Frames
10
Frames till override start
Duration
5
Duration (in frames) of override
HCI_Command_Complete_Event
Opcode
0xFD67
Controls MUX and activation for Analog / Digital PA
PA Mode
0xFF
0: Off, 1: DAC, 2: PWM, 3: Digital, 0xFF: Don't change.
CMD 1 Select
0xFF
CMD 2 Select
0x01
PA_EN Select
0x02
nPA_EN Select
3
HCI_Command_Complete_Event
Opcode
0xFD80
HCI VS DRPb Enable RF Calibration
Mode
0x00
0x00: Calibrate once, 0x01-0xFD: Period length (x10 Secs), 0xFE: Keep periodic calibration, 0xFF: Stop periodic calibration.
Calibration Procedures Selection
0xFFFFFFFF
0x0000-0xFFFF: Procedures bitmap, 0xFFFFFFFF: Keep last bitmap.
Override Temp Condition
0x00
0x00: Run selected calibrations only if temp range changed, 0x01: Run selected calibrations regardless of temp range changes
HCI_Command_Complete_Event
Opcode
0xFD81
HCI_VS_DRPb_Read_Calib_Results
Opcode
0xFD82
HCI VS DRPb Set Power Vector
Power Table Type
0x00
0: GFSK, 1: EDR 2MB, 2: EDR 3MB, 3 - All modulation types, 4 - DIG_EXT_PA_CMD
Power Level 0 Value
-50 *2
-50 to 10 (dBm).
Power Level 1 Value
-18 *2
-50 to 10 (dBm).
Power Level 2 Value
-18 *2
-50 to 10 (dBm).
Power Level 3 Value
-18 *2
-50 to 10 (dBm).
Power Level 4 Value
-18 *2
-50 to 10 (dBm).
Power Level 5 Value
-18 *2
-50 to 10 (dBm).
Power Level 6 Value
-18 *2
-50 to 10 (dBm).
Power Level 7 Value
-18 *2
-50 to 10 (dBm).
Power Level 8 Value
-18 *2
-50 to 10 (dBm).
Power Level 9 Value
-14 *2
-50 to 10 (dBm).
Power Level 10 Value
-10 *2
-50 to 10 (dBm).
Power Level 11 Value
-6 *2
-50 to 10 (dBm).
Power Level 12 Value
-2 *2
-50 to 10 (dBm).
Power Level 13 Value
2 *2
-50 to 10 (dBm).
Power Level 14 Value
6 *2
-50 to 10 (dBm).
Power Level 15 Value
10 *2
-50 to 10 (dBm).
tx_power_edr_epc_idx
0xFF
epc max level Threshold 0 to 15 edr2(bits 0-3)edr3(bits 4-7)
Externa PA Mode
0x00
HCI_Command_Complete_Event
Opcode
0xFD83
This command allows us to define the max power
MAX ACW Power 0
12.5 *256
the max ACW power in dbm. for Temperature regions 0/1
!!!! User must perform POWER_DEPENDENT_CALIBRATION at end of Init script if this command was used !!!
MAX ACW Power 1
12.5 *256
the max ACW power in dbm. for Temperature regions 2/3
MAX ACW Power 2
12.5 *256
the max ACW power in dbm. for Temperature regions 4/5
MAX ACW Power 3
12.5 *256
the max ACW power in dbm. for Temperature regions 6/7
MAX ACW Power 4
12.5 *256
the max ACW power in dbm. for Temperature regions 8/9
MAX ACW Power 5
12.5 *256
the max ACW power in dbm. for Temperature regions 10/11
HCI_Command_Complete_Event
Opcode
0xFD84
Continuous Transmit Mode
Modulation Scheme
0
Modulation Scheme
Test Pattern
0
Test Pattern
Frequency Index
0
0..78: Freq
Power level index
15
Valid in BT, Range 0-15: 15=Max Output Power, 0=Min Output Power.
Generator Init Value
0x00000000
0x00000000..0x00FFFFFF: Generator Init Value used in User Defined Pattern Only (for GFSK and EDR)
EDR Generator Mask Value
0x00000000
0x00000000..0x00FFFFFF: EDR Generator Mask Value used in User Defined Pattern Only (for EDR only)
HCI_Command_Complete_Event
Opcode
0xFDB7
For BLE use this command with HCI_VS_DRPb_Tester_Con_RX, if this command is not used the default modulation is BT
Modulation type
0x00
0x00 - BT RX START, 0x01 - BLE RX START
HCI_Command_Complete_Event
Opcode
0xFD17
Continuous reception Mode
Frequency Index
0
0..78: Freq
ADPLL loop mode
0x00
0x00 - Open loop, 0x01 - Closed loop
HCI_Command_Complete_Event
Opcode
0xFD85
Packet TX RX Mode
Frequency Mode
3
0 - Hopping, 3 - Single freq.
TX Single Frequency Index
0
0..78: Freq
RX Single Frequency Index
0xFF
0..78: Freq, 0xFF: Disable RX
ACL TX Packet Type
0
ACL TX Packet Type
ACL TX Packet Data Pattern
2
ACL TX Packet Data Pattern
Use Extended features
0
Enable or disable the extended features of the command
ACL Packet Data Length
27
0-17->DM1, 0-27->DH1, 0-121->DM3, 0-183->DH3, 0-224->DM5, 0-339->DH5
Power level index
15
Range 0-15 : 15=Max Output Power, 0=Min Output Power.
Disable whitening
1
0=Enable whitening, 1=Disable whitening
PRBS9 Init Value
0x01FF
0x0000-0x01FF: PRBS9 Init Value
RX Win Length
200
1-400->DH1, 1280-1600->DH3, 2500-2900->DH5
RX Packet Type
0
0-1 slot, 1 - 3 slots, 2 - 5 slots
Burst Length
1
1-0xFE Number of TX RX sequences, 0xFF - continuous
Burst Interval
2
Burst length plus no action period - in frames
TX_RX Order
0
0 : TX first(Master), 1: RX first(Slave)
HCI_Command_Complete_Event
Opcode
0xFD86
HCI_VS_DRPb_Debug_Mem_Setting
Opcode
0xFD87
HCI_VS_DRPb_Set_Class2_Single_Power
GFSK Power level index
10
Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.
EDR2 Power level index
10
Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.
EDR3 Power level index
10
Table entry to use as class 2 if peer does not support power control.Range 0-15 : 15=Max Output Power, 0=Min Output Power.
HCI_Command_Complete_Event
Opcode
0xFD88
HCI_VS_DRPb_Reset
HCI_Command_Complete_Event
Opcode
0xFD89
update ADPLL LF Params
Frequency
19200000
FREF clock being updated in Hz
ADPLL LF Set
0
The relevant set of LF parameters to be overridden.
Reserved
0
Alpha_Exp
0
Alpha Exp value
Alpha_Sig
0
Alpha Sig value
Rho_Exp
0
Rho Exp value
Rho_Sig
0
Rho Sig value
Gain_Exp
0
Gain Exp value
Gain_Sig
0
Gain Sig value
IIR_Lambda1
0
IIR_Lambda1 value
IIR_Lambda2
0
IIR_Lambda2 value
pi_gain_low
Alpha_Exp+(Alpha_Sig*16)+(Rho_Exp*256)
pi_gain_high
Rho_Sig+(Gain_Exp*16)+(Gain_Sig*256)
iir
IIR_Lambda2+(IIR_Lambda1*256)
HCI_Command_Complete_Event
Opcode
0xFD8A
Drp Run Mnem (2,1V)
Test Period
0
Test Period
Reserved
0
Reserved
Count Threshold
0
Count Threshold
Exception Counter
0
Exception Counter Fail-Pass limit
Decimation Mode
0
Decimation Mode
Wait Time
200
0-255 ms
Test Cont Flag
0
0-dont run VS_DRP_Tester_Continous_TX , 1- run VS_DRP_Tester_Continous_TX
HCI_Command_Complete_Event
Status
0x00
0 - success, Other - Error
Status Register Value
0x0000
Status Register Value
HCI_Command_Complete_Event
Opcode
0xFD8B
HCIPP Start DRP BER Meter
Frequency Channel
59
Frequency Channel
Reserved
0
Reserved
BD Address
0x000000000000
BD Address
LT Address
1
LT Address
ACL Packet Type
0x1
ACL Packet Type
packet length
27
Number of packets
500
PRBS Initilaize
0x1FF
PRBS Init state
POLL Period
0x1
In BT frames
HCI_Command_Complete_Event
Opcode
0xFD13
HCIPP Read DRP BER Meter Result
HCI_Command_Complete_Event
Status
0x00
0 - success, 1 - illegal command
Finished at least 1 test
0x00
0 - First test has not been finished, 1 - Values are valid for current measurment
Number of packet received in current measurment
0x00
Number of packet received in current measurment
Total bits counted
0x00
Total bits counted
Number of bits error found
0x00
Opcode
0xFD98
HCI VS DRPB Force Environment Settings
Set Process Type
0xFF
0x00: Nominal, 0x01: Weak, 0x02: Strong, 0xFF: Don't change.
Set Temperature Value
0x7F
-40 to 85: Temperature Value in Celsius (C) , 0x7E: Default, 0x7F: Don't change.
Temperature Region 00 Threshold
-70
-127 - +127:Temperature Region 00 Threshold, 0x80(-128):Don't change.
Temperature Region 01 Threshold
-30
-127 - +127:Temperature Region 01 Threshold, 0x80(-128):Don't change.
Temperature Region 02 Threshold
-20
-127 - +127:Temperature Region 02 Threshold, 0x80(-128):Don't change.
Temperature Region 03 Threshold
-10
-127 - +127:Temperature Region 03 Threshold, 0x80(-128):Don't change.
Temperature Region 04 Threshold
0
-127 - +127:Temperature Region 04 Threshold, 0x80(-128):Don't change.
Temperature Region 05 Threshold
10
-127 - +127:Temperature Region 05 Threshold, 0x80(-128):Don't change.
Temperature Region 06 Threshold
20
-127 - +127:Temperature Region 06 Threshold, 0x80(-128):Don't change.
Temperature Region 07 Threshold
30
-127 - +127:Temperature Region 07 Threshold, 0x80(-128):Don't change.
Temperature Region 08 Threshold
40
-127 - +127:Temperature Region 08 Threshold, 0x80(-128):Don't change.
Temperature Region 09 Threshold
50
-127 - +127:Temperature Region 09 Threshold, 0x80(-128):Don't change.
Temperature Region 10 Threshold
60
-127 - +127:Temperature Region 10 Threshold, 0x80(-128):Don't change.
Temperature Region 11 Threshold
70
-127 - +127:Temperature Region 11 Threshold, 0x80(-128):Don't change.
Temperature Region 12 Threshold
125
-127 - +127:Temperature Region 12 Threshold, 0x80(-128):Don't change.
HCI_Command_Complete_Event
Opcode
0xFD8C
HCI_VS_A3DP_OPEN_STREAM
Connection Handle
0x01
The ACL connection handle
L2CAP CID
0x40
L2CAP channel ID of the AVDTP data stream
L2CAP MTU
0x300
L2CAP max packet length
AVDTP Version Parameter
0x02
AVDTP protocol header Version parameter
AVDTP Payload Parameter
0x65
AVDTP protocol header Payload parameter
Reserved
0x0
Reserved
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD8D
Connection Handle
0x01
The ACL connection handle. The value 0x0 means close all streams
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD8E
Audio Source
0x00
Determines the audio source of the A2DP stream.
PCM Input Sample Frequency
0x9
The PCM sample frequency rate of the input PCM bus.
When this parameter is different from the SBC Input Sample Frequency the SRC will be used for sample rate conversion.
PCM Number of Channels
0x2
The number of channels of the PCM input.
SBC Input Sample Frequency
0x4
The sample frequency rate of the PCM input to SBC encoder
SBC channel Mode
0x2
Describes the channel mode used to encode a stream.
SBC Number of Blocks
16
Number of SBC Encoder Blocks (4,8,12,16)
SBC Number of Subbands
8
Number of SBC Encoder subbands (4,8) Currently only 8 is supported
SBC Allocation Method
0
SBC Allocation Method
SBC Bit Pool Low Boundary
35
The lower boundary of the negotiated bit pool range
SBC Recommended Bit pull
53
The Host can recommend for a specific bit pool value from the bit pool rate.
SBC dynamic Bit Pull Enable
0
Determines whether a dynamic bit pool mechanism should be used to performance/quality adjustment
Reserved
0x0
Reserved
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD96
SBC Bit Pool Low Boundary
15
The lower boundary of negotiated bit pool range (max of both SNK low boundary)
SBC Recommended Bit pull
53
The recommended bit pool of both SNK
SBC multiple SNK dynamic Bit Pull Enable
1
Determines whether a dynamic bit pool mechanism should be used during multiple SNK scenario
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD8F
Connection Handle
0x01
The ACL connection handle
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD90
Connection Handle
0x01
The ACL connection handle. The value 0x0 means stop all streams
Flush Flag
0x01
Determines whether the current internal buffers should be transmitted to the remotes device(s), or should be flushed immediately.
Generate Stop Event
0x00
Determines whether a stop stream event will be generated as soon as stream is stopped. To be used in Soft Flush
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Timeout
10000
Timeout in msec
Opcode
0x0300
GAP
Handle
0x01
Opcode
Opcode
0xFD91
Debug IPC Logger
0x01
Enable/Disable IPC logger messages. 1 - Enable. 0 - Disable
Reserved
0
Reserved
A3DP IO
0x01
Enable/Disable A3DP IOs. 1 - Enable. 0 - Disable
Reserved
0
Reserved
Reservede
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD99
Decrease Start Threshold
850
Used to calculate the IPC buffer occupation amount, above which bit pool decrease starts
Decrease Start Threshold Multi
1000
Used to calculate the IPC buffer occupation amount, above which bit pool decrease starts in multiple SNK scenario
Increase Start Threshold
600
Used to calculate the IPC buffer occupation amount, above which bit pool increase starts
Increase Rate
50
Defines how many encoding cycles passes between one bit pool increase to another
Increase Interations Boundary
2
Defines the number of iterations above which the factor for slowing the decrease rate is NOT increased for every decrease/ increase loop
Decrease Clear Interations Boundary
4
Defines the number of iterations above which the decrease rate becomes very fast
First Decrease
6
Defines the amount of bit pool unites which are decreased in the first decreasing cycle
Rate Factor
50
The rate of the dynamic bit pool determise how frequent (in terms of packet calc cycles)
will bit pool decrease be. If the rate is 1 - every calc cycle a decrease will occur
This variable is a factor in the rate calculation
Decrease Factor
2
Each time bit pool is lowered the decrease amount is calculated. The number of times the bit pool
was swinging up and down slows that decrease amount, in order to stabilize the bit pool on the
channel's current bandwidth. The following variable is a factor in the decrease amount calculation
Halt Value
37
Determines the value of the bit pool during halt
Bad RF Value
37
Determines the value of the bit pool during bad RF
Nack Threshold
20
Determines the threshold above which the channel is considered 'bad rf' channel for
the dynamic bit pool mechanism
Nack Threshold Multi
10
Determines the threshold above which the channel is considered 'bad rf' channel for
the dynamic bit pool mechanism in multiple SNK
RF statistics period
400
Determines the RF statistics period
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD6C
Configure page scan response that will be used when a connection attempt with the same Bluetooth address of an existing connection is made
page scan behavior
0
0 - allow new connection attempt and disconnect existing connection, 1 - reject new connection whilst existing connection remains present
HCI_Command_Complete_Event
Opcode
0xFD6D
configure the retransmission windows in diffrent Retransmission Effort mode
power consumption
1
Number of retransmission windows in power consumption mode.(Retransmission_Effort = 1)
link quality
2
Number of retransmission windows in link quality mode.(Retransmission_Effort = 2)
HCI_Command_Complete_Event
Opcode
0xFD7C
configure the number and length of ACL data buffers
Buffer length
1021
reserved
0
HCI_Command_Complete_Event
Status
0
0 - Success, 1 - Illegal command
Number of ACL buffers
0
X
Opcode
0xFD7D
configure the number and length of Extended ACL data buffers
Buffer length
1021
acl data threshold
1
Threshold for acl flow control
acl data timeout
800
HCID timer period
cortex_owner
0
0 - Wibree [Default]; 1 - None; 2 - AVPR
HCI_Command_Complete_Event
Status
0
0 - Success, 1 - Illegal command
Number of ACL buffers
0
X
Opcode
0xFD6E
This command configures the Class 1p5 mode
Mode
0xFF
0 - Direct Battery Input, 1 - SMPS High power Mode, , 2 - SMPS Low power Mode, 0xFF - Don't change
Class 1.5 LDO trim
0xFF
Control word for Class 1.5 Vout 0x0 - low 0xf = high (4 bit), 0xFF - Don't change
HCI_Command_Complete_Event
Opcode
0xFD7E
Configure debug messages over HCI
Not supported under Palau mode
Execute after setting Uart HCI Baudrate and not before it
Mode
1
0 - Disable mode, 1 - Enable mode
Not supported under Palau mode
Execute after setting Uart HCI Baudrate and not before it.
Timeout
80
time in BT Frames -
dispatch messages in case this time elapsed from last sent
HCI_Command_Complete_Event
Mode
1
0 - Disabled, 1 - Signal Priority on possible eSCO RWIN, 2 - Signal Priority only on Master when slave bad HEC
HCI_Command_Complete_Event
Reserved
0
Reserved
HCI_Command_Complete_Event
GPS
Opcode
0xFFC0
Power GPS On / Off
Power mode
0
HCI_Command_Complete_Event
Opcode
0xFD71
Configure pll sharing parameters
PLL Sharing Scheme Mode
1
Determine the PLL sharing scheme mode.
GPS requires HP
0
Configure whether GPS requires hp or not
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD72
Configure DC2DC parameters
External dc2dc
0xFF
Determine External DC2DC mode
Internal dc2dc
0
Determine Internal DC2DC mode
DC2DC clock priority
0
Determine DC2DC clock priority. Values: 0-0xFFF
Source input frequency
0xFF
Determine DC2DC clock priority.
Required Output Frequency
0xffff
0x0000-0xfffd :Required frequency in KHz\n
0xfffe: Use value from DC2DC_BANK_X_GENERAL , DC2DC_BANK_X_TOGGLE_1, DC2DC_BANK_X_TOGGLE_2\n
0xffff: Don't change
DC2DC bank X general
0xffff
Override to the relevant register
DC2DC bank X toggle 1
0xffff
Override to the relevant register
DC2DC bank X toggle 2
0xffff
Override to the relevant register
Standalone DC2DC output voltage trim
0xff
Override to the relevant register. 0xFFFF for don't change
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD73
Enable/Disable Quattro power save features
Dig LDO 1v at room temp
0xFF
Enable/disable Dig LDO 1v at room temp
Standalone features
0xFF
Enable/disable Global standalone
LP Bypass PLL Standalone
0xFF
Enable/disable LP Standalone sequence
dc2dc pwm frequncy standalone
0xFF
Enable/disable dc2dc pwm frequncy standalone
dc2dc vtrim standalone
0xFF
Enable/disable dc2dc vtrim standalone
BT ref clock blocking standalone
0xFF
Enable/disable BT ref clock blocking
Coex Pll Clock Blocking Standalone
0xFF
Enable/disable Coex Pll Clock Blocking Standalone
Slicer Itrim Override
0xFF
Enable/Disable Slicer Itrim Override
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD74
Enable/Disable JTAG for Quattro
WU source enable
0
Enable or disable JTAG as a wakeup source
RTCK muxing
0
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD75
Enable/disable GPS standalone mode
Standalone mode
0
Enable/disable GPS standalone mode
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD76
HCI VS DRPb set RF calibration info
Split Mode
0x01
0x00: Disable, 0x01: Enable
Calibrations with PA/LNA
0x00005421
Checked box = use PA/LNA, Unchecked box = don't use PA/LNA; 0x0000-0xFFFF: PA/LNA bitmap, 0xFFFFFFFF: Keep last bitmap.
Calibrations with protection
0x00005761
Checked box = protected, Unchecked box = unprotected; 0x0000-0xFFFF: Protection bitmap, 0xFFFFFFFF: Keep last bitmap.
PA_SD delay_ms
20
Trigger same calibration in [x] ms in case of non successive attempt due to PA_SD
Num of calib PA_SD attempts
5
Maximum number of additional non successive attempts due to WLAN PA_SD during calibration process
Interference delay_ms
10
Trigger same calibration in [x] ms in case of non successive attempt due to general interference
Num of calib interf attempts
5
Maximum number of additional non successive attempts due to general interference during calibration process
Calibration #1
00
Calibrations order
Calibration #2
07
Calibrations order
Calibration #3
06
Calibrations order
Calibration #4
10
Calibrations order
Calibration #5
04
Calibrations order
Calibration #6
05
Calibrations order
Calibration #7
08
Calibrations order
Calibration #8
09
Calibrations order
Calibration #9
11
Calibrations order
Calibration #10
12
Calibrations order
Calibration #11
13
Calibrations order
Calibration #12
14
Calibrations order
Calibration #13
16
Calibrations order
Calibration #14
16
Calibrations order
Calibration #15
16
Calibrations order
Calibration #16
16
Calibrations order
Calibration #17
16
Calibrations order
Calibration #18
16
Calibrations order
Calibration #19
16
Calibrations order
Calibration #20
16
Calibrations order
Calibration #21
16
Calibrations order
Calibration #22
16
Calibrations order
Calibration #23
16
Calibrations order
Calibration #24
16
Calibrations order
Calibration #25
16
Calibrations order
Calibration #26
16
Calibrations order
Calibration #27
16
Calibrations order
Calibration #28
16
Calibrations order
Calibration #29
16
Calibrations order
Calibration #30
16
Calibrations order
Calibration #31
16
Calibrations order
Calibration #32
16
Calibrations order
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0x1700
Auto recovery status change event
BD Address
BD address for which the recovery is being processed
State
0
Auto recovery state
Role
0
Auto recovery Role: Pager or scanner
Opcode
0xFDAA
Request Parameters for an Auto recovery session
connection handle
1
Connection handle to request parameters for
Reserved
0
Reserved
HCI_Command_Complete_Event
Status
0
0 - Success, 1 - Illegal command
connection handle
1
Connection handle to enable auto recovery on
Start Value
0x0
BT CLK to act as a reference point for anchor points
Anchor Interval
0x400
Interval between two recovery anchor points
Fast Timeout
1800
Fast recovery timeout (In seconds)
Slow Timeout
48000
Fast recovery timeout (In seconds)
Opcode
0xFDAC
Enable auto recovery on link
connection handle
1
Connection handle to enable auto recovery on
Start Value
0x0
BT CLK to act as a reference point for anchor points
Anchor Interval
0x400
Interval between two recovery anchor points
Fast Timeout
1800
Fast recovery timeout (In seconds)
Slow Timeout
48000
Fast recovery timeout (In seconds)
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFDAD
Disable auto recovery on link
BD Address
bd_addr
BD Address to disable auto recovery on
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9A
HCI_VS_A3DP_SNK_OPEN_STREAM
Connection Handle
0x01
The ACL connection handle
L2CAP CID
0x40
L2CAP channel ID of the AVDTP data stream
Reserved
0x0
Reserved
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9B
HCI_VS_A3DP_SNK_CLOSE_STREAM
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9C
PCM Number of Channels
0x2
The number of channels of the PCM input.
SBC Input Sample Frequency
0x3
The sample frequency rate of the PCM input to SBC encoder
SBC channel Mode
0x2
Describes the channel mode used to encode a stream.
SBC Number of Blocks
16
Number of SBC Encoder Blocks (4,8,12,16)
SBC Number of Subbands
8
Number of SBC Encoder subbands (4,8) Currently only 8 is supported
SBC Allocation Method
0
SBC Allocation Method
Reserved
0x0
Reserved
Reserved
0x0
Reserved
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9D
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9E
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD92
Enable/Disable AVPR
0x01
Enable/Disable The AVPR clock. Enable also reloads the AVPR code.
1 - Enable. 0 - Disable
A3DP role
0x00
Code upload
0x01
0x00 - Don't load A3DP code,0x01- Load A3DP code
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD9F
Buffering Threshold
1800
The threshold to move from BUFFERING state to STREAMING State in ARM7 state machine
Streaming Threshold
300
The threshold to move from STREAMING state to OVER-LOAD State in ARM7 state machine
Buffering after Underrun Threshold
1800
The threshold to move from BUFFERING state to STREAMING State after Underrun in ARM7 state machine
Underrun Threshold
5100
The threshold to move from STREAMING state to BUFFERING State in ARM7 state machine
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD24
Loas AM2AM and AM2PM tables
Process
0
0 - Nominal, 1 - Weak, 2 - Strong
Temperature Region
1
0 - Cold, 1 - Room, 2 - Hot
PM Config
1
0 - Battrery, 1 - DC2DC, 2 - Not Used
Size
04
1-200
Values
"00000000"
Data starts from left to right
HCI_Command_Complete_Event
Wibree
Opcode
0xFD7A
Set the masked traces debug configuration
Group 0: LE Data path Upper MAC
0x000
The bit mask enabling Data path Upper MAC traces
Group 1: LE Scheduling GENERAL/SCAN/CONNECT Upper MAC
0x000
The bit mask enabling Scheduling GENERAL/SCAN/CONNECT Upper MAC traces
Group 2: LE Scheduling CONNECTION Upper MAC
0x000
The bit mask Scheduling ADV/CONNECTION Upper MAC traces
Group 3: LE General Upper MAC
0x000
The bit mask enabling General Upper MAC traces
Group 4: LE Scheduling ADV Upper MAC
0x000
The bit mask enabling Scheduling ADV Upper MAC
Group 5: BT Group 1
0x000
The bit mask enabling BT Group 1
Group 6: BT Group 2
0x000
The bit mask enabling BT Group 2
Group 26: LE CONNECT/SCAN Lower MAC
0x000
The bit mask enabling ADV/SCAN Lower MAC traces
Group 27: LE Connection Lower MAC
0x000
The bit mask enabling Connect/Connection Lower MAC traces
Group 28: LE Mini Sync/General Lower MAC
0x000
The bit mask enabling Mini Sync/General Lower MAC traces
Group 29: LE ADV Lower MAC
0x000
The bit mask enabling Encryption Lower MAC traces
HCI_Command_Complete_Event
Wibree
Opcode
0xFDA8
Load Cortex
Mode
0x00
0x01 = Disable Cortex Sleep
HCI_Command_Complete_Event
Wibree
Opcode
0xFDC4
Run DRPB self test
Test Bitmask
0x00
bit_0 test TX_STOP to RX_START timing
HCI_Command_Complete_Event
Status
0x00
Status
test status
0
a 1 indicates failure in corresponding bit test
Opcode
0xFDDC
FE Detection Scheme
0x00
Detection scheme. 0 - Automatic; 1 - Manual
FE Type Manual
0x1
FE Type: The value ignored in case of Automatic Detection
FE Mode
0x00
0 - Single Band; 1 - Dual Band
Extended MAX Allowed Power
1
0-Set single value for MAX Allowed Power 1-Set multiple values for MAX Allowed Power
MAX Allowed Power GFSK - RFMD SB
0xFF
Maximal allowed power for GFSK RFMD Single band
MAX Allowed Power EDR - RFMD SB
2*9
Maximal allowed power for EDR RFMD Single band
MAX Allowed Power GFSK - TRIQ SB
0xFF
Maximal allowed power for GFSK TRIQ Single band
MAX Allowed Power EDR - TRIQ SB
0xFF
Maximal allowed power for EDR TRIQ Single band
MAX Allowed Power GFSK - SKW SB
0xFF
Maximal allowed power for GFSK SKW Single band
MAX Allowed Power EDR - SKW SB
0xFF
Maximal allowed power for EDR SKW Single band
MAX Allowed Power GFSK - Override SB
0xFF
Maximal allowed power for GFSK Override Single band
MAX Allowed Power EDR - Override SB
0xFF
Maximal allowed power for EDR Override Single band
MAX Allowed Power GFSK - RFMD DB
0xFF
Maximal allowed power for GFSK RFMD Dual band
MAX Allowed Power EDR - RFMD DB
2*9
Maximal allowed power for EDR RFMD Dual band
MAX Allowed Power GFSK - TRIQ DB
0xFF
Maximal allowed power for GFSK TRIQ Dual band
MAX Allowed Power EDR - TRIQ DB
0xFF
Maximal allowed power for EDR TRIQ Dual band
MAX Allowed Power GFSK - SKW DB
0xFF
Maximal allowed power for GFSK SKW Dual band
MAX Allowed Power EDR - SKW DB
0xFF
Maximal allowed power for EDR SKW Dual band
MAX Allowed Power GFSK - TRIQ HP DB
0xFF
Maximal allowed power for GFSK TRIQ HP Dual band
MAX Allowed Power EDR - TRIQ HP DB
0xFF
Maximal allowed power for EDR TRIQ HP Dual band
MAX Allowed Power GFSK - Override DB
0xFF
Maximal allowed power for GFSK Override Dual band
MAX Allowed Power EDR - Override DB
0xFF
Maximal allowed power for EDR Override Dual band
MAX Allowed Power
2*9
Maximal allowed power for EDR 2/3
HCI_Command_Complete_Event
Opcode
0xFDFC
Connection Handle
Handle
Read RSSI value without threshold for current handle
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Handle
RSSI
0
Opcode
0xFDB4
Slave BR
0x24
Configure min T sniff in frames for HID connection when there is a slave connected with basic rate throughput
Master BR
0x18
Configure min T sniff in frames for HID connection when there is a master connected with basic rate throughput
Slave EDR
0x20
Configure min T sniff in frames for HID connection when there is a slave connected with EDR throughput
Master EDR
0x10
Configure min T sniff in frames for HID connection when there is a master connected with EDR throughput
HCI_Command_Complete_Event
Opcode
0xFDDB
Block/Unblock Events
0x01
Block/Unblock Events to the host. 1 - Enable; 0 - Disable
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Wibree
Opcode
0xFD4C
set Wibree whitening mode
force connection access address
1
0=Don't Force,1=Force
whitening mode
1
1=Enable whitening, 0=Disable whitening
HCI_Command_Complete_Event
Wibree
Opcode
0xFD5B
Enable BLE sub-system
Enable , Disable
1
0=Disable,1=Enable
Load LE code
1
0=Dop not load code,1=Load code
HCI_Command_Complete_Event
Wibree
Opcode
0xFD21
set Wibree scan and connect to single period, hence together with setting (window = interval) will achive continues scan
force certain freq mask
1
0=Don't Force,1=Force
freq mask to be scanned
0x0
any number 0 - 7
HCI_Command_Complete_Event
Wibree
Opcode
0xFD6F
set Wibree access address manualy
force connection access address
1
0=Don't Force,1=Force
access_address
0x0
wb connection access address
HCI_Command_Complete_Event
Open
Encrypted
Slave
Master
Wibree
Opcode
0xFDA5
set sleep mode configurations
enable cortex deep sleep
1
1- enable cortex deep sleep while arm in big sleep, 0- disable.
HCI_Command_Complete_Event
Wibree
Opcode
0xFDA6
set sleep mode configurations
reply Transaction
0x000
Select the transaction that you want to reply with UNKNOWN_RSP to the peer
Ignore Transaction
0x000
Select the transaction that you want to Ignore
NACK Transaction
0x000
0- Default , 1- Send NACK
Ignore Advertise/Scanner Packet
0x000
Select the Advertise Packet that you want to Ignore
HCI_Command_Complete_Event
Wibree
Opcode
0xFDA7
LE_GENERAL_CONFIGURATION_ENABLE
cfg_0
0x5
mask for false SYNC (AA) filtering and more. See bitmap
cfg_1
0x000
mask for TBD ...
cfg_2
0x000
mask for TBD ...
cfg_3
0x000
mask for TBD ...
cfg_1
0x000
mask for TBD ...
cfg_1
0x000
mask for TBD ...
HCI_Command_Complete_Event
Wibree
Opcode
0xFDAB
configure connection parameters
MAX Event Duration
0xFF
set the max event duraration
Create connection override voice TH
0xFF
0-5
Voice override threshold (Non HID)
0xFF
number of connection intervals before LSTO in which BLE connection starts overriding voice
HID Voice override threshold - denominator
0xFF
The fraction (denominator) of LSTO in which BLE HID overrides voice
HID Voice override threshold - nominator
0xFF
The fraction (nominator) of LSTO in which BLE HID overrides voice
HID interval threshold
0xFF
Definitions the type of the BLE connections: Regular or HID. in frames
min trans distance in events
0xFF
Define the min indicate of the connEventCount when the channelMapNEW shall be applied,a minimum of 6 connection.in frames
Reserved
0xFFFF
Reserved
Reserved
0xFFFF
Reserved
HCI_Command_Complete_Event
Wibree
Opcode
0xFDAF
configure channel classification params
Short Long threshold
50
define the threshold between long and short sniff in mSec
Periodic Short Timer
200
periodic trigger for Short sniff, integer multiply of *Tsniff. 0x1 - always running , 0x0 - the timer never trigger the AFH
Periodic Long Timer
160
periodic trigger for Long sniff, integer multiply of *Tsniff. 0x1 - always running , 0x0 - the timer never trigger the AFH
No Sync RSSI threshold
-82
When RSSI level is above the threshold and we notice no Sync requiers to active afh_scan, in dBm
SNR RSSI threshold
-72
When RSSI level is above the threshold and SNR under the threshold requiers to active afh_scan, in dBm
Min SNR threshold
1
When RSSI level is above the threshold and SNR under the threshold requiers to active afh_scan
Short X 1sec timer
3
Indicate number of time to repeat the afh_scan 1 sec timer loop (0 is NA)
Long X 1sec timer
2
Indicate number of time to repeat the afh_scan 1 sec timer loop (0 is NA)
ULP Nscan Short Sniff
4
Number of afh_scan to perform every time the 1 sec timer is expierd
ULP Nscan Long Sniff
3
Number of afh_scan to perform every time the 1 sec timer is expierd
consecutive no sync
2
Trig AFH scan if (frame_from_last_sync > interval*(latency +1+ consecutive_no_sync)) 0-0xFD,0xFE - consecutive equal to latancy
channel map change threshold
5
min events between updates
1
min events (interval * latenct...) between two update channel map transactions
max events to block updates
20
max events (interval * latenct...) from last that update channel map transactions in which a new new map will be sent only if lots of channels have changed
AFH Tigger on no SYNC statistic threshold
0xA3
bits [7:4] events to count untils decision, bits [3:0] number of no syncs in events, if higher than threshold trigger AFH
HCI_Command_Complete_Event
Wibree
Opcode
0xFDA9
LE Channel Assessment Mode
AFH Channel Assessment Mode
0x00
0x00 = BLE channel assessment disabled 0x01 = BLE channel assessment enabled
HCI_Command_Complete_Event
Wibree
Opcode
0xFDC0
Configure Scan Parameters
Refresh Rate Threshhold
100
Set the Filter duplicate refresh rate threshhold
check data
0xFF
Send event to host if ADV data was change
wait for scan res
0xFF
Continue to send ADV ind event to host if Scan res did not received.
Reserved
0xFFFF
Reserved
HCI_Command_Complete_Event
Opcode
0xFDC1
Configure RSSI metering params for performing RSSI average.
Interval Thresshold
400
The inteval thresshold used to determine which Alpha to use: Short interval Alpha or long interval Alpha
Short interval Alpha
153
The Alpha to use, as a fraction of 256. For instance, for a value of 0.75, use 0.75*256 = 192
Long interval Alpha
204
The Alpha to use, as a fraction of 256. For instance, for a value of 0.25, use 0.25*256 = 64
Reserved
0
Reserved
HCI_Command_Complete_Event
Opcode
0xFDC2
Load Compressed data in order to decompress an image.
Please note that this command can be used in a dual syntax:
The second parameter may be the target address.
The third parameter may be the compressed image size.
The fourth parameter may be the compressed buffer.
Data Size
253
Number of compressed bytes in this packet
Values
"00000000"
Compressed data to load.
HCI_Command_Complete_Event
Wibree
Opcode
0xFDB3
LE Qualification Configuration - Act as tester
Configuration Bit Map
0x00
Param1
0x00
Depending on the bitmap is the interpritaion of the field
Param2
0x00
Depending on the bitmap is the interpritaion of the field
Param3
0x00
Depending on the bitmap is the interpritaion of the field
Reserved
0x00
Reserved for future use
HCI_Command_Complete_Event
Wibree
Opcode
0xFDAE
Read BER Test results
HCI_Command_Complete_Event
Status
0x00
Status
Number of BER in Type received
0
Number of BER in Type received
Number of BER in Length received
0
Number of BER in Length received
Number of BER in Payload Received Part 1
0
Number of BER in Payload received
Number of BER in Payload Received Part 2
0
Number of BER in Payload received
Number of BER in Payload Received Part 3
0
Number of BER in Payload received
Number of BER in Payload Received Part 4
0
Number of BER in Payload received
Number of BER in CRC received
0
Number of BER in CRC received
Number of SYNC Events received
0
Number of SYNC Events received
Number of Packet with Bad Type
0
Number of Packet with Bad Type received
Number of Packet with Bad Length
0
Number of Packet with Bad Length received
Number of Packet with Bad CRC
0
Number of Packet with Bad CRC received
Number of FA Events
0
Number of FA Events
Number of iac_1_indication
0
Number of iac_1_indication
Number of iac_2_indication
0
Number of iac_2_indication
Number of iac_3_indication
0
Number of iac_3_indication
Number of 32 bit corrlation
0
Number of 32 bit corrlation
Number of 31 bit corrlation
0
Number of 31 bit corrlation
Number of 30 bit corrlation
0
Number of 30 bit corrlation
Number of 28_29 bit corrlation
0
Number of 28_29 bit corrlation
Number of 26_27 bit corrlation
0
Number of 26_27 bit corrlation
Number of 25 or less bit corrlation
0
Number of 25 or less bit corrlation
Number of good crc band sync packets
0
Number of good crc band sync packets
Number of good sync band crc packets
0
Number of good sync band crc packets
Number of Packets with Good CRC
0
Number of Packets with Good CRC Received
Wibree
Opcode
0xFDC6
set BLE WLAN coex priority
priority_bitmask
0
bit 0 ADV
bit 1 scan
bit 2 connect
bit 3 reserved
bit 4 connection
HCI_Command_Complete_Event
Opcode
0xFDD0
Enable/Disable ANT
0x01
Enable/Disable The ANT Sub System.
1 - Enable. 0 - Disable
Code Upload
0x01
0x0 - Do not initialize ANT with code upload; 0x1 - initialize with code upload
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFDD1
Length
size(data)
Data
"00:11:22"
HCI_Command_Complete_Event
Opcode
0xFDDD
Power Level Index
15
Value indicating hte Power Level to be used for transmit output power of BLE
HCI_Command_Complete_Event
Timeout
10000
Timeout in msec
Opcode
0x0500
Opcode
Length
Data
"00:11:22"
WBS
Opcode
0xFD9A
TBD
ACL handle
0x1
TBD
HCI_Command_Complete_Event
WBS
Opcode
0xFD9B
TBD
HCI_Command_Complete_Event
Spec 1.1
Connection Handle
Handle
Text
"Hello World"
Boundary
0x02
0-Start Non-Flushable 1-Continuation 2-Start Flushable
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Spec 1.1
Timeout
5000
Time in msec
Connection Handle
Handle
Boundary
0x02
0-Start Non-Flushable 1-Continuation 2-Start Flushable
Data
"Hello World"
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Spec 1.1
Layer
0x02
Connection Handle
Handle
Boundary
0x02
0-Start Non-Flushable 1-Continuation 2-Start Flushable
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Payload Length
size(data)
Data
"00:11:22"
Timeout
5000
Time in msec to wait for the event
Layer
0x02
Connection Handle
Handle
Boundary
0x02
0-Start Non-Flushable 1-Continuation 2-Start Flushable
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Length
0
Data
&ACLData
Spec 1.1
0 && _acl_count_ > 0 then
# Already set, Do nothing
else
_acl_size_ = 0
_acl_count_ = 0
_acl_available_ = 0
end if
# Make sure we have the size of ACL packets and the buffers count
if _acl_size_ == 0 || _acl_count_ == 0 then
Send_HCI_Read_Buffer_Size
Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any
end if
# If still no information the error
if _acl_size_ == 0 || _acl_count_ == 0 then
Fail "ACL Buffer Size Error"
end if
_acl_available_ = _acl_count_
# Create the whole payload (to be splited later for each ACL
_data_ = todata(size(_data_), 2) + todata(_cid_,2) + todata(_data_)
_size_ = size(_data_)
_pos_ = 0
_segment_ = _acl_size_
if _segment_ > 0 then
while _pos_ < _size_
# Loop on all free buffers available
while _pos_ < _size_ && _acl_available_ > 0
abPayload = mid(_data_, _pos_, _segment_)
Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)
_pos_ += _segment_
_acl_available_--
wend
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
wend
# Wait for all completed events that still need to come up
while _acl_available_ < _acl_count_
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
wend
end if
]]>
Connection Handle
Handle
CID
0xDAD1
Data
"Hello World"
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Spec 1.1
0 && _acl_count_ > 0 then
# Already set, Do nothing
else
_acl_size_ = 0
_acl_count_ = 0
_acl_available_ = 0
end if
# Make sure we have the size of ACL packets and the buffers count
if _acl_size_ == 0 || _acl_count_ == 0 then
Send_HCI_Read_Buffer_Size
Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any
end if
# If still no information the error
if _acl_size_ == 0 || _acl_count_ == 0 then
Fail "ACL Buffer Size Error"
end if
_acl_available_ = _acl_count_
# Create the whole payload (to be splited later for each ACL
_data_ = todata(size(_data_)+1, 2) + todata(_cid_,2) + todata(_data_) + todata(0, 1)
_size_ = size(_data_)
_pos_ = 0
_segment_ = _acl_size_
if _segment_ > 0 then
while _pos_ < _size_
# Loop on all free buffers available
while _pos_ < _size_ && _acl_available_ > 0
abPayload = mid(_data_, _pos_, _segment_)
Send_HCI_ACL_Packet _handle_, _pos_==0 ? 2 : 1, _brdcst_, todata(abPayload)
_pos_ += _segment_
_acl_available_--
wend
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
wend
# Wait for all completed events that still need to come up
while _acl_available_ < _acl_count_
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
wend
end if
]]>
Connection Handle
Handle
CID
0xDAD1
Text
"Hello World"
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Spec 1.1
Timeout
5000
Time in msec to wait for the event
Connection Handle
Handle
CID
0xDAD1
Text
"Hello World"
Spec 1.1
Layer
0x02
Connection Handle
Handle
Boundary
0x02
1-Continuation 2-Start
Broadcast flag
0x00
0-No broadcast 1-active 2-all
CID
0xDad1
Text
"Hello World"
Payload Length
size(text)+5
L2CAP Payload Length
size(text)+1
CID
cid
Text
text
Spec 1.1
Layer
0x02
Connection Handle
Handle
Boundary
0x02
1-Continuation 2-Start
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Payload Length
size(data)+4
L2CAP Payload Length
size(data)
CID
0xDad1
Data
"00:11:22"
Spec 1.1
= 0) then
_name_ = mid(_path_, _pos_+1)
else
_name_ = _path_
end if
if _fmt_==2 then
LoadFile _FileData_, _path_
_size_ = size(_FileData_)
Send_HCI_L2CAP_Packet_Data _handle_, 0xDA00, todata(_name_) + todata(0, 1) + _FileData_, _brdcst_
else
# Only on init
if _acl_size_ > 0 && _acl_count_ > 0 then
# Already set, Do nothing
else
_acl_size_ = 0
_acl_count_ = 0
_acl_available_ = 0
end if
# Make sure we have the size of ACL packets and the buffers count
if _acl_size_ == 0 || _acl_count_ == 0 then
Send_HCI_Read_Buffer_Size
Wait_HCI_Command_Complete_Read_Buffer_Size_Event 5000, any, HCI_Read_Buffer_Size, 0, &_acl_size_, any, &_acl_count_, any
end if
# If still no information the error
if _acl_size_ == 0 || _acl_count_ == 0 then
Fail "ACL Buffer Size Error"
end if
_acl_available_ = _acl_count_
##############################
# Write Header
##############################
LoadFile _FileData_, _path_
_size_ = size(_FileData_)
abHeaderData = todata(_size_, 4) + todata(_name_) + todata(0, 1)
Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abHeaderData
_acl_available_--
_pos_ = 0
_segment_ = _acl_size_ - 4
if _segment_ > 0 then
while _pos_ < _size_
# Loop on all free buffers available
while _pos_ < _size_ && _acl_available_ > 0
abPayload = mid(_FileData_, _pos_, _segment_)
Send_HCI_ACL_L2CAP_Data _handle_, _bdry_, _brdcst_, 0xDada, abPayload
_pos_ += _segment_
_acl_available_--
wend
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
WEnd
# Wait for all completed events that still need to come up
while _acl_available_ < _acl_count_
Wait_HCI_Number_Of_Completed_Packets_Event 45000, 0x01, _handle_, &_freed_
_acl_available_ += _freed_
WEnd
End If
End If
End If
]]>
Connection Handle
Handle
Type
0
File Path
""
Text
"Hello World"
Boundary
0x02
1-Continuation 2-Start
Broadcast flag
0x00
0-No broadcast 1-active 2-all
Format
0x00
0-UPF 1-HCICommander 2-L2CAP
Layer
0x08
Fm_Opcode
0
opcode of FM module [8 bits]
Command Type
0
0 - Write, 1 - Read
Length
0x05
Fm_Opcode
fm_opcode_
Command Type
command_type
Length
0x02
Data
0x0000
Data to write
Length
0x09
Fm_Opcode
fm_opcode_
Command Type
command_type
Length
0x06
Addr
0x00000000
Fm register address [16 bits]
Address
address
Data
0x0000
Data to write
Data Length
4
Data Length 0-1024 [16 bits]
Length
length+3
Fm_Opcode
fm_opcode_
Command Type
command_type
Data Length
length
Data
"0000"
start Address in hex (16 bit), and new code
Length
0x03
Fm_Opcode
fm_opcode_
Command Type
command_type
Length
0x02
Length
0x03
Fm_Opcode
fm_opcode_
Command Type
command_type
Length
0x03
Data Length [16 bits], should be multiple of 3, Max Length 250
Length
0x05
Fm_Opcode
fm_opcode_
Command Type
command_type
Length
0x02
Addr
0x0000
Fm register address [16 bits]
Address_div_2_
address_/2
FM_Channel_8_Event
Timeout
5000
Time in msec to wait for the event
Layer
0x08
Length
Status
0x00
Status
Num_FM_HCI_Commands
any
FM Opcode
0x00
Command Type
0x00
Data Length
0x02
Data Parameters
0x00
Data Parameters
0x00
Data Parameters
0x00
HCILL_GO_TO_Sleep_Ack_Event
HCILL_Wake_Up_Ack_Event
Timeout
5000
Time in msec to wait for the event
Layer
0x30
Timeout
5000
Time in msec to wait for the event
Layer
0x31
Timeout
5000
Time in msec to wait for the event
Layer
0x32
Timeout
5000
Time in msec to wait for the event
Layer
0x33
Layer
0xF0
Opcode
0x0001
General
Length
0x04
Baud rate
0
0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0002
Length
0x24
Reset BT now, Init baudrate
0
0 = Don't Reset, baudtare = FREF/320,
1 = Reset BT, baudtare = FREF/320,
2 = Don't Reset, baudtare = 115200,
3 = Reset BT, baudtare = 115200
Start Negotiation now
1
0= No 1= Yes
Flow control
0
0= Byte wise, 1= Packet wise, 0x0002-0xFFFE = segmentation (segment size in bytes)
Clock of BT device
13000000
Hz
Baud rate
0
0=low=115.2kbps, 1=high= either 921.6kbps or 1000kbps, or type the baudrate directly.
Palau spec 3.0
1
0=old spec, 1=new (16-bit align, new negotiation, Etc.)
RTS pulse width
0
Minumum width of RTS pulse in packet wise (T5)
Enable Deep sleep after negotiation
1
0=Keep previous (Enb/Dis), 1=Enable, 2=Disable deep sleep after negotiation
Padding needed
0
0= No 1= Yes
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0003
Data Generation Configuration
Length
0x18
Period of statistic message
20
Sec.
Send ACL Data packets to host
0
0=No 1=Yes
Order of packets
0
(Not supported) 0=Cyclic 1=Random. For 2 or more connections
Read Buffer size
0
0=DOT sends the command, Else=Buffer size of BT
Context of packets
0
0=Incremental data, 1=All bytes are zero
ThreshHold for statistics
0
0=STT_Event only, 1 and above= DBG_Event
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0004
TBD, Host flow Control
Length
0x20
Enable
1
Number of host ACL buffers
5
0..20
Host packet size
100
0..65535
Threshold, for host_num..
4
1..20, minimum number of ACL packets
Timeout to send host_num..
2000
ms, 10..10000, if threhold didn't happen
Algorithm to choose handle
0
0=Recived handle, 1=Round Robin
Time between commands
0
Not supported
Burst of commands
0
0=Normal, 1=Dot trys to send burst of commands
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0006
Deep Sleep (Nokia Only)
Length
0x10
Enable deep sleep
1
0=Disable 1=Enable
Minimum sleep time
0
ms, Minimum low time for BT_WAKEUP signal.
Minimum awake time
0
ms, Minimum high time for BT_WAKEUP signal.
Wait for cts before rising bt wakeup
0
0=Drop and Immediate raise of BT wakeup is Alowed. 1=After Droping the bt_wakeup, Wait for RTS.
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x001B
Deep Sleep (Motorola Only)
Length
0x14
Enable deep sleep
1
0=Disable 1=Enable
Minimum sleep time
0
ms, Minimum deassert time for BT_WAKE signal.
Minimum awake time
0
ms, Minimum assert time for BT_WAKE signal.
Polarity of BT_WAKE signal
0
0=active low, 1=active high.
Polarity of HOST_WAKE signal
0
0=active low, 1=active high.
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0010
Deep Sleep
Length
0x1C
Enable and Protocol
2
0=Disable, 2=HCILL
Just Sleep Time range1
0
ms, Minimum low time for BT_WAKEUP signal. Random LOWER range
Just Sleep Time range2
100
ms, Minimum low time for BT_WAKEUP signal. Random UPPER range
Just Wake Time range1
0
ms, Minimum high time for BT_WAKEUP signal. Random LOWER range
Just Wake Time range2
100
ms, Minimum high time for BT_WAKEUP signal. Random UPPER range
Delay before Wakeup Ack
0
ms
Delay before Sleep Ack
0
ms
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0039
Deep Sleep
Length
0x14
Enable and Protocol
4
0=Disable, 4=EMP
Just Sleep Time lower range
0
ms, Minimum time that the device will be sleeping
Just Sleep Time upper range
100
ms, Minimum time that the device will be sleeping
Just Wake Time lower range
0
ms, Minimum time that the device will be awake (before setting the break indication)
Just Wake Time upper range
100
ms, Minimum time that the device will be awake (before setting the break indication)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0011
Write Hardware Register
Length
0x06
Address
0x03007ffc
Value
0x0000
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0012
Read Hardware Register
Length
0x04
Address
0x03007ffc
Layer
0xF0
Opcode
0x0032
Configure ARMIO Port
Length
0x02
Port number
2
Available IO's - 2,3,5,14
port direction
0x0
1-Input, 0 -output
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0036
Write ARMIO Port
Length
0x02
ARMIO Port Number
2
Available IO's - 2,3,5,14
ARMIO Port Level
0
0=False, 1=True
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0033
Read ARMIO Port
Length
0x01
ARMIO Port Number
0
Available IO's - 2,3,5,14
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0015
Force BT wakeup signal
Length
0x04
Value
0
0=low=, 1=high. Dot Deep sleep protocol must be 'Disable'
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0016
Dot will send a palau alive message to BT devive
Length
0x04
Period (sec)
70
0=disable, other=period
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0017
Generate_SCO_Data
Length
0x0c
Channel
0
0/1 - SCO Channel
Data Genration Type
0
0=Off, 1=Loopback, 2=Codec, 3=Pattern Sine, 4=Pattern Byte Saw Tooth, 5=Pattern Packet Saw Tooth
Data Genration Rate
8000
Rate [Bytes/sec]. Valid Params for Codec: 8000 (8KHz 8bit),
16000 (8KHz 16bit), 24000 (8KHz 24bit), 32000 (32KHz 8bit)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0018
Configure_SCO_Data - The DOT executes read buffer size
Length
0x14
Channel
0
0/1 - SCO Channel
Min SCO Buffer Threshold
30
Min SCO Buffer threshold [bytes]
Max SCO Buffer Threshold
30
Max SCO Buffer threshold [bytes]
Min SCO Packet Size
30
Min SCO Packet Size [bytes]
Max SCO Packet Size
30
Max SCO Packet Size [bytes]
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x001A
Host SCO flow Control
Length
24
BT Flow Control Enable
0
1/0 - Enable/Disable Flow control from the Host to the BT
Host Flow Control Enable
0
1/0 - Enable/Disable Flow control from the BT to the host
Number of host SCO buffers
10
0..40, DOT3: 0..6
Host SCO buffer size
120
0..255
Threshold, for host_num..
4
1..20, minimum number of SCO buffers
Algorithm to choose handle
0
0=Received handle, 1=Round Robin
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0019
Activate H5 protocol
Length
0x14
Enable
5
5=Use H5 protocol, 4=Use H4 protocol
Baudrate
115200
bps
Window size
4
1-7
Flow control
1
0=None, 1=HW(cts/rts), 2=SW (xon/xoff)
CRC allowed
0
0=crc is not allowed, 1=crc is allowed
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x001E
Activate SDIO
Length
0x08
SDIO Mode
0
SDIO Data bus width
0 = 1 bit , 1 = 4 bits
Receive over Transmit priority
1
Value more then 0, determines during interleaving how many packets are to be received before resume of current tranmission. Zero means NO interleaving
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0029
SDIO deep sleep
Length
0x14
Deep Sleep Enable
0
0 - Disable, 1 - Enable
Just Sleep Time range1
0
ms,
Just Sleep Time range2
100
ms, Make sure that max value range for deassertion timer in DOT must be smaller than deassertion timer in sleep protocol configurations VS.
SDIO Sleep Mode
0
0 - Commands will wake up the device, 1 - SDIO Clocks will wakeup the device
SDIO min wake time before sending commands
0
Time (in us) between waking up the device and sending the first packet (relevant when clocks will wakeup the device)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x001F
Change read acknowledgement behavior
Length
0x04
Set Read Acknowledgement
0
0 = Disable , 1 = Enable
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0020
Change SDIO max clock
Length
0x04
Clock
25000000
Clock im Hz
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0021
Issue command 52
Length
20
SDIO destination
0
0 - Legacy mode,
1 - Shared SDIO, BT
2 - Shared SDIO, WLAN
Read / write
0
0 - Read, 1 - Write
Function Number
0
0 - 7
Read After Write flag
0
Register Address
0
Write Data
0
Must be 0 in read commands
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0022
Issue command 52
Length
84
SDIO destination
0
0 - Legacy mode,
1 - Shared SDIO, BT
2 - Shared SDIO, WLAN
Read / write
0
0 - Read, 1 - Write
Function Number
0
0 - 7
Block Mode and Opcode
0
0 - R/W from fixed address, 1 - R/W from incrementing address
Register Address
0
Byte / Block count
0
Must be 0 in read commands
Data to be sent
Relevant only in write commands
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0023
Issue SDIO General command
Length
8
SDIO destination
0
0 = Legacy mode,
1 = Shared SDIO, BT
2 = Shared SDIO, WLAN
SDIO Command value
0
Argument
0
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0024
Configure codec emulator. This command stops the sco generation.
Length
60
Enable/Disable
0
1 - Enable, 0 - Disable
Emulator clock rate
2048
[64-16000] The PCM clock rate is between 64k to 4096k (Master mode) or 64K to 16M (Slave mode), it influence other params like: wait cycles, freq rate calcs and therefore shall be configured even if external clock is used
Emulator role
0x00
PCM clock and fsync direction: 0x00 - output (Master on PCM bus) sampled on rising edge. 0x01 - input (Slave on PCM bus).
Frame sync frequency
8000
[100Hz-173KHz] Actual frame sync frequency in Hz.
Frame sync duty cycle
0x0001
0x0000 - 50 % of Fsync period, [0x0001-0xFFFF] - Number of PCM clock cycles
Frame sync edge
0x00
0x00 - Driven/sampled at rising edge, 0x01 - Driven/sampled at falling edge
Frame sync polarity
0x00
0x00 - Active-high, 0x01 - Active-low
Data out size
0x0010
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
Data out offset ch1
1
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
Data out offset ch2
17
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
Data out edge
0x00
Data driven: 0x00 - rising edge, 0x01 - falling edge
Data in size
0x10
[0x0001-0x0280] Sample size in bits for each codec fsync. In case data size is greater than 24 bits, the size should be able to divide by 8.
Data in offset ch1
1
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
Data in offset ch2
17
[0x00-0xFF] Number of pcm clock cycles between rising of frame sync to data start.
Data in edge
0x01
Data sampled: 0x00- rising edge, 0x01 - falling edge
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0025
eSPI configuration
Length
48
eSPI Mode
1
0 = Init,
1 = Change timing parameters
RX Delay Interrupt -> CS
0
Delay between Interrupt line assertion until CS assertion [u sec]
TX Delay Interrupt -> Header
0
Delay between Interrupt line assertion until header (type1) is sent [u sec]
RX Delay CS -> Header
0
Delay between CS line assertion until header (type3) is sent [u sec]
Delay Header -> Data
0
Delay between header to data [u sec]
Delay Data -> CS
0
Delay between last data byte until CS deassertion [u sec]
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Time between two consequtive HCI packets
0
Time between two consequtive HCI packets [u sec]
Reset BT Device
0
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0026
configure RX validity checking
Length
4
Mode
1
0 = Disable checking validity,
1 = Enable checking validity
Layer
0xF0
Opcode
0x002B
SPI mode
Length
2
SPI Mode
1
0 = eSPI mode, 1 = TI SPI Mode
SPI SWAP Mode (Reserved)
0
(Reserved)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0027
Configure SDIO error generation for Rx flow
(NACK generation instead of ACK)
Length
0x10
Random Mode
0
0 = Non random, 1 = Random mode
(errors are generated at random times on random blocks)
Packet number
0
Upon reception of which packet error will be generated.
0 - No error will be generated
Block number
0
Upon reception of which SD block error generated.
One shot
1
1 - one shot. 0 - forever
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0028
Configure SDIO error generation for Tx flow.
Noise generation on DAT line while SDIO transmits
Length
0x10
Random Mode
0
0 = Non random, 1 = Random mode
(errors are generated at random times on random blocks)
Packet number
0
Upon transmission of which packet error will be generated.
0 - No error will be generated
Block number
0
Upon transmission of which SD block error generated.
One shot
1
1 - one shot. 0 - forever
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x002A
Set Uart HCI Baudrate parameters
Length
0x10
Divider
0
Baudrate Uart Divider
Oversampling
0
Baudrate Uart Oversampling
Swallow Period
0
Baudrate Uart Swallow Period
Middle of Bit
0
Middle of Bit value
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0034
DOT_Cpu_Idle_Time
Length
0x2
Time
80
0-Enter CPU test mode , 1-Exit CPU test mode, other - start and check for "param" * 8ms (Dot Timer ticks)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x002E
Set DOT uart debug baud rate
Length
0x04
Baud Rate
921600
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0035
DOT test debug
Length
0x04
Param
0
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0040
DOT SLIMbus initialization and Configuration
Length
0x0A
Mode
1
1: Initialize and Configure, 0: Configure (already initialize). This parameter should be set to 1 at the first time this command being called, and only then.
Dot is Active Framer
1
1: Active Framer role is done by the DOT, 0: Active Framer role is done by another framer on the bus. If the setup includes only DOT and WL7, this parameter must be set to 1. This parameter is "Don't care" if Mode == 0
Initial Root Frequency
1
All frequencies are in MHz: 1: 24.576, 2: 22.5792, 3: 15.36, 4: 16.8, 5: 19.2 6: 24, 7: 25, 8: 26, 9: 27. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0
Initial Clock Gear
9
0 to 10, in respect to the definitions in the SLIMbus Specification. 10: clock is not divided, 9: clock is divided by 2, 8: divided by 4, and so on. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0
Initial Subframe Mode
0xB
Subframe Mode according to the SLIMbus Specification, to be used initially until reconfigured otherwise using normal SLIMbus sequence (NEXT_SUBFRAME_MODE). This parameter is "Don't care" if Mode == 0
Clock Source Select
0
0 - CODEC (12.288 MHz or 12 MHz), 1 - External (FPGA external clock), 2 - FREF (19.2 MHz). This parameter is "Don't care" if Mode == 0
Clock Divider
4
0 - ratio 1:32 (gears 6 to 10 forbidden), 1 - ratio 1:16 (gears 7 to 10 forbidden), 2 - ratio 1:8 (gears 8 to 10 forbidden), 3 - ratio 1:4 (gears 9 to 10 forbidden), 4 - ratio 1:2 (gear 10 forbidden), 5 - ratio 1:1 (root frequency = input frequency), 6 - 1:2, 7 - 1:4, 8 - 1:8, 9 - 1:16, 10 - 1:32. Note: At the moment, Initial Root Frequency must be 24.576, Initial Clock Gear must be 9, and Clock Divider must be 4. This parameter is "Don't care" if Mode == 0
Enable HCI
1
1 - Enable, 0 - Disable, 0xFF - Don't change
Enable Debug Level 1 Trace Messages
1
1 - Enable, 0 - Disable, 0xFF - Don't change
Enable Debug Level 2 Trace Messages
0
1 - Enable, 0 - Disable, 0xFF - Don't change
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0042
DOT SLIMbus manual clock resume
Length
0x00
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0044
DOT SLIMbus Audio CODEC Configuration
Length
0x04
audio format
0x53
sample rate
0x0C
left volume
0x17
right volume
0x17
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0041
DOT SLIMbus initialize Audio
Length
0x26
audio format
0x53
sample rate
0x0C
left volume
0x17
right volume
0x17
Channel 0
1
0-disable 1-TX 2-RX
Source Device ID
2
TX Device logical number
Sink Device ID
5
Rx Device logical number
TX Port index
4
1-HCI_TX;
4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1
8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1
RX Port index
2
0-HCI_RX;
2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1
6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1
Channel number
0
channel number from 0 to 7
Transport protocol
0
segment distribution
0x24
segment length
4
frequency locked
0
presence rate
0x11
auxiliary bit format
0
data type
0
channel link
0
data length
4
Channel 1
2
0-disable 1-TX 2-RX
Source Device ID
5
TX Device logical number
Sink Device ID
2
RX Device logical number
TX Port index
4
1-HCI_TX
4-BT_AUDIO_TX_0;5-BT_AUDIO_TX_1
8-FM_AUDIO_TX_0;9-FM_AUDIO_TX_1
RX Port index
2
0-HCI_RX
2-BT_AUDIO_RX_0;3-BT_AUDIO_RX_1
6-FM_AUDIO_RX_0;7FM_AUDIO_RX_1
Channel number
1
channel number from 0 to 7
Transport protocol
0
segment distribution
0x28
segment length
4
frequency locked
0
presence rate
0x11
auxiliary bit format
0
data type
0
channel link
0
data length
4
Subframe mode
0xA
Clock gear
8
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0048
DOT SLIMbus send message for Debug purpose
Length
3 + size(dest) + size(data)
Message ID
0x0C
Destination Length
size(dest)
Destination
"11:22:33:44:55:66"
Payload Length
size(data)
Data
"00:11:22"
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0043
Slimbus Deep Sleep in band and out of band
Length
0x18
Enable and Protocol
5
0=Disable, 5=SBIS 6=SB Out of Band
Just Sleep Time range1
0
ms, Minimum low time for BT_WAKEUP signal. Random LOWER range
Just Sleep Time range2
100
ms, Minimum low time for BT_WAKEUP signal. Random UPPER range
Just Wake Time range1
0
ms, Minimum high time for BT_WAKEUP signal. Random LOWER range
Just Wake Time range2
100
ms, Minimum high time for BT_WAKEUP signal. Random UPPER range
Automatic Clock Pause on HCI SUSPENDED
0
Contols whether when both TX and RX are suspended, the DOT automatically sends a clock pause sequence (begin/pause/now). 0: Disable, 1: Enable, 0xFF: Don't change
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x000B
Start Data Generation
Length
0x04
Connection Handle
0x0001
Test Type
3
1=RX 2=TX 3=RX+TX
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x000C
Stop Data Generation
Length
0x02
Connection Handle
0x0001
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x000D
Packet size
Length
0x12
Connection Handle
0x0001
Unit of packet size
0
0=Packet has a Fix size , 1=Random
Fix packet size
339
5-339, Affective only with Fix size
Random lower range
5
5-339, Affective only with Random
Random upper range
339
5-339, Affective only with Random
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x000E
Rate
Length
14
Connection Handle
0x0001
Maximum rate
0
Bit per second. 0= Maximum rate
Resolution
2
1=Delay every 1 second, 2=Delay every 8ms
Number of Packets
0
limit the number of bt buffers to use in TX. 0=Max buffers, 1 - Max buffers (lowest - highest)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x000F
L2CAP Header
Length
0x12
Connection Handle
0x0001
Number of TX channel ID's
1
How many headers are in this list
Algoritm to choose an ID
1
0=Cyclyc, 1=Random
TX Channel ID #1
0x0041
TX Channel ID #2
0xDADA
TX Channel ID #3
0x0042
TX Channel ID #4
0x0043
TX Channel ID #5
0x0044
A3DP RX channel ID
0x0000
0 - No ID
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x0014
Host flow control Rate
Length
6
Connection Handle
0x0001
Maximum rate
0
Bit per second. 0= Maximum rate
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x2C
ACL Header
Length
0x10
Connection Handle
0x0001
Configure ACL Header
1
0-Set header with fixed params 1-Set header according to the following params
ACL Boundary
2
0-Force Start 1-Force Continuation 2-Auto according to the L2CAP packet size
ACL Automatically Flushable
1
0=No, 1=Yes.
ACL Broadcast flag
0
0-No broadcast 1-active 2-all
L2CAP Payload Size
1021
Packet size in bytes.
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x2D
GPS data
Length
0x0A
Start Test
1
0-Stop test, 1-Start test
Min Packet length
800
1-Max packet length in bytes
Max Packet length
2000
(bytes)
Interval
1000
time in between packets (millisec)
DOT_DBG_Response_Event
Layer
0xF0
Opcode
0x2F
Configure ACL buffers
Length
0x4
TX Buffer Length
1021
10 to 1021 (default 1021 = 5 buffers)
RX Buffer Length
1021
10 to 1021 (default 1021 = 6 buffers)
DOT_DBG_Response_Event
Timeout
5000
Time in msec to wait for the event
Opcode
0x01
get statistics string
handle
TX rate (bit/sec)
RX rate (bit/sec)
TX packets (Since prv msg)
RX packets (Since prv msg)
RX ERR packets (Since prv msg)
notes
Timeout
5000
Time in msec to wait for the event
Opcode
0x02
assert
ASSERT
File
Line
Var
File
Fill
Timeout
5000
Time in msec to wait for the event
Opcode
0x01
get debug string
data
string
Timeout
5000
Time in msec to wait for the event
Opcode
0x04
get debug string
data
string
Timeout
5000
Time in msec to wait for the event
Opcode
0x02
assert
ASSERT
File
Line
Var
Timeout
5000
Time in msec to wait for the event
Opcode
0x03
response
Status
0
any
any
Fill
Timeout
5000
Time in msec to wait for the event
Opcode
0x05
get statistics string
handle
TX rate (bit/sec)
RX rate (bit/sec)
TX packets (Since prv msg)
RX packets (Since prv msg)
RX ERR packets (Since prv msg)
notes
Data
"00:11:22"
Layer
0x03
Handle
SCO_Handle
Length
size(data)
SCO Data
"00:11:22"
Layer
0x03
Handle
SCO_Handle
Length
size(data)
SCO Text
"Hello Bluetooth"
Timeout
5000
Time in msec to wait for the event
Data
"00:11:22"
Timeout
5000
Time in msec to wait for the event
Layer
0x04
Event Type
Any
Param Length
size(data)
Parameters
"00:11:22"
Timeout
5000
Time in msec to wait for the event
Layer
0x03
Handle
SCO_Handle
Length
size(data)
SCO Data
"00:11:22"
Baud Rate
115200
Flow Control
1
0=None, 1=HW, 2=Packet Wise, 5=Three Wire
Alignment Type
0
0=Don't Change, 1=No Alignment, 2=Word, 3=Segment Padding
Sleep Type
1
Enable or Disable L2CAP data in HCI_ACL_DATA
Address
"127.0.0.1"
Address to connect
IP Port
80
IP Type
0
KeepAlive
True
Auto reconnect on disconnect
Timeout Minimum
2000
Minimum idle time before host requests to sleep
Timeout Maximum
0
Maximum time for a random timeout. 0 = Uses the Minimum as a fixed value
Enable/Disable
2000
Enable (1) or Disable (0) for automatic suspend and resume
Sleep or Wakeup
1
Set current state as Sleep (1) or Wakeup (0)
Enable or Disable
1
0 = Disable, 1 = Enable
ACL or SCO
1
1 = ACL, 2 = SCO
Minimum Packets
20
Minimum count of packets in buffer to send a complete command
Timeout
500
Time (msec) to wait for minimum packets count to send a complete event
Flow Control
1
0 = None, 1 = Hardware, 2 = Software
ACL or SCO
1
1 = ACL, 2 = SCO
Sliding Window Size
5
Data Integrity
1
0 = None, 1 = Use
IR Length
6
IR Data
0x3e
DR Length
5
DR Data
0x10
Address
0x3800
JTAG Address
Bytes Size
2
Address
0x3800
JTAG Address
Bytes Size
2
Value
0x0000
Time
4000
Time in msec to wait until the device is up
Duration
1000
in milliseconds
Level
1
Level
7
Level of log.
Text
"Log this"
Formatted text to be logged
Label
""
Packet type or command name
Enable
True
Sets or removes a trace filter
NetworkScope
False
Clear trace of all hosts in current network
File Path
""
Path of the file to be used
Type
0
Create or Append
Text
""
Name
Name of sync point
Count
2
Total sync points to wait for
Timeout
0
Time in msec to wait. 0 = infinite
Variable
VarName
Variable name whose contents should be outputted to the port
Offset
0
Port offset: 0=0x378, 1=0x0379, 2=0x37A
Data
0x00
Data value to write to the port
Offset
0
Offset value related to 0x378. LastResult is set with the returned value
Event Opcode
0x00
Ignore
0
Message
"My Log Message"
Param 1
Param 2
Param 3
Param 4
Param 5
Wait
True
Wait until the execution is finished
Command
""
Path to the file to be executed
Arguments
""
Command line arguments
Folder
""
Folder in which the execution will start
Prompt
"Hello"
Text to be displayed
Style
0
Title
"Script"
Prompt Message
"Click OK to continue, Cancel to abort."
Text
"Script failed"
Reason
Reason
""
Reason of failure
Timeout
5000
Time in msec
Event's Opcode
Value of event's opcode
File Name
Absolute or relative path of the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Parameter
Parameter value to be passed to the filename
Variable
FileData
Variable name to get the file contents
File Path
"<path>"
Absolute or relative path of the filename
Enable Incoming
0
0 = Disable, 1 = Enable
Enable Outgoing
0
0 = Disable, 1 = Enable
Path
""
Path to the XML library
Append
False
True to append new XML to the current one. False to replace it.
Enable
False
Enable or disable default state of asynchronous events
Timeout
5000
Time in msec
Include Infinite
True
Wait also for pending infinite events to finish
Include Infinite
True
Clear also pending infinite events
Wibree
Event Opcode
Status
0x00
Connection Id
Role
Address Type
Peer Device Address
Interval
Latency
Timeout
Clock Accuracy
Number of Devices
0x01
Advertising Event Type
Device Address Type
Device Address
Data Length
Data
RSSI
Status
0x00
Connection Id
Connection Interval
Connection Latency
Connection Timeout
Status
0x00
Connection Id
Features Set
Connection Handle
Random Number
Encrypted Diversifier
Wibree
Hci_LE Event Mask
0x1F00000000000000
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Wibree
HCI_Command_Complete_Event
Status
0x00
Command status
Data Packet Length
Max length of data packets
Number of Data Packets
Number of Data Packets
Wibree
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Feature Set
LE Controller feature support bit map. This is treated as a parameter in which the LSO is transmitted first.
Wibree
Local Device Private Address
"010203040506"
HCI_Command_Complete_Event
Status
0x00
Command status
Wibree
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Number of empty entries
Number of empty entries in the device address White List in the LE Controller. Range: 0x01 to 0xFF
Wibree
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Wibree
Device Address Type
0x00
Indicates device address type of the address added to the list. 0x00 = Public address, 0x01 = Random address, 0x02-0xFF = Reserved
Device Address
"010203040506"
Device address that is to be added to the White List.
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Wibree
Device Address Type
0x00
Indicates device address type of the address added to the list. 0x00 = Public address, 0x01 = Random address, 0x02-0xFF = Reserved
Device Address
"010203040506"
Device address that is to be added to the White List.
HCI_Command_Complete_Event
Status
0x00
0x00 = Command succeeded. 0x01 – 0xFF = Command failed.
Wibree
Advertise Min Interval
0x0000
advIntervalmin = Adv_Interval_Min * 0.625 ms, advIntervalmin range: 20 ms to 10.24 s, Does not apply to connectable directed events.
Advertise Max Interval
0x0000
advIntervalmax = Adv_Interval * 0.625 ms, advIntervalmax range: 20 ms to 10.24 s, advIntervalmax shall be set to a value equal to or greater than the advIntervalmin Values outside the range are reserved. Does not apply to connectable directed events.
Advertising Type
0x00
advIntervalmax = Adv_Interval * 0.625 ms, advIntervalmax range: 20 ms to 10.24 s, advIntervalmax shall be set to a value equal to or greater than the advIntervalmin Values outside the range are reserved. Does not apply to connectable directed events.
Own_Address_Type
0x00
Public or random device address to use. The default is to use public
Direct Address Type
0x00
Public or random device address to use.The default is to use public
Direct Address
"010203040506"
Advertising Channel Map
7
Whcih channels out of 3 Adv channels to be used
Advertising Filter Policy
0
Advertiser filtering policy to be applied
HCI_Command_Complete_Event
Status
Command status
0x00
Wibree
HCI_Command_Complete_Event
Status
Command status
0
Advertising Channel TX Power
Transmit power of advertising channel
0x00
Wibree
Data Length
0x00
Advertising data
"000102030405060708090A0B0C0D0E0F"
HCI_Command_Complete_Event
Status
Command status
0x00
Wibree
Data Length
0x0000
Data
HCI_Command_Complete_Event
Status
Command status
0x00
Wibree
Advertise Mode
0x00
0x01 = On (start advertising), 0x00 = Off (stop advertising), 0x02-0xFF = Reserved
HCI_Command_Complete_Event
Status
Command status
0x00
Wibree
Scan Mode
0x01
Scan Interval
0x0004
Scan Window
0x0004
Local Device Address Type
0x00
Scanning Filter Policy
0x00
0 - Accept all advertisement packets,1 Ignore advertisement packets from devices not in the White List Only
HCI_Command_Complete_Event
Status
Command status
0x00
Wibree
Scan Enable
0x00
0x01 = On (start scanning), 0x00 = Off (stop scanning), 0x02-0xFF = Reserved
Filter Duplicates
0x01
0x0 = Duplicate filtering is disabled, 0x01 = Duplicate filtering is enabled
HCI_Command_Complete_Event
Status
0x00
0x00 = LE Controller started or stopped scan service successfully. 0x01 – 0xFF = Command failed.
Wibree
Scan Interval
0x0004
Time between consecutive scans. scanInterval = Scan_Interval * 0.625 ms, scanInterval range: 2.5 ms to 10.24 s, Scan_Interval range: 0x0004 to 0x4000.
Scan Window
0x0004
Duration of the scan. scanWindow = Scan_Window * 0.625 ms, scanWindow range: 2.5 ms to 10.24 s, Scan_Window range: 0x0004 to 0x4000.
Initiator_Filter_Policy
0x0
0x00 = White List not used but the advertiser’s address in this command is used, 0x01 = White List is used and the advertiser’s address in this command is not used, 0x02 – 0xFF = Reserved
Peer Device Address Type
0x00
Valid only if White_List = 0x00. Indicates address type of the advertiser’s address. 0x00 = Public address, 0x01 = Random address, 0x02 – 0xFF = Reserved.
Peer Device Address
"010203040506"
Valid only if White_List = 0x00. Device address of the advertiser to which the connection is to be created.
Local Device Address Type
0x00
Indicates whether to use own public or private device address. 0x00 = Public address, 0x01 = Random address, 0x02 – 0xFF = Reserved
Min Connection Interval
0x0008
connIntervalmin = Conn_Interval * 1.25 ms, Conn_Interval_Min range: 0x0006 to 0x0C80.
Max Connection Interval
0x0008
connIntervalmax = Conn_Interval * 1.25 ms, Conn_Interval_Max range: 0x0006 to 0x0C80, Shall be equal to or greater than the Conn_Interval_Min.
Connection Latency
"0x0002"
connSlaveLatency = Conn_Latency (as number of LL connection events). Conn_Latency range: 0x0000 to 0x03E8.
Connection Timeout
"0x0001"
connTimeout = Conn_Timeout * 10 ms Conn_Timeout range: 0x000A to 0x0C80.
Minimum Length
0x0000
minimum length = Minimum_Length * 0.625 ms, Minimum_Length range: 0x01 to 2*Conn_Interval
Maximum Length
0x0000
maximum length = Maximum_Length * 0.625 ms, Maximum_Length range: 0x01 to 2*Conn_Interval
HCI_Command_Status_Event
Wibree
HCI_Command_Complete_Event
Status
0x00 = Connection creation stopped. 0x01 – 0xFF = Command failed.
0x00
Wibree
Connection Handle
0x0000
Local identifier of the LL connection
Min Connection Interval
0x0003
connInterval = Conn_Interval * 1.25 ms, Conn_Interval range: 0x0006 to 0x0C80
Max Connection Interval
0x0003
connIntervalmax = Conn_Interval * 1.25 ms, Conn_Interval_Max range: 0x0006 to 0x0C80, Shall be equal to or greater than the Conn_Interval_Min.
Connection Latency
0x0000
connSlaveLatency = Conn_Latency (as number of LL connection events). Conn_Latency range: 0x0000 to 0x01F4
Connection Timeout
0x0001
connTimeout = Conn_Timeout * 10 ms, Conn_Timeout range: 0x000A to 0x0C80
Minimum Length
0x0000
minimum length = Minimum_Length * 0.625 ms, Minimum_Length range: 0x01 to 2*Conn_Interval
Maximum Length
0x0000
maximum length = Maximum_Length * 0.625 ms, Maximum_Length range: 0x01 to 2*Conn_Interval
HCI_Command_Status_Event
Wibree
BLE Channel Map
"FFFFFFFF1F"
HCI_Command_Complete_Event
Status
0x00
Status
Handle
0x0000
HCI_Command_Complete_Event
Status
0x00
Handle
0x0000
BLE Channel Map
"FFFFFFFF1F"
Wibree
Connection Handle
0x401
Local identifier of the LL connection
HCI_Command_Status_Event
HCI_Command_Complete_Event
Status
0x00
Command status
Feature Set
Indicates the size of the Feature_Set parameter in octets
Wibree
Key
"05AF519CF0E41E8A0C3C76C0D550A6A9"
Data
"85B2261C8E840E389868E9EFEA18A27F"
HCI_Command_Complete_Event
Status
0x00
Command status
Encrypted Data
Wibree
HCI_Command_Complete_Event
Status
0x00
Command status
Random Data
Wibree
Connection Handle
Local identifier of the LL connection to which the command applies
Random
Random vector used in device identification
Encrypted Diversifier
Encrypted diversifier
Long Term Key
Long term key
HCI_Command_Status_Event
Wibree
Connection Handle
Local identifier of the LL connection to which the command applies
Key
"0102030405060708090A0B0C0D0E0F10"
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Wibree
Connection Handle
Local identifier of the LL connection to which the command applies
HCI_Command_Complete_Event
Status
0x00
Status
Connection Handle
Wibree
HCI_Command_Complete_Event
Status
0x00
Status
Supported States
0
LE States as defined in spec
Wibree
RX Frequency
0x00
Frequency on which the tester sends data
HCI_Command_Complete_Event
Status
0x00
Status
Wibree
TX Frequency
0x00
Frequency on which the DUT sends data
Data Length
0x00
Data Length
Packet Payload Type
0
Payload type: 0 - PRBS 9, 1 - Pattern 11110000, 2 - Pattern 10101010, 3 - PRBS 15, 4 - All 1, 5 - All 0, 6 - 00001111, 7 - 0101
HCI_Command_Complete_Event
Status
0x00
Status
Wibree
HCI_Command_Complete_Event
Status
0x00
Status
Number of packets received
0
Number of packets received.Zero in TX test
Spec 1.1
Pin Name
1
Select pin to Mux
AUD_IN Pin mux
0x00
AUD_IN Pin mux
AUD_OUT Pin mux
0x00
AUD_OUT Pin mux
AUD_CLK Pin mux
0x00
AUD_CLK Pin mux
AUD_FSYNC Pin mux
0x00
AUD_FSYNC Pin mux
TX_HCI Pin mux
0x00
TX_HCI Pin mux
RX_HCI Pin mux
0x00
TX_HCI Pin mux
CTS_HCI Pin mux
0x00
CTS_HCI Pin mux
RTS_HCI Pin mux
0x00
RTS_HCI Pin mux
BT_FUNC_1 Pin mux
0x00
BT_FUNC1 Pin mux
BT_FUNC_2 Pin mux
0x00
BT_FUNC2 Pin mux
BT_FUNC_3 Pin mux
0x00
BT_FUNC3 Pin mux
BT_FUNC_4 Pin mux
0x00
BT_FUNC4 Pin mux
BT_FUNC_5 Pin mux
0x00
BT_FUNC5 Pin mux
BT_FUNC_1 Pin mux
0x00
BT_FUNC6 Pin mux
BT_FUNC_7 Pin mux
0x00
BT_FUNC1 Pin mux
BT_FUNC_8 Pin mux
0x00
BT_FUNC8 Pin mux
BT_FUNC_1 Pin mux
0x00
BT_FUNC1 Pin mux
BT_FUNC_10 Pin mux
0x00
BT_FUNC10 Pin mux
Spec 1.1
Pin Name
1
Select pin to Mux
TX_HCI Pin mux
0x00
TX_HCI Pin mux
RX_HCI Pin mux
0x00
RX_HCI Pin mux
CTS_HCI Pin mux
0x00
CTS_HCI Pin mux
RTS_HCI Pin mux
0x00
RTS_HCI Pin mux
AUD_IN Pin mux
0x00
AUD_IN Pin mux
AUD_OUT Pin mux
0x00
AUD_OUT Pin mux
AUD_CLK Pin mux
0x00
AUD_CLK Pin mux
AUD_FSYNC Pin mux
0x00
AUD_FSYNC Pin mux
BT_FUNC_1 Pin mux
0x00
BT_FUNC1 Pin mux
BT_FUNC_2 Pin mux
0x00
BT_FUNC2 Pin mux
TX_DBG Pin mux
0x00
TX_DBG Pin mux
BT_FUNC_4 Pin mux
0x00
BT_FUNC4 Pin mux
BT_FUNC_6 Pin mux
0x00
BT_FUNC6 Pin mux
BT_FUNC_7 Pin mux
0x00
BT_FUNC_7 Pin mux
CLK_REQ_OUT Pin mux
0x00
CLK_REQ_OUT Pin mux
FM_IRQ Pin mux
0x00
FM_IRQ Pin mux
FM_SCL Pin mux
0x00
FM_SCL Pin mux
FM_SDA Pin mux
0x00
FM_SDA Pin mux
FM_I2S_DI Pin mux
0x00
FM_I2S_DI Pin mux
FM_I2S_DO Pin mux
0x00
FM_I2S_DO Pin mux
FM_I2S_CLK Pin mux
0x00
FM_I2S_CLK Pin mux
FM_I2S_WS Pin mux
0x00
FM_I2S_WS Pin mux
Spec 1.1
Pin Name
1
Select pin to Mux
TX_HCI Pin mux
0x00
TX_HCI Pin mux
RX_HCI Pin mux
0x00
RX_HCI Pin mux
CTS_HCI Pin mux
0x00
CTS_HCI Pin mux
RTS_HCI Pin mux
0x00
RTS_HCI Pin mux
AUD_IN Pin mux
0x00
AUD_IN Pin mux
AUD_OUT Pin mux
0x00
AUD_OUT Pin mux
AUD_CLK Pin mux
0x00
AUD_CLK Pin mux
AUD_FSYNC Pin mux
0x00
AUD_FSYNC Pin mux
BT_FUNC_1 Pin mux
0x00
BT_FUNC_1 Pin mux
BT_FUNC_2 Pin mux
0x00
BT_FUNC_2 Pin mux
BT_FUNC_5 Pin mux
0x00
BT_FUNC_5 Pin mux
BT_FUNC_3 Pin mux
0x00
BT_FUNC_3 Pin mux
BT_FUNC_6 Pin mux
0x00
BT_FUNC_6 Pin mux
BT_FUNC_7 Pin mux
0x00
BT_FUNC_7 Pin mux
SB_DATA Pin mux
0x00
SB_DATA Pin mux
CSB_CLK Pin mux
0x00
SB_CLK Pin mux
WL_TX Pin mux
0x00
WL_TX Pin mux
WL_RX Pin mux
0x00
WL_RX Pin mux
FREF_CLK_REQ Pin mux
0x00
FREF_CLK_REQ Pin mux
FM_I2S_DI Pin mux
0x00
FM_I2S_DI Pin mux
FM_I2S_DO Pin mux
0x00
FM_I2S_DO Pin mux
FM_I2S_CLK Pin mux
0x00
FM_I2S_CLK Pin mux
FM_I2S_WS Pin mux
0x00
FM_I2S_WS Pin mux
SPI_CSX Pin mux
0x00
SPI_CSX Pin mux
WLAN_IRQ Pin mux
0x00
WLAN_IRQ Pin mux
WL_UART_DBG Pin mux
0x00
WL_UART_DBG Pin mux
WL_PAEN_A Pin mux
0x00
WL_PAEN_A Pin mux
WL_PAEN_B Pin mux
0x00
WL_PAEN_B Pin mux
WL_BTH_SW Pin mux
0x00
WL_BTH_SW Pin mux
WL_EXT_LNA_EN Pin mux
0x00
WL_EXT_LNA_EN Pin mux
WL_RS232_RX Pin mux
0x00
WL_RS232_RX Pin mux
WL_RS232_TX Pin mux
0x00
WL_RS232_TX Pin mux
JTAG_TCK Pin mux
0x00
JTAG_TCK Pin mux
JTAG_TMS Pin mux
0x00
JTAG_TMS Pin mux
JTAG_TDI Pin mux
0x00
JTAG_TDI Pin mux
JTAG_TDO Pin mux
0x00
JTAG_TDO Pin mux
GPS_UART_TX Pin mux
0x00
GPS_UART_TX Pin mux
GPS_UART_RX Pin mux
0x00
GPS_UART_RX Pin mux
GPS_SENS_I2C_SCL Pin mux
0x00
GPS_SENS_I2C_SCL Pin mux
GPS_SENS_I2C_SDA Pin mux
0x00
GPS_SENS_I2C_SDA Pin mux
TESTMODE Pin mux
0x00
TESTMODE Pin mux
TCXO_CLK_REQ Pin mux
0x00
TCXO_CLK_REQ Pin mux
GPS_IRQ Pin mux
0x00
GPS_IRQ Pin mux
GPS_TIMESTAMP Pin mux
0x00
GPS_TIMESTAMP Pin mux
GPS_PPS_OUT Pin mux
0x00
GPS_PPS_OUT Pin mux
GPS_I2C_UART_SELECT Pin mux
0x00
GPS_I2C_UART_SELECT Pin mux
GPS_EXT_LNA_EN Pin mux
0x00
GPS_EXT_LNA_EN Pin mux
GPS_PA_EN Pin mux
0x00
GPS_PA_EN Pin mux
DC2DC_MODE Pin mux
0x00
DC2DC_MODE Pin mux
TCXO_SLI_OUT Pin mux
0x00
TCXO_SLI_OUT Pin mux
WL_SPI_DIN Pin mux
0x00
WL_SPI_DIN Pin mux
WL_SPI_DOUT Pin mux
0x00
WL_SPI_DOUT Pin mux
WL_SDIO_D1 Pin mux
0x00
WL_SDIO_D1 Pin mux
WL_SDIO_D2 Pin mux
0x00
WL_SDIO_D2 Pin mux
Spec 1.1
GCM signal select
0x00
1-Selects the output clock on test_clk output
DBG pin number
0x01
Selects the outputs to be muxed on the test output
Spec 1.1
0 then
# WRITE _test_dtst_enable to DTST_CTRL Register
# Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0x1B, 0x001f
# Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE DTST Enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_dtst_enable<<4, 0x0010
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE _test_apll_clk_select to DTST_CTRL Register
end if
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
if _test_clk_mux_sel > 3 & _test_clk_mux_sel < 7 then
# WRITE _test_mirror_enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,1, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
else
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
end if
log "test_dtst_enable %d", _test_dtst_enable
#******************* DRP DTST REG CONFIG END *******************************************************#
#******************* DRP DTST Bus Override *******************************************************#
# WRITE TestBusOverrideSelect to Register
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021e, _TestBusOverrideSelect
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
# WRITE TestBusOverrideValue to Register
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021c, _TestBusOverrideValue
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
if _TestBusOverrideSelect > 0 then
# WRITE _test_mirror_enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190102, 1<<12, 0x1000
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE _test_apll_clk_select to DTST_CTRL Register
end if
#******************* DRP DTST Bus Override End *******************************************************#
]]>
Signal_sel
0x00
1-Selects the signals to Mux
Module_sel
0x00
Selects the DRP Module
shift_select
0x00
0 - Select Number of bits to mux
test_clk_mux_sel
0x00
Selects the output clock on test_clk output
test_dtst_enable
1
0 - Enable\Disable DTST
test_mirror_enable
0
0 - Enable Mirrore
test_apll_clk_select
0
TestBusOverrideSelect
0
TestBusOverrideValue
0x0000
1-Enter TestBusOverrideValue
pins_group_select
0x00
0 - Select between IO pins and External Memory pins works only for NL5500
Spec 1.1
0)
chunk_size = Min(block_size,200)
Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x00190200, chunk_size
Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata
WriteFile FileName1, 1, StrData(mydata)
WriteFile FileName1, 1, "\n"
block_size-=chunk_size
Wend
# Reset start address
#DTST_MEM_OCP_PARAMS - write start_address
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190216, 0
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
# config _DTST_Mem_Addr_Load =1
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190210, 0x0001<<4, 0x0010
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# read 2st block - from buffer_start to stp_addr
block_size = (stp_addr+1)*4
While (block_size>0)
chunk_size = Min(block_size,200)
Send_HCI_VS_Read_Memory_Block_From_DTST 0xFD7F, 0x00190200, chunk_size
Wait_HCI_Command_Complete_VS_Read_Memory_Block_From_DTST_Event 5000, any, HCI_VS_Read_Memory_Block_From_DTST, 0x00, &mydata
WriteFile FileName1, 1, StrData(mydata)
WriteFile FileName1, 1, "\n"
block_size-=chunk_size
Wend
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190218, DtstParamL
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021a, DtstParamL
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190210, DtstMemCtrl
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190206, DtstCtrl
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x00190214, saveddtst
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
#************************************************************************************************************#
]]>
DTST_Mem_Max_Use
0x04
Selects Memory Size
DTST_filename
"C:\Temp\DTST_results"
Chose the Path and filename
Spec 1.1
DTST_Mem_Mode
0x00
Selects the Memory Mode
DTST_Mem_Enable
1
0 - Enable\Disable Mem
DTST_Enable
1
0 - Enable\Disable Mem
DTST_Signal_sel
0x00
1-Selects the signals to Mux
DTST_Module_sel
0x00
Selects the DRP Module
DTST_Clk_Sel
0x00
Selects the output clock on test_clk output
DTST_Mem_Max_Use
0x00
Selects Memory Size
DTST_Mem_Step_Size
0x00
0 - Select Step Size in bytes
DTST_Mem_Word_Select
0x00
Selects DTST Mem Word MSB LSB
DTST_Mem_Offset
0x000
1-Selects the DTST Mem Offset up to 4KByte
DTST_Mem_Wrap_Enable
1
0 - Enable\Disable Wrap
DTST_sleep_time
0x0000
Selects how length of the recording procudure in us (sleep between redord enable/disable
Spec 1.1
DTST_Mem_Mode
0x00
Selects the Memory Mode
DTST_Mem_Enable
1
0 - Enable\Disable Mem
DTST_Enable
1
0 - Enable\Disable Mem
DTST_Signal_sel
0x00
1-Selects the signals to Mux
DTST_Module_sel
0x00
Selects the DRP Module
DTST_Clk_Sel
0x00
Selects the output clock on test_clk output
DTST_Mem_Max_Use
0x00
Selects Memory Size
DTST_Mem_Step_Size
0x00
0 - Select Step Size in bytes
DTST_Mem_Word_Select
0x00
Selects DTST Mem Word MSB LSB
DTST_Mem_Offset
0x000
1-Selects the DTST Mem Offset up to 4KByte
DTST_Mem_Wrap_Enable
1
0 - Enable\Disable Wrap
Spec 1.1
Spec 1.1
> 8
valL = valLT << 8
GFSKPowerValue=valL+valH
WriteFile FileNameGFSK,1, "%x",GFSKPowerValue
next
WriteFile FileNameGFSK, 1, "\""
#GFSK LOOP
WriteFile FileNameEDR2, 0,"EDR2PowerValue=\""
for loop=0 to ( LoopNom )
EDR2PowerValueT=EDR2PowerValueT-EDR2DeltaPowerValueT
valLT = EDR2PowerValueT&0x00ff
valHT = EDR2PowerValueT&0xff00
valH = valHT >> 8
valL = valLT << 8
EDR2PowerValue=valL+valH
WriteFile FileNameEDR2,1, "%x",EDR2PowerValue
next
WriteFile FileNameEDR2, 1, "\""
#EDR3 LOOP
WriteFile FileNameEDR3, 0,"EDR3PowerValue=\""
for loop=0 to ( LoopNom )
EDR3PowerValueT=EDR3PowerValueT-EDR3DeltaPowerValueT
valLT = EDR3PowerValueT&0x00ff
valHT = EDR3PowerValueT&0xff00
valH = valHT >> 8
valL = valLT << 8
EDR3PowerValue=valL+valH
WriteFile FileNameEDR3,1, "%x",EDR3PowerValue
next
WriteFile FileNameEDR3, 1, "\""
callfile "C:\Temp\GFSKPowerSet.txt"
callfile "C:\Temp\EDR2PowerSet.txt"
callfile "C:\Temp\EDR3PowerSet.txt"
#write GFSK POWER values
Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193356, 32,GFSKPowerValue
Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00
#write EDR2 POWER values
Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193376, 32,EDR2PowerValue
Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00
#write EDR3 POWER values
Send_HCI_VS_Write_Memory_Block 0xFF05, 0x193396, 32,EDR3PowerValue
Wait_HCI_Command_Complete_VS_Write_Memory_Block_Event 5000, any, HCI_VS_Write_Memory_Block, 0x00
]]>
GFSKMaxPowerValue
0x0000
1-Selects GFSK Max Power
GFSKDeltaPowerValue
0x0000
1-Selects GFSK Delta Power
EDR2MaxPowerValue
0x0000
1-Selects EDR2 Max Power
EDR2DeltaPowerValue
0x0000
1-Selects EDR2 Delta Power
EDR3MaxPowerValue
0x0000
1-Selects EDR3 Max Power
EDR3DeltaPowerValue
0x0000
1-Selects EDR3 Delta Power
Opcode
0xFD93
Enabel Conversion from 48KHz rate to 8/16KHz
Enable Rate
0x0
Bit0=convert to 8KHz enable, Bits 1-7=Reserved
Reserved
0x0
Reserved
Reserved
0x0
Reserved
Reserved
0x0
Reserved
HCI_Command_Complete_Event
Opcode
0xFD94
Set Source for Voice Links
Voice Handle
0x0000
0x0000 - Clear Association, 0x0101..0x702 - Associate Existing Handle, 0xFFFF - Associate Next Handle
Source
0
0 - Host(Default), 1 - FM
Path
0
0 - Regular voice connection, 1 - WBS conneciton
HCI_Command_Complete_Event
Opcode
0xFD95
Controls the audio output pin mux and override pull registers
PCMI override
0xFFFFFFFF
The value of the PCMI_TOP_CTRL_REG. 0xFFFFFFFF indicates no change. For Quattro pull upddate done through Quatt pcmi pull config only when override filed is not 0xFFFFFFFF. The value in Quattro sets PCM CTRL reg. Value of 0xFFFFFFFE updates only PCM pull reg for Quattro
I2S override
0xFFFFFFFF
The value of the I2S_TOP_CTRL_REG. 0xFFFFFFFF indicates no change. For Quattro pull upddate done through Quatt i2s pull config only when override filed is not 0xFFFFFFFF. The value in Quattro sets I2S CTRL reg. Value of 0xFFFFFFFE updates only I2S pull reg for Quattro
BT Audio Path
0xFF
0 - None, 1 - PCM, 2 - I2S, 0xFF - Don't Change
FM Audio Path
0xFF
0 - None, 1 - PCM, 2 - I2S, 0xFF - Don't Change
TDM Enable
0xFF
0 - Enable TDM with BT M, 1 - Enable TDM with FM M, 2 - Enable TDM with Host M, 3 - Disable TDM, 0xFF - Don't Change
Quattro PCMI pull config
0
Quattro pcmi pull config (fieled is applied when PCMI override is 0xFFFFFFFE or different than 0xFFFFFFFF) 0:1- Audio in, 2:3- audio out, 4:5- audio clock, 6:7- audio fsync
Quattro I2S pull config
0
Quattro i2s pull config (fieled is applied when I2S override is 0xFFFFFFFE or different than 0xFFFFFFFF) 0:1- Din, 2:3- Dout, 4:5- clock, 6:7- fsync
Reserved
0
Reserved
0
HCI_Command_Complete_Event
Opcode
0xFD77
Sets parameters for the BLE Test Mode
TX Power Level
0xF
Transmit power level
RX Mode
1
0 - Normal mode, 1 - Wide Window, 2 - Continious RX, 3 - Wide window and power saving
Packets to transmit
0
A number of packets to transmit.0 means continious TX
Access Code
0x71764129
An access code to sync/transmit.Default value is 0x71764129
BLE BER Test Enable
0
Enable of the BER test
BLE Ber Test pattern
0
A data pattern of the payload that is expected to be received
BER Test packet length
10
A number of payload bytes that are expected to be received in the BER test
BER FA Threshold
20
A threshold for the FA detection
Trace Enable
0
Enables or Disables traces during the BER test
Referance CRC
0
Referance CRC value for the packet
HCI_Command_Complete_Event
Opcode
0xFDA4
Sets GPIO waving of BLE BB signals, if value is 0xFF do not wave IO for this signal
TX strech select
0xFF
IO pin for TX strech
RX strech select
0xFF
IO pin for RX strech
CRC OK select
0xFF
IO pin for CRC OK
CONNECT_REQ TX select
0xFF
IO pin for CONNECT_REQ TX
SCAN_REQ TX select
0xFF
IO pin for CAN_REQ TX
CTRL PACKET RECEIVED select
0xFF
IO pin for signals ctrl packet received
CTRL PACKET SENT select
0xFF
IO pin for ctrl packet sent
RETRANSMIT DATA select
0xFF
IO pin for retransmit data packet sent
NO_SYNC_TIME
0xFF
IO pin indicating NO SYNC, set high every time RX was expected but there was no SYNC
reserved5
0xFF
IO pin for reserved
HCI_Command_Complete_Event
Spec 1.1
0 then
# WRITE _test_dtst_enable to DTST_CTRL Register
# Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, 0x1B, 0x001f
# Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE DTST Enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190206, _test_dtst_enable<<4, 0x0010
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE _test_apll_clk_select to DTST_CTRL Register
end if
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
if _test_clk_mux_sel > 3 & _test_clk_mux_sel < 7 then
# WRITE _test_mirror_enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,1, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
else
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00191260,0, 0x0001
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
end if
log "test_dtst_enable %d", _test_dtst_enable
#******************* DRP DTST REG CONFIG END *******************************************************#
#******************* DRP DTST Bus Override *******************************************************#
# WRITE TestBusOverrideSelect to Register
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021e, _TestBusOverrideSelect
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
# WRITE TestBusOverrideValue to Register
Send_HCI_VS_Write_Hardware_Register 0xFF01, 0x0019021c, _TestBusOverrideValue
Wait_HCI_Command_Complete_VS_Write_Hardware_Register_Event 5000, any, HCI_VS_Write_Hardware_Register, 0x00
if _TestBusOverrideSelect > 0 then
# WRITE _test_mirror_enable to DTST_CTRL Register
Send_HCI_VS_Read_Modify_Write_Hardware_Register 0xFD09, 0x00190102, 1<<12, 0x1000
Wait_HCI_Command_Complete_VS_Read_Modify_Write_Hardware_Register_Event 5000, any, HCI_VS_Read_Modify_Write_Hardware_Register, 0x00
# WRITE _test_apll_clk_select to DTST_CTRL Register
end if
#******************* DRP DTST Bus Override End *******************************************************#
]]>
Signal_sel
0x00
1-Selects the signals to Mux
Module_sel
0x00
Selects the DRP Module
shift_select
0x00
0 - Select Number of bits to mux
test_clk_mux_sel
0x00
Selects the output clock on test_clk output
test_dtst_enable
1
0 - Enable\Disable DTST
test_mirror_enable
0
0 - Enable Mirrore
test_apll_clk_select
0
TestBusOverrideSelect
0
TestBusOverrideValue
0x0000
1-Enter TestBusOverrideValue
Opcode
0xFDA1
HCIPP Read LE Statistics
HCI_Command_Complete_Event
Status
0
0 - Success, 1 - Illegal command
Num_ADV_sent_ch0
Any
Num of ADV packets sent by advertiser on ch 0
Num_ADV_sent_ch1
Any
Num of ADV packets sent by advertiser on ch 1
Num_ADV_sent_ch2
Any
Num of ADV packets sent by advertiser on ch 2
Num_SCAN_RSP_sent_ch0
Any
Num of SCAN_RSP packets sent by advertiser on ch 0
Num_SCAN_RSP_sent_ch1
Any
Num of SCAN_RSP packets sent by advertiser on ch 1
Num_SCAN_RSP_sent_ch2
Any
Num of SCAN_RSP packets sent by advertiser on ch 2
Num_SCAN_REQ_received_ch0
Any
Num of SCAN_REQ packets received by advertiser on ch 0
Num_SCAN_REQ_received_ch1
Any
Num of SCAN_REQ packets received by advertiser on ch 1
Num_SCAN_REQ_received_ch2
Any
Num of SCAN_REQ packets received by advertiser on ch 2
Num_ADV_received_ch0
Any
Num of ADV packets received by scanner on ch 0
Num_ADV_received_ch1
Any
Num of ADV packets received by scanner on ch 1
Num_ADV_received_ch2
Any
Num of ADV packets received by scanner on ch 2
Num_SCAN_RSP_received_ch0
Any
Num of SCAN_RSP packets received by scanner on ch 0
Num_SCAN_RSP_received_ch1
Any
Num of SCAN_RSP packets received by scanner on ch 1
Num_SCAN_RSP_received_ch2
Any
Num of SCAN_RSP packets received by scanner on ch 2
Num_SCAN_REQ_sent_ch0
Any
Num of SCAN_REQ packets sent by scanner on ch 0
Num_SCAN_REQ_sent_ch1
Any
Num of SCAN_REQ packets sent by scanner on ch 1
Num_SCAN_REQ_sent_ch2
Any
Num of SCAN_REQ packets sent by scanner on ch 2