Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
===================================================================
--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-02-08 14:05:34.034501648 -0600
+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-02-08 14:07:19.010677033 -0600
@@ -42,7 +42,8 @@
 ALLOW_PIO3=y
 CONFIG_HAS_PIO3=y
 CPU_HAS_PMECC=y
-CONFIG_LOAD_ONE_WIRE=y
+# MTS: don't load one wire
+# CONFIG_LOAD_ONE_WIRE is not set
 
 #
 # Memory selection
@@ -102,4 +103,5 @@
 # CONFIG_USER_HW_INIT is not set
 CONFIG_THUMB=y
 CONFIG_SCLK=y
-CONFIG_DISABLE_WATCHDOG=y
+# MTS: don't disable watchdog
+# CONFIG_DISABLE_WATCHDOG is not set
Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h
===================================================================
--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.h	2013-02-08 14:03:42.050364515 -0600
+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h	2013-02-08 14:07:56.500399983 -0600
@@ -95,7 +95,8 @@
 #define CONFIG_SYS_NAND_CLE_PIN		AT91C_PIN_PD(3)
 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91C_PIN_PD(4)
 
-#define	PMECC_ERROR_CORR_BITS		2
+/* MTS: use 4-bit PMECC */
+#define	PMECC_ERROR_CORR_BITS		4
 #define	PMECC_SECTOR_SIZE		512
 
 #define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET	0xC000
Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c
===================================================================
--- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.c	2013-02-08 14:03:57.562179405 -0600
+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c	2013-02-08 14:11:56.477737850 -0600
@@ -268,10 +268,9 @@
 
 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
 	reg |= AT91C_EBI_CS3A_SM;
-	if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST))
-		reg &= ~AT91C_EBI_NFD0_ON_D16;
-	else
-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
+	/* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */
+	reg &= ~AT91C_EBI_NFD0_ON_D16;
+	reg &= ~AT91C_EBI_DDR_MP_EN;
 
 	reg &= ~AT91C_EBI_DRV;
 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
@@ -300,10 +299,7 @@
 		| AT91_SMC_TDF_(1)),
 		AT91C_BASE_SMC + SMC_CTRL3);
 
-	/* Configure the PIO controller */
-	if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST))
-		pio_configure(nand_pins_lo);
-	else
+	/* MTR2 */
 		pio_configure(nand_pins_hi);
 
 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));