From c6096a2290cec993d135e79676c259a8876065ec Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Wed, 13 Feb 2013 11:29:14 -0600 Subject: linux-2.6.39.4: add support for mtocgd3 Uses the following patches from Atmel for AT91SAM9X5 support * 2.6.39-at91-exp.2 patches * SAM9X5 PMECC patches * SAM9X5 atmel_serial patches --- ...ine-at_hdmac-modify-way-to-use-interrupts.patch | 75 + ...at_hdmac-add-cyclic-DMA-operation-support.patch | 319 ++ ...t_hdmac-debug-information-sg_len-for-prep.patch | 32 + ...t_hdmac-remove-channel-status-testing-in-.patch | 41 + ...t_hdmac-specialize-AHB-interfaces-to-opti.patch | 121 + ...ine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch | 33 + ...-rtc-at91-workaround-for-5series-ES-chips.patch | 79 + ...exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch | 41 + ...91-overall-definition-add-5series-support.patch | 356 +++ ...0-ARM-at91-PMC-header-add-5series-support.patch | 121 + ...t91-clock-add-5series-chip-family-support.patch | 215 ++ ...T91SAM9x5-processors-and-EK-board-support.patch | 3216 ++++++++++++++++++++ ...M-at91-provide-defconfig-for-at91sam9x5ek.patch | 218 ++ ...9-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch | 32 + ...-0015-ARM-at91-pio-add-new-PIO3a-features.patch | 440 +++ ...sb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch | 39 + ...ocksource-tcb-add-support-for-32-bit-mode.patch | 114 + ...atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch | 100 + ...19-serial-atmel-convert-to-use-dma-engine.patch | 562 ++++ ...eo-atmel_lcdfb-add-support-for-AT91SAM9x5.patch | 1803 +++++++++++ ..._lcdfb-The-output-bpp-should-not-change-a.patch | 66 + ...el_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch | 410 +++ ..._tsadcc-add-touch-screen-pressure-measure.patch | 109 + ..._tsadcc-enable-touchscreen-averaging-and-.patch | 81 + ..._tsadcc-add-ACR-register-and-change-trigg.patch | 97 + ...D-atmel_nand-Add-PMECC-controller-support.patch | 1175 +++++++ ...nand-optimize-read-write-buffer-functions.patch | 130 + ...pi-atmel_spi-trivial-change-some-comments.patch | 40 + ...9-spi-atmel_spi-add-physical-base-address.patch | 39 + ...l_spi-call-unmapping-on-transfers-buffers.patch | 43 + ...pi-status-information-passed-through-cont.patch | 80 + ...pi-add-flag-to-controller-data-for-lock-o.patch | 119 + ...-0033-spi-atmel_spi-add-dmaengine-support.patch | 654 ++++ ...0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch | 33 + ...0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch | 34 + ...Input-qt1070-trivial-fix-CHANGE-line-typo.patch | 30 + ...t1070-add-power-management-suspend-resume.patch | 166 + ...t_hdmac-clear-channel-status-on-channel-r.patch | 30 + ...t_hdmac-set-residue-as-total-len-in-atc_t.patch | 41 + ...t_hdmac-implement-pause-and-resume-in-atc.patch | 170 ++ ...t_hdmac-pause-no-need-to-wait-for-FIFO-em.patch | 60 + ...t_hdmac-replace-spin_lock-with-irqsave-va.patch | 244 ++ ...t_hdmac-improve-power-management-routines.patch | 182 ++ ...d-atmel-pcm-trivial-typo-in-debug-comment.patch | 30 + ...-pcm-trivial-typo-in-atmel_pcm_dma_params.patch | 31 + ...ngine-at_hdmac-add-slave-config-operation.patch | 58 + ...xp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch | 29 + ...0048-sound-wm8731-rework-power-management.patch | 44 + ...atmel-ssc-add-phybase-in-device-structure.patch | 44 + ...c-dmaengine-usage-switch-depending-on-cpu.patch | 36 + ...51-sound-atmel_ssc_dai-fix-ssc-error-path.patch | 35 + ..._ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch | 706 +++++ ...5_wm8731-machine-driver-for-at91sam9x5-wm.patch | 291 ++ ...and-do-not-scream-while-using-PIO-instead.patch | 33 + ...2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch | 83 + ...-fix-wm8731_check_osc-connected-condition.patch | 37 + ...am9g20_wm8731-use-the-proper-SYSCKL-value.patch | 34 + ..._ssc_dai-PM-actually-stopping-clock-on-su.patch | 73 + ...-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch | 29 + ...pi-add-bit-in-mode-register-to-prevent-ov.patch | 130 + ...am9x5-video-new-driver-for-the-high-end-o.patch | 1530 ++++++++++ ...n-at91_can-don-t-align-struct-definitions.patch | 81 + ...n-at91_can-fix-comment-about-priv-tx_next.patch | 31 + ...1_can-don-t-copy-data-to-rx-ed-RTR-frames.patch | 42 + ...n-let-get_tx_-functions-return-unsigned-i.patch | 44 + ...-at91_can-directly-define-AT91_MB_RX_LAST.patch | 39 + ...n-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch | 74 + ...n-convert-derived-mailbox-constants-into-.patch | 296 ++ ...n-add-id_table-and-convert-prime-mailbox-.patch | 337 ++ ...n-register-mb0-sysfs-entry-only-on-at91sa.patch | 45 + ...1_can-add-support-for-the-AT91SAM9X5-SOCs.patch | 139 + ...ideobuf2-memops-use-pr_debug-for-debug-me.patch | 51 + ...fb-initially-split-atmelfb-into-a-driver-.patch | 2622 ++++++++++++++++ ....2-0074-video-atmelfb-refactor-core-setup.patch | 403 +++ ....2-0075-video-atmelfb-refactor-start-stop.patch | 196 ++ ...t91-exp.2-0076-video-atmelfb-refactor-isr.patch | 154 + ...video-atmelfb-refactor-backlight-routines.patch | 256 ++ ....2-0078-video-atmelfb-refactor-dma_update.patch | 211 ++ ...t91-exp.2-0079-video-atmelfb-refactor-LUT.patch | 80 + ...0-video-atmelfb-refactor-limit_screeninfo.patch | 92 + ...xp.2-0081-arm-at91-refactor-lcdc-includes.patch | 2648 ++++++++++++++++ ....2-0082-video-atmel_hlcdfb-add-new-driver.patch | 606 ++++ ...0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch | 30 + ...at91-sam9x5ek-use-16bpp-as-default-for-fb.patch | 34 + ...xp.2-0085-create-platform-device-for-ovl1.patch | 97 + ....39-at91-exp.2-0086-WIP-add-clut-resource.patch | 167 + ...el_lcdfb-add-error-msg-when-out-of-memory.patch | 33 + ...cut-vb2_reqbufs-in-case-the-format-change.patch | 42 + ...-change-atmel-lcdfb-driver-selection-mode.patch | 95 + ..._ssc_dai-add-a-missing-space-to-an-error-.patch | 35 + ...-Atmel-Image-Sensor-Interface-ISI-support.patch | 1233 ++++++++ ...exp.2-0092-add-isi-support-in-board-files.patch | 238 ++ ...1-exp.2-0093-media-at91-add-dumb-set_parm.patch | 40 + ...-5series-add-ISI-device-and-board-support.patch | 232 ++ ...095-AT91-board-remove-not-needed-comments.patch | 47 + ...-exp.2-0096-AT91-5series-update-defconfig.patch | 266 ++ ...atmel_tsadcc-rework-irq-infrastructure-an.patch | 191 ++ ...es-Update-LCD-timings-to-avoid-flickering.patch | 33 + ...cdfb-change-pixel-clock-ratio-calculation.patch | 31 + ...and_pmecc-fix-warning-about-uninitialized.patch | 27 + ...MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch | 29 + ...ASoC-wm8731-active-bit-and-OSC-management.patch | 98 + ...91-at91sam9x5-add-can-clocks-to-9x25-chip.patch | 27 + ...T91-LCD-include-remove-not-needed-comment.patch | 27 + ...s-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch | 102 + ...ug-incorrect-register-address-for-remaind.patch | 27 + ...2-0107-ARM-at91-add-smd-device-definition.patch | 112 + ...D-atmel_nand-Add-PMECC-controller-support.patch | 1177 +++++++ ...atmel_nand-optimize-read-write-buffer-fun.patch | 126 + ...tract-hw-ecc-initialization-to-one-functi.patch | 229 ++ ...nd-add-PMECC-parameters-in-nand-structure.patch | 30 + ...mel_nand-add-Programmable-Multibit-ECC-co.patch | 980 ++++++ ...port-to-2.6.39.-modify-function-definitio.patch | 65 + ...pass-the-pmecc-parameter-from-board-file-.patch | 86 + ...el_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch | 38 + .../0009-atmel_nand-enable-dma-for-9x5ek.patch | 28 + .../linux-2.6.39.4-atmel_serial_disable_hwhs.patch | 32 + .../linux-2.6.39.4-ledtrig-netdev.patch | 488 +++ .../linux-2.6.39.4-option-telit.patch | 43 + .../recipes/linux/linux-2.6.39.4/mtocgd3/defconfig | 2328 ++++++++++++++ ...ux-2.6.39.4-at91sam9_wdt-10second-timeout.patch | 14 + .../linux-2.6.39.4-at91sam9x5-extreset.patch | 16 + .../linux-2.6.39.4-atmel-mci-force-detect.patch | 30 + .../mtocgd3/linux-2.6.39.4-macb-force-link.patch | 75 + .../mtocgd3/linux-2.6.39.4-mach-at91-mtocgd3.patch | 403 +++ .../mtocgd3/linux-2.6.39.4-wl12xx-sdio-irq.patch | 15 + ...DMA-AT91-Get-residual-bytes-in-dma-buffer.patch | 327 ++ ...igure-DMAC-configuration-register-for-usa.patch | 73 + ...gure-peripheral-id-and-enable-basic-usart.patch | 153 + ...-Serial-Enable-Serial-cyclic-DMA-transfer.patch | 399 +++ .../0005-Serial-AT91-Refine-tx-dma.patch | 167 + ...-AT91-refine-error-handler-in-probe-stage.patch | 70 + ...T91-Add-dma-support-for-rs485-and-iso7816.patch | 71 + ...8-Serial-AT91-remove-tx-dma-issue-pending.patch | 32 + ...-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch | 37 + ...91-Make-DBGU-support-dma-and-pdc-transfer.patch | 183 ++ .../serial_dma_rx_at91sam9x5_1.0/Change-log.txt | 30 + .../serial_dma_rx_at91sam9x5_1.0/how to apply.txt | 16 + multitech/recipes/linux/linux_2.6.39.4.bb | 151 +- 139 files changed, 34894 insertions(+), 1 deletion(-) create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0013-ARM-at91-provide-defconfig-for-at91sam9x5ek.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0014-usb-AT91SAM9X5-has-EHCI.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0015-ARM-at91-pio-add-new-PIO3a-features.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0016-usb-AT91SAM9X5-has-a-atmel_usba_udc-device.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0017-clocksource-tcb-add-support-for-32-bit-mode.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0018-mmc-atmel-mci-add-support-for-ARCH_AT91SAM9X5.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0019-serial-atmel-convert-to-use-dma-engine.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0020-video-atmel_lcdfb-add-support-for-AT91SAM9x5.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0021-video-atmel_lcdfb-The-output-bpp-should-not-change-a.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0022-input-atmel_tsadcc-add-support-for-ARCH_AT91SAM9X5.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0023-input-atmel_tsadcc-add-touch-screen-pressure-measure.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0024-input-atmel_tsadcc-enable-touchscreen-averaging-and-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0025-input-atmel_tsadcc-add-ACR-register-and-change-trigg.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0026-MTD-atmel_nand-Add-PMECC-controller-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0027-MTD-atmel_nand-optimize-read-write-buffer-functions.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0028-spi-atmel_spi-trivial-change-some-comments.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0029-spi-atmel_spi-add-physical-base-address.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0030-spi-atmel_spi-call-unmapping-on-transfers-buffers.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0031-spi-atmel_spi-status-information-passed-through-cont.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0032-spi-atmel_spi-add-flag-to-controller-data-for-lock-o.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0033-spi-atmel_spi-add-dmaengine-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0034-net-can-allow-CAN_AT91-on-AT91SAM9X5.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0035-Input-qt1070-Add-MODULE_DEVICE_TABLE.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0036-Input-qt1070-trivial-fix-CHANGE-line-typo.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0037-Input-qt1070-add-power-management-suspend-resume.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0038-dmaengine-at_hdmac-clear-channel-status-on-channel-r.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0039-dmaengine-at_hdmac-set-residue-as-total-len-in-atc_t.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0040-dmaengine-at_hdmac-implement-pause-and-resume-in-atc.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0041-dmaengine-at_hdmac-pause-no-need-to-wait-for-FIFO-em.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0042-dmaengine-at_hdmac-replace-spin_lock-with-irqsave-va.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0043-dmaengine-at_hdmac-improve-power-management-routines.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0044-sound-atmel-pcm-trivial-typo-in-debug-comment.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0045-sound-atmel-pcm-trivial-typo-in-atmel_pcm_dma_params.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0046-dmaengine-at_hdmac-add-slave-config-operation.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0047-SPI-m25p80-add-serial-flash-IDs.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0048-sound-wm8731-rework-power-management.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0049-atmel-ssc-add-phybase-in-device-structure.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0050-atmel-ssc-dmaengine-usage-switch-depending-on-cpu.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0051-sound-atmel_ssc_dai-fix-ssc-error-path.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0052-sound-atmel_ssc_dai-atmel-pmc-adapt-to-dmaengine-usa.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0053-sound-sam9x5_wm8731-machine-driver-for-at91sam9x5-wm.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0054-mtd-atmel_nand-do-not-scream-while-using-PIO-instead.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0055-MMC-PM-suspend-resume-in-atmel-mci.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0056-ASoc-wm8731-fix-wm8731_check_osc-connected-condition.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0057-ASoc-sam9g20_wm8731-use-the-proper-SYSCKL-value.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0058-sound-atmel_ssc_dai-PM-actually-stopping-clock-on-su.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0059-ARM-at91-sam9x5-increase-CONSISTENT_DMA_SIZE.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0060-SPI-atmel_spi-add-bit-in-mode-register-to-prevent-ov.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0061-media-at91sam9x5-video-new-driver-for-the-high-end-o.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0062-can-at91_can-don-t-align-struct-definitions.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0063-can-at91_can-fix-comment-about-priv-tx_next.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0064-can-at91_can-don-t-copy-data-to-rx-ed-RTR-frames.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0065-can-at91_can-let-get_tx_-functions-return-unsigned-i.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0066-can-at91_can-directly-define-AT91_MB_RX_LAST.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0067-can-at91_can-rename-AT91_MB_RX_MASK-to-AT91_IRQ_MB_R.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0068-can-at91_can-convert-derived-mailbox-constants-into-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0069-can-at91_can-add-id_table-and-convert-prime-mailbox-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0070-can-at91_can-register-mb0-sysfs-entry-only-on-at91sa.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0071-can-at91_can-add-support-for-the-AT91SAM9X5-SOCs.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0072-media-V4L-videobuf2-memops-use-pr_debug-for-debug-me.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0073-video-atmelfb-initially-split-atmelfb-into-a-driver-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0074-video-atmelfb-refactor-core-setup.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0075-video-atmelfb-refactor-start-stop.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0076-video-atmelfb-refactor-isr.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0077-video-atmelfb-refactor-backlight-routines.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0078-video-atmelfb-refactor-dma_update.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0079-video-atmelfb-refactor-LUT.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0080-video-atmelfb-refactor-limit_screeninfo.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0081-arm-at91-refactor-lcdc-includes.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0082-video-atmel_hlcdfb-add-new-driver.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0083-arm-at91-sam9x5-use-new-hlcdc-driver.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0084-arm-at91-sam9x5ek-use-16bpp-as-default-for-fb.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0085-create-platform-device-for-ovl1.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0086-WIP-add-clut-resource.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0087-video-atmel_lcdfb-add-error-msg-when-out-of-memory.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0088-Don-t-shortcut-vb2_reqbufs-in-case-the-format-change.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0089-at91-video-change-atmel-lcdfb-driver-selection-mode.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0090-sound-atmel_ssc_dai-add-a-missing-space-to-an-error-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0091-at91-add-Atmel-Image-Sensor-Interface-ISI-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0092-add-isi-support-in-board-files.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0093-media-at91-add-dumb-set_parm.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0094-AT91-5series-add-ISI-device-and-board-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0095-AT91-board-remove-not-needed-comments.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0096-AT91-5series-update-defconfig.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0097-AT91-input-atmel_tsadcc-rework-irq-infrastructure-an.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0098-5series-Update-LCD-timings-to-avoid-flickering.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0099-atmel_lcdfb-change-pixel-clock-ratio-calculation.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0100-MTD-atmel_nand_pmecc-fix-warning-about-uninitialized.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0101-MTD-atmel_nand-fix-wrong-use-of-0-as-NULL.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0102-ASoC-wm8731-active-bit-and-OSC-management.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0103-AT91-at91sam9x5-add-can-clocks-to-9x25-chip.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0104-AT91-LCD-include-remove-not-needed-comment.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0105-AT91-5series-fix-SPI0-MCI1-ISI-pins-conflicts-in-boa.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0106-PMECC-Fix-bug-incorrect-register-address-for-remaind.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0107-ARM-at91-add-smd-device-definition.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0001-Revert-MTD-atmel_nand-Add-PMECC-controller-support.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0002-Revert-MTD-atmel_nand-optimize-read-write-buffer-fun.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0003-mtd-at91-extract-hw-ecc-initialization-to-one-functi.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0004-atmel_nand-add-PMECC-parameters-in-nand-structure.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0005-mtd-at91-atmel_nand-add-Programmable-Multibit-ECC-co.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0006-atmel_nand-port-to-2.6.39.-modify-function-definitio.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0007-atmel_nand-pass-the-pmecc-parameter-from-board-file-.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0008-atmel_nand-9x5ek-enable-PMECC-in-9x5ek-board.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/9x5_pmecc_2639/0009-atmel_nand-enable-dma-for-9x5ek.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-atmel_serial_disable_hwhs.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-ledtrig-netdev.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/linux-2.6.39.4-option-telit.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/defconfig create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9_wdt-10second-timeout.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-at91sam9x5-extreset.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-atmel-mci-force-detect.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-macb-force-link.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-mach-at91-mtocgd3.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/mtocgd3/linux-2.6.39.4-wl12xx-sdio-irq.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0001-DMA-AT91-Get-residual-bytes-in-dma-buffer.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0002-Serial-Configure-DMAC-configuration-register-for-usa.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0003-Configure-peripheral-id-and-enable-basic-usart.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0004-Serial-Enable-Serial-cyclic-DMA-transfer.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0005-Serial-AT91-Refine-tx-dma.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0006-Serial-AT91-refine-error-handler-in-probe-stage.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0007-Serial-AT91-Add-dma-support-for-rs485-and-iso7816.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0008-Serial-AT91-remove-tx-dma-issue-pending.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0009-Serial-AT91-Fix-DBGU-peripheral_id-wrong.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/0010-serial-at91-Make-DBGU-support-dma-and-pdc-transfer.patch create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/Change-log.txt create mode 100644 multitech/recipes/linux/linux-2.6.39.4/serial_dma_rx_at91sam9x5_1.0/how to apply.txt diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch new file mode 100644 index 0000000..4967bd3 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0001-dmaengine-at_hdmac-modify-way-to-use-interrupts.patch @@ -0,0 +1,75 @@ +From e22e7d2f67c4f8003215863361f19ac6acdb927e Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 1 Feb 2011 19:58:30 +0100 +Subject: [PATCH 001/107] dmaengine: at_hdmac: modify way to use interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Now we use Buffer Transfer Completed interrupts. If we +want a chained buffer completed information, we setup the +ATC_IEN bit in CTRLB register in the lli. +This is done by set_desc_eol() function and used by +memcpy/slave_sg functions. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/at_hdmac.c | 4 ++-- + drivers/dma/at_hdmac_regs.h | 11 ++++++++--- + 2 files changed, 10 insertions(+), 5 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index 235f53b..5124e09 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -464,7 +464,7 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id) + + for (i = 0; i < atdma->dma_common.chancnt; i++) { + atchan = &atdma->chan[i]; +- if (pending & (AT_DMA_CBTC(i) | AT_DMA_ERR(i))) { ++ if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { + if (pending & AT_DMA_ERR(i)) { + /* Disable channel on AHB error */ + dma_writel(atdma, CHDR, atchan->mask); +@@ -549,7 +549,7 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + } + + ctrla = ATC_DEFAULT_CTRLA; +- ctrlb = ATC_DEFAULT_CTRLB ++ ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN + | ATC_SRC_ADDR_MODE_INCR + | ATC_DST_ADDR_MODE_INCR + | ATC_FC_MEM2MEM; +diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h +index 495457e..8303306 100644 +--- a/drivers/dma/at_hdmac_regs.h ++++ b/drivers/dma/at_hdmac_regs.h +@@ -309,8 +309,8 @@ static void atc_setup_irq(struct at_dma_chan *atchan, int on) + struct at_dma *atdma = to_at_dma(atchan->chan_common.device); + u32 ebci; + +- /* enable interrupts on buffer chain completion & error */ +- ebci = AT_DMA_CBTC(atchan->chan_common.chan_id) ++ /* enable interrupts on buffer transfer completion & error */ ++ ebci = AT_DMA_BTC(atchan->chan_common.chan_id) + | AT_DMA_ERR(atchan->chan_common.chan_id); + if (on) + dma_writel(atdma, EBCIER, ebci); +@@ -347,7 +347,12 @@ static inline int atc_chan_is_enabled(struct at_dma_chan *atchan) + */ + static void set_desc_eol(struct at_desc *desc) + { +- desc->lli.ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS; ++ u32 ctrlb = desc->lli.ctrlb; ++ ++ ctrlb &= ~ATC_IEN; ++ ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS; ++ ++ desc->lli.ctrlb = ctrlb; + desc->lli.dscr = 0; + } + +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch new file mode 100644 index 0000000..63d1757 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0002-dmaengine-at_hdmac-add-cyclic-DMA-operation-support.patch @@ -0,0 +1,319 @@ +From 50730e4e5183b199232b7c0f93eadd8af1e439a6 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 1 Feb 2011 16:39:11 +0100 +Subject: [PATCH 002/107] dmaengine: at_hdmac: add cyclic DMA operation + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/at_hdmac.c | 187 +++++++++++++++++++++++++++++++++++++++--- + drivers/dma/at_hdmac_regs.h | 14 +++- + 2 files changed, 185 insertions(+), 16 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index 5124e09..a58ae65 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -237,16 +237,12 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) + static void + atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) + { +- dma_async_tx_callback callback; +- void *param; + struct dma_async_tx_descriptor *txd = &desc->txd; + + dev_vdbg(chan2dev(&atchan->chan_common), + "descriptor %u complete\n", txd->cookie); + + atchan->completed_cookie = txd->cookie; +- callback = txd->callback; +- param = txd->callback_param; + + /* move children to free_list */ + list_splice_init(&desc->tx_list, &atchan->free_list); +@@ -278,12 +274,19 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) + } + } + +- /* +- * The API requires that no submissions are done from a +- * callback, so we don't need to drop the lock here +- */ +- if (callback) +- callback(param); ++ /* for cyclic transfers, ++ * no need to replay callback function while stopping */ ++ if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) { ++ dma_async_tx_callback callback = txd->callback; ++ void *param = txd->callback_param; ++ ++ /* ++ * The API requires that no submissions are done from a ++ * callback, so we don't need to drop the lock here ++ */ ++ if (callback) ++ callback(param); ++ } + + dma_run_dependencies(txd); + } +@@ -419,6 +422,26 @@ static void atc_handle_error(struct at_dma_chan *atchan) + atc_chain_complete(atchan, bad_desc); + } + ++/** ++ * atc_handle_cyclic - at the end of a period, run callback function ++ * @atchan: channel used for cyclic operations ++ * ++ * Called with atchan->lock held and bh disabled ++ */ ++static void atc_handle_cyclic(struct at_dma_chan *atchan) ++{ ++ struct at_desc *first = atc_first_active(atchan); ++ struct dma_async_tx_descriptor *txd = &first->txd; ++ dma_async_tx_callback callback = txd->callback; ++ void *param = txd->callback_param; ++ ++ dev_vdbg(chan2dev(&atchan->chan_common), ++ "new cyclic period llp 0x%08x\n", ++ channel_readl(atchan, DSCR)); ++ ++ if (callback) ++ callback(param); ++} + + /*-- IRQ & Tasklet ---------------------------------------------------*/ + +@@ -434,8 +457,10 @@ static void atc_tasklet(unsigned long data) + } + + spin_lock(&atchan->lock); +- if (test_and_clear_bit(0, &atchan->error_status)) ++ if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) + atc_handle_error(atchan); ++ else if (test_bit(ATC_IS_CYCLIC, &atchan->status)) ++ atc_handle_cyclic(atchan); + else + atc_advance_work(atchan); + +@@ -469,7 +494,7 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id) + /* Disable channel on AHB error */ + dma_writel(atdma, CHDR, atchan->mask); + /* Give information to tasklet */ +- set_bit(0, &atchan->error_status); ++ set_bit(ATC_IS_ERROR, &atchan->status); + } + tasklet_schedule(&atchan->tasklet); + ret = IRQ_HANDLED; +@@ -759,6 +784,127 @@ err_desc_get: + return NULL; + } + ++/** ++ * atc_dma_cyclic_prep - prepare the cyclic DMA transfer ++ * @chan: the DMA channel to prepare ++ * @buf_addr: physical DMA address where the buffer starts ++ * @buf_len: total number of bytes for the entire buffer ++ * @period_len: number of bytes for each period ++ * @direction: transfer direction, to or from device ++ */ ++static struct dma_async_tx_descriptor * ++atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, ++ size_t period_len, enum dma_data_direction direction) ++{ ++ struct at_dma_chan *atchan = to_at_dma_chan(chan); ++ struct at_dma_slave *atslave = chan->private; ++ struct at_desc *first = NULL; ++ struct at_desc *prev = NULL; ++ unsigned long was_cyclic; ++ unsigned int periods = buf_len / period_len; ++ unsigned int reg_width; ++ u32 ctrla; ++ u32 ctrlb; ++ unsigned int i; ++ ++ dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", ++ direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", ++ buf_addr, ++ periods, buf_len, period_len); ++ ++ if (unlikely(!atslave || !buf_len || !period_len)) { ++ dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); ++ return NULL; ++ } ++ ++ was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); ++ if (was_cyclic) { ++ dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); ++ return NULL; ++ } ++ ++ reg_width = atslave->reg_width; ++ ++ /* Check for too big/unaligned periods and unaligned DMA buffer */ ++ if (period_len > (ATC_BTSIZE_MAX << reg_width)) ++ goto err_out; ++ if (unlikely(period_len & ((1 << reg_width) - 1))) ++ goto err_out; ++ if (unlikely(buf_addr & ((1 << reg_width) - 1))) ++ goto err_out; ++ if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) ++ goto err_out; ++ ++ /* prepare common CRTLA/CTRLB values */ ++ ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla ++ | ATC_DST_WIDTH(reg_width) ++ | ATC_SRC_WIDTH(reg_width) ++ | period_len >> reg_width; ++ ctrlb = ATC_DEFAULT_CTRLB; ++ ++ /* build cyclic linked list */ ++ for (i = 0; i < periods; i++) { ++ struct at_desc *desc; ++ ++ desc = atc_desc_get(atchan); ++ if (!desc) ++ goto err_desc_get; ++ ++ switch (direction) { ++ case DMA_TO_DEVICE: ++ desc->lli.saddr = buf_addr + (period_len * i); ++ desc->lli.daddr = atslave->tx_reg; ++ desc->lli.ctrla = ctrla; ++ desc->lli.ctrlb = ctrlb ++ | ATC_DST_ADDR_MODE_FIXED ++ | ATC_SRC_ADDR_MODE_INCR ++ | ATC_FC_MEM2PER; ++ break; ++ ++ case DMA_FROM_DEVICE: ++ desc->lli.saddr = atslave->rx_reg; ++ desc->lli.daddr = buf_addr + (period_len * i); ++ desc->lli.ctrla = ctrla; ++ desc->lli.ctrlb = ctrlb ++ | ATC_DST_ADDR_MODE_INCR ++ | ATC_SRC_ADDR_MODE_FIXED ++ | ATC_FC_PER2MEM; ++ break; ++ ++ default: ++ return NULL; ++ } ++ ++ if (!first) { ++ first = desc; ++ } else { ++ /* inform the HW lli about chaining */ ++ prev->lli.dscr = desc->txd.phys; ++ /* insert the link descriptor to the LD ring */ ++ list_add_tail(&desc->desc_node, ++ &first->tx_list); ++ } ++ prev = desc; ++ } ++ ++ /* lets make a cyclic list */ ++ prev->lli.dscr = first->txd.phys; ++ ++ /* First descriptor of the chain embedds additional information */ ++ first->txd.cookie = -EBUSY; ++ first->len = buf_len; ++ ++ return &first->txd; ++ ++err_desc_get: ++ dev_err(chan2dev(chan), "not enough descriptors available\n"); ++ atc_desc_put(atchan, first); ++err_out: ++ clear_bit(ATC_IS_CYCLIC, &atchan->status); ++ return NULL; ++} ++ ++ + static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) + { +@@ -795,6 +941,10 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + + spin_unlock_bh(&atchan->lock); + ++ /* XXX/ukl: should this be done with bh disabled? */ ++ /* if channel dedicated to cyclic operations, free it */ ++ clear_bit(ATC_IS_CYCLIC, &atchan->status); ++ + return 0; + } + +@@ -853,6 +1003,10 @@ static void atc_issue_pending(struct dma_chan *chan) + + dev_vdbg(chan2dev(chan), "issue_pending\n"); + ++ /* Not needed for cyclic transfers */ ++ if (test_bit(ATC_IS_CYCLIC, &atchan->status)) ++ return; ++ + spin_lock_bh(&atchan->lock); + if (!atc_chan_is_enabled(atchan)) { + atc_advance_work(atchan); +@@ -1092,10 +1246,15 @@ static int __init at_dma_probe(struct platform_device *pdev) + if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) + atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; + +- if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { ++ if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) + atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; ++ ++ if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) ++ atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; ++ ++ if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) || ++ dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) + atdma->dma_common.device_control = atc_control; +- } + + dma_writel(atdma, EN, AT_DMA_ENABLE); + +diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h +index 8303306..c79a9e0 100644 +--- a/drivers/dma/at_hdmac_regs.h ++++ b/drivers/dma/at_hdmac_regs.h +@@ -181,12 +181,22 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd) + /*-- Channels --------------------------------------------------------*/ + + /** ++ * atc_status - information bits stored in channel status flag ++ * ++ * Manipulated with atomic operations. ++ */ ++enum atc_status { ++ ATC_IS_ERROR = 0, ++ ATC_IS_CYCLIC = 24, ++}; ++ ++/** + * struct at_dma_chan - internal representation of an Atmel HDMAC channel + * @chan_common: common dmaengine channel object members + * @device: parent device + * @ch_regs: memory mapped register base + * @mask: channel index in a mask +- * @error_status: transmit error status information from irq handler ++ * @status: transmit status information from irq/prep* functions + * to tasklet (use atomic operations) + * @tasklet: bottom half to finish transaction work + * @lock: serializes enqueue/dequeue operations to descriptors lists +@@ -201,7 +211,7 @@ struct at_dma_chan { + struct at_dma *device; + void __iomem *ch_regs; + u8 mask; +- unsigned long error_status; ++ unsigned long status; + struct tasklet_struct tasklet; + + spinlock_t lock; +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch new file mode 100644 index 0000000..d3770f0 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0003-dmaengine-at_hdmac-debug-information-sg_len-for-prep.patch @@ -0,0 +1,32 @@ +From a4353fd9418ab145376c08ec57ffd2b7c231db30 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 7 Feb 2011 15:07:37 +0100 +Subject: [PATCH 003/107] dmaengine: at_hdmac: debug information sg_len for + prep_slave_sg +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/at_hdmac.c | 3 ++- + 1 files changed, 2 insertions(+), 1 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index a58ae65..1c1508e 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -664,7 +664,8 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + struct scatterlist *sg; + size_t total_len = 0; + +- dev_vdbg(chan2dev(chan), "prep_slave_sg: %s f0x%lx\n", ++ dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", ++ sg_len, + direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", + flags); + +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch new file mode 100644 index 0000000..60c4bfb --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0004-dmaengine-at_hdmac-remove-channel-status-testing-in-.patch @@ -0,0 +1,41 @@ +From 1e96442285f67be04287e3f2cb536328f2cbae58 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Thu, 10 Feb 2011 12:33:54 +0100 +Subject: [PATCH 004/107] dmaengine: at_hdmac: remove channel status testing + in tasklet +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is no need to test if channel is enabled in tasklet: +- in error path, channel is disabled in interrupt routine +- in normal path, this test is performed in sub functions to report +a misuse of the engine. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/at_hdmac.c | 7 ------- + 1 files changed, 0 insertions(+), 7 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index 1c1508e..858358a 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -449,13 +449,6 @@ static void atc_tasklet(unsigned long data) + { + struct at_dma_chan *atchan = (struct at_dma_chan *)data; + +- /* Channel cannot be enabled here */ +- if (atc_chan_is_enabled(atchan)) { +- dev_err(chan2dev(&atchan->chan_common), +- "BUG: channel enabled in tasklet\n"); +- return; +- } +- + spin_lock(&atchan->lock); + if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) + atc_handle_error(atchan); +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch new file mode 100644 index 0000000..dd7d738 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0005-dmaengine-at_hdmac-specialize-AHB-interfaces-to-opti.patch @@ -0,0 +1,121 @@ +From d319913ecdc643e960902b456069b7259e260a65 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 14 Feb 2011 19:27:46 +0100 +Subject: [PATCH 005/107] dmaengine: at_hdmac: specialize AHB interfaces to + optimize transfers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DMA controller has two AHB interfaces on the SOC internal +matrix. +It is more efficient to specialize each interface as the +access to memory can introduce latencies that are not compatible +with peripheral accesses requirements. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/at_hdmac.c | 20 ++++++++++---------- + drivers/dma/at_hdmac_regs.h | 2 ++ + 2 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c +index 858358a..db2c0bd 100644 +--- a/drivers/dma/at_hdmac.c ++++ b/drivers/dma/at_hdmac.c +@@ -37,8 +37,7 @@ + + #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) + #define ATC_DEFAULT_CTRLA (0) +-#define ATC_DEFAULT_CTRLB (ATC_SIF(0) \ +- |ATC_DIF(1)) ++#define ATC_DEFAULT_CTRLB (ATC_SIF(MEM_IF) | ATC_DIF(MEM_IF)) + + /* + * Initial number of descriptors to allocate for each channel. This could +@@ -670,14 +669,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + reg_width = atslave->reg_width; + + ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; +- ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN; ++ ctrlb = ATC_IEN; + + switch (direction) { + case DMA_TO_DEVICE: + ctrla |= ATC_DST_WIDTH(reg_width); + ctrlb |= ATC_DST_ADDR_MODE_FIXED + | ATC_SRC_ADDR_MODE_INCR +- | ATC_FC_MEM2PER; ++ | ATC_FC_MEM2PER | ATC_SIF(MEM_IF) | ATC_DIF(PER_IF); + reg = atslave->tx_reg; + for_each_sg(sgl, sg, sg_len, i) { + struct at_desc *desc; +@@ -718,7 +717,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + ctrla |= ATC_SRC_WIDTH(reg_width); + ctrlb |= ATC_DST_ADDR_MODE_INCR + | ATC_SRC_ADDR_MODE_FIXED +- | ATC_FC_PER2MEM; ++ | ATC_FC_PER2MEM | ATC_SIF(PER_IF) | ATC_DIF(MEM_IF); + + reg = atslave->rx_reg; + for_each_sg(sgl, sg, sg_len, i) { +@@ -798,7 +797,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + unsigned int periods = buf_len / period_len; + unsigned int reg_width; + u32 ctrla; +- u32 ctrlb; ++ u32 ctrlb = 0; + unsigned int i; + + dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", +@@ -829,12 +828,11 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) + goto err_out; + +- /* prepare common CRTLA/CTRLB values */ ++ /* prepare common CRTLA value */ + ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla + | ATC_DST_WIDTH(reg_width) + | ATC_SRC_WIDTH(reg_width) + | period_len >> reg_width; +- ctrlb = ATC_DEFAULT_CTRLB; + + /* build cyclic linked list */ + for (i = 0; i < periods; i++) { +@@ -852,7 +850,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + desc->lli.ctrlb = ctrlb + | ATC_DST_ADDR_MODE_FIXED + | ATC_SRC_ADDR_MODE_INCR +- | ATC_FC_MEM2PER; ++ | ATC_FC_MEM2PER ++ | ATC_SIF(MEM_IF) | ATC_DIF(PER_IF); + break; + + case DMA_FROM_DEVICE: +@@ -862,7 +861,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + desc->lli.ctrlb = ctrlb + | ATC_DST_ADDR_MODE_INCR + | ATC_SRC_ADDR_MODE_FIXED +- | ATC_FC_PER2MEM; ++ | ATC_FC_PER2MEM ++ | ATC_SIF(PER_IF) | ATC_DIF(MEM_IF); + break; + + default: +diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h +index c79a9e0..9afcb8d 100644 +--- a/drivers/dma/at_hdmac_regs.h ++++ b/drivers/dma/at_hdmac_regs.h +@@ -103,6 +103,8 @@ + /* Bitfields in CTRLB */ + #define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */ + #define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */ ++#define MEM_IF 0 /* specify AHB interface 0 as memory interface */ ++#define PER_IF 1 /* specify AHB interface 1 as peripheral interface */ + #define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */ + #define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */ + #define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */ +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch new file mode 100644 index 0000000..b388baf --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0006-dmaengine-AT91SAM9X5-has-a-Atmel-AHB-DMA-engine.patch @@ -0,0 +1,33 @@ +From b58656e215f783ca2099e29ee58396122a8220c7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Mon, 18 Apr 2011 17:19:18 +0200 +Subject: [PATCH 006/107] dmaengine: AT91SAM9X5 has a Atmel AHB DMA engine +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This change was part of a patch provided (non-publically) by Atmel. I +split it off because it was unrelated to the commit log and the other +changes in that commit. + +Signed-off-by: Uwe Kleine-König +--- + drivers/dma/Kconfig | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig +index a572600..354fcfa 100644 +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -91,7 +91,7 @@ config DW_DMAC + + config AT_HDMAC + tristate "Atmel AHB DMA support" +- depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 ++ depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5 + select DMA_ENGINE + help + Support the Atmel AHB DMA controller. This can be integrated in +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch new file mode 100644 index 0000000..7c802ca --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0007-rtc-at91-workaround-for-5series-ES-chips.patch @@ -0,0 +1,79 @@ +From ef74ff3fcfc0072cbac374553e1a6b2f3bf099c4 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Tue, 19 Oct 2010 13:36:53 +0200 +Subject: [PATCH 007/107] rtc/at91: workaround for 5series ES chips +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The RTC IMR register is not working on 5series ES chips. Fake it with a static +variable and some accessors functions. +This workaround does not modify the original RTC code. + +XXX: reevaluate if the hardware-guys fixed it, if yes, drop this, + patch, if no send them some stinking fish and rework patch to make + the driver aware of the shortcoming. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + .../include/mach/at91sam9x5_rtc_workaround.h | 31 ++++++++++++++++++++ + drivers/rtc/rtc-at91rm9200.c | 4 ++ + 2 files changed, 35 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h + +diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h b/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h +new file mode 100644 +index 0000000..4b9f0d7 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9x5_rtc_workaround.h +@@ -0,0 +1,31 @@ ++/* ++ * Real Time Clock workaround header file ++ * apply to at91sam9x5 family Engineering Samples ++ * ++ * Copyright (C) 2010 Atmel, Nicolas Ferre ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ */ ++ ++static u32 sam9x5es_rtc_imr = 0; ++ ++#define at91_sys_read(x) ( \ ++ (x) == AT91_RTC_IMR? \ ++ sam9x5es_rtc_imr: \ ++ at91_sys_read(x) \ ++ ) ++ ++#define at91_sys_write(y, x) do { \ ++ if ((y) == AT91_RTC_IDR) { \ ++ at91_sys_write(AT91_RTC_IDR, (x)); \ ++ sam9x5es_rtc_imr &= ~(x); \ ++ } else if ((y) == AT91_RTC_IER) { \ ++ sam9x5es_rtc_imr |= (x); \ ++ at91_sys_write(AT91_RTC_IER, (x)); \ ++ } else { \ ++ at91_sys_write((y), (x)); \ ++ } \ ++ } while (0) +diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c +index e39b77a..b9038f4 100644 +--- a/drivers/rtc/rtc-at91rm9200.c ++++ b/drivers/rtc/rtc-at91rm9200.c +@@ -32,6 +32,10 @@ + + #include + ++#if defined(CONFIG_ARCH_AT91SAM9X5) ++#include ++#endif ++ + + #define AT91_RTC_EPOCH 1900UL /* just like arch/arm/common/rtctime.c */ + +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch new file mode 100644 index 0000000..1e4ad49 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0008-rtc-AT91SAM9X5-has-an-at91_rtc.patch @@ -0,0 +1,41 @@ +From 25d339722fe977695b998ebb8b2ff2fab9faf7bb Mon Sep 17 00:00:00 2001 +From: Dan Liang +Date: Mon, 2 Aug 2010 16:01:39 +0800 +Subject: [PATCH 008/107] rtc: AT91SAM9X5 has an at91_rtc +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Dan Liang +[ukleinek: reword commit log] +Signed-off-by: Uwe Kleine-König +--- + drivers/rtc/Kconfig | 6 +++--- + 1 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index e187887..fa5a072 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -789,15 +789,15 @@ config RTC_DRV_AT32AP700X + + config RTC_DRV_AT91RM9200 + tristate "AT91RM9200 or some AT91SAM9 RTC" +- depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 ++ depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5 + help + Driver for the internal RTC (Realtime Clock) module found on +- Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips ++ Atmel AT91RM9200's and some AT91SAM9 chips. On AT91SAM9 chips + this is powered by the backup power supply. + + config RTC_DRV_AT91SAM9 + tristate "AT91SAM9x/AT91CAP9 RTT as RTC" +- depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) ++ depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40 || ARCH_AT91SAM9X5) + help + RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT + (Real Time Timer). These timers are powered by the backup power +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch new file mode 100644 index 0000000..133588d --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0009-ARM-at91-overall-definition-add-5series-support.patch @@ -0,0 +1,356 @@ +From 4b93b1ba993ae9c9d60a86d0a55108a4d2ee2244 Mon Sep 17 00:00:00 2001 +From: Dan Liang +Date: Tue, 13 Jul 2010 15:56:23 +0800 +Subject: [PATCH 009/107] ARM: at91: overall definition: add 5series support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +[at91sam9x5.h] +Add the definitions of peripheral and system registers for 5series chips family. + +[at91sam9x5_matrix.h] +Add definitions of Matrix registers for 5series chips family. + +[cpu.h] +Add ARCH_ID and basic cpu macros definition for 5series chips family. + +Signed-off-by: Dan Liang +Signed-off-by: Uwe Kleine-König +--- + arch/arm/mach-at91/include/mach/at91sam9x5.h | 179 ++++++++++++++++++++ + .../arm/mach-at91/include/mach/at91sam9x5_matrix.h | 136 +++++++++++++++ + 2 files changed, 315 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5.h + create mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h + +diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h +new file mode 100644 +index 0000000..c263b46 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h +@@ -0,0 +1,179 @@ ++/* ++ * Chip-specific header file for the AT91SAM9x5 family ++ * ++ * Copyright (C) 2009-2010 Atmel Corporation. ++ * ++ * Common definitions. ++ * Based on AT91SAM9x5 preliminary datasheet. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9X5_H ++#define AT91SAM9X5_H ++ ++/* ++ * Peripheral identifiers/interrupts. ++ */ ++#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ ++#define AT91_ID_SYS 1 /* System Controller Interrupt */ ++#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ ++#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ ++#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ ++#define AT91SAM9X5_ID_USART0 5 /* USART 0 */ ++#define AT91SAM9X5_ID_USART1 6 /* USART 1 */ ++#define AT91SAM9X5_ID_USART2 7 /* USART 2 */ ++#define AT91SAM9X5_ID_USART3 8 /* USART 3 */ ++#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ ++#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ ++#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ ++#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ ++#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ ++#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ ++#define AT91SAM9X5_ID_UART0 15 /* UART 0 */ ++#define AT91SAM9X5_ID_UART1 16 /* UART 1 */ ++#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ ++#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ ++#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ ++#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ ++#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ ++#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ ++#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ ++#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ ++#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ ++#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ ++#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ ++#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ ++#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ ++#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ ++#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ ++#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ ++ ++/* ++ * User Peripheral physical base addresses. ++ */ ++#define AT91SAM9X5_BASE_SPI0 0xf0000000 ++#define AT91SAM9X5_BASE_SPI1 0xf0004000 ++#define AT91SAM9X5_BASE_MCI0 0xf0008000 ++#define AT91SAM9X5_BASE_MCI1 0xf000c000 ++#define AT91SAM9X5_BASE_SSC 0xf0010000 ++#define AT91SAM9X5_BASE_CAN0 0xf8000000 ++#define AT91SAM9X5_BASE_CAN1 0xf8004000 ++#define AT91SAM9X5_BASE_TCB0 0xf8008000 ++#define AT91SAM9X5_BASE_TC0 0xf8008000 ++#define AT91SAM9X5_BASE_TC1 0xf8008040 ++#define AT91SAM9X5_BASE_TC2 0xf8008080 ++#define AT91SAM9X5_BASE_TCB1 0xf800c000 ++#define AT91SAM9X5_BASE_TC3 0xf800c000 ++#define AT91SAM9X5_BASE_TC4 0xf800c040 ++#define AT91SAM9X5_BASE_TC5 0xf800c080 ++#define AT91SAM9X5_BASE_TWI0 0xf8010000 ++#define AT91SAM9X5_BASE_TWI1 0xf8014000 ++#define AT91SAM9X5_BASE_TWI2 0xf8018000 ++#define AT91SAM9X5_BASE_USART0 0xf801c000 ++#define AT91SAM9X5_BASE_USART1 0xf8020000 ++#define AT91SAM9X5_BASE_USART2 0xf8024000 ++#define AT91SAM9X5_BASE_USART3 0xf8028000 ++#define AT91SAM9X5_BASE_EMAC0 0xf802c000 ++#define AT91SAM9X5_BASE_EMAC1 0xf8030000 ++#define AT91SAM9X5_BASE_PWMC 0xf8034000 ++#define AT91SAM9X5_BASE_LCDC 0xf8038000 ++#define AT91SAM9X5_BASE_UDPHS 0xf803c000 ++#define AT91SAM9X5_BASE_UART0 0xf8040000 ++#define AT91SAM9X5_BASE_UART1 0xf8044000 ++#define AT91SAM9X5_BASE_ISI 0xf8048000 ++#define AT91SAM9X5_BASE_ADC 0xf804c000 ++#define AT91_BASE_SYS 0xffffc000 ++ ++/* ++ * System Peripherals (offset from AT91_BASE_SYS) ++ */ ++#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS) ++#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS) ++#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS) ++#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) ++#define AT91_SMC (0xffffea00 - AT91_BASE_SYS) ++#define AT91_DMA0 (0xffffec00 - AT91_BASE_SYS) ++#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS) ++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ++#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) ++#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) ++#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) ++#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) ++#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) ++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) ++#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS) ++#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) ++#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS) ++#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS) ++#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) ++#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS) ++ ++#define AT91_USART0 AT91SAM9X5_BASE_US0 ++#define AT91_USART1 AT91SAM9X5_BASE_US1 ++#define AT91_USART2 AT91SAM9X5_BASE_US2 ++#define AT91_USART3 AT91SAM9X5_BASE_US3 ++ ++/* ++ * Internal Memory. ++ */ ++#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ ++#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ ++ ++#define AT91SAM9X5_ROM_BASE 0x00100000 /* Internal ROM base address */ ++#define AT91SAM9X5_ROM_SIZE SZ_1M /* Internal ROM size (1Mb) */ ++ ++#define AT91SAM9X5_SMD_BASE 0x00400000 /* SMD Controller */ ++#define AT91SAM9X5_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ ++#define AT91SAM9X5_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ ++#define AT91SAM9X5_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ ++ ++#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1 ++ ++#define CONSISTENT_DMA_SIZE SZ_4M ++ ++/* ++ * DMA0 peripheral identifiers ++ * for hardware handshaking interface ++ */ ++#define AT_DMA_ID_MCI0 0 ++#define AT_DMA_ID_SPI0_TX 1 ++#define AT_DMA_ID_SPI0_RX 2 ++#define AT_DMA_ID_USART0_TX 3 ++#define AT_DMA_ID_USART0_RX 4 ++#define AT_DMA_ID_USART1_TX 5 ++#define AT_DMA_ID_USART1_RX 6 ++#define AT_DMA_ID_TWI0_TX 7 ++#define AT_DMA_ID_TWI0_RX 8 ++#define AT_DMA_ID_TWI2_TX 9 ++#define AT_DMA_ID_TWI2_RX 10 ++#define AT_DMA_ID_UART0_TX 11 ++#define AT_DMA_ID_UART0_RX 12 ++#define AT_DMA_ID_SSC_TX 13 ++#define AT_DMA_ID_SSC_RX 14 ++ ++/* ++ * DMA1 peripheral identifiers ++ * for hardware handshaking interface ++ */ ++#define AT_DMA_ID_MCI1 0 ++#define AT_DMA_ID_SPI1_TX 1 ++#define AT_DMA_ID_SPI1_RX 2 ++#define AT_DMA_ID_SMD_TX 3 ++#define AT_DMA_ID_SMD_RX 4 ++#define AT_DMA_ID_TWI1_TX 5 ++#define AT_DMA_ID_TWI1_RX 6 ++#define AT_DMA_ID_ADC_RX 7 ++#define AT_DMA_ID_DBGU_TX 8 ++#define AT_DMA_ID_DBGU_RX 9 ++#define AT_DMA_ID_UART1_TX 10 ++#define AT_DMA_ID_UART1_RX 11 ++#define AT_DMA_ID_USART2_TX 12 ++#define AT_DMA_ID_USART2_RX 13 ++#define AT_DMA_ID_USART3_TX 14 ++#define AT_DMA_ID_USART3_RX 15 ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +new file mode 100644 +index 0000000..c3e6b64 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +@@ -0,0 +1,136 @@ ++/* ++ * Matrix-centric header file for the AT91SAM9x5 family ++ * ++ * Copyright (C) 2009-2010 Atmel Corporation. ++ * ++ * Memory Controllers (MATRIX, EBI) - System peripherals registers. ++ * Based on AT91SAM9x5 preliminary datasheet. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9X5_MATRIX_H ++#define AT91SAM9X5_MATRIX_H ++ ++#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ ++#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ ++#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ ++#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ ++#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ ++#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ ++#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ ++#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ ++#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ ++#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ ++#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ ++#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ ++#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ ++#define AT91_MATRIX_ULBT_INFINITE (0 << 0) ++#define AT91_MATRIX_ULBT_SINGLE (1 << 0) ++#define AT91_MATRIX_ULBT_FOUR (2 << 0) ++#define AT91_MATRIX_ULBT_EIGHT (3 << 0) ++#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) ++#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) ++#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) ++#define AT91_MATRIX_ULBT_128 (7 << 0) ++ ++#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ ++#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ ++#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ ++#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ ++#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ ++#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ ++#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ ++#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ ++#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ ++#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ ++#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ ++#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) ++#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ ++ ++#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ ++#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ ++#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ ++#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ ++#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ ++#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ ++#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ ++#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ ++#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ ++#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ ++#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ ++#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ ++#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ ++#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ ++#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ ++#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ ++#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ ++#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ ++#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ ++#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ ++#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ ++#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ ++#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ ++#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ ++#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ ++#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ ++#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ ++#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ ++#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ ++#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ ++ ++#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ ++#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ ++#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ ++#define AT91_MATRIX_RCB2 (1 << 2) ++#define AT91_MATRIX_RCB3 (1 << 3) ++#define AT91_MATRIX_RCB4 (1 << 4) ++#define AT91_MATRIX_RCB5 (1 << 5) ++#define AT91_MATRIX_RCB6 (1 << 6) ++#define AT91_MATRIX_RCB7 (1 << 7) ++#define AT91_MATRIX_RCB8 (1 << 8) ++#define AT91_MATRIX_RCB9 (1 << 9) ++#define AT91_MATRIX_RCB10 (1 << 10) ++#define AT91_MATRIX_RCB11 (1 << 11) ++ ++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ ++#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ ++#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) ++#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) ++#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ ++#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) ++#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) ++#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ ++#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) ++#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) ++#define AT91_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */ ++#define AT91_MATRIX_EBI_DBPD_ON (0 << 9) ++#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) ++#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ ++#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) ++#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) ++#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ ++#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) ++#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) ++#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ ++#define AT91_MATRIX_MP_OFF (0 << 25) ++#define AT91_MATRIX_MP_ON (1 << 25) ++ ++#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ ++#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ ++#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) ++#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) ++#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ ++ ++#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ ++#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ ++#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) ++#define AT91_MATRIX_WPSR_WPV (1 << 0) ++#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ ++ ++#endif +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch new file mode 100644 index 0000000..b6dd5d4 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0010-ARM-at91-PMC-header-add-5series-support.patch @@ -0,0 +1,121 @@ +From 70174744ea113add6279afb8642ea71acafb8d69 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Fri, 9 Jul 2010 19:33:10 +0200 +Subject: [PATCH 010/107] ARM: at91: PMC header: add 5series support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add 5series chips family support in PMC header file: +Alternate prescaler location and CSS length for PCKR is added. +The new Peripheral Control Register management is added. +Protection mode register is modified to complete its management. + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + arch/arm/mach-at91/include/mach/at91_pmc.h | 63 ++++++++++++++++++++++------ + 1 files changed, 50 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h +index e46f93e..1782178 100644 +--- a/arch/arm/mach-at91/include/mach/at91_pmc.h ++++ b/arch/arm/mach-at91/include/mach/at91_pmc.h +@@ -47,9 +47,13 @@ + #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ + + #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +-#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +-#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ +-#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ ++#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ ++#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ ++#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ ++#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ ++#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ ++#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ ++#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ + + #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ + #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +@@ -74,14 +78,24 @@ + #define AT91_PMC_CSS_PLLA (2 << 0) + #define AT91_PMC_CSS_PLLB (3 << 0) + #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ +-#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +-#define AT91_PMC_PRES_1 (0 << 2) +-#define AT91_PMC_PRES_2 (1 << 2) +-#define AT91_PMC_PRES_4 (2 << 2) +-#define AT91_PMC_PRES_8 (3 << 2) +-#define AT91_PMC_PRES_16 (4 << 2) +-#define AT91_PMC_PRES_32 (5 << 2) +-#define AT91_PMC_PRES_64 (6 << 2) ++#define PMC_PRES_OFFSET 2 ++#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ ++#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) ++#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) ++#define PMC_ALT_PRES_OFFSET 4 ++#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ ++#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) ++#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) + #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ + #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ + #define AT91RM9200_PMC_MDIV_2 (1 << 8) +@@ -105,7 +119,14 @@ + #define AT91_PMC_USBS_UPLL (1 << 0) + #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ + ++#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */ ++#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ ++#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ ++#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) ++ + #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ ++#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ ++#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ + #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ + #define AT91_PMC_CSSMCK_CSS (0 << 8) + #define AT91_PMC_CSSMCK_MCK (1 << 8) +@@ -123,11 +144,27 @@ + #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ + #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ + #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ ++#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ ++#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ ++#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ + #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + +-#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +-#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ ++#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9, AT91CAP9 revC only] */ ++#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ ++#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ ++#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ ++ ++#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */ ++#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ ++#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ + + #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ + ++#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */ ++#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ ++#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ ++#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ ++#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) ++#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ ++ + #endif +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch new file mode 100644 index 0000000..180e515 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0011-ARM-at91-clock-add-5series-chip-family-support.patch @@ -0,0 +1,215 @@ +From 6a6e54c0091962d01f6b343958bbda95487bb9f5 Mon Sep 17 00:00:00 2001 +From: Nicolas Ferre +Date: Mon, 12 Jul 2010 19:24:14 +0200 +Subject: [PATCH 011/107] ARM: at91: clock: add 5series chip family support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Several changes to PMC have to be managed for adding this 5series support: +- alternate prescaler location for both MCKR and PCKR +- alternate CSS length for PCKR +- added cpu_is_at91sam9x5() to functional switches +- manage UTMI bias like sam9g45 chip family + +Signed-off-by: Nicolas Ferre +Signed-off-by: Uwe Kleine-König +--- + arch/arm/mach-at91/clock.c | 85 ++++++++++++++++++++++++++++++++++---------- + 1 files changed, 66 insertions(+), 19 deletions(-) + +diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c +index 9113da6..6c92db8 100644 +--- a/arch/arm/mach-at91/clock.c ++++ b/arch/arm/mach-at91/clock.c +@@ -49,24 +49,37 @@ + */ + #define cpu_has_utmi() ( cpu_is_at91cap9() \ + || cpu_is_at91sam9rl() \ +- || cpu_is_at91sam9g45()) ++ || cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5()) + + #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ +- || cpu_is_at91sam9g45()) ++ || cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5()) + + #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) + + #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ +- || cpu_is_at91sam9g45())) ++ || cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5())) + +-#define cpu_has_upll() (cpu_is_at91sam9g45()) ++#define cpu_has_upll() (cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5()) + + /* USB host HS & FS */ + #define cpu_has_uhp() (!cpu_is_at91sam9rl()) + + /* USB device FS only */ + #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ +- || cpu_is_at91sam9g45())) ++ || cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5())) ++ ++#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5()) ++ ++#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ ++ || cpu_is_at91sam9x5()) ++ ++#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5()) + + static LIST_HEAD(clocks); + static DEFINE_SPINLOCK(clk_lock); +@@ -139,13 +152,6 @@ static void pmc_uckr_mode(struct clk *clk, int is_on) + { + unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); + +- if (cpu_is_at91sam9g45()) { +- if (is_on) +- uckr |= AT91_PMC_BIASEN; +- else +- uckr &= ~AT91_PMC_BIASEN; +- } +- + if (is_on) { + is_on = AT91_PMC_LOCKU; + at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); +@@ -210,11 +216,26 @@ static struct clk __init *at91_css_to_clk(unsigned long css) + return &utmi_clk; + else if (cpu_has_pllb()) + return &pllb; ++ break; ++ /* alternate PMC: can use master clock */ ++ case AT91_PMC_CSS_MASTER: ++ return &mck; + } + + return NULL; + } + ++ ++static int pmc_prescaler_divider(u32 reg) ++{ ++ if (cpu_has_alt_prescaler()) { ++ return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET); ++ } else { ++ return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET); ++ } ++} ++ ++ + /* + * Associate a particular clock with a function (eg, "uart") and device. + * The drivers can then request the same 'function' with several different +@@ -353,12 +374,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate) + { + unsigned long flags; + unsigned prescale; ++ unsigned long prescale_offset, css_mask; + unsigned long actual; + + if (!clk_is_programmable(clk)) + return -EINVAL; + if (clk->users) + return -EBUSY; ++ ++ if (cpu_has_alt_prescaler()) { ++ prescale_offset = PMC_ALT_PRES_OFFSET; ++ css_mask = AT91_PMC_ALT_PCKR_CSS; ++ } else { ++ prescale_offset = PMC_PRES_OFFSET; ++ css_mask = AT91_PMC_CSS; ++ } ++ + spin_lock_irqsave(&clk_lock, flags); + + actual = clk->parent->rate_hz; +@@ -367,8 +398,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate) + u32 pckr; + + pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); +- pckr &= AT91_PMC_CSS; /* clock selection */ +- pckr |= prescale << 2; ++ pckr &= css_mask; /* keep clock selection */ ++ pckr |= prescale << prescale_offset; + at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); + clk->rate_hz = actual; + break; +@@ -415,11 +446,17 @@ static void __init init_programmable_clock(struct clk *clk) + { + struct clk *parent; + u32 pckr; ++ unsigned int css_mask; ++ ++ if (cpu_has_alt_prescaler()) ++ css_mask = AT91_PMC_ALT_PCKR_CSS; ++ else ++ css_mask = AT91_PMC_CSS; + + pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); +- parent = at91_css_to_clk(pckr & AT91_PMC_CSS); ++ parent = at91_css_to_clk(pckr & css_mask); + clk->parent = parent; +- clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2)); ++ clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); + } + + #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ +@@ -697,7 +734,7 @@ int __init at91_clock_init(unsigned long main_clock) + if (pll_overclock) + pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + +- if (cpu_is_at91sam9g45()) { ++ if (cpu_has_plladiv2()) { + mckr = at91_sys_read(AT91_PMC_MCKR); + plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ + } +@@ -719,6 +756,10 @@ int __init at91_clock_init(unsigned long main_clock) + * (obtain the USB High Speed 480 MHz when input is 12 MHz) + */ + utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; ++ ++ /* UTMI bias and PLL are managed at the same time */ ++ if (cpu_is_at91sam9g45() || cpu_is_at91sam9x5()) ++ utmi_clk.pmc_mask |= AT91_PMC_BIASEN; + } + + /* +@@ -737,7 +778,7 @@ int __init at91_clock_init(unsigned long main_clock) + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; +- freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ ++ freq /= pmc_prescaler_divider(mckr); /* prescale */ + if (cpu_is_at91rm9200()) { + mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + } else if (cpu_is_at91sam9g20()) { +@@ -745,13 +786,19 @@ int __init at91_clock_init(unsigned long main_clock) + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + if (mckr & AT91_PMC_PDIV) + freq /= 2; /* processor clock division */ +- } else if (cpu_is_at91sam9g45()) { ++ } else if (cpu_has_mdiv3()) { + mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? + freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + } else { + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + } + ++ if (cpu_has_alt_prescaler()) { ++ /* Programmable clocks can use MCK */ ++ mck.type |= CLK_TYPE_PRIMARY; ++ mck.id = 4; ++ } ++ + /* Register the PMC's standard clocks */ + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + list_add_tail(&standard_pmc_clocks[i]->node, &clocks); +-- +1.7.5.4 + diff --git a/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch new file mode 100644 index 0000000..6078e73 --- /dev/null +++ b/multitech/recipes/linux/linux-2.6.39.4/2.6.39-at91-exp.2/2.6.39-at91-exp.2-0012-ARM-at91-AT91SAM9x5-processors-and-EK-board-support.patch @@ -0,0 +1,3216 @@ +From 31f087cd051928de83fe17aee4d1e2a6416e88ee Mon Sep 17 00:00:00 2001 +From: Dan Liang +Date: Fri, 23 Jul 2010 13:00:56 +0200 +Subject: [PATCH 012/107] ARM: at91: AT91SAM9x5 processors and EK board + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch is based on many smaller patches by Dan Liang, Hong Xu, Josh +Wu and Nicolas Ferre. + +XXX: try to put support for AT91SAM9x5 into an existing choice item + +Signed-off-by: Dan Liang +Signed-off-by: Hong Xu +Signed-off-by: Josh Wu +Signed-off-by: Nicolas Ferre +[ukleinek: remove .phys_io and .io_pg_offst] +Signed-off-by: Uwe Kleine-König +--- + arch/arm/mach-at91/Kconfig | 21 + + arch/arm/mach-at91/Makefile | 4 + + arch/arm/mach-at91/at91sam9x5.c | 416 ++++++ + arch/arm/mach-at91/at91sam9x5_devices.c | 1785 ++++++++++++++++++++++++ + arch/arm/mach-at91/board-sam9x5cm.c | 236 ++++ + arch/arm/mach-at91/board-sam9x5ek.c | 358 +++++ + arch/arm/mach-at91/generic.h | 2 + + arch/arm/mach-at91/include/mach/board-sam9x5.h | 91 ++ + arch/arm/mach-at91/include/mach/board.h | 18 +- + arch/arm/mach-at91/include/mach/hardware.h | 2 + + arch/arm/mach-at91/include/mach/timex.h | 5 + + arch/arm/mach-at91/pm.h | 19 + + arch/arm/mach-at91/pm_slowclock.S | 11 +- + 13 files changed, 2961 insertions(+), 7 deletions(-) + create mode 100644 arch/arm/mach-at91/at91sam9x5.c + create mode 100644 arch/arm/mach-at91/at91sam9x5_devices.c + create mode 100644 arch/arm/mach-at91/board-sam9x5cm.c + create mode 100644 arch/arm/mach-at91/board-sam9x5ek.c + create mode 100644 arch/arm/mach-at91/include/mach/board-sam9x5.h + +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 2d299bf..b5d29ef 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -78,6 +78,13 @@ config ARCH_AT91SAM9G45 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + ++config ARCH_AT91SAM9X5 ++ bool "AT91SAM9X5" ++ select CPU_ARM926T ++ select GENERIC_CLOCKEVENTS ++ select HAVE_FB_ATMEL ++ select HAVE_NET_MACB ++ + config ARCH_AT91CAP9 + bool "AT91CAP9" + select CPU_ARM926T +@@ -426,6 +433,20 @@ endif + + # ---------------------------------------------------------- + ++if ARCH_AT91SAM9X5 ++ ++comment "AT91SAM9x5 Series Board Type" ++ ++config MACH_AT91SAM9X5EK ++ bool "Atmel AT91SAM9x5 Series Evaluation Kit" ++ help ++ Select this if you re using Atmel's AT91SAM9x5-EK Evaluation Kit. ++ Supported chips are sam9g15, sam9g25, sam9x25, sam9g35 and sam9x35. ++ ++endif ++ ++# ---------------------------------------------------------- ++ + if ARCH_AT91CAP9 + + comment "AT91CAP9 Board Type" +diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile +index a83835e..3d82460 100644 +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d + obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o + obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o + obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o ++obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o at91sam9x5_devices.o sam9_smc.o + obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o + obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o + obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o +@@ -75,6 +76,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o + # AT91SAM9G45 board-specific support + obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o + ++# AT91SAM9X5 board-specific support ++obj-$(CONFIG_MACH_AT91SAM9X5EK) += board-sam9x5cm.o board-sam9x5ek.o ++ + # AT91CAP9 board-specific support + obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o + +diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c +new file mode 100644 +index 0000000..de456e6 +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9x5.c +@@ -0,0 +1,416 @@ ++/* ++ * Chip-specific setup code for the AT91SAM9x5 family ++ * ++ * Copyright (C) 2010 Atmel Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "generic.h" ++#include "clock.h" ++ ++static struct map_desc at91sam9x5_io_desc[] __initdata = { ++ { ++ .virtual = AT91_VA_BASE_SYS, ++ .pfn = __phys_to_pfn(AT91_BASE_SYS), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = AT91_IO_VIRT_BASE - AT91SAM9X5_SRAM_SIZE, ++ .pfn = __phys_to_pfn(AT91SAM9X5_SRAM_BASE), ++ .length = AT91SAM9X5_SRAM_SIZE, ++ .type = MT_DEVICE, ++ } ++}; ++ ++/* -------------------------------------------------------------------- ++ * Clocks ++ * -------------------------------------------------------------------- */ ++ ++/* ++ * The peripheral clocks. ++ */ ++static struct clk pioAB_clk = { ++ .name = "pioAB_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioCD_clk = { ++ .name = "pioCD_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk smd_clk = { ++ .name = "smd_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_SMD, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart0_clk = { ++ .name = "usart0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_USART0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart1_clk = { ++ .name = "usart1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_USART1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart2_clk = { ++ .name = "usart2_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_USART2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* USART3 clock - Only for sam9g25/sam9x25 */ ++static struct clk usart3_clk = { ++ .name = "usart3_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_USART3, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi0_clk = { ++ .name = "twi0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_TWI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi1_clk = { ++ .name = "twi1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_TWI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi2_clk = { ++ .name = "twi2_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_TWI2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc0_clk = { ++ .name = "mci0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_MCI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi0_clk = { ++ .name = "spi0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_SPI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi1_clk = { ++ .name = "spi1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_SPI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uart0_clk = { ++ .name = "uart0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_UART0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uart1_clk = { ++ .name = "uart1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_UART1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tcb0_clk = { ++ .name = "tcb0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_TCB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pwm_clk = { ++ .name = "pwm_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_PWM, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk adc_clk = { ++ .name = "adc_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_ADC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk dma0_clk = { ++ .name = "dma0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_DMA0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk dma1_clk = { ++ .name = "dma1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_DMA1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uhphs_clk = { ++ .name = "uhphs_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk udphs_clk = { ++ .name = "udphs_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */ ++static struct clk macb0_clk = { ++ .name = "macb0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */ ++static struct clk lcdc_clk = { ++ .name = "lcdc_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_LCDC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* isi clock - Only for sam9g25 */ ++static struct clk isi_clk = { ++ .name = "isi_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_ISI, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc1_clk = { ++ .name = "mci1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_MCI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* emac1 clock - Only for sam9x25 */ ++static struct clk macb1_clk = { ++ .name = "macb1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc_clk = { ++ .name = "ssc_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_SSC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* can0 clock - Only for sam9x35 */ ++static struct clk can0_clk = { ++ .name = "can0_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_CAN0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++/* can1 clock - Only for sam9x35 */ ++static struct clk can1_clk = { ++ .name = "can1_clk", ++ .pmc_mask = 1 << AT91SAM9X5_ID_CAN1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++ ++/* One additional fake clock for ohci */ ++static struct clk ohci_clk = { ++ .name = "ohci_clk", ++ .pmc_mask = 0, ++ .type = CLK_TYPE_PERIPHERAL, ++ .parent = &uhphs_clk, ++}; ++ ++/* One additional fake clock for second TC block */ ++static struct clk tcb1_clk = { ++ .name = "tcb1_clk", ++ .pmc_mask = 0, ++ .type = CLK_TYPE_PERIPHERAL, ++ .parent = &tcb0_clk, ++}; ++ ++static struct clk *periph_clocks[] __initdata = { ++ &pioAB_clk, ++ &pioCD_clk, ++ &smd_clk, ++ &usart0_clk, ++ &usart1_clk, ++ &usart2_clk, ++ &twi0_clk, ++ &twi1_clk, ++ &twi2_clk, ++ &mmc0_clk, ++ &spi0_clk, ++ &spi1_clk, ++ &uart0_clk, ++ &uart1_clk, ++ &tcb0_clk, ++ &pwm_clk, ++ &adc_clk, ++ &dma0_clk, ++ &dma1_clk, ++ &uhphs_clk, ++ &udphs_clk, ++ &mmc1_clk, ++ &ssc_clk, ++ // irq0 ++ &ohci_clk, ++ &tcb1_clk, ++}; ++ ++/* ++ * The two programmable clocks. ++ * You must configure pin multiplexing to bring these signals out. ++ */ ++static struct clk pck0 = { ++ .name = "pck0", ++ .pmc_mask = AT91_PMC_PCK0, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 0, ++}; ++static struct clk pck1 = { ++ .name = "pck1", ++ .pmc_mask = AT91_PMC_PCK1, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 1, ++}; ++ ++static void __init at91sam9x5_register_clocks(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) ++ clk_register(periph_clocks[i]); ++ ++ if (cpu_is_at91sam9g25() ++ || cpu_is_at91sam9x25()) ++ clk_register(&usart3_clk); ++ ++ if (cpu_is_at91sam9g25() ++ || cpu_is_at91sam9x25() ++ || cpu_is_at91sam9g35() ++ || cpu_is_at91sam9x35()) ++ clk_register(&macb0_clk); ++ ++ if (cpu_is_at91sam9g15() ++ || cpu_is_at91sam9g35() ++ || cpu_is_at91sam9x35()) ++ clk_register(&lcdc_clk); ++ ++ if (cpu_is_at91sam9g25()) ++ clk_register(&isi_clk); ++ ++ if (cpu_is_at91sam9x25()) ++ clk_register(&macb1_clk); ++ ++ if (cpu_is_at91sam9x35()) { ++ clk_register(&can0_clk); ++ clk_register(&can1_clk); ++ } ++ ++ clk_register(&pck0); ++ clk_register(&pck1); ++} ++ ++/* -------------------------------------------------------------------- ++ * GPIO ++ * -------------------------------------------------------------------- */ ++ ++static struct at91_gpio_bank at91sam9x5_gpio[] = { ++ { ++ .id = AT91SAM9X5_ID_PIOAB, ++ .offset = AT91_PIOA, ++ .clock = &pioAB_clk, ++ }, { ++ .id = AT91SAM9X5_ID_PIOAB, ++ .offset = AT91_PIOB, ++ .clock = &pioAB_clk, ++ }, { ++ .id = AT91SAM9X5_ID_PIOCD, ++ .offset = AT91_PIOC, ++ .clock = &pioCD_clk, ++ }, { ++ .id = AT91SAM9X5_ID_PIOCD, ++ .offset = AT91_PIOD, ++ .clock = &pioCD_clk, ++ } ++}; ++ ++static void at91sam9x5_reset(void) ++{ ++ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); ++} ++ ++static void at91sam9x5_poweroff(void) ++{ ++ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); ++} ++ ++ ++/* -------------------------------------------------------------------- ++ * AT91SAM9x5 processor initialization ++ * -------------------------------------------------------------------- */ ++ ++void __init at91sam9x5_initialize(unsigned long main_clock) ++{ ++ /* Map peripherals */ ++ iotable_init(at91sam9x5_io_desc, ARRAY_SIZE(at91sam9x5_io_desc)); ++ ++ at91_arch_reset = at91sam9x5_reset; ++ pm_power_off = at91sam9x5_poweroff; ++ at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0); ++ ++ /* Init clock subsystem */ ++ at91_clock_init(main_clock); ++ ++ /* Register the processor-specific clocks */ ++ at91sam9x5_register_clocks(); ++ ++ /* Register GPIO subsystem */ ++ at91_gpio_init(at91sam9x5_gpio, 4); ++} ++ ++/* -------------------------------------------------------------------- ++ * Interrupt initialization ++ * -------------------------------------------------------------------- */ ++ ++/* ++ * The default interrupt priority levels (0 = lowest, 7 = highest). ++ */ ++static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = { ++ 7, /* Advanced Interrupt Controller (FIQ) */ ++ 7, /* System Peripherals */ ++ 1, /* Parallel IO Controller A and B */ ++ 1, /* Parallel IO Controller C and D */ ++ 4, /* Soft Modem */ ++ 5, /* USART 0 */ ++ 5, /* USART 1 */ ++ 5, /* USART 2 */ ++ 5, /* USART 3 */ ++ 6, /* Two-Wire Interface 0 */ ++ 6, /* Two-Wire Interface 1 */ ++ 6, /* Two-Wire Interface 2 */ ++ 0, /* Multimedia Card Interface 0 */ ++ 5, /* Serial Peripheral Interface 0 */ ++ 5, /* Serial Peripheral Interface 1 */ ++ 5, /* UART 0 */ ++ 5, /* UART 1 */ ++ 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ ++ 0, /* Pulse Width Modulation Controller */ ++ 0, /* ADC COntroller */ ++ 0, /* DMA Controller 0 */ ++ 0, /* DMA Controller 1 */ ++ 2, /* USB Host High Speed port */ ++ 2, /* USB Device High speed port */ ++ 3, /* Ethernet MAC 0 */ ++ 3, /* LDC Controller or Image Sensor Interface */ ++ 0, /* Multimedia Card Interface 1 */ ++ 3, /* Ethernet MAC 1 */ ++ 4, /* Synchronous Serial Interface */ ++ 4, /* CAN Controller 0 */ ++ 4, /* CAN Controller 1 */ ++ 0, /* Advanced Interrupt Controller (IRQ0) */ ++}; ++ ++void __init at91sam9x5_init_interrupts(unsigned int priority[NR_AIC_IRQS]) ++{ ++ if (!priority) ++ priority = at91sam9x5_default_irq_priority; ++ ++ /* Initialize the AIC interrupt controller */ ++ at91_aic_init(priority); ++ ++ /* Enable GPIO interrupts */ ++ at91_gpio_irq_setup(); ++} +diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c +new file mode 100644 +index 0000000..e601ae4 +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9x5_devices.c +@@ -0,0 +1,1785 @@ ++/* ++ * On-Chip devices setup code for the AT91SAM9x5 family ++ * ++ * Copyright (C) 2010 Atmel Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include