From 68c9fc1875d00dcc233b3a83ac85acc810c41280 Mon Sep 17 00:00:00 2001
From: Mike Fiore <mfiore@multitech.com>
Date: Fri, 26 Apr 2013 12:40:11 -0500
Subject: at91bootstrap: add patch for mtocgd

---
 .../mtocgd/at91bootstrap-3.5.3-mtocgd.patch        | 63 ++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd/at91bootstrap-3.5.3-mtocgd.patch

diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd/at91bootstrap-3.5.3-mtocgd.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd/at91bootstrap-3.5.3-mtocgd.patch
new file mode 100644
index 0000000..4e3aac0
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd/at91bootstrap-3.5.3-mtocgd.patch
@@ -0,0 +1,63 @@
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-24 11:49:10.237842512 -0500
+@@ -42,7 +42,8 @@
+ ALLOW_PIO3=y
+ CONFIG_HAS_PIO3=y
+ CPU_HAS_PMECC=y
+-CONFIG_LOAD_ONE_WIRE=y
++# MTS: don't load one wire
++# CONFIG_LOAD_ONE_WIRE is not set
+ # CONFIG_MMC_SUPPORT is not set
+ 
+ #
+@@ -81,8 +82,8 @@
+ #
+ # PMECC Configuration
+ #
+-CONFIG_PMECC_CORRECT_BITS_2=y
+-# CONFIG_PMECC_CORRECT_BITS_4 is not set
++# CONFIG_PMECC_CORRECT_BITS_2 is not set
++CONFIG_PMECC_CORRECT_BITS_4=y
+ # CONFIG_PMECC_CORRECT_BITS_8 is not set
+ # CONFIG_PMECC_CORRECT_BITS_12 is not set
+ # CONFIG_PMECC_CORRECT_BITS_24 is not set
+@@ -116,4 +117,5 @@
+ # CONFIG_USER_HW_INIT is not set
+ CONFIG_THUMB=y
+ CONFIG_SCLK=y
+-CONFIG_DISABLE_WATCHDOG=y
++# MTS: don't disable watchdog
++# CONFIG_DISABLE_WATCHDOG is not set
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2013-04-24 11:53:09.981847111 -0500
+@@ -312,10 +312,9 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
+-	if (get_cm_rev() == 'A')
+-		reg &= ~AT91C_EBI_NFD0_ON_D16;
+-	else
+-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++	/* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */
++	reg &= ~AT91C_EBI_NFD0_ON_D16;
++	reg &= ~AT91C_EBI_DDR_MP_EN;
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -345,10 +344,8 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
+-	if (get_cm_rev() == 'A')
+-		pio_configure(nand_pins_lo);
+-	else
+-		pio_configure(nand_pins_hi);
++	/* MTR2 */
++	pio_configure(nand_pins_lo);
+ 
+ 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
+ }
-- 
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