From 260d7e7252cf4a5670de4f4e5b82830113dfed59 Mon Sep 17 00:00:00 2001
From: Jesse Gilles <jgilles@multitech.com>
Date: Thu, 19 Dec 2013 09:51:46 -0600
Subject: at91bootstrap-2.13: add debug prints for slew rate and voltage

---
 .../at91bootstrap-2.13/memory_bus_1.8v.patch       | 23 +++++++++++-----------
 .../at91bootstrap-2.13/sdram_slow_slew_rate.patch  |  7 ++++---
 .../at91bootstrap/at91bootstrap_2.13.bbappend      |  6 ++----
 3 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch
index 045f255..f08489b 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/memory_bus_1.8v.patch
@@ -1,22 +1,21 @@
-Only in at91bootstrap-2.13/build: at91sam9g20nf
-Only in at91bootstrap-2.13/config: .depend
-Only in at91bootstrap-2.13: .config
-diff -ru at91bootstrap-2.13/main.c at91bootstrap-2.13_new/main.c
---- at91bootstrap-2.13/main.c	2010-01-12 15:13:39.000000000 -0600
-+++ at91bootstrap-2.13_new/main.c	2011-03-08 06:26:35.463088000 -0600
-@@ -174,6 +174,14 @@
+Index: at91bootstrap-2.13/main.c
+===================================================================
+--- at91bootstrap-2.13.orig/main.c	2010-01-12 15:13:39.000000000 -0600
++++ at91bootstrap-2.13/main.c	2013-12-19 09:27:29.213520415 -0600
+@@ -174,6 +174,16 @@
  	user_hw_init();
  #endif
  
 +#ifdef CONFIG_USER_EBI_1V8
-+//This patch will configure the 9G20 to run a 1.8V memory bus
-+        *((int *)AT91C_CCFG_EBICSA) &= ~(0x1 << 16);  //1.8V bus
-+#else        
-+        *((int *)AT91C_CCFG_EBICSA) |= (0x1 << 16); //3.3V bus        
++	//This patch will configure the 9G20 to run a 1.8V memory bus
++	dbg_print("Memory bus: 1.8v\r\n");
++	*((int *)AT91C_CCFG_EBICSA) &= ~(0x1 << 16);  //1.8V bus
++#else
++	dbg_print("Memory bus: 3.3v\r\n");
++	*((int *)AT91C_CCFG_EBICSA) |= (0x1 << 16); //3.3V bus
 +#endif
 +
 +
  #if	defined(CONFIG_SDRAM) || defined(CONFIG_SDDRC) || defined(CONFIG_DDR2)
  #if	defined(CONFIG_LONG_TEST)
  	/* This will not work for the CAP9 where RAM in elsewhere */
-Only in at91bootstrap-2.13/result: at91sam9g20nf-nandflashboot-2.13-r0.map
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch
index a2cb3d4..f45bfcd 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch
@@ -1,13 +1,14 @@
 Index: at91bootstrap-2.13/board/at91sam9g20ek/at91sam9g20ek.c
 ===================================================================
---- at91bootstrap-2.13.orig/board/at91sam9g20ek/at91sam9g20ek.c	2011-10-31 13:20:49.207272783 -0500
-+++ at91bootstrap-2.13/board/at91sam9g20ek/at91sam9g20ek.c	2011-10-31 13:21:39.099957717 -0500
-@@ -116,8 +116,8 @@
+--- at91bootstrap-2.13.orig/board/at91sam9g20ek/at91sam9g20ek.c	2010-01-12 15:13:39.000000000 -0600
++++ at91bootstrap-2.13/board/at91sam9g20ek/at91sam9g20ek.c	2013-12-19 09:14:45.018624931 -0600
+@@ -116,8 +116,9 @@
  #endif /* CONFIG_VERBOSE */
  
  #ifdef CONFIG_SDRAM
 -	/* Initialize the matrix (memory voltage = 3.3) */
 -	writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1<<16), AT91C_BASE_CCFG + CCFG_EBICSA);
++	dbg_print("SDRAM: slow slew rate\r\n");
 +	/* Initialize the matrix (memory voltage = 3.3, slow slew rate) */
 +	writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1<<16) | (1<<17), AT91C_BASE_CCFG + CCFG_EBICSA);
  
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
index 9b78b06..9ebb283 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
@@ -1,16 +1,14 @@
 FILESEXTRA := "${THISDIR}"
 FILESPATHBASE =. "${FILESEXTRA}:"
 
-PR .= ".corecdp4"
+PR .= ".corecdp5"
 
 SRC_URI += "file://defconfig \
 			file://nand_ids_toshiba.patch \
 			file://sdram_slow_slew_rate.patch \
+			file://memory_bus_1.8v.patch \
 			"
 
 # run memory bus at 1.8v for mt100eocg
-SRC_URI_append_mt100eocg = " file://memory_bus_1.8v.patch"
 AT91BOOTSTRAP_FLAGS_append_mt100eocg = " -DCONFIG_USER_EBI_1V8"
-
-SRC_URI_append_mt100eocg-pcie-dk = " file://memory_bus_1.8v.patch"
 AT91BOOTSTRAP_FLAGS_append_mt100eocg-pcie-dk = " -DCONFIG_USER_EBI_1V8"
-- 
cgit v1.2.3