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-rw-r--r--multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch15
-rw-r--r--multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend3
2 files changed, 17 insertions, 1 deletions
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch
new file mode 100644
index 0000000..a2cb3d4
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-2.13/sdram_slow_slew_rate.patch
@@ -0,0 +1,15 @@
+Index: at91bootstrap-2.13/board/at91sam9g20ek/at91sam9g20ek.c
+===================================================================
+--- at91bootstrap-2.13.orig/board/at91sam9g20ek/at91sam9g20ek.c 2011-10-31 13:20:49.207272783 -0500
++++ at91bootstrap-2.13/board/at91sam9g20ek/at91sam9g20ek.c 2011-10-31 13:21:39.099957717 -0500
+@@ -116,8 +116,8 @@
+ #endif /* CONFIG_VERBOSE */
+
+ #ifdef CONFIG_SDRAM
+- /* Initialize the matrix (memory voltage = 3.3) */
+- writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1<<16), AT91C_BASE_CCFG + CCFG_EBICSA);
++ /* Initialize the matrix (memory voltage = 3.3, slow slew rate) */
++ writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1<<16) | (1<<17), AT91C_BASE_CCFG + CCFG_EBICSA);
+
+ /* Configure SDRAM Controller */
+ sdram_init( AT91C_SDRAMC_NC_9 |
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
index 6578d28..2bd3fd8 100644
--- a/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_2.13.bbappend
@@ -1,10 +1,11 @@
FILESEXTRA := "${THISDIR}"
FILESPATHBASE =. "${FILESEXTRA}:"
-PR .= ".corecdp2"
+PR .= ".corecdp3"
SRC_URI += "file://defconfig \
file://nand_ids_toshiba.patch \
+ file://sdram_slow_slew_rate.patch \
"
# run memory bus at 1.8v for mt100eocg